Method for moving semiconductor layers

Abstract

One aspect of the present invention relates to a method for transferring a semiconductor layer (40) from a donor substrate (10) to a recipient substrate (20), the method comprising the following successive steps: - a first implantation (S120) of first light ions (3a) into the donor substrate (10) at a predetermined implantation depth (30) so as to form a buried weak plane (300) therein; - epitaxy (S130) in the donor substrate (10) of the transferred semiconductor layer (40); - a second implantation (S140) of second light ions (3b) into the donor substrate (10) through the transferred semiconductor layer (40) at the same height as the weak plane (300); The method includes the assembly (S150) of a receiving substrate (20) and a donor substrate (10) covered with a semiconductor layer (40) to be transferred by bonding, the semiconductor layer (40) to be transferred being placed between the receiving substrate (20) and the donor substrate (10), and the fracture (S160) of the donor substrate (10) by annealing the donor substrate (10) along the buried plane of weakness (300), called fracture annealing (S160), in which first ions (3a) are selected and implanted with a first dose (D1) so as to prevent fracture at a predetermined implantation depth (30) during epitaxy (S130), and second ions (3b) are selected and implanted with a second dose (D2) so as to fracture the donor substrate (10) during the fracture annealing (S160).

Description

[Technical Field]

[0001] The technical field of the present invention is the technical field of methods for transferring semiconductor layers.

[0002] More specifically, the present invention relates to a method for moving a semiconductor layer by ion implantation, assembly, and crushing, wherein the semiconductor layer has defects reduced before the assembly step. [Background technology]

[0003] To increase the integration density of integrated circuits, a new technique called 3D monolithic integration involves stacking layers of electronic devices so that they overlap each other.

[0004] Electronic devices are typically transistors. Each layer or level of a transistor is formed in a semiconductor layer called the active layer. The first level of a transistor is formed on the surface of an initial substrate, also called a wafer. The second level of a transistor is manufactured from a semiconductor layer formed on top of the first level of the transistor, or in other words, above the surface of the initial substrate.

[0005] To obtain such a semiconductor layer, it is possible to transfer the semiconductor layer from another so-called donor substrate onto an initial so-called receiver substrate. A known transfer technique called Smart Cut™ is based on a combination of light ion implantation into the donor substrate, molecular bonding assembly of the donor and receiver substrates, and fracturing annealing of the donor substrate.

[0006] This method includes: 1) preparing a donor substrate, typically a silicon wafer; 2) implanting ions, typically light ions such as hydrogen, through the surface of the donor substrate to create nanocavities embedded within the donor substrate to a depth determined by the injection depth, and to demarcate the semiconductor layer to be moved; 3) assembling the donor substrate onto a receiver substrate; and 4) finally, annealing (heating) the assembly to activate the formation of dihydrogen (H2). This gas supplies and grows the nanocavities. Due to the mechanical stress created at the interface between the assembled donor substrate and the receiver substrate, the nanocavities expand at the depth determined by the injection, converge laterally, and create microcracks and final fractures that rapidly spread throughout the wafer. Separation of the semiconductor layer from the donor substrate and migration of the semiconductor layer to the receiver substrate then occur.

[0007] This method offers many advantages and is well mastered. However, several problems remain, particularly those inherent in the light ion implantation step. In fact, light ion implantation creates defects in the semiconductor layer that alter its electrical properties and, consequently, its quality. These defects are related to the fact that ions create different types of defects (vacancies, interstitial defects, hydrogen complexes, nanocavities) not only around the specified implantation depth but also along the ion path in the donor substrate. Thus, defects exist in the semiconductor layer due to light ion implantation at a density proportional to the dose at which implantation is performed. These defects affect the mobility of charge carriers and, therefore, the electrical properties of the semiconductor layer. It should be noted that heating performed during fragmentation annealing does not effectively repair defects formed by implantation and may even lead to the growth / formation of new defects or cavities.

[0008] It is important to reduce the number of defects in the semiconductor layer in order to ensure satisfactory electrical performance for the electronic components manufactured within the semiconductor layer by maintaining an injection dose adapted to the movement of the semiconductor layer.

[0009] In contrast, conventional solutions involve reducing the number of defects after the migration step by exposing the receiving substrate (containing the migrated semiconductor layer) to high temperatures, i.e., temperatures above 900°C or 1000°C, applied for extended periods, such as several hours. However, such temperatures must be avoided when the semiconductor layer is being migrated to a receiving substrate containing a pre-formed electronic device layer. Indeed, they degrade the performance, particularly the electrical performance, of the underlying electronic device. Therefore, this method is ineffective in reducing defects created by light ion implantation.

[0010] In the context of methods for moving semiconductor layers based on light ion implantation, it is therefore necessary to reduce the number of defects in the semiconductor layer by means other than annealing performed at high temperatures after fracturing. [Prior art documents] [Non-patent literature]

[0011] [Non-Patent Document 1] Hartmann et al., “A benchmark of 300mm RP-CVD chambers for the low temperature epitaxy of Si and SiGe,” ECS Transactions, 86(7)219-231 (2018) [Non-Patent Document 2] Hartmann et al., "Potentialities of disilane for the low temperature epitaxy of intrinsic and boron-doped SiGe", Thin Solid Films 557,19 (2014) [Non-Patent Document 3] Aubin et al., "Epitaxial growth of Si and SiGe at temperatures lower than 500℃ with disilane and germane", Thin Solid Films 602, 36 (2016) [Non-Patent Document 4] Hartmann et al., "A benchmark of germane and digermane for the low temperature growth of intrinsic and heavily in-situ boron-doped SiGe", ECS Transactions 75(8), 281 (2016) [Non-Patent Document 5] Aubin et al., "Very low temperature epitaxy of Ge and Ge rich SiGe alloys with Ge2H6 in a Reduced Pressure - Chemical Vapour Deposition tool", Journal of Crystal Growth 445, 65 (2016) [Non-Patent Document 6] Aubin and Hartmann, "GeSn growth kinetics in reduced pressure chemical vapor deposition from Ge2H6 and SnCl4", Journal of Crystal Growth 482, 30 (2018) [Non-Patent Document 7] Khazaka et al., "Growth and characterization of SiGeSn pseudomorphic layers on 200mm Ge virtual substrates" Semiconductor Science and Technology 33, 124011 (2018) [Summary of the Invention] [Problems to be Solved by the Invention]

[0012] The present invention provides a solution to the aforementioned problems by replacing a single implantation step with two implantation steps and by performing an epitaxial growth step of a semiconductor layer between the two implantation steps. Further, the implantation conditions for each of the implantation steps, particularly the ions to be implanted and the selected implantation dose, are adapted according to the epitaxy and the fragmentation annealing so as to cause fragmentation only during the fragmentation annealing.

Means for Solving the Problems

[0013] One aspect of the present invention thus relates to a method for transferring a semiconductor layer from a donor substrate to a recipient substrate, the method comprising the following successive steps, namely: - First implanting a first light ion into the donor substrate at a predetermined implantation depth so as to form an embedded brittle plane at the predetermined implantation depth; - Epitaxially growing the semiconductor layer to be transferred on the donor substrate; - Second implanting a second light ion into the donor substrate through the semiconductor layer to be transferred at the brittle plane; - Assembling by bonding the recipient substrate and the donor substrate covered with the semiconductor layer to be transferred, the semiconductor layer to be transferred being disposed between the recipient substrate and the donor substrate; - Fragmenting by annealing the donor substrate at the embedded brittle plane, called fragmentation annealing; and in the method: - During epitaxy, the first ion is selected and implanted at a first dose so that there is no fragmentation at the predetermined implantation depth; - During fragmentation annealing, the second ion is selected and implanted at a second dose so that fragmentation of the donor substrate occurs.

[0014] Therefore, when epitaxially growing the semiconductor layer to be moved, the implantation of the first light ion, i.e., an ion with an atomic weight of 11 or less, is performed at a dose such that the first ion does not cause fragmentation at a predetermined implantation depth.

[0015] Under these conditions, the thermal history used during the epitaxy step (defined by temperature and the duration of application of this temperature) does not result in the growth and aggregation of nanocavities in the embedded brittle plane, i.e., nanocavities formed at a predetermined injection depth by the first injection. Several reasons for this exist, including insufficient density of nanocavities and / or the amount of gas produced.

[0016] It should be noted that if a single implantation is performed before epitaxy, the ions to be implanted are necessarily selected so that fragmentation occurs at the implanted dose after the donor and acceptor substrates have been assembled. Therefore, the implanted dose becomes high enough that the heat treatment inherent in epitaxy causes fragmentation of the donor substrate. To avoid this, the epitaxy temperature needs to be limited to a maximum of 400°C. However, it is currently not possible to form semiconductor layers at such temperatures.

[0017] Therefore, the first injection allows epitaxy to be performed without fracturing the donor substrate or creating defects in the semiconductor layer.

[0018] Furthermore, a second implantation follows the epitaxial growth of the semiconductor layer. This second implantation is performed at substantially the same depth as the first implantation (taking epitaxial thickness into account) so that during fracturing annealing, fracturing of the donor substrate is achieved due to the accumulation of ions implanted during the first and second implantations. The implantation depth depends primarily on the ion implantation energy. Software (e.g., SRIM, "Stopping and Range of Ions in Matter") can be used to simulate the required implantation energy. Both implantations are performed substantially in the same plane. Differences of a few nanometers are possible, as the implanted ions can reach nanocavities in the brittle plane during fracturing annealing.

[0019] Therefore, the resulting semiconductor layer advantageously contains only ions implanted during a second implantation through it, in a much smaller quantity than the light ions conventionally required when a single implantation is performed.

[0020] Therefore, the number of defects in the semiconductor layer is reduced before migration and without requiring a high-temperature annealing step.

[0021] According to the first alternative embodiment, the method includes a further surface preparation step between the first implantation of light ions and the step of epitaxially growing the semiconductor layer to be moved, the further surface preparation step being the following consecutive substeps: - A step of deoxidizing the free surface of the donor substrate, - A step of annealing a donor substrate in a hydrogen-containing atmosphere at a temperature of 400°C or higher (and beneficially 500°C or higher) for a duration of 5 seconds to 10 minutes. Includes.

[0022] The higher the thermal history of this hydrogen-containing annealing, known as H2 annealing, the less residual oxygen atom contaminants there are at the interface between the substrate and the epitaxially grown semiconductor layer, resulting in better quality of the migrated semiconductor layer. The effect of H2 annealing conditions on the quality of the deposited film can be better understood by referring to Hartmann et al., "A benchmark of 300 mm RP-CVD chambers for the low temperature epitaxy of Si and SiGe," ECS Transactions, 86(7)219-231 (2018).

[0023] Therefore, the surface of the donor substrate is prepared for epitaxial growth of the migrated semiconductor layer. This contributes to the formation of a semiconductor layer with a reduced number of defects.

[0024] According to a second alternative embodiment, the method further steps, namely: - A step of depositing a sacrificial layer on the free surface of the donor substrate before the first injection, - After the first injection and before the step of epitaxially growing the semiconductor layer to be moved, the sacrificial layer is removed. Includes.

[0025] The combination of sacrificial layer deposition and removal aims to prepare the surface for epitaxial growth of the semiconductor layer to be moved.

[0026] According to the first evolution of this second alternative embodiment, the sacrificial layer is a dielectric layer.

[0027] The dielectric layer is, for example, a silicon oxide layer. The dielectric layer functions as a protective layer that shields the surface of the donor substrate from contaminants or impurities. Since epitaxy is performed on this surface, the migrated semiconductor layer is formed under better conditions, and its quality is improved.

[0028] According to a second evolution of this second alternative embodiment, the sacrificial layer comprises a stack of a first sublayer of a silicon / germanium alloy called a first etch-stopping layer and a second sublayer of a dielectric material disposed on the first sublayer, and the step of removing the sacrificial layer includes the step of selectively removing the second dielectric sublayer relative to the first etch-stopping layer, and then the step of removing the first etch-stopping layer.

[0029] Similar to the dielectric layer, the first etch-stopping layer protects the surface on which epitaxy is performed from impurities that could degrade the semiconductor layer.

[0030] The step of removing the first etch stop layer allows for improved surface preparation by obtaining a lower surface roughness.

[0031] According to one alternative embodiment of the second preceding evolution, the step of epitaxially growing the moving semiconductor layer is performed for at least 30 minutes after the step of removing the first stop layer.

[0032] Preferably, the step of epitaxially growing the semiconductor layer to be moved is performed for at least 10 minutes after the step of removing the first stop layer.

[0033] This short timeframe allows for the epitaxial growth of the moving semiconductor layer to be limited by the risk of contamination of the surface on which it is carried out.

[0034] According to another alternative embodiment of the second evolution, the steps of removing the first etch stop layer and epitaxially growing the semiconductor layer to be moved are performed in the same apparatus.

[0035] Therefore, the risk of surface contamination is reduced, and the method is simplified.

[0036] Beneficiently, the method includes a further step of annealing a donor substrate, performed in the same apparatus as the steps of removing the first etch stop layer and epitaxially growing the semiconductor layer to be moved, after the step of removing the first etch stop layer and before the step of epitaxially growing the semiconductor layer to be moved.

[0037] In epitaxy equipment, this step of annealing the donor substrate in situ completes the step of removing the first etch stop layer and improves the quality of the surface on which the migrated semiconductor layer is formed.

[0038] Beneficially, the further step of annealing the donor substrate is carried out under the following temperature, pressure, and duration conditions: 500°C, 2666 Pa (i.e., 20 Torr), and 2 minutes.

[0039] Under such a thermal history, the properties of the layer (or brittle plane) damaged by the first injection still conform to the layer migration after the second injection.

[0040] In addition to the features already described in the preceding paragraphs, a method according to one aspect of the present invention may have one or more complementary features from the following, which are compatible with all the aforementioned alternative embodiments and which are considered individually or in any technically possible combination:

[0041] The first light ion is a helium ion, a hydrogen ion, a boron ion, a mixture of helium and hydrogen ions, or a mixture of hydrogen and boron ions.

[0042] The second light ion is a helium ion, a hydrogen ion, or a mixture of helium and hydrogen ions.

[0043] It should be noted that using hydrogen ions for the second injection is particularly beneficial, even at higher injection doses, because hydrogen ions result in fewer defects than helium ions.

[0044] The semiconductor layer being moved is a layer of silicon (i.e., Si), germanium (i.e., Ge), silicon / germanium (i.e., SiGe) alloy, silicon / germanium / carbon (i.e., SiGeC) alloy, germanium / tin (i.e., GeSn) alloy, or silicon / germanium / tin (SiGeSn) alloy, or a stack of silicon sublayers and silicon / germanium (Si / SiGe) alloy sublayers.

[0045] Alternatively, the semiconductor layer to be moved comprises a first so-called active sublayer of silicon (i.e., Si), germanium (i.e., Ge), silicon / germanium (i.e., SiGe) alloy, silicon / germanium / carbon (SiGeC) alloy, germanium / tin (GeSn) alloy, or silicon / germanium / tin (SiGeSn) alloy, and a second so-called etch-stopping sublayer located below the first active sublayer, such as an etch-stopping sublayer of a silicon / germanium alloy, wherein the receiving substrate has a residual layer derived from the donor substrate after the crushing step, and the method then proceeds with the following sequential steps, namely: - A step of removing the residual layer originating from the donor substrate by selectively etching the residual layer with respect to the second etch-stopped sublayer, - Step to remove the second etch-stopped sublayer. Includes.

[0046] Thanks to the etch-stopping sublayer and the step of selectively etching the remaining layer after migration, chemical and mechanical polishing is not required to remove the remaining layer originating from the donor substrate. In addition, the surface roughness of the migrated layer is reduced, and the thickness of the migrated layer is controlled to achieve a thinner thickness. Thus, the quality of the migrated layer is further improved.

[0047] The present invention and its different applications will be better understood by reading the following description and examining the accompanying drawings.

[0048] The drawings were created using the methods shown and do not in any way limit the purpose of the present invention. [Brief explanation of the drawing]

[0049] [Figure 1A] This figure schematically illustrates the steps of the method of the present invention. [Figure 1B] This figure schematically illustrates the steps of the method of the present invention. [Figure 1C] This figure schematically illustrates the steps of the method of the present invention. [Figure 1D] This figure schematically illustrates the steps of the method of the present invention. [Figure 1E] This figure schematically illustrates the steps of the method of the present invention. [Figure 1F] This figure schematically illustrates the steps of the method of the present invention. [Figure 1G] This figure schematically illustrates the steps of the method of the present invention. [Figure 2] Figures 1A to 1G show several alternative embodiments of the epitaxy step of the movement method. [Figure 3] This figure shows the final multilayer structure obtained by the movement method from Figure 1A to Figure 1G. [Figure 4A] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4B] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4C] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4D] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4E] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4F] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4G] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4H] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4I] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4J] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 4K] Figures 1A to 1G schematically represent a first specific embodiment of the method that enables improvement of the quality of semiconductor layers. [Figure 5A] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5B] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5C] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5D] Figures 1A to 1G schematically represent a second specific embodiment of the method which further enables improvement of the quality of the semiconductor layer. [Figure 5E] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5F]Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5G] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5H] Figures 1A to 1G schematically represent a second specific embodiment of the method which further enables improvement of the quality of the semiconductor layer. [Figure 5I] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5J] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5K] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5L] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 5M] Figures 1A to 1G schematically represent a second specific embodiment of the method, which further enables improvement of the quality of the semiconductor layer. [Figure 6] This diagram schematically represents the first test substrate used to determine the first injection dose. [Figure 7] Figure 1B is a block diagram showing the sequence of steps for determining the first maximum dose in the first injection step. [Figure 8] This diagram schematically represents the second test substrate used to determine the second injection dose. [Figure 9] Figure 1D is a block diagram showing the sequence of steps for determining the second minimum dose for the second injection step. [Figure 10]This figure shows the density of defects created in a silicon substrate by implanting hydrogen ions and by implanting a mixture of helium and hydrogen ions. [Figure 11] This figure shows the etching rate of the SiGe layer depending on the etching partial pressure and the proportion of Ge in the SiGe alloy. [Figure 12] This is a block diagram showing the sequence of steps for performing a further surface preparation step, which lies between the second and third steps of the method shown in Figures 1A to 1G. [Modes for carrying out the invention]

[0050] Unless otherwise specified, the same element appearing in different diagrams will have a single symbol.

[0051] Figures 1A to 1G show schematic cross-sectional views of steps S110 to S160 of a method for transferring a semiconductor layer 40 from a donor substrate 10 to a receiving substrate 20, which enables obtaining a semiconductor layer 40 with reduced defects.

[0052] "Defects" refer to nanocavities, vacancies, interstitial defects, hydrogen complexes, bubbles, and delaminations that exist in or on the surface of a semiconductor layer and degrade the electrical performance of the semiconductor layer.

[0053] This transfer method, similar to the conventional Smart Cut™ method, includes implanting light ions, assembling two substrates by bonding, and performing crushing annealing.

[0054] The transport method of the present invention is noteworthy in that it includes two steps S120 and S140 (Figures 1B and 1D) for implanting light ions before the actual transport performed by the bonding step S150 and the crushing step S160 (Figures 1E and 1F), as well as an epitaxy step S130 (Figure 1C) interposed between these two implantation steps S120 and S140.

[0055] Referring to Figure 1A, the transfer method begins with a first step S110, which involves preparing a donor substrate 10. The donor substrate 10 represents, for example, a silicon support substrate, preferably a semiconductor substrate. Generally speaking, "substrate" represents a wafer or slice.

[0056] The donor substrate 10 has an upper surface 11 which is called a substantially planar free surface.

[0057] Referring to Figure 1B, the first step S110 is followed by step S120, in which the first light ions 3a are implanted into the donor substrate 10 through the free surface 11 to a predetermined depth 30 called the implantation depth. This first implantation S120 creates defects in the donor substrate 10 at a so-called brittle plane 300 located at the implantation depth 30. Since the created defects embrittle the donor substrate 10, the plane 300 is considered brittle.

[0058] The implantation depth 30 is, for example, between 100 nm and 1000 nm. The implantation depth 30 is measured from the free surface 11 to a point perpendicular to it. For example, the implantation of the first ion S120 is performed at an energy such that the maximum value of the profile of the implanted ion is at a depth of approximately 300 nm.

[0059] This injection energy depends on the selected ion species. If the first species to be injected is helium, the injection energy required to achieve an injection depth of 300 nm is approximately 35 keV.

[0060] Light ions are species defined by atomic weights of 11 or less. The first ion 3a is preferably selected from hydrogen (or H), helium (or He), boron (or B), a mixture of helium and hydrogen (or "He + H"), or a mixture of hydrogen and boron (or "H + B"). These species are known to actually create embedded brittle planes that can result in Smart Cut™ migration.

[0061] In the Smart Cut™ method, the step of implanting light ions is related to an annealing step, which is conventionally performed at an annealing temperature generally between 350°C and 600°C to break down the donor substrate and to move the semiconductor layer.

[0062] In the method according to the present invention, the step S120 in which the first ion 3a is implanted is followed not by a “conventional” annealing step to form the semiconductor layer 40, but by an epitaxy step S130 shown in Figure 1C.

[0063] Figure 2 illustrates several alternative embodiments for performing this epitaxy step S130.

[0064] At the end of step S130, the semiconductor layer 40 may be a semiconductor layer 410 which is preferably thin, i.e., has a thickness between 5 nm and 30 nm, and is formed from one of the following materials, i.e.: silicon (or Si), germanium (or Ge), silicon / germanium (or SiGe) alloy, silicon / germanium / carbon (or SiGeC) alloy, germanium / tin (or GeSn) alloy, or silicon / germanium / tin (SiGeSn) alloy.

[0065] The semiconductor layer 40 may alternatively be a stack of semiconductor sublayers, for example, a stack of a silicon sublayer and a silicon / germanium (Si / SiGe) alloy sublayer, or preferably a stack of a first so-called active sublayer 430 and a second so-called etch-stopping sublayer 420, for example, a silicon / germanium (SiGe) alloy etch-stopping sublayer. The etch-stopping sublayer 420 is located below the active sublayer 430.

[0066] Next, the active sublayer 430 is similar to the semiconductor layer 410, that is, the active sublayer 430 is formed from one of the following materials: silicon (or Si), silicon / germanium (or SiGe) alloy, silicon / germanium / carbon (SiGeC) alloy, germanium / tin (or GeSn) alloy, or silicon / germanium / tin (SiGeSn) alloy, with a thickness between 2 nm and 30 nm. The etch-stopping sublayer 420 is preferably a SiGe alloy with a germanium concentration between 20% and 50%. The etch-stopping sublayer 420 may further have a thickness between 5 nm and 150 nm.

[0067] More generally, a stack of semiconductor sublayers may comprise several alternately arranged active and etch-stopping sublayers (not shown in Figure 2). The thicknesses of the active and etch-stopping sublayers may vary according to their positions in the stack, as well as the Si / Ge ratio forming the etch-stopping sublayers.

[0068] This epitaxy step S130 is performed in an epitaxy apparatus and includes growing a crystal corresponding to the desired crystal for the semiconductor single crystal layer 40 from the free surface 11 of a donor substrate 10 implanted with first ions in an oriented manner. The epitaxy step may include forming a so-called nucleated crystal sublayer (not shown) on the free surface 11. The semiconductor layer 40 is then epitaxially grown after this sublayer. The semiconductor layer 40 can be formed by chemical vapor deposition (CVD) techniques, such as reduced-pressure chemical vapor deposition (RP-CVD) or plasma-enhanced chemical vapor deposition (PECVD). Techniques such as molecular beam epitaxy (MBE) may also be used. In RP-CVD, operating points described in Hartmann et al., "Potentialities of disilane for the low temperature epitaxy of intrinsic and boron-doped SiGe," Thin Solid Films 557,19 (2014), Aubin et al., "Epitaxial growth of Si and SiGe at temperatures lower than 500℃ with disilane and germane," Thin Solid Films 602,36 (2016), or Hartmann et al., "A benchmark of germane and digermane for the low temperature growth of intrinsic and heavily in-situ boron-doped SiGe," ECS Transactions 75(8),281 (2016) may be used to deposit Si or SiGe layers at low temperatures (below 500℃).

[0069] To deposit a pure Ge layer at temperatures below 500°C, epitaxy conditions similar to those described by Aubin et al., "Very low temperature epitaxy of Ge and Ge-rich SiGe alloys with Ge2H6in a Reduced Pressure - Chemical Vapour Deposition tool," Journal of Crystal Growth 445,65 (2016), can be used.

[0070] Finally, growth conditions for epitaxial growth of GeSn or SiGeSn layers at temperatures below 350°C can be found in Aubin and Hartmann, "GeSn growth kinetics in reduced pressure chemical vapor deposition from Ge2H6 and SnCl4," Journal of Crystal Growth 482,30 (2018), and Khazaka et al., "Growth and characterization of SiGeSn pseudomorphic layers on 200mm Ge virtual substrates," Semiconductor Science and Technology 33,124011 (2018).

[0071] These techniques allow for an epitaxy duration that can range from 1 to 120 minutes. ep Duration d ep The epitaxy temperature T can vary between 300°C and 600°C over time. ep Temperature T ep This involves applying the epitaxy temperature T. ep For example, 500°C and the epitaxy duration d ep It is 10 minutes.

[0072] It should be noted that the temperature involved in this epitaxy step S130 can produce the same effect as fragmentation annealing on the injected first ions 3a. For this reason, the first injection (and in particular the injected first ions 3a and the selected first injection dose) is determined according to the temperature and duration conditions of the epitaxy step S130 in order to avoid (and not obtain) fragmentation of the donor substrate 10 during the epitaxy step S130. In fact, in the opposite case, when there is no particular mechanical stress (or stiffener) on the donor substrate 10 (which has not yet been assembled to the receiving substrate 20), the gas-supplied nanocavities spread freely in both the lateral and longitudinal directions, which results in the appearance of bubbles, blistering, and delamination on the surface and in the semiconductor layer 40 that is formed, and thus this becomes a defect.

[0073] In contrast, light ions that do not generate bubbles due to the thermal history of epitaxy S130 can be selected as the first ion 3a. This is the case, for example, when boron or helium is implanted. The heavier the implanted atom (He, B), the more beneficial it is to implant the atom before epitaxy S130 in order to limit damage to the moving semiconductor layer 40.

[0074] Preferably, the first light ion 3a is a helium ion.

[0075] If the first injection S120 is performed using hydrogen, a first dose D1 is used that is less than the first threshold S1, which, if exceeded, causes the first light ions 3a to fracture to a predetermined injection depth 30 during epitaxy S130.

[0076] The first threshold S1 can be experimentally predetermined using the first test substrate 6, as shown in Figure 6. The first test substrate 6 includes several test zones, for example, four test zones Q11, Q12, Q13, and Q14. Each test zone is subjected to implantation of the first ion at a test dose and the duration of epitaxy d epThe temperature T of the epitaxy S130 over time ep is subjected to heat treatment.

[0077] Next, the first threshold value S1 is determined by visually inspecting and mechanically searching for the presence of surface peeling indicating that cracking and thus layer movement occur if there is an interface under stress (e.g., the interface between the donor substrate 10 and the acceptor substrate 20 when they are assembled).

[0078] Preferably, the first threshold value S1 is determined by following the order from step S710 to step S730 in FIG. 7.

[0079] These steps are as follows, namely: - Step S710 of implanting the first light ions 3a into the first test zone Q11 of the test substrate 6 at the implant energy of the first light ions 3a and at a low first test dose DT11, e.g., 1 e 16 / cm 2 - Step S720 of heat-treating the test substrate 6 at the epitaxy temperature T over an epitaxy duration d ep ep - Step S730 of inspecting the free surface 66 of the test substrate 6, preferably by visually inspecting an image of the test zone obtained by optical microscopy - If the free surface 66 is deteriorated (output “D” of step S730), the first threshold value S1 is equal to the first test dose DT1 (1 - If the free surface is not deteriorated (output “ND” of step S730), the first test dose DT12 is increased (DT12 > DT11), and the implant step S710, the heat treatment step S720, and the inspection step S730 are repeated in the next test zone Q12 by applying the increased test dose D12 to the implant step S710.

[0080] ​​​​"Degraded free surface" refers to the presence of blistering or delamination on the free surface 66. This damage corresponds to a dark spot in the optical microscopy image and is easily detected (see spot P in image IMG1 in Figure 7).

[0081] "An undegraded free surface 66" means the absence of blistering or delamination on the free surface 66. Dark spots are not detected in images obtained by optical microscopy (see IMG2 in Figure 7).

[0082] For this first injection S120, it is also possible to combine several ions 3a, in particular helium and / or boron with hydrogen. The more species injected during this first injection, the fewer species will be needed during the second injection, and therefore the less damage the epitaxial growth layer will suffer.

[0083] Following the aforementioned epitaxy step S130, a second step called step S140 is performed, in which light ions 3b are implanted. This step S140 is shown in Figure 1D, and the crushing annealing temperature T RF And, the duration of the crushing annealing d RF This relates to the subsequent step S160 shown in Figure 1E, which is included in the crushing and annealing step S150 that is carried out over a certain period.

[0084] The second ion 3b is a light species, such as helium (He), hydrogen (H), or a mixture of helium and hydrogen ("H+He"). The second ion 3b may be the same as the first ion 3a.

[0085] Preferably, the second light ion 3b contains or is a hydrogen ion.

[0086] The depth of this second implantation S140 is the implantation depth 30 determined during the first implantation S120 of the first ion 3a, with the thickness of the epitaxially grown semiconductor layer 40 added to it. The energy at which the second implantation S140 is performed is set such that the maximum value of the implantation profile overlaps with that of the first implantation S120.

[0087] Referring to Figure 1D, the second implantation S140 is performed on the donor substrate 10 through the moving semiconductor layer 40 so that the second ion 3b reaches the embedded brittle plane 300.

[0088] Therefore, the brittle plane 300 is a plane in which the density of nanocavities and the overall content of light ions, i.e., the cumulative content of the first light ion 3a and the second light ion 3b, can trigger the formation of a gaseous composite that results in the fracture of the donor substrate 10 during the fracture annealing step S160.

[0089] In response to this, a second injection S140 is performed using ions 3b injected at one or more doses during the fracture annealing S160, such that the accumulation of the first ions 3a and the second ions 3b causes fracture of the donor substrate 10 in the embedded brittle plane 300.

[0090] If the second injection S140 contains hydrogen ions injected at a second dose D2, this dose is preferably determined experimentally in a similar manner to determining the first threshold S1, based on the presence or absence of delamination on the surface of the second test substrate, such as the second test substrate 8 shown in Figure 8.

[0091] In a similar manner to that of the first test board 6, the second test board 8 can be divided into several test zones, for example, four zones Q21, Q22, Q23, and Q24.

[0092] Steps S910 through S950 (see Figure 9) are executed. They include the following steps: - Step S910 implants the first ion 3a into the first zone Q21 with the implantation energy of the first ion. For example, helium ions are implanted with an energy of 35 keV (to create a brittle plane at a depth of 300 nm relative to the surface), and 2 e 16 / cm 2 It is injected at dose D1. - For example, to create a 30nm epitaxially grown layer, the epitaxy temperature T ep and epitaxy duration d ep Step S920 involves epitaxially growing the second test substrate 8 over time. - Step S930 involves implanting a second ion 3b with an implantation energy such that these ions reach the embedded brittle plane. If the implanted ion is hydrogen, it is implanted with an energy of 24 keV to reach the brittle plane located 330 nm from the surface. These ions are, for example, 1E16 / cm 2 It is injected with a second, lower test dose, DT21, which is equal to [the previous dose]. - Crushing annealing temperature T RF And, the duration of the crushing annealing d RF Step S940 involves heat-treating the second test substrate 8 over time. - Step S950 to inspect the quality of the free surface 88 of the second test substrate 8. - If the surface quality is degraded (output "D" in inspection step S950), the second dose D2 is greater than or equal to the second test dose DT21. - If the surface quality is not degraded (output "ND" in inspection step S950), the test dose DT21 is increased, and steps S910 through S930 are repeated in another test zone Q22, with step S930, injecting the second ion 3b, being performed with the increased second test dose DT22.

[0093] By applying these steps, for example, the crushing conditions given in Table 1 or Table 2 can be obtained. "Crushing conditions" refers to the set of parameters associated with the implantation of the first ion S120, epitaxy S130, implantation of the second ion S140, and crushing annealing S160.

[0094] [Table 1]

[0095] [Table 2]

[0096] Higher epitaxy temperature T ep Using 500°C (see Table 2) compared to 400°C (see Table 1) results in a larger first dose D1 (1.3 e 16 / cm 2 Compared to 2 e 16 / cm 2 ), and a larger second dose D2(9 e 15 / cm 2 Compared to 2 e 16 / cm 2 Please note that this may result in...

[0097] In this case, the total dose (He 36keV 2 e 16 / cm 2 , and H 24keV 2 e 16 / cm 2 It should be further noted that this dose is greater than the dose applied by standard methods in the case of a single light ion implantation. However, fewer defects are created, especially since helium ions do not pass through the semiconductor layer 40 being implanted. As shown in Figure 10, even for hydrogen ion implantation doses greater than twice the helium ion implantation dose, the density of atoms moved when hydrogen ions are implanted is actually lower compared to helium ions.

[0098] Referring to Figure 1E, the method then includes step S150 of assembling by joining a receiving substrate 20 and a donor substrate 10 covered with a movable semiconductor layer 40. The donor substrate 10 is inverted beforehand, and the movable semiconductor layer 40 is positioned between the receiving substrate 20 and the donor substrate 10 in the formed assembly 1.

[0099] The receiving substrate 20 is preferably a substrate comprising one or more layers of electronic devices 210.

[0100] This assembly step S150 is carried out using a conventional bonding method, preferably a molecular bonding assembly method also known as direct bonding.

[0101] Following the assembly step S150, a step S160, also called the crushing annealing step S160, is performed in which the donor substrate 10 is crushed by annealing on the embedded brittle plane 300. The crushing annealing temperature is in the range of 400°C to 600°C, preferably 500°C or lower. The duration of the crushing annealing is preferably between 30 minutes and 180 minutes.

[0102] At the end of step S160, which involves annealing and fragmentation, portion 10b of the donor substrate 10 is separated from the receiving substrate 20 on which the semiconductor layer to be moved 40 is placed, and from the remaining layer 10a originating from the donor substrate 10. Thus, the movement of the semiconductor layer 40 is carried out.

[0103] Referring to Figure 1G, the crushing step S160 may be followed by an optional step S170 in which the remaining layer 10a originating from the donor substrate 10 is removed until the semiconductor layer 40 is reached. At the end of this step S170, in which the remaining layer 10a is removed, the final semiconductor structure 3 shown in Figure 3 is obtained.

[0104] Figures 4A to 4K schematically represent a first specific embodiment of the movement method that has already been described in general terms.

[0105] Figures 5A to 5M schematically illustrate a second specific embodiment of the movement method.

[0106] Step S110 for preparing the donor substrate 10, step S120 for the first injection, and step S140 for the second injection, as shown in Figures 4A and 5A, 4C and 5D, and 4G and 5I, have each been previously described in relation to, for example, Figures 1A, 1B, and 1D, respectively.

[0107] In common to these two specific embodiments, the epitaxy step S130 includes two substeps S130A and S130B for forming a semiconductor layer 40 comprising an active sublayer 430 and an etch-stopping sublayer 420, as shown in Figure 2, and two further steps S170 (see Figures 4J and 5L) and S180 (see Figures 4K and 5M) are performed after the assembly step S150 (see Figures 4H and 5J) and the crushing step S160 (see Figures 4I and 5K), and for the purpose of releasing the active sublayer 430.

[0108] Referring to Figure 4E (first embodiment) and Figure 5G (second embodiment), step S130A includes epitaxially growing a so-called etch-stopping sublayer 420 from the free surface 11 of the donor substrate 10. The epitaxy temperature is, for example, 500°C.

[0109] Referring to Figure 4F (first embodiment) and Figure 5H (second embodiment), step S130B includes epitaxial growth of a so-called active sublayer 430 from the etch-stop sublayer 420. This epitaxy S130B is preferably carried out at the same epitaxy temperature as the epitaxy S130A of the etch-stop sublayer, 500°C as specified herein.

[0110] Referring to Figure 4J (first embodiment) and Figure 5L (second embodiment), the receiving substrate 20 has a residual layer 10a derived from the donor substrate 10 on the surface of the etch-stopping sublayer 420 after the crushing step S160. Next, step S170 is a step S170 in which the residual layer 10a derived from the donor substrate 10 is removed by selectively etching the residual layer 10a with respect to the second etch-stopping sublayer 420. This selective etching is preferably wet etching.

[0111] Step S180, following step S170, is the step of removing the etch-stop sublayer 420 from the active sublayer 430 by selective (preferably wet) etching.

[0112] At the end of step S180, which removes the etch-stopped sublayer 430, the active sublayer 430 is released, beneficially having a smooth surface and reduced thickness.

[0113] More commonly in the first and second embodiments, the transfer method further includes one or more steps aimed at preparing a free surface 11 of the donor substrate 10 for the epitaxy S130 of the semiconductor layer 40.

[0114] In the first embodiment, the surface preparation for epitaxy S130 includes further steps S115 and S125, shown in Figures 4B and 4D, respectively.

[0115] In the second embodiment, the surface preparation for epitaxy S130 includes further steps S115A, S115B, S125A, and S125B, as shown in Figures 5B, 5C, 5E, and 5F, respectively.

[0116] The surface preparation performed in the first embodiment is described below.

[0117] Step S115 (Figure 4B) is performed before S120, in which the first ions 3a are implanted, and includes forming a sacrificial layer 50 on the free surface 11 of the donor substrate 10. Preferably, the sacrificial layer 50 is a dielectric layer 500, for example, a silicon oxide (i.e., SiO2) layer.

[0118] The dielectric layer 500 is obtained from the free surface 11 of the donor substrate 10 by oxide growth or by dielectric deposition.

[0119] Therefore, at the end of step S115, the donor substrate 10 includes a so-called dielectric sacrificial layer that beneficially protects the free surface from defects and impurities (e.g., carbon or oxygen atoms). In step S120, in which the first ions 3a are implanted, the first ions 3a are implanted through the sacrificial dielectric layers 50, 520.

[0120] Step S125 (Figure 4D) is performed after S120, in which the first ions are implanted, and before step S130, in which the semiconductor layer 40 to be moved is epitaxially grown. Step S125 includes removing the sacrificial layers 50, 510 formed in step S115.

[0121] This removal is performed, for example, by wet etching using a hydrofluoric acid-based solution.

[0122] At the end of step S125, the free surface 11 of the donor substrate 10 is beneficially clean, i.e., free from impurities and contaminants.

[0123] In the second embodiment (see Figure 4C), the sacrificial layer 50 comprises a stack of a first sublayer 510 called the first etch-stopping layer 510 and a second dielectric sublayer 520 placed on the first sublayer 510.

[0124] Therefore, step S115A is a step of forming the first etch-stopping layer 510, and step S115B is a step of forming the second dielectric sublayer 520.

[0125] The dielectric material is preferably a silicon oxide.

[0126] The first etch-stopping layer 510 is, for example, a layer of silicon / germanium (SiGe) alloy having the following ratios: 25% (Si) and 50% (Ge).

[0127] In step S115A, the formation of the first etch-stopping layer 510 is preferably carried out by epitaxial growth from the free surface 11 of the donor substrate 10. Thus, the thickness of the obtained first etch-stopping layer 510 is between 10 nm and 50 nm. The epitaxy of the first etch-stopping layer 510 may further follow a surface preparation step carried out by the methods of the Existing Art, preferably at a temperature higher than 650°C, and more preferably at a temperature higher than 850°C.

[0128] In step S115B, to obtain a second dielectric sublayer 520 having a thickness between 5 nm and 50 nm, the second dielectric sublayer 520 is obtained by oxide growth from the surface of the first etch-stopping layer 510 or by deposition of a dielectric on the surface of the first etch-stopping layer 510.

[0129] The removal step S125A (Figure 5E) is a step S125A in which the second dielectric sublayer 520 is removed.

[0130] Removing the second dielectric sublayer 520 is performed, for example, using wet etching based on a solution containing hydrogen fluoride.

[0131] Step S125B (Figure 5F), which removes the first etch stop layer 510, can be performed outside the epitaxy instrument or within the epitaxy instrument (this is called in situ removal).

[0132] In the first case (outside the epitaxy apparatus), step S125B includes performing selective wet etching on SiGe using a wet etching based on a solution containing, for example, acetic acid, hydrogen fluoride, and hydrogen peroxide (i.e., H2O2), and then performing an epitaxy step S130, preferably with a time interval between 10 and 30 minutes.

[0133] In other words, the time interval between step S125B, in which the first etch stop layer 510 is removed by wet etching, and step S130, in which the semiconductor layer 40 to be moved is epitaxially grown, is therefore preferably between 10 and 30 minutes.

[0134] In the second case, step S125B, which removes the first etch stop layer 510, is performed in an epitaxy device. In other words, step S125B, which removes the first etch stop layer 510, and the epitaxy step S130 are performed in the same epitaxy device.

[0135] Removal of S125B is then carried out by wet etching using a solution containing hydrochloric acid (i.e., HCl) at a temperature of preferably less than 500°C. Beneficially, the etching is selective to the silicon of the donor substrate 10. Referring to Figure 11, partial pressures of HCl from 23998 Pa to 47996 Pa (i.e., 180 Torr or 360 Torr) can be used. At a temperature of 500°C, the etching rate (ER) shown on the y axis is set such that the etching of SiGe is selective to the silicon of the donor substrate 10. Beneficially, the etching selectivity, i.e., the ratio between the etching rate of the SiGe layer and the etching rate of Si, is about 13 for a Ge concentration of 20% in the etch-stop layer 510, about 50 for a Ge concentration of 30%, and about 186 for a Ge concentration of 40%.

[0136] Next, the removal S125B is followed by the aforementioned epitaxy step S130, which may further be followed by a step S125B to remove the first stop layer 510, and a further step S132 (not shown) to anneal the donor substrate 10 after epitaxy, which is performed in the same epitaxy apparatus as step S130 to epitaxially grow the semiconductor layer 40 to be moved.

[0137] The first and second embodiments represent two methods for preparing the free surface 11 of the donor substrate 10 for epitaxy S130.

[0138] A third method for preparing the free surface 11 is shown in Figure 12 along with step S122. Step S122 is a series of substeps between the implantation of the first light ions S120 and step S130 for epitaxial growth of the semiconductor layer 40 to be moved, namely: - Step S122A: Deoxidizing the free surface 11 of the donor substrate 10. - Typically, step S122B involves annealing the donor substrate 10 in a hydrogen-containing atmosphere at a temperature higher than 400°C for a duration of 5 seconds to 10 minutes. This includes performing the following actions.

[0139] The deoxidation treatment step S122A is carried out chemically, for example, under hydrogen fluoride (i.e., HF), followed by the SC1(TM) method (i.e., surface exposure to the chemical solution NH4OH:H2O2:H2O, resulting in the formation of silicon oxide), and then the SICONI(TM) method (i.e., (i)NH (3) This is followed by surface cleaning by converting the silicon oxide formed as a result of the SC1(TM) method into an oxide salt using an NF3-based remote plasma, and then sublimating this salt under neutral gas at a temperature below 200°C. The temperature used is preferably 500°C or less.

[0140] The annealing step S122B following the deoxidation step S122A is preferably performed in an epitaxy apparatus. The annealing temperature may be less than 500°C. To obtain optimal surface preparation, the temperature may be higher, for example, higher than 500°C, 650°C, or even higher than 800°C. In this case, the annealing duration is preferably as short as possible, in the range of 5 seconds to 10 minutes.

[0141] At the end of this further step S122, the free surface 11 of the donor substrate 10 has, beneficially, more reduced contaminants (carbon, fluorine, oxygen, etc.) prior to epitaxy S130.

[0142] The method may further include a further step S135 (not shown) after epitaxy S130 and before implantation of the second ion 3b S140, in which an oxide layer is formed by epitaxial growth from the semiconductor layer 40 formed at the end of step S130 (or S130B). This step S135 is preferably performed under an oxidizing plasma at a temperature of less than 500°C or less than 400°C. Step S135 may also be performed by plasma-assisted chemical deposition.

[0143] By using two injection steps (first injection S120 and second injection S140) performed with a first ion 3a and a first dose, and a second ion 3b and a second dose, respectively, and by interposing epitaxy of the semiconductor layer 40 between these two injection steps, the transfer method makes it possible to limit the adverse effects of the injection, i.e., limit the damage or defects caused by the species injected along their paths in the donor substrate 10. Therefore, the method makes it possible to obtain a semiconductor layer 40 with reduced defects before the transfer steps S150-S160.

[0144] Several explanations exist for this, namely: firstly, during epitaxy, the first ion 3a is directed toward the free surface 11 and the first dose is adapted so as not to result in the growth of nanocavities into the formed semiconductor layer 40; and secondly, the semiconductor layer 40 has only the second ion 3b passing through it at a second, lower dose compared to the dose corresponding to a single injection.

[0145] Crushing and annealing temperatures below 500°C can be used as described above, adapting the transport method to 3D monolithic integration.

Claims

1. A method for transferring a semiconductor layer (40) from a donor substrate (10) to a receiving substrate (20), wherein the method comprises the following series of steps, namely, Step (S120) is to first implant first light ions (3a) into a donor substrate (10) at a predetermined implantation depth (30) so as to form an embedded brittle plane (300) at a predetermined implantation depth (30), Step (S130) involves epitaxially growing the movable semiconductor layer (40) onto the donor substrate (10), Step (S140) of second implanting light ions (3b) into a donor substrate (10) through a semiconductor layer (40) that moves in a brittle plane (300), Step (S150) of assembling by joining a receiving substrate (20) and a donor substrate (10) covered with a movable semiconductor layer (40), wherein the movable semiconductor layer (40) is placed between the receiving substrate (20) and the donor substrate (10), Step (S160) is to fracture the donor substrate (10) by annealing it on an embedded brittle plane (300), which is called crushing annealing (S160). Including, in the method, In the epitaxial growth step (S130), in order to prevent fragmentation at a predetermined injection depth (30), a first light ion (3a) is selected and injected at a first dose (D1) in the first injection step (S120). A method comprising a second injection step (S140) in which a second light ion (3b) is selected and injected at a second dose (D2) so that fragmentation of the donor substrate (10) occurs during fragmentation annealing (S160).

2. The first light ion (3a) is a helium ion, a hydrogen ion, a boron ion, a mixture of helium ions and hydrogen ions, or a mixture of hydrogen ions and boron ions. The method according to claim 1, wherein the second light ion (3b) is a helium ion, a hydrogen ion, or a mixture of a helium ion and a hydrogen ion.

3. Between the first injection step (S120) and the step of epitaxially growing the semiconductor layer to be moved (40) (S130), the following consecutive substeps are included, namely, Step (S122A): Deoxidizing the free surface (11) of the donor substrate (10), Step (S122B): Annealing the donor substrate (10) in a hydrogen-containing atmosphere at a temperature of 400°C or higher for a duration of 5 seconds to 10 minutes. The method according to claim 1 or 2, further comprising a further surface preparation step (S122) including the following.

4. A further step, namely, Firstly, before the injection step (S120), a sacrificial layer (50) is deposited on the free surface (11) of the donor substrate (10) in a step (S115). After the first injection step (S120) and before the step of epitaxially growing the semiconductor layer (40) to be moved (S130), the sacrificial layer (50) is removed (S125). The method according to claim 1 or 2, including the method according to claim 1 or 2.

5. The method according to claim 4, wherein the sacrificial layer (50) is a dielectric layer (500).

6. The method according to claim 4, wherein the sacrificial layer (50) comprises a stack of a first sublayer (510) of a silicon / germanium alloy called a first etch-stopping layer (510) and a second sublayer (520) of a dielectric material disposed on the first sublayer (510), and the step of removing the sacrificial layer (50) (S125) includes the step of removing the second sublayer (520) of the dielectric material (S125A) and then the step of removing the first etch-stopping layer (510) (S125B).

7. The method according to claim 6, wherein the step of epitaxially growing the moving semiconductor layer (40) (S130) is performed for less than 30 minutes after the step of removing the first etch stop layer (S125B).

8. The method according to claim 6, wherein the steps of removing a first etch stop layer (510) (S125B) and epitaxially growing a moving semiconductor layer (40) (S130) are performed in the same apparatus.

9. The method according to claim 8, further comprising the step of removing the first etch stop layer (510) (S1225B) and the step of epitaxially growing the semiconductor layer to be moved (40), followed by the step of removing the first etch stop layer (S125B) and before the step of epitaxially growing the semiconductor layer to be moved (40) (S130), the step of annealing the donor substrate (10).

10. The method according to claim 9, wherein the further step (S132) of annealing the donor substrate (10) is performed under the following temperature, pressure, and duration conditions, namely 500°C, 2666 Pa, and 2 minutes.

11. The method according to claim 1, wherein the semiconductor layer to be moved (40) is a layer (410) of silicon (i.e., Si), germanium (i.e., Ge), silicon / germanium (i.e., SiGe) alloy, silicon / germanium / carbon (i.e., SiGeC) alloy, germanium / tin (i.e., GeSn) alloy, or silicon / germanium / tin (SiGeSn) alloy, or a stack of a silicon sublayer and a silicon / germanium (Si / SiGe) alloy sublayer.

12. The moving semiconductor layer (40) comprises a first active sublayer (430) of silicon (i.e., Si), germanium (i.e., Ge), silicon / germanium (i.e., SiGe) alloy, silicon / germanium / carbon (i.e., SiGeC) alloy, germanium / tin (i.e., GeSn) alloy, or silicon / germanium / tin (SiGeSn) alloy, and a second etch-stopping sublayer (420) disposed below the first active sublayer (430) and between the first active sublayer and the donor substrate (10), wherein the receiving substrate (20) has a residual layer (10a) derived from the donor substrate (10) after the crushing step (S160), and the method comprises the following consecutive steps, i.e., Step (S170) to remove the remaining layer (10a) originating from the donor substrate (10) by selectively etching the remaining layer (10a) with respect to the second etch-stopping sublayer (420) with a selectivity greater than 10. Step (S180) to remove the second etch-stopped sublayer (420) The method according to claim 1, including the method described in claim 1.

13. The method according to claim 12, wherein the second etch-stopping sublayer is an etch-stopping sublayer of a silicon / germanium alloy.

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