Semiconductor equipment

Abstract

To provide a semiconductor device in which switching breakdown is suppressed.SOLUTION: A semiconductor device includes a gate trench part 40 and a dummy trench part 30 adjacent to the gate trench part. The semiconductor device includes a drift region of a first conductivity type provided on a semiconductor substrate 10, a base region 14 of a second conductivity type provided over the drift region, an emitter region 12 of the first conductivity type provided over the base region and having higher doping concentration than the drift region, and a contact region 15 of the second conductivity type provided over the base region and having higher doping concentration than the base region. In a mesa part 71 between the gate trench part and the dummy trench part, the contact region is provided below a lower end of the emitter region on the dummy trench part side.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 describes "improving characteristics such as saturation current in a semiconductor device". [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2018-195798 [Patent Document 2] International Publication No. 2018 / 052098 Pamphlet

Summary of the Invention

Problems to be Solved by the Invention

[0003] To provide a semiconductor device that suppresses switching breakdown.

Means for Solving the Problems

[0004] In a first aspect of the present invention, there is provided a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The semiconductor device may include a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type provided above the drift region, an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region, and a contact region of a second conductivity type provided above the base region and having a higher doping concentration than the base region. In a mesa portion between the gate trench portion and the first trench portion, the contact region may be provided below the lower end of the emitter region.

[0005] The contact region may be in contact with the first trench portion.

[0006] In the mesa portion, the contact region may be spaced apart from the gate trench portion.

[0007] The contact region may be spaced at least 0.6 μm apart from the gate trench portion in the trench arrangement direction.

[0008] The contact area may be provided on the side wall of the first trench portion on the front surface of the semiconductor substrate.

[0009] The semiconductor device may include an interlayer insulating film provided above the semiconductor substrate. The emitter region may be electrically connected to the emitter electrode via a contact hole provided through the interlayer insulating film.

[0010] The emitter region may extend in the trench arrangement direction from the gate trench portion, across the contact hole, to the first trench portion.

[0011] The semiconductor device may include a first-conductivity type accumulation region between the drift region and the base region, where the doping concentration is higher than that of the drift region.

[0012] The semiconductor device may include a plurality of gate trenches and a plurality of first trenches. The ratio of the number of gate trenches to the number of first trenches may be 1:1.

[0013] The semiconductor device may include a plurality of gate trenches and a plurality of first trenches. The ratio of the number of gate trenches to the number of first trenches may be 1:2.

[0014] The emitter region may extend from the gate trench to the dummy trench in the trench arrangement direction. The emitter region may terminate without reaching the first trench.

[0015] The emitter region may extend from the gate trench to the first trench in the trench arrangement direction.

[0016] On the front surface of the semiconductor device, the contact region and the emitter region may be arranged alternately in contact with the gate trench portion in the direction of trench extension.

[0017] The first trench portion may be set to the emitter potential.

[0018] The first trench portion may be set to the gate potential.

[0019] The first trench portion may be a dummy trench. The emitter region may be in contact with the gate trench portion and separated from the first trench portion in the mesa portion. The contact region may be provided below the lower end on the first trench portion side of the emitter region in the mesa portion.

[0020] The first trench portion may be set to the gate potential and include a dummy gate trench portion that does not contact the emitter region.

[0021] The first trench portion may include a dummy trench portion set to the emitter potential.

[0022] The emitter region may have a first emitter region that is in contact with the gate trench portion and separated from the first trench portion in the mesa portion. The contact region may be provided below the lower end on the first trench portion side of the first emitter region in the mesa portion.

[0023] The emitter region may further have a second emitter region that is in contact with the first trench portion and separated from the gate trench portion in the mesa portion. The contact region may also be provided below the lower end on the gate trench portion side of the second emitter region in the mesa portion.

[0024] In the trench extension direction of the gate trench portion, the first emitter region and the second emitter region may be provided alternately. [[ID=B]]

[0025] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0026] [Figure 1A] A top view of the semiconductor device 100 is shown. [Figure 1B] This is an example of a cross-sectional view along the line a-a' in Figure 1A. [Figure 1C] This is an example of a cross-sectional view between b-b' in Figure 1A. [Figure 2] An example of an enlarged cross-sectional view of the mesa section 71 is shown. [Figure 3] An example of a top view of a semiconductor device 100 having an unopened contact hole 54 is shown. [Figure 4A] An example of simulation results for the static characteristics of semiconductor device 100 is shown. [Figure 4B] An example of the simulation results for the ON characteristics of semiconductor device 100 is shown. [Figure 4C] An example of the simulation results for the off-state characteristics of the semiconductor device 100 is shown. [Figure 5A] An example of a top view of the semiconductor device 100 is shown. [Figure 5B] Figure 5A is an example of a cross-sectional view along the line c-c'. [Figure 6A] An example of a top view of the semiconductor device 100 is shown. [Figure 6B] This is an example of a d-d' cross-sectional view in Figure 6A. [Figure 7A] An example of a modified semiconductor device 100 is shown as a top view. [Figure 7B] This is an example of a cross-sectional view of e-e' in Figure 7A. [Figure 8A] An example of a top view of the semiconductor device 100 is shown. [Figure 8B] This is an example of a cross-sectional view of the f-f' section in Figure 8A. [Figure 9A] An example of a top view of the semiconductor device 100 is shown. [Figure 9B] This is an example of a g-g' cross-sectional view in Figure 9A. [Figure 10A] An example of a top view of the semiconductor device 100 is shown. [Figure 10B] This is an example of an h-h' cross-sectional view in Figure 10A. [Figure 10C] This is another example of the h-h' cross-sectional view in Figure 10A. [Figure 11A] An example of a top view of the semiconductor device 100 is shown. [Figure 11B] This is an example of a cross-sectional view of i-i' in Figure 11A. [Figure 12A] An example of a top view of the semiconductor device 100 is shown. [Figure 12B] This is an example of a cross-sectional view along the line j-j' in Figure 12A. [Figure 13A] An example of a top view of the semiconductor device 100 is shown. [Figure 13B] This is an example of a k-k' cross-sectional view in Figure 13A. [Modes for carrying out the invention]

[0027] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0028] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as the "top," and the other side as the "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the front surface, and the other surface as the back surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction of attachment to the substrate, etc., when mounting a semiconductor device.

[0029] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. In this specification, the plane parallel to the front surface of the semiconductor substrate is defined as the XY plane, and the Z axis is defined as the direction that forms a right-handed system with the X and Y axes and is parallel to the depth direction of the semiconductor substrate.

[0030] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will have opposite polarities.

[0031] In this specification, layers or regions prefixed with N or P indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to N and P indicate higher and lower doping concentrations, respectively, compared to layers or regions without these signs.

[0032] Figure 1A shows an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 is a semiconductor chip comprising a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a trench-gate type RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) with multiple trench sections arranged in a row. In this example, the multiple trench sections are arranged in the X-axis direction and extend in the Y-axis direction.

[0033] The transistor section 70 is the region projected onto the upper surface of the semiconductor substrate 10 from the collector region 22, which is located on the back side of the semiconductor substrate 10 and will be described later in Figure 1B. The collector region 22 has a second conductivity type. In this example, the collector region 22 is of type P+. The transistor section 70 includes a transistor such as an IGBT.

[0034] The diode section 80 is the region projected onto the upper surface of the semiconductor substrate 10 from the cathode region 82 provided on the back side of the semiconductor substrate 10, as described later in Figure 1B. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is of type N+. The diode section 80 includes a diode such as a freewheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0035] Figure 1A shows the region around the chip end, which is the edge side of the semiconductor device 100, and omits other regions. For example, an edge termination structure is provided in the negative region in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. In this example, for convenience, the negative edge in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0036] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate.

[0037] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface of the semiconductor substrate 10. The semiconductor device 100 in this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.

[0038] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. The gate metal layer 50 is located above the gate trench 40 and well region 17.

[0039] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. For example, at least a portion of the emitter electrode 52 is formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separated from each other.

[0040] The emitter electrode 52 and gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1A. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0041] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the gate trench portion 40 of the transistor portion 70. A plug made of tungsten or the like may be formed inside the contact hole 55.

[0042] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part in the dummy trench 30. A plug made of tungsten or the like may be formed inside the contact hole 56.

[0043] The connection portion 25 electrically connects the front-side electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this case, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0044] The gate trenches 40 are arranged at predetermined intervals along a predetermined trench arrangement direction (in this example, the X-axis direction). For example, the gate trenches 40 are arranged with a trench spacing of 1.5 μm, but the trench spacing is not limited to this interval. The gate trenches 40 in this example may have two extended portions 41 that extend along a trench stretching direction (in this example, the Y-axis direction) that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the trench arrangement direction, and a connecting portion 43 that connects the two extended portions 41.

[0045] Preferably, at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 in the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0046] In this example, the dummy trench section 30 is electrically connected to the emitter electrode 52 and is set to the emitter potential. The dummy trench section 30, like the gate trench section 40, is arranged at predetermined intervals along a predetermined trench arrangement direction (in this example, the X-axis direction). As an example, the dummy trench section 30 is arranged with a trench spacing of 1.5 μm, but the trench spacing is not limited to this interval. In particular, the trench spacing of the dummy trench section 30 may be set to be different from the trench spacing of the gate trench section 40. In this example, the dummy trench section 30, like the gate trench section 40, has a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trench section 30 may have two extended portions 31 that extend along the trench extension direction and a connecting portion 33 that connects the two extended portions 31. The dummy trench section 30 may be at a floating potential. The dummy trench section 30 is an example of a first trench section adjacent to the gate trench section 40.

[0047] The transistor section 70 in this example has a structure in which two gate trench sections 40 having a connecting portion 43 and two dummy trench sections 30 without a connecting portion are repeatedly arranged. That is, the arrangement ratio of the gate trench sections 40 and the dummy trench sections 30 may be set to a predetermined desired arrangement ratio. In the transistor section 70 in this example, the ratio of the number of gate trench sections 40 to the number of dummy trench sections 30 is 1:1. The transistor section 70 in this example has dummy trench sections 30 between two extension sections 41 connected by a connecting portion 43. Note that the number of gate trench sections 40 may be the same as the number of extension sections 41. The number of dummy trench sections 30 may be the same as the number of extension sections 31.

[0048] However, the ratio of gate trenches 40 to dummy trenches 30 is not limited to this example. The ratio of gate trenches 40 to dummy trenches 30 may be 2:3 or 2:4. By increasing the number of dummy trenches 30 relative to the number of gate trenches 40, electric field concentration in the mesa portion 71 can be mitigated, and the voltage and current withstand capability of the semiconductor device 100 can be increased. Furthermore, by adjusting the ratio of gate trenches 40 to dummy trenches 30, the gate capacitance for driving the semiconductor device 100 can be adjusted. Increasing the number of dummy trenches 30 relative to the number of gate trenches 40 increases the gate capacitance and reduces the saturation current. Alternatively, the transistor portion 70 may be a so-called full-gate structure in which dummy trenches 40 are not provided and the entire portion is a gate trench 40. Note that the ratio of gate trenches 40 to dummy trenches 30 disclosed herein may be read as the ratio of gate trenches 40 to dummy trenches. The dummy trench includes a trench in which no channels are formed in the side walls, such as the dummy trench section 30 or the dummy gate trench section 130 described later.

[0049] The well region 17 is a second conductivity type region located on the front side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region located on the edge side of the semiconductor device 100. The well region 17 is, for example, of P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the ends of the gate trench portion 40 and the dummy trench portion 30 in the trench extension direction may be covered by the well region 17.

[0050] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The emitter region 12 and the contact region 15 are exposed within the contact holes 54. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the trench stretching direction.

[0051] Mesa portions 71 and 81 are mesa portions provided adjacent to trench portions in a plane parallel to the front surface of the semiconductor substrate 10. A mesa portion is a part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as a single trench portion. That is, the region sandwiched between two extended portions may be considered as a mesa portion.

[0052] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. On the front surface of the semiconductor substrate 10, the mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15.

[0053] On the other hand, the mesa portion 81 is provided in the diode portion 80 adjacent to the dummy trench portion 30. The trench portion in the mesa portion 81 may be electrically connected to the emitter electrode 52 through the contact hole 56 and set to the emitter potential. In other words, the trench portion provided in the diode portion 80 may be the dummy trench portion 30.

[0054] The mesa portion 81 has a well region 17 and a base region 14 on the front surface of the semiconductor substrate 10. An emitter electrode 52 is also placed on the upper surface of the mesa portion 81. That is, the metal layer of the emitter electrode 52 may function as the anode electrode in the diode portion 80.

[0055] The base region 14 is a second conductivity type region located on the front side of the semiconductor substrate 10 in the transistor section 70. The base region 14 is, for example, P-type. The base region 14 may be located at both ends of the mesa section 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that Figure 1A shows only one end of the base region 14 in the Y-axis direction.

[0056] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18, which will be described later in Figure 1B. In this example, the emitter region 12 is N+ type. For example, the dopant of the emitter region 12 is phosphorus (P) or arsenic (As). The emitter region 12 is provided on the front surface of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0057] The emitter region 12 may extend to the dummy trench portion 30 and be in contact with the dummy trench portion 30. However, the emitter region 12 may terminate without reaching the dummy trench portion 30 and not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is not in contact with the dummy trench portion 30.

[0058] The contact region 15 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the contact region 15 is a P+ type. An example of a dopant for the contact region 15 is boron (B). In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. However, the contact region 15 may be spaced apart from the gate trench portion 40 below the emitter region 12 in the portion where the emitter region 12 is in contact with the gate trench portion 40.

[0059] The contact area 15 may or may not be in contact with the gate trench portion 40. Similarly, the contact area 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact area 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40. The contact area 15 is also provided below the contact hole 54. Furthermore, the contact area 15 may also be provided in the mesa portion 81.

[0060] Figure 1B is an example of a cross-sectional view along the line a-a' in Figure 1A. The a-a' cross-section extends from the transistor section 70 to the diode section 80, and in the transistor section 70, it is the XZ plane passing through the emitter region 12. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0061] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0062] The buffer region 20 is a first-conductivity region located below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0063] The collector region 22 is located below the buffer region 20 in the transistor section 70. The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal.

[0064] The base region 14 is a second conductive region located above the drift region 18 in the mesa portions 71 and 81. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0065] The emitter region 12 is provided in the mesa portion 71 between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0066] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, and contact region 15 is provided, each trench penetrates these regions as well, reaching the drift region 18. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trenches. Manufacturing in which doping regions are formed between trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0067] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38. The potential of a gate electrode such as an IGBT is applied to the gate conductive portion 44.

[0068] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, separated by the gate insulating film 42. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0069] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 by an interlayer insulating film 38. The potential of the emitter electrode of an IGBT or the like is applied to the dummy conductive portion 34. The dummy conductive portion 34 may be at a floating potential.

[0070] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided through the interlayer insulating film 38.

[0071] The lower end 13 is the lower end of the emitter region 12 in the mesa portion 71 on the side facing the dummy trench portion 30. When the emitter region 12 reaches the dummy trench portion 30, the lower end 13 is in contact with the dummy trench portion 30.

[0072] At least a portion of the contact region 15 is provided below the lower end 13 in the mesa portion 71. That is, the contact region 15 is provided deeper than the emitter region 12 and partially overlaps with the emitter region 12. In this example, the contact region 15 extends in the trench arrangement direction from the dummy trench portion 30 to below the lower end 13 of the emitter region 12. This makes it more difficult for holes below the emitter region 12 to be directly extracted through the emitter region 12, and makes it easier for hole currents to be extracted from the contact region 15. As a result, it becomes more difficult for the NPNP type parasitic thyristor from the emitter region 12 to the collector region 22 to turn on, and latch-up of the semiconductor device 100 can be suppressed.

[0073] In the cross-section of this example, the contact region 15 is spaced apart from the gate trench portion 40 in the mesa portion 71. As a result, the semiconductor device 100 operates stably without the contact region 15 hindering the formation of the inversion layer on the side surface of the gate trench portion 40.

[0074] In this example, the contact region 15 is provided spanning both sides of the dummy trench portion 30 in the X-axis direction. In the manufacturing process of the contact region 15 in this example, a resist is provided on the semiconductor substrate 10, and the contact region 15 spanning the area where the trench portion is provided can be installed by ion implantation. The dummy trench portion 30 can be installed by etching the semiconductor substrate 10 after the contact region 15 has been provided.

[0075] In recent years, so-called process pitch miniaturization has been carried out to shorten the spacing between mesa portions 71, with the aim of miniaturizing semiconductor devices 100. For example, when a diffusion region is created in a silicon semiconductor substrate 10 by ion implantation, the dopant tends to diffuse within a certain range. With the structure of the contact region 15 in this example, even when the process pitch is miniaturized, it becomes easy to manufacture the contact region 15 which extends below the lower end 13 of the emitter region 12 and is spaced apart from the gate trench portion 40. As a result, a semiconductor device 100 with high latch-up resistance can be provided without significantly affecting the electrical characteristics. However, the latch-up suppression effect can be achieved as long as the contact region 15 is provided so as to be connected in the direction of trench extension, and is not limited to a configuration in which the contact region 15 is in contact with the dummy trench portion 30.

[0076] In the diode section 80, a buffer section 20 is stacked above the cathode section 82, and a drift section 18 is stacked above the buffer section 20. In the mesa section 81, a base section 14 is stacked above the drift section 18, and a PN junction is formed between the base section 14 and the drift section 18. The base section 14 is electrically connected to the emitter electrode 52 via a contact hole 54.

[0077] Figure 1C is an example of a b-b' cross-sectional view in Figure 1A. The b-b' cross-section is the XZ plane in the transistor section 70 that does not pass through the emitter region 12. In this example, the mesa section 71 in the transistor section 70 has a base region 14 and a contact region 15 above the drift region 18. In the diode section 80, the mesa section 81 has the same structure as in the example in Figure 1B.

[0078] The contact region 15 extends from the gate trench portion 40 to the dummy trench portion 30. A contact hole 54 is provided above the contact region 15. A positive hole is withdrawn from the contact region 15 through the contact hole 54.

[0079] If the contact region 15 located below the emitter region 12 and the contact region 15 in the cross-section of this example are formed by the same process, then the depths of these contact regions 15 will be the same. In this case, the contact region 15 will be deeper than the emitter region 12. However, the contact region 15 may be formed at different depths below the emitter region 12 and in other regions.

[0080] Figure 2 shows an example of an enlarged cross-sectional view of the mesa portion 71. In this example, the XZ plane passing through the emitter region 12 is shown in the transistor portion 70.

[0081] The emitter region 12 extends in the trench arrangement direction from the gate trench portion 40, beyond the contact hole 54, to the dummy trench portion 30. This facilitates current conduction from the emitter region 12 through the contact hole 54, resulting in improved electrical characteristics of the semiconductor device 100. In this example, the emitter region 12 extends in the trench arrangement direction from the gate trench portion 40 to the dummy trench portion 30, and terminates without reaching the dummy trench portion 30. However, the emitter region 12 may also be provided extending from the gate trench portion 40 to the dummy trench portion 30 in the trench arrangement direction.

[0082] The contact region 15 is provided on the front surface 21 of the semiconductor substrate 10 at the side wall of the dummy trench portion 30. The contact region 15 comprises a surface region 92 and a lower region 94.

[0083] The surface region 92 is a region in the semiconductor substrate 10 that has the same depth as the emitter region 12. For example, the depth of the surface region 92 is 0.5 μm. However, the depth of the surface region 92 may be different. When the emitter region 12 extends from the gate trench portion 40 to the dummy trench portion 30 and reaches the dummy trench portion 30, the surface region 92 is not provided in the cross section in which the emitter region 12 is exposed to the front surface 21 of the semiconductor substrate 10. The impurity concentration of the surface region 92 may be in the range of 5E19 / cm3 or more and 2E20 / cm3 or less.

[0084] The lower region 94 is located in the semiconductor substrate 10 in a region deeper than the emitter region 12. The lower region 94 extends beyond the lower end 13 on the gate trench 40 side of the emitter region 12, which extends from the gate trench 40 to the dummy trench 30, and continues toward the gate trench 40 side. The impurity concentration in the lower region 94 may be in the range of 1E19 / cm3 or more and 1E20 / cm3 or less.

[0085] The width Wc is the width of the contact region 15 in the trench arrangement direction. The width Wc is the width measured from the center of the dummy trench portion 30 to the lower end of the emitter region 12 on the dummy trench portion 30 side. That is, the width Wc corresponds to the maximum reachable position on the gate trench portion 40 side of the lower region 94, measured from the center of the dummy trench portion 30. The width Wc may be 1.2 μm or less, or 1.1 μm or less. Here, the width of the surface region 92 in the trench arrangement direction may be in the range of 15% to 40% of the distance between adjacent trenches. The width of the lower region 94 in the trench arrangement direction may be in the range of 30% to 70% of the distance between adjacent trenches. Furthermore, the width of the portion of the lower region 94 that overlaps with the emitter region 12 in the trench arrangement direction may be in the range of 0% to 30% of the distance between adjacent trenches, and more preferably in the range of 10% to 20%.

[0086] The thickness Dc is the thickness of the contact region 15 in the depth direction of the semiconductor substrate 10. The thickness Dc is greater than the depth of the lower end 13 of the emitter region 12 and less than the depth of the base region 14. For example, the thickness Dc is 0.5 μm or more and 2.0 μm or less. The thickness of the surface region 92 may be in the range of 0.3 μm or more and 0.8 μm or less. The thickness of the lower region 94 may be in the range of 0.3 μm or more and 1.1 μm or less.

[0087] The width Ws is the distance between the contact region 15 and the gate trench portion 40 in the trench arrangement direction. The width Ws may be set so that a channel can be formed at the end of the gate trench portion 40. That is, the width Ws corresponds to the separation distance between the contact region 15 and the gate trench portion 40. In one example, the width Ws is 0.6 μm or more. The width Ws in the trench arrangement direction may be in the range of 30% to 70% of the distance between adjacent trenches.

[0088] Figure 3 shows an example of a top view of a semiconductor device 100 with an unopened contact hole 54. Figure 3 is an example of an enlarged view of the top of the semiconductor device 100.

[0089] The non-connected region 59 is a region on the front surface 21 where the emitter electrode 52 is not electrically connected to the contact region 15. For example, the non-connected region 59 is an unopened region where contact holes 54 have not been formed in the interlayer insulating film 38 due to poor oxide film etching caused by particles or foreign matter. Alternatively, the non-connected region 59 may be a region on the front surface 21 where the contact region 15 was not formed due to residual resist or the like.

[0090] In this example, the hole current that would have been extracted in the unconnected region 59 flows through the contact region 15 and is extracted through the contact hole 54 above the other neighboring contact region 15. That is, the hole current does not flow through the base region 14 below the emitter region 12, but flows through the contact region 15, which has lower resistance to holes than the base region 14, thus suppressing latch-up. This suppresses switching failure caused by process defects. Therefore, a semiconductor device 100 with a redundant element structure that is resistant to process defects is provided.

[0091] Figure 4A shows an example of the simulation results of the static characteristics of the semiconductor device 100. This example shows the change in static characteristics with respect to the width Wc of the contact region 15. This example shows the case where the width of the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40 is 1.5 μm. In order to show the qualitative properties of the simulation results, the values ​​on the vertical axis in this example are scaled to normalized values ​​where the initial value corresponding to the contact region width Wc=0 is normalized to 1. The units of each normalized value may be appropriate units having dimensions corresponding to each physical quantity.

[0092] The relationship between the width Wc, the collector-emitter saturation voltage Vce when the semiconductor device 100 is driven, the collector-emitter saturation current when the semiconductor device 100 is driven, and the threshold voltage Vth of the semiconductor device 100 are shown. When the width Wc is 1.2 μm or less, the influence of the contact region 15 on channel formation in the base region 14 is small. Therefore, when the width Wc is within this range, the influence on all of these static characteristic values ​​can be kept within a small range.

[0093] Figure 4B shows an example of the simulation results of the ON characteristics of the semiconductor device 100. This example shows the change in ON characteristics with respect to the width Wc of the contact region 15. Note that the values ​​on the vertical axis in this example have been scaled to normalized values.

[0094] The relationship between Wc and the maximum value dV / dt_max (Normalized) of the time variation of the collector-emitter voltage Vce when driving the semiconductor device 100, the relationship between Wc and the maximum value di / dt_max (Normalized) of the time variation of the collector-emitter current when driving the semiconductor device 100, and the on-dissipation Eon (Normalized) of the semiconductor device 100 are shown. When the width Wc is 1.2 μm or less, the influence of the contact region 15 on channel formation in the base region 14 is small. Therefore, when the width Wc is within this range, the influence on all of these on-characteristic values ​​can be kept within a small range.

[0095] Figure 4C shows an example of the simulation results of the off-state characteristics of the semiconductor device 100. This example shows the change in off-state characteristics with respect to the width Wc of the contact region 15. Note that the values ​​on the vertical axis in this example have been scaled to normalized values.

[0096] The relationship between Wc and the maximum value dV / dt_max (Normalized) of the time variation of the collector-emitter voltage Vce when driving the semiconductor device 100, the relationship between Wc and the maximum value di / dt_max (Normalized) of the time variation of the collector-emitter current when driving the semiconductor device 100, and the relationship between Wc and the off-loss Eoff (Normalized) of the semiconductor device 100 are shown. When the width Wc is 1.2 μm or less, the influence of the contact region 15 on channel formation in the base region 14 is small. Therefore, when the width Wc is within this range, the influence on all of these off-characteristic values ​​can be kept within a small range.

[0097] As shown in the simulation results in Figures 4B and 4C, the semiconductor device 100 in this example does not affect the dynamic electrical characteristics due to the structure of the contact region 15. Therefore, as shown in the simulation results in Figures 4A to 4C, the semiconductor device 100 in this example does not significantly affect the electrical characteristics in both static and dynamic characteristics. The semiconductor device 100 in this example improves latch-up tolerance without causing fluctuations in electrical characteristics.

[0098] Figure 5A shows an example of a top view of the semiconductor device 100. This example differs from Figure 1A in that the emitter region 12 is provided in contact with the dummy trench portion 30. The differences between this example and Figure 1A will be explained in particular.

[0099] In this example, the emitter region 12 extends from the gate trench portion 40 to the dummy trench portion 30 in the trench arrangement direction. The emitter region 12 and the contact region 15 are provided on the front surface 21 of the semiconductor substrate 10, alternately in contact with the gate trench portion 40 and the dummy trench portion 30, respectively, in the trench extension direction.

[0100] Figure 5B is an example of a c-c' cross-sectional view in Figure 5A. The c-c' cross-section is the XZ plane extending from the transistor section 70 to the diode section 80, passing through the emitter region 12 in the transistor section 70. The XZ cross-section extending from the transistor section 70 to the diode section 80, passing through the contact region 15 in the transistor section 70, is the same as in Figure 1C.

[0101] In this example, the surface area 92 of the contact region 15 is not provided in the c-c' cross section. The contact region 15 in this example has the same structure as in the example in Figure 1B in the lower region 94. That is, at least a part of the contact region 15 is provided below the lower end 13 in the mesa portion 71. This makes it difficult for holes below the emitter region 12 to be directly extracted through the emitter region 12, and the hole current can be extracted from the contact region 15 to suppress latch-up.

[0102] Figure 6A shows an example of a top view of the semiconductor device 100. In this example, the ratio of the number of gate trenches 40 to the number of dummy trenches 30 is 1:2. The semiconductor device 100 in this example can have improved resistance to defects by increasing the ratio of dummy trenches 30.

[0103] In this example, a U-shaped gate trench 40 and two I-shaped dummy trenches 30 are arranged in the transistor section 70 on the front surface of the semiconductor substrate 10. However, the structures of the gate trench 40 and dummy trenches 30 are not limited to these, as long as the arrangement ratio of the gate trench 40 and dummy trenches 30 is maintained at 1:2. For example, the dummy trench 30 may have a U-shaped structure, and the region within the dummy trench may be a floating region.

[0104] Figure 6B is an example of a d-d' cross-sectional view in Figure 6A. The d-d' cross-section extends from the transistor section 70 to the diode section 80, and in the transistor section 70, it is the XZ plane that passes through the emitter region 12. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in a d-d' cross-section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38. The semiconductor device 100 in this example also has a storage region 16 between the drift region 18 and the base region 14.

[0105] The storage region 16 is a first conductivity type region located between the base region 14 and the drift region 18. In this example, the storage region 16 is of type N+. The storage region 16 is provided in the transistor section 70 and the diode section 80. This allows the semiconductor device 100 to avoid mask misalignment of the storage region 16.

[0106] Furthermore, the accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region 18. The ion implantation dose in the accumulation region 16 is 1E12cm -2 Above, 1E13cm -2 The following may be the case. Also, the ion implantation dose for the storage region 16 is 3E12cm -2 The above is 6E12cm -2 The following may also be the case. By providing the storage region 16, the carrier injection enhancement effect can be increased, and the on-voltage of the transistor section 70 can be reduced. Note that E means a power of 10, for example 1E12cm -2 is 1 x 10 12 cm -2 It means...

[0107] In this example as well, the contact regions 15 are located below the emitter region 12 and electrically connect adjacent contact regions 15 to each other. Regardless of the presence or absence of the storage region 16 and the arrangement ratio of the gate trench portion 40 and the dummy trench portion 30, the semiconductor device 100 can suppress latch-up due to the structure of the contact regions 15.

[0108] Figure 7A shows an example of a modified semiconductor device 100 top view. In this example, the differences from Figure 1A will be explained in particular. The semiconductor device 100 in this example has a dummy gate trench 130 that does not come into contact with the emitter region 12, instead of the dummy trench 30. The dummy gate trench 130 is an example of a first trench adjacent to the gate trench 40.

[0109] The dummy gate trench 130 is a trench that is set to the gate potential and does not come into contact with the emitter region 12. In other words, the dummy gate trench 130 is a trench that is set to the gate potential but does not drive the transistor in the adjacent mesa region 71, and is an example of a dummy trench separate from the dummy trench 30. In order to set the dummy gate trench 130 to the gate potential, the dummy gate trench 130 extends in the Y-axis direction to the region where the gate metal layer 50 is provided. The dummy gate trench 130 is connected to the gate metal layer 50 via a contact hole 58 and is set to the gate potential.

[0110] Although the dummy gate trench 130 is set to the gate potential, it does not come into contact with the emitter region 12, so a channel formed by the inversion layer of the first conductivity type is not formed on the side wall of the dummy gate trench 130. The dummy gate trench 130 makes it easier to attract carriers to the mesa region 71, so its properties such as gate capacitance differ from those of the dummy gate trench 130. Therefore, by using the dummy gate trench 130 and the dummy trench 30 in combination, it is possible to adjust the threshold voltage, saturation current, field concentration, and gate capacitance of the semiconductor device 100.

[0111] On the front surface of the semiconductor substrate 10, the gate trench portion 40 in this example has a U-shaped structure, and the dummy gate trench portion 130 has an I-shaped structure. However, the structures of the gate trench portion 40 and the dummy gate trench portion 130 are not limited to these structures as long as the desired arrangement ratio can be achieved.

[0112] In this example, the dummy gate trench section 130 in the diode section 80 has the same structure as in Figure 1A. That is, the dummy gate trench section 130 is connected to the emitter electrode 52 via the contact hole 56 and is set to the emitter potential.

[0113] Figure 7B is an example of an e-e' cross-sectional view in Figure 7A. The e-e' cross-section extends from the transistor section 70 to the diode section 80, and in the transistor section 70, it is the XZ plane passing through the emitter region 12. The dummy gate trench section 130 has a second gate insulating film 132 and a second gate conductive section 134.

[0114] In this example, the semiconductor device 100 has the same configuration as the cross-sectional view in Figure 1B, except that the dummy gate trench portion 130 of the semiconductor device 100 has an emitter potential. That is, in this example as well, the contact regions 15 are located below the emitter region 12 and electrically connect adjacent contact regions 15 to each other. Therefore, regardless of the potential of the dummy gate trench portion, the semiconductor device 100 can suppress latch-up due to the structure of the contact regions 15.

[0115] Figure 8A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 in this example includes a contact trench portion 60.

[0116] The contact trench 60 extends from the front surface 21 in the depth direction of the semiconductor substrate 10. The contact trench 60 electrically connects the emitter electrode 52 and the semiconductor substrate 10. The contact trench 60 extends in the trench extension direction. In this example, the contact trench 60 is arranged in a stripe pattern along the gate trench 40 and the dummy trench 30.

[0117] The contact trenches 60 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact trenches 60 are formed above the base region 14 in the diode section 80. The contact trenches 60 are not provided above the well regions 17 provided at both ends in the Y-axis direction. One or more contact trenches 60 may be provided extending in the trench extension direction.

[0118] In the mesa portion 71 between the gate trench portion 40 and the contact trench portion 60, the emitter region 12 and the contact region 15 may be arranged alternately in the trench extension direction. In the trench extension direction, the width of the emitter region 12 may be greater than the width of the contact region 15. The width of the emitter region 12 in the trench extension direction may be 0.6 μm or more and 1.6 μm or less. By appropriately controlling the ratio of the emitter region 12 to the contact region 15, latch-up can be more easily suppressed.

[0119] Figure 8B is an example of a cross-sectional view of the f-f' section in Figure 8A. In this example, the contact trench 60 is formed to be shallower than the emitter region 12.

[0120] The contact trench portion 60 extends from the front surface 21 towards the back surface 23 of the semiconductor substrate 10. In this example, the lower end of the contact trench portion 60 is shallower than the lower end of the emitter region 12. Emitter regions 12 are provided at both ends of the contact trench portion 60 in the trench arrangement direction. The contact trench portion 60 has a plug 62 and a barrier metal layer 64.

[0121] The plug 62 is a conductive material provided inside the contact trench portion 60. The plug 62 may be made of the same material as the emitter electrode 52, or a different material. The plug 62 may contain materials such as tungsten.

[0122] The barrier metal layer 64 is provided below the plug 62. In this example, the barrier metal layer 64 is provided between the plug 62 and the emitter region 12. The barrier metal layer 64 may contain a material such as titanium nitride.

[0123] The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 extends toward the dummy trench portion 30 rather than the contact trench portion 60 in the trench arrangement direction. That is, the lower end 13 is provided between the dummy trench portion 30 and the contact trench portion 60 in the trench arrangement direction.

[0124] At least a portion of the contact area 15 is provided below the lower end 13 in the mesa portion 71. In this example, the contact area 15 extends in the trench arrangement direction from the dummy trench portion 30 to below the lower end 13 of the emitter area 12. The contact area 15 may extend beyond the contact trench portion 60 from the dummy trench portion 30 in the trench arrangement direction, or it may not extend beyond the contact trench portion 60. In this example, the contact area 15 is provided between the dummy trench portion 30 and the contact trench portion 60 in the trench arrangement direction.

[0125] The trench bottom region 19 is a second conductivity type region located below the dummy trench portion 30 and the gate trench portion 40. In this example, the trench bottom region 19 covers the lower ends of the dummy trench portion 30 and the gate trench portion 40. The doping concentration of the trench bottom region 19 may be lower than that of the base region 14. The trench bottom region 19 is located between the drift region 18a and the drift region 18b. By providing the trench bottom region 19, the avalanche tolerance is improved. Although embodiments in which the semiconductor device 100 includes the trench bottom region 19 may be described, the trench bottom region 19 may be omitted.

[0126] The drift region 18a is located between the base region 14 and the trench bottom region 19 in the mesa region 71 and the mesa region 81. The drift region 18b is located below the trench bottom region 19. The doping concentrations in the drift region 18a and the drift region 18b may be the same.

[0127] Figure 9A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 in this example differs from the embodiment in Figure 8A in the arrangement of the emitter region 12 and the contact region 15 on the front surface 21. In this example, the differences from the embodiment in Figure 8A will be explained in particular. In this example, the emitter region 12 is provided on one side of the contact trench portion 60, which is different from the embodiment in Figure 8A.

[0128] The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 extends from the gate trench portion 40 to the side wall of the contact trench portion 60 in the trench arrangement direction. The emitter region 12 does not necessarily have to be provided between the dummy trench portion 30 and the contact trench portion 60.

[0129] Figure 9B is an example of a g-g' cross-sectional view in Figure 9A. The contact trench 60 in this example is formed deeper than in the embodiment shown in Figure 8B.

[0130] The contact trench portion 60 extends beyond the emitter region 12 towards the back surface 23 of the semiconductor substrate 10. That is, the lower end of the contact trench portion 60 in this example is deeper than the lower end of the emitter region 12. The lower end of the contact trench portion 60 in this example is shallower than the lower end of the contact region 15.

[0131] The emitter region 12 extends from the gate trench portion 40 to the side wall of the contact trench portion 60 in the trench arrangement direction. Therefore, the lower end 13 is located between the gate trench portion 40 and the contact trench portion 60 in the trench arrangement direction, and is situated on the side wall of the contact trench portion 60.

[0132] Figure 10A shows an example of a top view of the semiconductor device 100. This example of the semiconductor device 100 differs from the embodiment shown in Figure 8A in that it does not include a diode section 80.

[0133] Figure 10B is an example of an h-h' cross-sectional view in Figure 10A. The contact trench 60 in this example is formed deeper than in the embodiment shown in Figure 8B.

[0134] The contact trench 60 extends beyond the emitter region 12 towards the back surface 23 of the semiconductor substrate 10. In this example, the lower end of the contact trench 60 is deeper than the lower end of the emitter region 12 and shallower than the lower end of the contact region 15. Emitter regions 12 are provided at both ends of the contact trench 60 in the trench arrangement direction.

[0135] The emitter region 12 is provided extending toward the dummy trench portion 30 side of the contact trench portion 60 in the trench arrangement direction. That is, the lower end 13 is provided between the dummy trench portion 30 and the contact trench portion 60 in the trench arrangement direction.

[0136] Figure 10C is another example of the h-h' cross-sectional view in Figure 10A. In this example, the depth of the contact trench 60 differs from that of the embodiment in Figure 10B. In this example, the contact trench 60 is formed to be shallower than the emitter region 12. That is, the lower end of the contact trench 60 in this example is shallower than the lower end of the emitter region 12.

[0137] As described above, the depth of the contact trench portion 60 is not limited to the embodiment and may be changed as appropriate. Also, the emitter region 12 may be provided at both ends of the contact trench portion 60 in the trench arrangement direction, or it may be provided on one side. Furthermore, in each embodiment, the semiconductor device 100 may or may not have a trench bottom region 19.

[0138] Figure 11A shows an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 includes a dummy trench portion 30 provided adjacent to the gate trench portion 40, as well as a dummy gate trench portion 130 provided adjacent to the gate trench portion 40.

[0139] The dummy gate trench section 130 is set to the gate potential and is a trench section that does not come into contact with the emitter region 12. In this example, the dummy gate trench section 130 is connected to the extended section 41 by a connecting section 43.

[0140] The emitter region 12 is located in the mesa portion 71 between the gate trench portion 40 and the dummy gate trench portion 130, in contact with the gate trench portion 40 and spaced apart from the dummy gate trench portion 130.

[0141] Furthermore, the emitter region 12 is located in the mesa portion 71 between the gate trench portion 40 and the dummy trench portion 30, in contact with the gate trench portion 40 and spaced apart from the dummy trench portion 30.

[0142] Figure 11B is an example of an i-i' cross-sectional view in Figure 11A. The semiconductor device 100 in this example includes a contact trench 60 that is shallower than the emitter region 12, and emitter regions 12 provided at both ends of the contact trench 60 in the trench arrangement direction, but is not limited to this. The dummy gate trench 130 is a dummy trench, just like the dummy trench 30. Therefore, a part of the dummy gate trench 130 may be replaced with a dummy trench 30 at the emitter potential. This allows the gate capacitance to be adjusted, thereby achieving an optimal switching speed.

[0143] The contact region 15 is located in the mesa portion 71 between the gate trench portion 40 and the dummy gate trench portion 130, below the lower end 13 of the emitter region 12 on the dummy gate trench portion 130 side. The contact region 15 is also located in the mesa portion 71 between the gate trench portion 40 and the dummy trench portion 30, below the lower end 13 of the emitter region 12 on the dummy trench portion 30 side.

[0144] Figure 12A shows an example of a top view of the semiconductor device 100. In this example, the semiconductor device 100 is a gate trench 40, and differs from the embodiment in Figure 11A in that it has a staggered structure, with the first trench portion adjacent to the gate trench portion 40 being a gate trench portion 40. The semiconductor device 100 has a plurality of adjacent gate trench portions 40. The plurality of adjacent gate trench portions 40 may be connected to each other by a connecting portion 43.

[0145] Multiple adjacent gate trenches 40 are in contact with the emitter region 12 at different positions in the trench extension direction. That is, the semiconductor device 100 has a staggered structure and includes emitter regions 12 arranged alternately. In this case, each adjacent gate trench 40 has both a portion that becomes a gate trench and a portion that becomes a first trench. In other words, in the mesa portion between adjacent gate trenches 40, there is an emitter region 12 (first emitter region) that is in contact with one gate trench 40 and spaced apart from the other gate trench 40, and an emitter region 12 (second emitter region) that is spaced apart from one gate trench 40 and in contact with the other gate trench 40. The contact region 15 is provided in a region that includes the area below the lower end 13 on the other gate trench portion 40 side of the first emitter region and the area below the lower end 13 on one gate trench portion 40 side of the second emitter region. In the trench extension direction of the gate trench portion 40, the first emitter region and the second emitter region are provided alternately with the contact region 15 in between.

[0146] Figure 12B is an example of a j-j' cross-sectional view in Figure 12A. The semiconductor device 100 in this example includes a contact trench portion 60 that is shallower than the emitter region 12 and emitter regions 12 provided at both ends of the contact trench portion 60 in the trench arrangement direction, but is not limited to this. That is, the semiconductor device 100 may include a contact trench portion 60 that is deeper than the emitter region 12, or it may include an emitter region 12 provided on one side of the contact trench portion 60. The semiconductor device 100 may or may not include a trench bottom region 19.

[0147] Figure 13A shows an example of a top view of the semiconductor device 100. This example of the semiconductor device 100 differs from the embodiment in Figure 12A in that it does not have a dummy trench portion 30, and only a gate trench portion 40 is provided. Similar to the embodiment in Figure 12A, this example of the semiconductor device 100 has a staggered structure in which the emitter regions 12 are arranged alternately. In this example of the semiconductor device 100, the ratio of the emitter region 12 on the front surface 21 is larger than in the embodiment in Figure 12A. Even when the ratio of the emitter region 12 on the front surface 21 is larger in this example of the semiconductor device 100, a part of the emitter region 12 is separated from the gate trench portion 40, so latch-up of the semiconductor device 100 can be suppressed.

[0148] Figure 13B is an example of a k-k' cross-sectional view in Figure 13A. The semiconductor device 100 in this example includes a contact trench 60 that is shallower than the emitter region 12, and emitter regions 12 provided at both ends of the contact trench 60 in the trench arrangement direction, but is not limited to this. In this example, the emitter regions 12 are provided at both ends of the gate trench 40 in the trench arrangement direction. In this case, by patterning adjacent emitter regions 12 on either side of the gate trench 40 together, process reliability can be maintained even when the mesa width is reduced.

[0149] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It is clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. For example, although an RC-IGBT was used as an example in this description, the invention is also applicable to IGBTs and MOSFETs.

[0150] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0151] 10...Semiconductor substrate, 12...Emitter region, 13...Bottom edge, 14...Base region, 15...Contact region, 16...Storage region, 17...Well region, 18...Drift region, 19...Trench bottom region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extended portion, 42...Gate insulating film, 43...Connection Part, 44...Gate conductive part, 50...Gate metal layer, 52...Emitter electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 58...Contact hole, 59...Non-connected area, 60...Contact trench part, 62...Plug, 64...Barrier metal layer, 70...Transistor part, 71...Mesa part, 80...Diode part, 81...Mesa part, 82...Cathode area, 92...Surface area, 94...Lower area, 100...Semiconductor device, 130...Dummy gate trench part, 132...Second gate insulating film, 134...Second gate conductive part

Claims

1. A trench gate type semiconductor device having a plurality of trench portions and a plurality of mesa portions which are portions sandwiched between two adjacent trench portions on the front side of a semiconductor substrate, wherein the plurality of mesa portions include a first mesa portion and a second mesa portion, and the plurality of trench portions include gate trench portions, A first conductivity type drift region provided on the semiconductor substrate, A second conductivity type base region is provided above the drift region, In the first mesa portion, a first contact trench portion extends in the depth direction from the front surface of the semiconductor substrate, In the second mesa portion, a second contact trench portion extends in the depth direction from the front surface of the semiconductor substrate, In the trench arrangement direction, one or more high-concentration regions of a first conductivity type with a higher doping concentration than the drift region are provided, extending from the gate trench portion to one side wall of the first contact trench portion and not in contact with the lower end of the first contact trench portion. A second conductivity type contact region with a higher doping concentration than the base region, Equipped with, The contact region in the first mesa portion is provided between the other side wall of the first contact trench portion and the trench portion in the trench arrangement direction, and includes a second conductivity type surface region with a higher doping concentration than the base region, which is arranged to extend from one end to the other of at least one of the high-concentration regions in the trench extension direction. The contact region in the second mesa portion is in contact with both side walls of the second contact trench portion in the trench arrangement direction. Trench gate type semiconductor device.

2. The high-concentration region is in contact with the side wall of the first contact trench with respect to the first contact trench. The trench gate type semiconductor device according to claim 1.

3. A trench gate type semiconductor device having a plurality of trench portions and a plurality of mesa portions which are portions sandwiched between two adjacent trench portions on the front side of a semiconductor substrate, wherein the plurality of mesa portions include a first mesa portion and a second mesa portion, and the plurality of trench portions include gate trench portions, A first conductivity type drift region provided on the semiconductor substrate, A second conductivity type base region is provided above the drift region, In the first mesa portion, a first contact trench portion extends in the depth direction from the front surface of the semiconductor substrate, In the second mesa portion, a second contact trench portion extends in the depth direction from the front surface of the semiconductor substrate, In the trench arrangement direction, an extension is provided from the gate trench portion to one side wall of the first contact trench portion, and one or more high-concentration regions of the first conductivity type with a doping concentration higher than that of the drift region, A second conductivity type contact region with a higher doping concentration than the base region, Equipped with, The contact region in the first mesa portion is provided between the other side wall of the first contact trench portion and the trench portion in the trench arrangement direction, and includes a second conductivity type surface region with a higher doping concentration than the base region, which is arranged to extend from one end to the other of at least one of the high-concentration regions in the trench extension direction. The contact region in the second mesa portion is in contact with both side walls of the second contact trench portion in the trench arrangement direction. The lower end of the high-concentration region is closer to the front surface of the semiconductor substrate than the lower end of the first contact trench. Trench gate type semiconductor device.

4. The contact region includes a lower region of a second conductivity type having a higher doping concentration than the base region, which is located in a region deeper than the high-concentration region in the first mesa portion. A trench gate type semiconductor device according to any one of claims 1 to 3.

5. The lower region covers the lower end of the first contact trench portion. The trench gate type semiconductor device according to claim 4.

6. The surface region and the lower region are in contact. The trench gate type semiconductor device according to claim 5.

7. When a gate voltage is applied to the gate trench portion, a channel is formed in the first mesa portion, and the channel is not formed in the second mesa portion. The trench gate type semiconductor device according to claim 6.

8. The first mesa portion is sandwiched between the gate trench portion and the dummy trench portion or the dummy gate trench portion. The trench gate type semiconductor device according to claim 7.

9. The surface region is in contact with the dummy trench portion or the dummy gate trench portion in the first mesa portion and extends in the trench extending direction. The trench gate type semiconductor device according to claim 8.

10. The surface region is arranged alternately with the high-concentration region in the trench extension direction between the gate trench portion and one side wall of the first contact trench portion. The trench gate type semiconductor device according to claim 9.

11. The semiconductor substrate is a silicon substrate or a silicon carbide substrate. A trench gate type semiconductor device according to any one of claims 1 to 3.

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