Wafer positioning system and method

Abstract

In the present invention, a wafer positioning system and method are provided. [Solution] The wafer positioning method of the present invention includes the steps of: a manipulator transporting a wafer to a predetermined position on a first support area of ​​a lower cavity of a semiconductor processing device, i.e., a position corresponding to the current position setting parameter, according to a set or updated current position setting parameter; etching an edge area of ​​the wafer; acquiring etched edge information of the wafer by performing image collection and image recognition on the wafer mounted at the predetermined position and etched according to the current position setting parameter; calculating a position deviation parameter of the current position setting parameter according to the acquired etched edge information of the wafer; a control device updating the current position setting parameter with the position deviation parameter to acquire an updated current position setting parameter, and controlling the manipulator to transport the wafer onto the first support area of ​​the lower cavity according to the updated current position setting parameter. By calibrating the manipulator, the position of the wafer can be determined more accurately.

Description

[Technical Field]

[0001] The present invention belongs to the technical field of wafer positioning, and more particularly to wafer positioning systems and methods. [Background technology]

[0002] In the semiconductor manufacturing process, various processes must be performed on the semiconductor wafer to meet the high standards of the semiconductor industry. In the semiconductor wafer manufacturing process, the wafer edges must be uniform, flat, undamaged, and smooth. Because uniform wafer edges and precise corrosion of the wafer edges are required, the semiconductor wafer manufacturing process needs improvement.

[0003] Figure 1a is a plan view showing the structure of a semiconductor wafer 100. The semiconductor wafer 100 includes a substrate 101 and a thin film layer 102 stacked on the substrate 101. Figure 1b is a cross-sectional view showing section AA of Figure 1a. Measurement points 1 to 8 in Figure 1a are positions where predetermined values ​​of the semiconductor wafer are measured. As shown in Figure 1b, the corrosion width refers to the difference between the radius of the substrate 101 and the radius of the thin film layer 102. The corrosion widths at measurement points 1 to 8 are approximately the same. The smaller the difference between the maximum and minimum corrosion widths, the better the uniformity of the corrosion. For example, when designing the edge width to be 0.7 mm, the difference between the maximum and minimum corrosion widths must be 0.1 mm or less; failure to meet this requirement may result in uneven edge widths. If the difference between the maximum and minimum corrosion widths exceeds 0.1 mm, it may affect subsequent processing. This may affect the performance of the integrated circuit chip and reduce the yield rate of manufactured chips. Figure 1a schematically shows the shape of a semiconductor wafer 100. Actual semiconductor wafers are not formed in a purely circular shape. For example, a 6-inch wafer may be a polygon with a wafer flat, and a 6-inch wafer may have positioning notches formed on it.

[0004] Wet processing methods for semiconductor wafers have the advantages of being simple in principle, having good process flexibility, and being inexpensive. Conventional wet corrosion methods for processing the edges of the semiconductor wafer surface include various methods. For example, these include methods of polishing the edge area of ​​the semiconductor wafer, methods of rotating the semiconductor wafer, and methods of removing a thin film layer on the substrate by mechanical friction means and chemical corrosion methods. When using the polishing method, there is a risk of damaging the remaining thin film layer and the substrate, so the polishing method is usually used for the manufacture of semiconductor wafers with low precision requirements. Damage to the edge of the semiconductor wafer can cause the wafer to move during processing, which may result in the wafer being discarded. Another commonly used method is to adsorb the semiconductor wafer with a vacuum. In the vacuum adsorption method, the wafer is adsorbed by a vacuum adsorption unit. When the wafer is adsorbed by the vacuum adsorption unit, a predetermined portion of the thin film that does not need to be removed is covered by the vacuum adsorption unit, and a predetermined portion of the thin film that needs to be removed is exposed to the outside of the vacuum adsorption unit. Next, the vacuum adsorption unit and the wafer are immersed together in a chemical corrosion solution to remove a predetermined portion of the thin film exposed to the outside of the vacuum adsorption unit. However, when using the vacuum adsorption method, it may not be possible to remove the thin film layer smoothly, potentially resulting in uneven corrosion. Another commonly used method is the thin film bonding method. In the thin film bonding method, a predetermined portion of the thin film to be removed is protected with a high-purity corrosion-resistant plastic such as PTFE or PE. Next, the exposed portion is corroded by introducing them into a chemical corrosion gas or immersing them in a chemical corrosion solution. When using the thin film bonding method, it may be difficult to overlap the center of the pre-cut thin film with the center of the wafer substrate, potentially resulting in uneven corrosion. Furthermore, the thin film bonding method involves many steps and requires the use of numerous devices, such as a thin film bonding device, a wet corrosion device, a cleaning device, and a thin film removal device. To solve these problems, a spraying method has been proposed. The spraying method allows for accurate, even, flat, and damage-free corrosion by precisely spraying the corrosion liquid onto the edge area of ​​a rotating wafer using a predetermined nozzle.While the effectiveness of corrosion can be improved by using a spraying method, the high requirements for equipment design and components result in high equipment costs, and the high requirements for the process also lead to high processing costs.

[0005] Advanced wafer edge corrosion technologies and their equipment all require precise wafer positioning. This is because there is a growing demand for uniformity and range of wafer edge corrosion. When corroding a wafer edge, the uniformity of the corrosion width depends on whether the wafer is precisely positioned. Therefore, it is necessary to propose wafer positioning systems and methods that allow for constant fine-tuning. [Overview of the project] [Problems that the invention aims to solve]

[0006] The object of the present invention is to provide an improved wafer positioning system and method that allows for fine-tuning and calibration of the manipulator's positioning parameters, thereby enabling the manipulator to accurately mount the wafer in a predetermined position. [Means for solving the problem]

[0007] To achieve the above objective, a wafer positioning system is provided in a first example of the present invention. The wafer positioning system of the present invention includes a semiconductor processing apparatus, an image edge detection apparatus, a wafer transfer apparatus, and a positioning and calibration module. The semiconductor processing apparatus includes a lower cavity in which a first support area is formed and an upper cavity in which a second support area is formed. When the upper cavity and the lower cavity are joined, the wafer is mounted between the first support area and the second support area, a first passage is formed in the edge area of ​​the first or second support area, the first passage constitutes a first space, and the edge area of ​​the wafer is corroded by one or more chemical fluids injected into the first space. The wafer transfer apparatus includes a manipulator and a control device, the control device sets or updates a current position setting parameter, and the manipulator transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing apparatus, i.e., a position corresponding to the current position setting parameter, according to the set or updated current position setting parameter. The image edge detection apparatus obtains the corroded edge of the wafer by image acquisition and image recognition of the wafer mounted at the predetermined position and corroded according to the current position setting parameter. The positioning and calibration module calculates a position deviation parameter for the current position setting parameter based on the corrosion edge information of the wafer obtained by image recognition. The control device obtains an updated current position setting parameter by updating the current position setting parameter with the position deviation parameter, and controls the manipulator to move the wafer to a predetermined position on the first support area of ​​the lower cavity, i.e., a position corresponding to the updated current position setting parameter, based on the updated current position setting parameter.

[0008] To achieve the above objective, a wafer positioning method is further provided in a second example of the present invention. The wafer positioning method of the present invention includes the steps of: a manipulator moving a wafer to a predetermined position on the first support area of ​​the lower cavity of a semiconductor processing apparatus, i.e., a position corresponding to the current position setting parameter, based on a set or updated current position setting parameter; the semiconductor processing apparatus corroding the edge area of ​​the wafer; acquiring corroded edge information of the wafer by performing image acquisition and image recognition on the wafer that has been mounted at a predetermined position and corroded based on the current position setting parameter; a positioning and calibration module calculating a position deviation parameter of the current position setting parameter based on the acquired corroded edge information of the wafer; and a control device acquiring an updated current position setting parameter by updating the current position setting parameter with the position deviation parameter, and controlling the manipulator to move the wafer to a predetermined position on the first support area of ​​the lower cavity, i.e., a position corresponding to the updated current position setting parameter, based on the updated current position setting parameter. [Effects of the Invention]

[0009] Compared to conventional technologies, the wafer positioning system and method of the present invention acquires the corroded edge of a wafer by performing image recognition on a wafer that has been corroded, calculates a position deviation parameter of the current position setting parameter based on the corroded edge information of the wafer acquired by image recognition, and obtains the updated current position setting parameter by updating the current position setting parameter with the position deviation parameter. In other words, the present invention fine-tunes and calibrates the current position setting parameter of the manipulator based on the corroded edge information of the wafer. As a result, the manipulator can accurately mount the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing apparatus, and the corrosion of the wafer edge can be made more uniform.

[0010] It should be noted that the purpose of describing the outline of the invention is to provide a general understanding of the subject matter of the invention by referring to the outline of the embodiments of the invention. The embodiments are merely illustrative of the invention, and there is no intention to limit the scope or gist of the invention by the embodiments. The features, form, and effects of the invention relating to the embodiments of the invention can be easily understood by the following specific embodiments and drawings of the invention. That is, the principle of the invention will be explained in detail with reference to the drawings and embodiments of the invention. [Brief explanation of the drawing]

[0011] The present invention can be easily understood by referring to the drawings and detailed description below. The same reference numerals indicate the same structure in the drawings. [Figure 1a] A bottom view showing the structure of a semiconductor wafer. [Figure 1b] This is a cross-sectional view showing section AA in Figure 1a. [Figure 2a] This is a cross-sectional view showing a semiconductor processing apparatus according to an embodiment of the present invention. [Figure 2b] This is an enlarged view showing part A of Figure 2a. [Figure 2c] This is an enlarged view showing part B of Figure 2b. [Figure 2d] This is an enlarged view showing section C in Figure 2c. [Figure 2e] Figure 2a is a bottom view showing the upper cavity of the semiconductor processing unit. [Figure 2f] Figure 2a is a plan view showing the lower cavity of the semiconductor processing apparatus. [Figure 3] This figure shows a semiconductor processing system according to an embodiment of the present invention, which includes a semiconductor processing device and a material storage device. [Figure 4] This figure shows an exemplary method for processing the edge region of a semiconductor wafer using a semiconductor processing apparatus according to an embodiment of the present invention. [Figure 5] This is a block diagram of a wafer positioning system according to an embodiment of the present invention. [Figure 6] This is a perspective view showing an image edge detection device according to one embodiment of the present invention. [Figure 7] It is a side view showing the image edge detection device of FIG. 6. [Figure 8] It is a figure showing the result obtained by recognizing the wafer edge with respect to the collected image. [Figure 9] It is a comparison figure comparing the collected image of the corroded wafer of the present invention and its HLS image. [Figure 10] It is a figure showing a plurality of lines obtained by performing edge recognition on the HLS image. [Figure 11] It is a flowchart showing the method for measuring the corrosion edge of the wafer according to the embodiment of the present invention. [Figure 12] It is a plan view showing a 6-inch wafer with its edge corroded. [Figure 13] It is a plan view showing a wafer with a diameter of 8 inches or more and its edge corroded. [Figure 14] It is a flowchart showing the wafer positioning method according to the embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described in detail by referring to the drawings of the present invention. The following embodiments are only some of the embodiments of the present invention and do not represent all embodiments of the present invention. The embodiments of the present invention can further include various forms of embodiments in addition to the following embodiments. The purpose of providing the following embodiments is to explain the matters of the present invention in detail and to enable those skilled in the art to understand the matters of the present invention in detail. For example, unless otherwise specifically explained, terms with numbers such as first, second, etc. do not imply the order of matters. Although it is described that a certain component is above another component, (depending on the different observation directions) a certain component may be below another component (except when there is a specific explanation), and the reverse is also the same. Also, although it is described that a certain component is on the left side, (depending on the different observation directions) that component may be on the right side, and the reverse is also the same. Unless otherwise specifically explained, the same reference numerals always represent the same components.

[0013] Figures 1a and 1b show the structure of a semiconductor wafer 100. Figure 1a is a bottom view showing the structure of the semiconductor wafer 100, and Figure 1b is a cross-sectional view showing the AA section of Figure 1a. As shown in Figures 1a and 1b, the semiconductor wafer 100 includes a substrate 101 and a thin film layer 102 laminated on the upper surface of the substrate 101, and a portion of the substrate 101 can be covered by the thin film layer 102. In other embodiments, the entire substrate 101 can be covered by the thin film layer 102. In other embodiments, both sides of the surface of the substrate 101 can also be covered by the thin film layer 102.

[0014] In this embodiment, the edges of the thin film layer 102 on the substrate 101 are removed by processing the semiconductor wafer. As shown in Figures 1a and 1b, the radius of the thin film layer 102 is smaller than the radius of the substrate 101, and the corrosion width refers to the difference between the radius of the thin film layer 102 and the radius of the substrate 101. Measurement points 1 to 8 in Figure 1a are positions where predetermined values ​​of the semiconductor wafer are measured. The corrosion widths at measurement points 1 to 8 are approximately the same, and the smaller the difference between the maximum and minimum corrosion widths, the better the uniformity of the corrosion. For example, when the edge width is 0.7 mm, the difference between the maximum corrosion width and the minimum corrosion width is required to be 0.1 mm or less. In this embodiment of the present invention, part or all of the thin film layer 102 covering both sides of the surface of the substrate 101 is removed. The corrosion width on each side of the substrate 101 may be the same or different.

[0015] first part Referring to Figures 2a to 2f, these figures show the structure of a semiconductor processing apparatus 200 according to an embodiment of the present invention. Figure 2a is a cross-sectional view of the semiconductor processing apparatus 200, Figure 2b is an enlarged view of part A of Figure 2a, Figure 2c is an enlarged view of part B of Figure 2b (through holes omitted), Figure 2d is an enlarged view of part C of Figure 2c, Figure 2e is a bottom view showing the upper cavity 220 of the semiconductor processing apparatus 200 in Figure 2a, and Figure 2f is a plan view showing the lower cavity 210 of the semiconductor processing apparatus 200 in Figure 2a.

[0016] In an embodiment of the present invention, as shown in Figures 1 and 2a-2f, the semiconductor processing apparatus 200 includes a lower cavity 210 in which a first support area 212 is formed. The first support area 212 can support a wafer 100. As shown in Figure 2a, the first support area 212 has an upper surface facing the wafer 100. The wafer 100 can be mounted on the upper surface of the first support area 212. In an embodiment of the present invention, the semiconductor processing apparatus 200 includes an upper cavity 220 in which a second support area 222 is formed. As shown in Figure 2a, the second support area 222 has a lower surface facing the wafer 100. When the upper cavity 220 and the lower cavity 210 are joined, the wafer 100 is mounted between the first support area 212 and the second support area 222. The upper cavity 220 can move between two positions relative to the lower cavity 210. When the upper cavity 220 is in the first position, the wafer 100 can be mounted on or removed from the first support area 212. As shown in Figure 2a, when the upper cavity 220 is in the second position, the upper cavity 220 and the lower cavity 210 are coupled, and the wafer 100 can be processed by fixing it between the upper surface of the first support area 212 and the lower surface of the second support area 222. In an embodiment of the present invention, the upper cavity 220 can move between the two positions by drive, and the lower cavity 210 can remain stationary. In another embodiment, the lower cavity 210 can move between the two positions by drive, and the upper cavity 220 can remain stationary, or the upper cavity 220 and the lower cavity 210 can move simultaneously by drive.

[0017] In one embodiment or a combination of embodiments of the present invention, referring to Figures 2a to 2c, the semiconductor processing apparatus 200 includes a first passage 230 which is composed of the peripheral area of ​​a first support area 212 or a second support area 222. The first passage 230 constitutes a first space 232, and the peripheral area of ​​the wafer 100 can be corroded by injecting one or more types of chemical fluids into the first space 232. Referring to Figures 2a to 2c, the first passage 230 is composed of the peripheral area of ​​the second support portion 222 of the upper cavity 220. The first passage 230 is formed on the lower surface of the upper cavity 220, and one opening of the first passage 230 faces the wafer 100. In this embodiment, the first passage 230 constitutes a first space 232, and the peripheral area of ​​the wafer 100 can be corroded by injecting one or more types of chemical fluids into the first space 232. Referring to Figures 2a to 2c, the first space 232 is composed of the first passage 230 and the inner surface of the wafer 100. In this embodiment, the first passage 230 is formed in an annular shape and is formed to surround the peripheral area of ​​the wafer 100. The entire peripheral area of ​​the wafer 100 is housed within the first space 232. In other embodiments, the first passage 230 is formed in an arc shape with an angle of 360° or less, and the peripheral area of ​​the wafer 100 can be housed within a predetermined area of ​​the first space 232. One or more chemical fluids can flow in the arc portion of the first space 232 to corrode the peripheral area of ​​the wafer 100.

[0018] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, referring to Figures 2a to 2c, the upper cavity 220 includes a protrusion 240 that abuts against the edge of the wafer 100. The protrusion 240 can directly contact and abut against the edge of the wafer 100. Referring to Figure 2a, the central axis XX of the wafer 100 is perpendicular to the upper surface of the wafer 100, and the central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the second support area 222. The protrusion 240 allows the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 to overlap. When the upper cavity 220 is in the first position, the wafer 100 is mounted on the first support area 212. The central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 do not necessarily have to overlap. When the upper cavity 220 moves from the first position to the second position, the protrusion 240 contacts the edge of the wafer 100 and then abuts against the edge of the wafer 100, thereby moving the wafer 100 on the upper surface of the first support area 212. When the upper cavity 220 is in the second position, the wafer 100 is fixed on the upper surface of the first support area 212, and the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 are either aligned in parallel or overlap.

[0019] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, the protrusion 240 is adjacent to the second support area 222 and extends toward the lower cavity 210. Referring to Figures 2a and 2b, the protrusion 240 is connected to the second support area 222. When the upper cavity 220 is in the second position, the protrusion 240 extends toward the lower cavity 210. Referring to Figures 2a and 2b, in this embodiment, the protrusion 240 is located beside the first passage 230. Referring to Figure 2a, the central axis XX of the wafer 100 is perpendicular to the upper surface of the wafer 100, the central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the second support area 222, and the upper surface of the wafer 100 is parallel to the lower surface of the second support area 222. In an embodiment of the present invention, when the upper cavity 220 is in the second position, a portion of the upper surface of the wafer 100 overlaps with the lower surface of the second support area 222, and the central axis XX of the wafer 100 overlaps with the central axis X'-X' of the second support area 222.

[0020] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, the protrusion 240 can be a closed loop surrounding the wafer 100. Referring to Figure 2a, the protrusion 240 includes a closed loop. The closed loop surrounds the entire edge region of the wafer 100. By the protrusion 240 contacting the edge region of the wafer 100, the central axis XX of the wafer 100 and the central axis X'-X' of the second support region 222 can be superimposed. In other embodiments, the closed loop is an arc shape with a holding angle of 360° or less, and a predetermined portion of the closed loop can contact the edge region of the wafer 100. By forming the protrusion 240, the central axis XX of the wafer 100 and the central axis X'-X' of the second support region 222 can be aligned in parallel or superimposed. In other embodiments, the protrusion 240 can also be an open loop.

[0021] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, the protrusion 240 includes an interior angle facing the central axis X'-X' of the second support area 222. Referring to Figure 2c, the protrusion 240 includes an inner surface 242, and the angle between the inner surface 242 and the first reference direction Y-Y is α. The first reference direction Y-Y is parallel to the lower surface of the second support area 222. The range of the angle α is 20° to 90°. As shown in Figures 2b and 2c, the interior angle is formed by the inner surface 242 of the protrusion 240 and the inner surface of the first passage 230 and faces the central axis X'-X' of the second support area 222. In the embodiment of the present invention, the interior angle abuts the edge area of ​​the wafer 100. As shown in Figure 2b, when the upper cavity 220 moves from the first position to the second position, the inner angle of the protrusion 240 contacts the edge of the wafer 100 and then abuts against the edge of the wafer 100, thereby moving the wafer 100. When the upper cavity 220 is in the second position, the wafer 100 is fixed on the upper surface of the first support area 212, and the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 are either aligned in parallel or can overlap.

[0022] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, the first tank 250 is composed of the peripheral region 214 of the lower cavity 210, and one or more chemical fluids can flow in the first tank space 252 formed by the first tank 250. Referring to Figures 2a, 2b, and 2f, the first tank 250 is composed of the peripheral region 214 of the lower cavity 210 and is close to the first support region 212 of the lower cavity 210. By forming the first tank space 252 with the first tank 250, one or more chemical fluids can flow from the first space 232 of the first passage 230 into the first tank space 252.

[0023] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, the passage 260 is located between the upper cavity 220 and the lower cavity 210. Referring to Figures 2b and 2f, the lower cavity 210 has a first upper surface 262 located between the first support area 212 and the first tank 250. The passage 260 is located between the first upper surface 262 of the lower cavity 210 and the inner surface 242 of the protrusion 240. By connecting the first space 232 and the first tank space 252, the passage 260 allows one or more chemical fluids to flow from the first space 232 to the first tank space 252 through the passage 260. In an embodiment of the present invention, the passage 260 can be blocked by the protrusion 240, thereby preventing one or more chemical fluids from flowing from the first space 232 to the first tank space 252. In other embodiments, the passage 260 can be blocked by the first support area 212, thereby preventing one or more chemical fluids from flowing from the first space 232 to the first tank space 252.

[0024] In a semiconductor processing apparatus 200 according to one embodiment or a combination of embodiments of the present invention, as shown in Figures 2a to 2c, the first passage 230 is located in the peripheral area of ​​the second support area 222. The upper cavity 220 includes a first through-hole 270 through which one or more chemical fluids can flow between the first space 232 and the outside of the semiconductor processing apparatus 200. The first through-hole 270 penetrates the upper cavity 220 from the outside of the semiconductor processing apparatus 200 and is then connected in communication with the first space 232. In embodiments of the present invention, one or more chemical fluids can flow between the first space 232 and the outside of the semiconductor processing apparatus 200 through the first through-hole 270. In other embodiments, the upper cavity 220 may include two or more through-holes similar to the first through-hole 270 (for example, it may include other first through-holes 272 in Figures 2a and 2e). In this embodiment, at least one first through-hole (e.g., first through-hole 270) can be used as an inlet, and another first through-hole (e.g., another first through-hole 272) can be used as an outlet. The first space 232 can be connected to the outside in communication with the outside by the first through-hole 270 and the other first through-hole 272. In this embodiment, one or more chemical fluids can flow from outside the semiconductor processing apparatus 200 into the first space 232 of the first passage 230 through the first through-hole 270, and from the first space 232 to outside the semiconductor processing apparatus 200 through the other first through-hole 272.

[0025] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, the second passage 280 is composed of the peripheral area of ​​the first support area 212, and the peripheral area of ​​the wafer 100 can be corroded by injecting one or more types of chemical fluids into the second space 282 of the second passage 280. Referring to Figures 2a to 2c, the second passage 280 is composed of the peripheral area of ​​the first support area 212 of the lower cavity 210. Referring to Figures 2a to 2c, the second passage 280 is formed on the upper surface of the lower cavity 210, and one side opening of the second passage 280 faces the wafer 100. In this embodiment, the second space 282 is composed of the second passage 280, and the peripheral area of ​​the wafer 100 can be corroded by injecting one or more types of chemical fluids into the second space 282. Referring to Figures 2a to 2c, the second space 282 can be composed of the inner surface of the second passage 280 and the wafer 100. In an embodiment of the present invention, the second passage 280 is formed in an annular shape and is formed to surround the peripheral area of ​​the wafer 100. In another embodiment, the second passage 280 is formed in an arc shape with an angle of 360° or less, and the peripheral area of ​​the wafer 100 can be exposed to a predetermined area of ​​the second space 282. In that case, one or more chemical fluids can flow in the arc portion of the second space 282 to corrode the peripheral area of ​​the wafer 100. In an embodiment of the present invention, the shape of the second passage 280 and the shape of the first passage 230 can be designed similarly. The second passage 280 is close to the first upper surface 262 and is located between the first support area 212 and the first tank 250. The passage 260 is located between the first upper surface 262 of the lower cavity 210 and the inner surface 242 of the upper cavity 220. Because the passage 260 is formed, one or more chemical fluids can flow from the second space 282 to the first tank space 252 through the passage 260. In one embodiment of the present invention, the convex portion 240 blocks the passage 260, thereby preventing one or more types of chemical fluids from flowing from the second space 282 to the first tank space 252. In another embodiment, the first support area 212 blocks the passage 260, thereby preventing one or more types of chemical fluids from flowing from the second space 282 to the first tank space 252.

[0026] In a semiconductor processing apparatus 200 according to one embodiment or a combination of multiple embodiments of the present invention, a second through-hole 290 is formed in the lower cavity 210, allowing one or more chemical fluids to flow between the second space 282 and the outside of the semiconductor processing apparatus 200. Referring to Figures 2a and 2b, the second through-hole 290 penetrates the lower cavity 210 from the outside of the semiconductor processing apparatus 200 and is connected in communication with the second space 282 of the second passage 280. In an embodiment of the present invention, one or more chemical fluids can flow between the second space 282 and the outside of the semiconductor processing apparatus 200 through the second through-hole 290. In another embodiment, one or more chemical fluids can flow from the outside of the semiconductor processing apparatus 200 through the second through-hole 290 into the second space 282 of the second passage 280, and then flow from the second space 282 of the second passage 280 into the first tank space 252 of the first tank 250 via the passage 260. In other embodiments, the lower cavity 210 may further include one or more second through holes similar to the second through hole 290 (for example, it may further include other second through holes 292 in Figure 2a). In that case, at least one second through hole (e.g., second through hole 290) may be used as an inlet and other first through holes (e.g., other second through holes 292) may be used as outlets. The second space 282 may be connected to the outside in communication with the outside by the second through hole 290 and other second through holes 292. In this embodiment, one or more chemical fluids may flow from outside the semiconductor processing apparatus 200 into the second space 282 of the second passage 280 through the second through hole 290, and then flow from the second space 282 to outside the semiconductor processing apparatus 200 through other second through holes 292. In other embodiments, one or more chemical fluids can flow from outside the semiconductor processing apparatus 200 through the second through-hole 290 and other second through-holes 292 into the second space 282 of the second passage 280, and then flow from the second space 282 of the second passage 280 into the first tank space 252 of the first tank 250 through the passage 260.

[0027] Figure 3 shows a semiconductor processing system 300 according to an embodiment of the present invention, which includes a semiconductor processing apparatus 310 and a material storage apparatus 320. The semiconductor processing apparatus 310 can refer to the semiconductor processing apparatus 200 shown in Figures 2a to 2f. The semiconductor processing apparatus 310 includes a lower cavity in which a first support area for supporting a wafer is formed, and an upper cavity in which a second support area is formed. By joining the upper cavity and the lower cavity, the wafer can be fixed between the first support area and the second support area. The first passage is located in the peripheral area of ​​the first support area or the second support area, and the first passage constitutes a first space. By injecting one or more types of chemical fluids into the first space, the peripheral area of ​​the wafer can be corroded. In the embodiment of the present invention, the upper cavity includes a convex portion, and by the convex portion contacting the edge of the wafer, the central axis of the wafer and the central axis of the second support area can be superimposed. The material storage device 320 is connected to the semiconductor processing device 310, and the material storage device 320 stores one or more types of chemical fluids and facilitates the flow of one or more types of chemical fluids between the semiconductor processing device 510 and the material storage device 520. In the embodiments of the present invention, one or more types of chemical fluids can be H3PO4, HF, HCl, HNO3, H2O2, or a combination thereof.

[0028] In a semiconductor processing system 300 according to one embodiment or a combination of multiple embodiments of the present invention, the convex portion is adjacent to the second support area and extends in a direction toward the lower cavity. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second support area. In the embodiment of the present invention, the convex portion includes a closed loop surrounding the wafer, and the central axis of the wafer and the central axis of the second support area can be superimposed by the convex portion evenly contacting the edge area of ​​the wafer.

[0029] In a semiconductor processing system 300 according to one embodiment or a combination of multiple embodiments of the present invention, the convex portion is adjacent to the second support area and extends in a direction toward the lower cavity. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second support area. In the embodiment of the present invention, the convex portion includes a plurality of protrusions arranged in an annular manner around the wafer, and the plurality of protrusions evenly abut the peripheral area of ​​the wafer.

[0030] In a semiconductor processing system 300 according to one embodiment or a combination of multiple embodiments of the present invention, a first tank is formed in the peripheral area of ​​the lower cavity, and one or more types of chemical fluids can flow within the space of the first tank, which is formed by the first tank. In an embodiment of the present invention, a passage is formed between the upper cavity and the lower cavity, and the first space and the first tank space are connected by the passage, so that one or more types of chemical fluids can flow from the first space to the first tank space through the passage. In an embodiment of the present invention, a second tank is formed in the peripheral area of ​​the upper cavity, and the second tank is positioned above the first tank. In an embodiment of the present invention, an elastic component is installed between the first tank and the second tank, and the elastic component can prevent one or more types of chemical fluids from flowing from the first space to the first tank space.

[0031] In a semiconductor processing system 300 according to one embodiment or a combination of multiple embodiments of the present invention, the semiconductor processing system 300 includes a control device 330. The control device 330 can communicate with and control a semiconductor processing apparatus 310 and a material storage apparatus 320. For example, the control device 330 can control the movement of the upper cavity between a first position for loading or removing a wafer and a second position for processing the wafer by combining the upper cavity and the lower cavity. The control device 330 can also control the flow velocity and flow direction of one or more chemical fluids. The control device 330 can detect the flow velocity, flow direction, state of one or more chemical fluids and failures of the semiconductor processing apparatus 310. In embodiments of the present invention, the control device may include a PLC, a control unit, sensors, and a storage device (e.g., memory, hard disk drive, SSD, etc.).

[0032] Figure 4 shows an exemplary method 400 for processing the edge region of a semiconductor wafer 100 using a semiconductor processing apparatus according to an embodiment of the present invention. The method can use the semiconductor processing system shown in Figures 2a to 2f and Figure 3.

[0033] In step 402 of Figure 4, according to an embodiment of the present invention, the semiconductor processing apparatus 200 places the fed wafer on the first support area of ​​the lower cavity. In step 404, the semiconductor processing apparatus fixes the wafer between the first support area and the second support area of ​​the upper cavity by joining the upper cavity and the lower cavity. In step 406, a first passage is formed in the edge area of ​​the first support area or the second support area, and a first space is formed in the first passage. In step 408, the semiconductor processing apparatus superimposes the central axis of the wafer and the central axis of the second support area by bringing a protrusion into contact with the edge area of ​​the wafer. In step 410, the semiconductor processing apparatus corrodes the edge area of ​​the wafer by injecting one or more types of chemical fluids into the first space.

[0034] In step 402 of method 400 according to one embodiment or a combination of embodiments of the present invention, a wafer is fed onto a first support area of ​​the lower cavity of the semiconductor processing apparatus 200 by a wafer transfer device. The upper surface of the first support area faces the wafer. When the wafer transfer device feeds the wafer onto the upper surface of the first support area, a portion of the lower surface of the wafer is covered by the upper surface of the first support area. In the embodiment of the present invention, when the upper cavity of the semiconductor processing apparatus 200 is in a first position, the wafer can be mounted on or removed from the first support area. That is, the wafer can be fed from the wafer transfer device onto the upper surface of the first support area.

[0035] In step 404 of method 400 according to one embodiment or a combination of embodiments of the present invention, the semiconductor processing apparatus 200 fixes the wafer between a first support area and a second support area of ​​the upper cavity by coupling the upper cavity and the lower cavity. When the upper cavity is in the second position, the wafer is fixed between the first support area and the second support area by coupling the upper cavity and the lower cavity, thereby enabling processing of the edge area of ​​the wafer. The upper cavity includes a second support area facing the lower surface of the wafer. By coupling the upper cavity and the lower cavity, the wafer can be fixed between the first support area and the second support area. That is, the wafer can be fixed between the lower surface of the first support area and the upper surface of the second support area.

[0036] In step 406 of method 400 according to one embodiment or a combination of embodiments of the present invention, a first passage is formed in the peripheral area of ​​a first support area or a second support area. The first passage may also be formed on the lower surface of the upper cavity. The opening of the first passage faces the wafer. In embodiments of the present invention, the first passage forms a first space, in which the peripheral area of ​​the wafer can be processed. For example, the peripheral area of ​​the wafer is corroded by injecting one or more chemical fluids into the first space. In embodiments of the present invention, the first passage may be designed as a closed loop. In embodiments of the present invention, the first passage may also be designed as a circle. The semiconductor processing apparatus 200 or wafer transfer apparatus can feed all or part of the peripheral area of ​​the wafer into the first space for processing. In embodiments of the present invention, the first passage may be formed as an arc with a leading angle of 360° or less. The semiconductor processing apparatus 200 or wafer transfer apparatus can feed a portion of the peripheral area of ​​the wafer into the first space for processing.

[0037] A protrusion is formed in the upper cavity or lower cavity of the semiconductor processing apparatus 200 used in step 408 of Method 400 according to one embodiment or a combination of embodiments of the present invention. The semiconductor processing apparatus can bring the protrusion into contact with the edge area of ​​the wafer. When the upper cavity moves from a first position to a second position, the protrusion comes into contact with the edge of the wafer. Subsequently, by bringing the protrusion into contact with the edge of the wafer, the wafer can be moved on the upper surface of the first support area of ​​the lower cavity. When the upper cavity and the lower cavity are joined, the wafer is fixed on the upper surface of the first support area, and the central axis XX of the wafer and the central axis X'-X' of the second support area are aligned parallel to each other. The distance between the central axis XX of the wafer and the central axis X'-X' of the second support area is 0 mm to 0.1 mm. In embodiments of the present invention, the protrusion is adjacent to the second support area and extends toward the lower cavity. In embodiments of the present invention, the protrusion is located near the first passage.

[0038] In embodiments of the present invention, the convex portion includes an interior angle opposite the central axis X'-X' of the second support area. The interior angle is formed by the inner surface of the convex portion and the inner surface of the first passage and is opposite the central axis X'-X' of the second support area. In embodiments of the present invention, the interior angle abuts against the edge area of ​​the wafer. When the upper cavity moves from the first position to the second position, the wafer can be moved by the interior angle of the convex portion contacting the edge of the wafer and then abutting against the edge of the wafer. In other embodiments, the wafer can also be moved by the inner surface of the convex portion contacting the edge of the wafer and then abutting against the edge of the wafer.

[0039] In step 410 of method 400 according to one embodiment or a combination of embodiments of the present invention, the semiconductor processing apparatus 200 corrodes the edge region of a wafer by injecting one or more types of chemical fluids into a first space. The one or more types of chemical fluids can corrode the edge region of the wafer exposed in the first space by flowing in a direction around the edge of the wafer in the first space. In embodiments of the present invention, the semiconductor processing apparatus includes through holes that connect the first space to the outside of the semiconductor processing apparatus in a communication manner. One or more types of chemical fluids can flow into the first space through the through holes. In embodiments of the present invention, one or more types of chemical fluids can flow from the first space to the outside of the semiconductor processing apparatus through the through holes. In other embodiments, the semiconductor processing apparatus includes two through holes, each of which is connected to the first space and the outside of the semiconductor processing apparatus in a communication manner. The two through holes are separated by a predetermined distance, and one or more types of chemical fluids can flow into the first space through one through hole and out of the first space to the outside of the semiconductor processing apparatus through the other through hole.

[0040] second part The method for determining the position of the cavity center shown in Figures 2a to 2f is adopted. That is, the cavity structure, protrusions, etc., ensure that the center of the wafer and the center of the cavity overlap. However, when the wafer is held between the protrusions 240, there is a risk that the portion of the wafer in contact with the protrusions 240 may not be corroded. Therefore, it is necessary to provide a new wafer positioning method. In the new wafer positioning method, it is not necessary to form the protrusions 240 that determine the position of the wafer, but forming the protrusions 240 can also support the positioning of the wafer.

[0041] Figure 5 is a block diagram showing the wafer positioning system of the present invention. As shown in Figure 5, the wafer positioning system includes a semiconductor processing apparatus 610, an image edge detection device 500, a positioning calibration module 620, and a wafer transfer device 630. The semiconductor processing apparatus 610 is a part of the semiconductor processing apparatus 200, and the semiconductor processing apparatus 610 can corrode the edge of the wafer 100. The semiconductor processing apparatus 610 can also be a modified version of the semiconductor processing apparatus 200. For example, it can be a semiconductor processing apparatus 200 in which no protrusions for determining the position of the wafer 100 are formed. In an embodiment of the present invention, the positioning calibration module 620 can be integrated with the image edge detection device 500, or the positioning calibration module 620 can be integrated with the wafer transfer device. In another embodiment, the positioning calibration module 620, the image edge detection device 500, and the wafer transfer device 630 can be integrated together.

[0042] The image edge detection device 500 can quickly detect the corrosion effect on the wafer edge by capturing an image of the edge of the wafer 100 that has been corroded, thereby enabling evaluation of the corrosion effect on the wafer edge of the wafer 100. The wafer transfer device 630 can transfer the wafer 100 from the semiconductor processing apparatus 610 that has been corroded to the image edge detection device 500.

[0043] Figure 6 is a perspective view showing an image edge detection device 500 according to one embodiment of the present invention, Figure 7 is a side view showing the image edge detection device 500 of Figure 6, and Figure 8 is a diagram showing the results obtained by recognizing the wafer edge (hereinafter abbreviated as edge recognition) on the collected image.

[0044] As shown in Figures 6 and 7, the image edge detection device 500 includes a line scanning camera 510, a light source 520, a rotating device 530, a positioning device 540, an alignment device (not shown), and an image processing unit (not shown).

[0045] The rotating device 530 supports the wafer 100 and can drive the wafer 100 to rotate around the rotation axis. The alignment device ensures that the center of the wafer and the rotation center of the rotating device overlap. The line scan camera 510 is positioned on the edge of the wafer 100. When the wafer 100 rotates, the line scan camera 510 collects an image of the wafer using a line scan method and stops collecting images when the collected image reaches a preset height. The image processing unit is electrically connected to the line scan camera 510 and obtains a first line indicating the edge of the corroded thin film layer and a second line indicating the wafer edge by performing edge recognition in a specific area of ​​the collected image. The image processing unit can recognize the wafer edge by employing various methods of the prior art. In Figure 8, P2 is the thin film layer (area where corrosion is not performed) and P1 is the substrate (area where the edge is corroded). As shown in Figure 8, when the grayscale of the corrosion edge (i.e., the area where corrosion has been carried out and the area where corrosion has not been carried out) changes abruptly, the first line L1 and the second line L2 can be recognized by the abrupt change in the grayscale. In the present invention, the image processing algorithms of the image processing unit can be simplified by converting the plane rectangular coordinate system of the imaging data to a polar coordinate system using the line scanning method.

[0046] The light source 520 is a light source that supplies light rays directed towards the scanning of the line scan camera 510. The positioning device 540 determines the position of the wafer by recognizing the positioning notch and wafer flat of the wafer. The line scan camera 510 can collect images of the wafer at various positions. For example, it can collect images after rotating the wafer by 90 degrees, 120 degrees, 180 degrees, etc., from the positioning notch or wafer flat. This allows for sampling at fixed positions or random positions.

[0047] When the rotating device 530 rotates, it outputs a synchronous pulse signal to the line scan camera 510, which then performs scanning and sampling. The preset height is 1 / N of the circumference of the wafer 100, where N can be a value greater than or equal to 1, such as 20. The length of the collected image can be set by setting N. N can be set to a large value to accelerate the detection speed.

[0048] The image processing unit can detect the distance between the first line L1 and the second line L2, and the roughness of the first line L1. The distance indicates the width of the corrosion, and the roughness of the first line L1 indicates the smoothness of the corrosion edge. The roughness of the first line L1 can be indicated by the error of the root mean square of the first line L1.

[0049] The image processing unit further recognizes the third line L3. Both the second line L2 and the third line L3 are edges of the wafer. Because the wafer edge is composed of arcs (not straight lines), the image processing unit may detect two lines. In that case, it is usually determined that only the third line L3 is the outermost edge of the wafer. In other embodiments, either the second line L2 or the third line L3 can be recognized by adjusting the light source or by other means. For example, the corrosion width of the wafer edge can be represented by the distance between the third line L3 and the first line L1. In that case, only one of the second line L2 or the third line L3 can be recognized. The first line L1, the second line L2, and the third line L3 can be straight lines or curves similar to straight lines. Most of the pixel points after magnification are not arranged in straight lines but in curves similar to straight lines. That is, the pixel points in the row above are arranged in curves similar to straight lines.

[0050] The embodiments of the present invention will be described in more detail below.

[0051] In 12-inch wafers, once the wafer edge corrosion process is complete, it is necessary to collect information and take measurements to understand the formation of the oxide layer and corrosion edge at the wafer edge. This allows for the determination of the stability of the wafer support structure and whether the final processing process meets the required specifications. Visual inspection of the edge corrosion results plays a crucial role in the processing of the entire wafer (wafer disk or wafer). This provides a strong calibration standard for the processing process of the entire apparatus and can improve the functionality of the processing apparatus. If an abnormality occurs in the process, the processing can be stopped, thus preventing the damage of a large number of wafers due to equipment malfunctions.

[0052] By taking photographs of the edges of a processed 12-inch wafer using a predetermined camera and light source, a three-level grayscale image is formed. Specifically, a three-level grayscale image is formed consisting of the wafer's corrosion layer, substrate, and bevel. By fitting the edges of each layer using an image algorithm, the edge contour can be detected. The width of each layer of the processed wafer can vary within a certain range, and this range of variation must not exceed the maximum permissible error of the processing step.

[0053] The current image edge detection device 500 can achieve an ideal minimum detection value of 3.5 micrometers. However, due to distortion when using an industrial camera and contamination of the image by the nozzle during image capture, the actual minimum detection value of the image edge detection device 500 can reach ±10 micrometers. While the ideal image edge detection device 500 can detect one wafer per minute, the detection time of the image edge detection device 500 can be reduced to a shorter duration.

[0054] The Line Scan Camera 510 can acquire clear, high-amplitude image content in a very short time. After image acquisition, noise reduction and enhancement are performed on the acquired images using a dedicated Visual Processing Library. Next, the main contour is detected, and keypoints are detected within the detected clear contour. The necessary boundary lines are fitted using the least squares method with the detected keypoints. Finally, three lines L1, L2, and L3 are obtained through fitting.

[0055] third part However, in wafers with different specifications, whether or not the substrate surface is polished significantly affects the single-channel grayscale value. For example, the grayscale value of the corrosion area of ​​a wafer that is not polished can reach 120-180, while the grayscale value of the corrosion area of ​​another wafer that is not polished can reach 70-100. Since the grayscale value of the corrosion area of ​​a wafer that is polished can reach 200-255, a method of inspecting the edges using grayscale values ​​can be adopted. Because the upper and lower limits differ for various wafers, inspection cannot be performed without manually setting parameters, which leads to increased costs.

[0056] In an embodiment of the present invention, an improved wafer corrosion edge measurement method 700 is further provided. The corrosion edge detection method 700 can measure wafers with corroded edges. The corrosion edge measurement method 700 is performed by the image processing unit of the image edge detection device 500. Figure 11 is a flowchart showing the wafer corrosion edge measurement method 700 according to an embodiment of the present invention. As shown in Figure 11, the method includes the following steps.

[0057] In step 710, an image of the wafer with corroded edges is collected.

[0058] In step 720, the collected wafer image is converted into an HLS image.

[0059] In HLS, H represents color tone, L represents brightness, and S represents saturation.

[0060] Regardless of whether the wafer is polished or not, all corroded areas of the wafer have a specific color tone value, and the entire corroded area of ​​the wafer is biased towards green (or has a color similar to green). Figure 9 is a comparison diagram showing a sample image of a corroded wafer and its HLS image. The image on the left is the sample image (i.e., the original image), and the image on the right is the HLS image. The corroded areas in the HLS image are biased towards green. In this embodiment, the corroded areas of the wafer can be determined by H (color tone) and L (luminance). This method can determine the corroded areas of the wafer more accurately than the method that uses only grayscale values.

[0061] In step 730, after detecting pixel points in the HLS image where the brightness value L is less than or equal to a preset brightness threshold and the hue value H is less than or equal to a preset hue threshold, these are concatenated and denoised to obtain the bevel area and the contour lines on both sides of the bevel area. As shown in Figure 10, L11 is the outer edge contour line of the bevel area, and L12 is the inner edge contour line of the bevel area. When the range of brightness and hue values ​​is 0 to 255, the preset brightness threshold can be, for example, 10, and the preset hue threshold can be, for example, 8 or 0.

[0062] In step 740, the bevel region of the HLS image is roughly defined into bevel region A1, corroded region A2, and uncorroded region A3 based on the luminance value. As shown in Figure 10, a region with a pre-set size is selected within the corroded region to be used as a corroded region sample, and the upper limit value and lower limit value of luminance L, and the upper limit value and lower limit value of color tone H are obtained from this corroded region sample. As shown in Figure 10, line L13 is the corroded region sample.

[0063] In step 750, the HLS image is binarized using the upper and lower limits of luminance L and hue H, and then enlarged and stitched together to obtain the final contour of the corroded area. This final contour includes the corrosion boundary line located between the corroded and uncorroded areas. As shown in Figure 10, L14 is the corrosion boundary line.

[0064] The aforementioned corrosion boundary line allows for various calculations, such as the calculation of corrosion width and corrosion roughness.

[0065] In the embodiment of the present invention, after determining the upper and lower limits of H (color tone) and L (luminance) of the corroded area using an automatic sampling method, the accurate contour of the corroded area can be obtained. In other words, the present invention allows for the acquisition of appropriate grayscale values ​​without manually setting parameters. Furthermore, compared to using a single channel, using two channels allows for the acquisition of an even more accurate contour.

[0066] Fourth part As shown in Figure 12, Figure 12 is a plan view showing a 6-inch wafer with corroded edges. As shown in Figure 12, the wafer includes a single wafer flat 810, an outer edge contour line 820 located at the outermost edge, and a corrosion boundary line 830 located on the inside. The corrosion boundary line 830 can be the corrosion boundary line L14 obtained by image recognition and shown in Figure 10, and the outer edge contour line 820 can be the outer edge contour line L11 obtained by image recognition and shown in Figure 10. Although Figure 12 schematically shows the entire outer edge contour line 820 and the entire corrosion boundary line 830 of the wafer, in a specific embodiment, the image edge detection device can detect only a part of the outer edge contour line 820 and a part of the corrosion boundary line 830 by the image recognition means. As shown in Figure 12, when the position of the center of the wafer is accurately determined and the entire edge of the wafer is corroded uniformly, that is, when the corrosion widths of the 10 measurement points 1 to 10 in Figure 12 are the same, it is possible to determine whether the position of the wafer can be accurately determined by detecting the corrosion width of each measurement point.

[0067] As described above, the wafer positioning system includes a positioning and calibration module 620 and a wafer transfer device 630.

[0068] The wafer transfer device 630 includes a manipulator and a control device, the control device sets or updates a configuration parameter, and the positioning and calibration module transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing device 610, i.e., to a position corresponding to the configuration parameter, based on the set or updated configuration parameter. As described above, the semiconductor processing device 610 can corrode the edges of wafers mounted inside the semiconductor processing device. As described above, the image edge detection device 500 can acquire the corroded edges of the wafer by performing image acquisition and image recognition on the wafer that has been mounted at a predetermined position and corroded according to the configuration parameter. The corroded edges can be determined by the outer edge contour line and the corrosion boundary line or by other means.

[0069] The positioning and calibration module 620 calculates a position deviation parameter for the current position setting parameter based on the corrosion edge information of the wafer obtained by image recognition. The control device of the wafer transfer device 630 obtains an updated current position setting parameter by updating the current position setting parameter with the position deviation parameter, and controls the manipulator to transfer the wafer to a predetermined position on the first support area of ​​the lower cavity, i.e., a position corresponding to the updated current position setting parameter, based on the updated current position setting parameter.

[0070] In an embodiment of the present invention, the positioning and calibration module 620 calculates the position deviation parameter of the current position setting parameter and then determines whether the position deviation parameter falls within a preset position deviation range. If the position deviation parameter falls within the preset position deviation range, the update of the current position setting parameter is stopped. If the position deviation parameter does not fall within the preset position deviation range, the current position setting parameter is updated using the position deviation parameter. Next, the corrosion edge of the wafer is acquired again using the updated current position setting parameter, the position deviation parameter of the updated current position setting parameter is calculated again, and the above step is repeated until the position deviation parameter corresponding to the updated current position setting parameter falls within the preset position deviation range.

[0071] In an embodiment of the present invention, the positioning and calibration module 620 calculates the corrosion width of multiple measurement points on the wafer based on the corrosion edge information of the wafer obtained by image recognition, and calculates the position deviation parameter based on the corrosion width of the multiple measurement points. As shown in Figure 12, Figure 12 is a plan view showing a 6-inch wafer with a corroded edge. As shown in Figure 13, Figure 13 is a plan view showing an 8-inch or larger wafer with a corroded edge. Figure 12 shows 10 measurement points, i.e., measurement points 1 to 10, and Figure 13 shows 8 measurement points, i.e., measurement points 1 to 8. As shown in Figure 12, the wafer comprises a wafer flat 810, and as shown in Figure 13, the wafer comprises a positioning notch 850.

[0072] The position deviation parameter includes a distance deviation Δx in the first direction and a distance deviation Δy in the second direction, and the current position setting parameter includes a position coordinate x1 in the first direction and a position coordinate y1 in the second direction, with the first and second directions being perpendicular. In this embodiment, the first direction can be the X-axis direction and the second direction can be the Y-axis direction. Specifically, the distance deviation Δx in the first direction of the position deviation parameter represents a positioning deviation where the center of the wafer and the center of the first support area are misaligned in the first direction (hereinafter abbreviated as the first-direction positioning deviation), and the distance deviation Δy in the second direction of the position deviation parameter can represent a positioning deviation where the center of the wafer and the center of the first support area are misaligned in the second direction (hereinafter abbreviated as the second-direction positioning deviation). The first-direction position coordinate of the updated current position setting parameter can be obtained using the first-direction position coordinate x1 of the current position setting parameter and the first-direction distance deviation Δx of the position deviation parameter. The second-direction position coordinate of the updated current position setting parameter can be obtained using the second-direction position coordinate y1 of the current position setting parameter and the second-direction distance deviation Δy of the position deviation parameter.

[0073] The aforementioned multiple measurement points include multiple pairs of measurement points. As shown in Figure 12, measurement points 4 and 8 form a pair, measurement points 5 and 9 form a pair, measurement points 2 and 7 form a pair, and measurement points 6 and 10 form a pair. As shown in Figure 13, measurement points 1 and 5 form a pair, measurement points 2 and 6 form a pair, measurement points 3 and 7 form a pair, and measurement points 4 and 8 form a pair. The straight line connecting the pairs of measurement points passes through the center of the wafer. That is, the pairs of measurement points are located at both ends of the wafer.

[0074] The first-direction distance deviation Δx of the aforementioned position deviation parameter corresponds to one or more pairs of measurement points. The straight line connecting the pairs of measurement points corresponding to the first-direction distance deviation Δx passes through the center of the wafer. In the example in Figure 12, the three pairs of measurement points corresponding to the first-direction distance deviation Δx can be 4 and 8, 5 and 9, and 6 and 10, respectively. In other examples, the first-direction distance deviation Δx can correspond to only one pair of measurement points. For example, it can correspond to any one of the pairs of measurement points from 4 and 8, 5 and 9, and 6 and 10. Multiple first-direction distance deviations Δx can each correspond to multiple pairs of measurement points. Similarly, in Figure 13, the first-direction distance deviation Δx also corresponds to three pairs of measurement points, but this will not be explained again here. The first-direction distance deviation Δx is calculated using the difference in corrosion width between each pair of measurement points in a pair or multiple pairs of measurement points.

[0075] JPEG0007859705000001.jpg shows the corrosion width at point 6, where w10 is the corrosion width at measurement point 10. The distance deviation Δx in the first direction can also be calculated using w5 and w9, w4 and w8, and w6 and w10. In this embodiment, the distance deviation Δx in the first direction is a positive number, and the updated current position setting parameter's first direction position coordinate x1 d = x1 ± Δx. That is, when the distance deviation Δx in the first direction is tilted in one direction of the X axis, x1 d = x1 + Δx, and when the distance deviation Δx in the first direction is tilted in the other direction of the X axis, x1 d=x1 - Δx. The distance deviation Δy in the second direction of the position deviation parameter corresponds to one or more pairs of measurement points. The straight line connecting the pair of measurement points corresponding to the distance deviation Δy in the second direction passes through the center of the wafer. In the example of FIG. 12, the three pairs of measurement points corresponding to the distance deviation Δy in the second direction can be 4 and 8, 2 and 7, and 6 and 10 respectively. In other examples, the distance deviation Δy in the second direction can correspond to only one pair of measurement points. For example, it can correspond to only one pair of measurement points among 4 and 8, 2 and 7, and 6 and 10. The plurality of distance deviations Δy in the second direction can each correspond to a plurality of pairs of measurement points. Similarly, in FIG. 13, the distance deviation Δy in the second direction also corresponds to 3 pairs of measurement points, but it will not be explained again here. The distance deviation Δy in the second direction is calculated by the difference value of the corrosion widths of each pair of measurement points at one or more pairs of measurement points. is the corrosion width of JPEG0007859705000002.jpg241706, and w10 is the corrosion width of measurement point 10. The distance deviation Δy in the second direction can be calculated by w2 and w7, w4 and w8, and w6 and w10. In this embodiment, the distance deviation Δy in the second direction is a positive number, and the position coordinate y1 in the second direction of the updated current position setting parameter d is y1 d =y1 ± Δy. That is, when the distance deviation Δy in the second direction inclines in one direction of the Y-axis, y1 d =y1 + Δy, and when the distance deviation Δy in the second direction inclines in the other direction of the Y-axis, y1 d =y1 - Δy.

[0076] In other embodiments, the distance deviation Δx in the first direction and the distance deviation Δy in the second direction can be made positive or negative. For example, inclining in one direction can be made positive, and inclining in the other direction can be made negative. At that time, y1 d =y1 ± Δy, x1 d =x1 ± Δx.

[0077] One or more pairs of measurement points corresponding to the distance deviation Δx in the first direction and one or more pairs of measurement points corresponding to the distance deviation Δy in the second direction are superimposed. Since measurement point 4 is located at 45 degrees, measurement point 8 is located at 225 degrees, measurement point 6 is located at 315 degrees, and measurement point 10 is located at 135 degrees, the distance deviation Δx in the first direction or the distance deviation Δy in the second direction can be calculated from the difference between the corrosion width at measurement point 4 and the corrosion width at measurement point 8, and / or the difference between the corrosion width at measurement point 6 and the corrosion width at measurement point 10.

[0078] In embodiments of the present invention, the position deviation parameter further includes a positioning angle deviation Δθ, and the current position setting parameter further includes a positioning angle θ. The positioning angle of the updated current position setting parameter can be obtained from the positioning angle θ of the current position setting parameter and the positioning angle deviation Δθ of the position deviation parameter. For example, the positioning angle of the updated current position setting parameter can be = θ + Δθ. The positioning angle deviation Δθ of the position deviation parameter refers to the positioning angle deviation between the wafer and the first support area. For example, as shown in Figure 12, a 6-inch wafer has a positioning edge 810, and the corrosion width of the positioning edge 810 differs because the positioning angle θ of the wafer and the positioning angle of the first support area do not match. The positioning angle deviation Δθ of the position deviation parameter corresponds to multiple measurement points. As shown in Figure 12, the three measurement points corresponding to the positioning angle deviation Δθ are measurement point 1, measurement point 2, and measurement point 3. In other embodiments, the positioning angle deviation Δθ can be calculated using only two measurement points, for example, measurement point 1 and measurement point 3. The inclination ratio of the fitting straight line between a set of measurement points can be calculated based on the difference in corrosion width between a set of predetermined measurement points and the distance between the measurement points. The positioning angle deviation Δθ can then be obtained from the inclination ratio of the fitting straight line. For example, the distance between measurement point 1 and measurement point 3 is D1, and the inclination ratio of the fitting straight line is K=(w1-w2) / D1=tanα. In this equation, w1 is the corrosion width at measurement point 1, and w2 is the corrosion width at measurement point 2.

[0079] When using 8-inch and larger wafers, a positioning notch 850 can be formed on the wafer without forming a wafer flat (see Figure 13). When a positioning notch 850 is formed on the wafer, a positioning column can be formed at a predetermined position in the upper cavity 220 or lower cavity 210 of the semiconductor processing apparatus 200. The angle of the wafer can be determined by the positioning column being coupled to the positioning notch 850. If the angle of the wafer cannot be accurately determined by the positioning column, the positioning angle deviation Δθ can also be determined by the corrosion width of the measurement points. Specifically, the positioning angle deviation Δθ of the position deviation parameter corresponds to one or more pairs of measurement points, and each pair of measurement points corresponding to the positioning angle deviation Δθ is located on both sides of the positioning notch 850 on the wafer, and the positioning angle deviation Δθ can be calculated from the difference in corrosion width of each pair of measurement points in one or more pairs of measurement points. The larger the positioning angle deviation Δθ, the larger the difference in corrosion width of the measurement points located on both sides of the positioning notch 850.

[0080] The calibration of the manipulator of the present invention involves setting a current position setting parameter, mounting the wafer at a position corresponding to the current position setting parameter and corroding the rear edge, obtaining the corroded edge and corrosion width of the wafer by performing image recognition on the corroded wafer, calculating a position deviation parameter of the current wafer mounting position setting parameter based on the corroded edge of the wafer, determining whether the position deviation parameter falls within a preset position deviation range, and if the position deviation parameter does not fall within the preset position deviation range, updating or calibrating the current position setting parameter based on the position deviation parameter. In the present invention, the position deviation parameter is brought within a preset position deviation range by performing multiple calibrations, and when the position deviation parameter falls within the preset position deviation range, wafer positioning is stopped. When performing multiple calibrations, the process of each calibration is the same and will not be explained again here.

[0081] The wafer's position can be accurately determined by calibrating the current position setting parameters. However, after a certain period of time, the wafer's size may change due to temperature changes, different wafer product batches, or other factors, potentially causing the quality of the wafer's corrosion edge to fail to meet predetermined requirements. In such cases, the wafer's position can be re-determined by recalibrating the current position setting parameters. This ensures that the quality of the wafer's corrosion edge meets predetermined requirements and that the position deviation parameter falls within a preset position deviation range.

[0082] The present invention allows the position of the wafer to be determined by continuously calibrating the current position setting parameters of the manipulator. The present invention allows the position of the wafer 100 to be determined by using both the calibration method and the protrusion of the semiconductor processing apparatus 200, or by using only the calibration method.

[0083] The step of the manipulator moving the wafer to a position corresponding to the current position setting parameter can be carried out by conventional methods. For example, the manipulator can be artificially controlled so that after it takes a wafer from the wafer storage section, it moves the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing apparatus 200. At that time, the control device can acquire the current position setting parameter corresponding to the predetermined position. In other embodiments, the current position setting parameter can also be set directly to the control device.

[0084] An embodiment of the present invention provides a wafer positioning method. Figure 14 is a flowchart showing a wafer positioning method 900 according to an embodiment of the present invention. As shown in Figure 14, the wafer positioning method 900 includes the following steps.

[0085] In step 902, the manipulator moves the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing apparatus, i.e., to a position corresponding to the current position setting parameter, according to the set or updated current position setting parameter.

[0086] In step 904, the semiconductor processing apparatus corrodes the edge region of the wafer. The specific process of corrosion can be found in the section above.

[0087] In step 906, image acquisition and image recognition are performed on the wafer that has been mounted in a predetermined position according to the current position setting parameter and on which corrosion has been carried out, thereby obtaining corrosion edge information of the wafer (e.g., corrosion width, corrosion edge line). The specific process of image recognition can be found in the matters described in the second and third parts above.

[0088] In step 908, the positioning and calibration module calculates the position deviation parameter of the current position setting parameter based on the acquired corrosion edge information of the wafer.

[0089] In step 910, the control device obtains the updated current position setting parameter by updating the current position setting parameter with the position deviation parameter, and controls the manipulator to move the wafer to a predetermined position on the first support area of ​​the lower cavity, i.e., to a position corresponding to the updated current position setting parameter, using the updated current position setting parameter.

[0090] In an embodiment of the present invention, the positioning and calibration module calculates the position deviation parameter of the current position setting parameter and then further determines whether the position deviation parameter falls within a preset position deviation range. If the position deviation parameter falls within the preset position deviation range, the update of the current position setting parameter is stopped. If the position deviation parameter does not fall within the preset position deviation range, the current position setting parameter is updated using the position deviation parameter. Next, the corrosion edge of the wafer is acquired again using the updated current position setting parameter, the position deviation parameter of the updated current position setting parameter is calculated again, and the above step is repeated until the position deviation parameter corresponding to the updated current position setting parameter falls within the preset position deviation range.

[0091] Other aspects of the wafer positioning method 900 can be found by referring to the predetermined information described in the wafer positioning system, and will not be explained again here.

[0092] Although specific embodiments of the present invention have been described above, these embodiments are for illustrative purposes only and do not limit the present invention. Since the specific embodiments are merely illustrative of the present invention, the present invention is not limited to these embodiments. The scope of the present invention is defined by the claims and exevalent claims of this application.

[0093] In this specification, “one embodiment (example)” or “embodiment (example)” means that the features, structure, or characteristics relating to the example are included in at least one embodiment of the present invention. When the term “in one embodiment” appears in various parts of this specification, it does not refer only to the same embodiment, nor does it refer only to a single embodiment that excludes other embodiments or to a specific embodiment. The terms “many” or “multiple” in this invention refer to two or more matters. The terms “and / or” in this invention refer to a relationship between “and” or “or”. The terms “first,” “second,” “third,” “fourth,” etc. in this invention distinguish multiple different matters and are not intended to limit the order of each matter. The terms in this invention describe specific matters and are not limiting.

[0094] It should be noted that in other embodiments, the functions / operations of the present invention do not necessarily have to be performed in the order shown in the drawings. For example, the functions / operations shown in two drawings can be performed simultaneously or in a reversed order.

[0095] It should be noted that although the steps of the present invention have been described above in a specific order, other steps can be added between any two steps. By adjusting the steps of the present invention, the execution time of each step can be made different, or each step can be performed by different systems. The systems can perform multiple steps simultaneously.

[0096] When an engineer in the art implements various modifications of the present invention and matters of other embodiments, it is assumed that the engineer has common knowledge and some basic data in the art. It should be noted that the present invention is not limited to the embodiments described above, but may further include other embodiments that do not depart from the spirit of the invention. Although the elements and functions relating to specific embodiments have been described above with reference to the embodiments and specific drawings, it is natural that other elements and functions included in the claims of this application are also included in the present invention. The claims of this application may further include not only the elements and matters explicitly described above, but also other elements, matters that differ from them, and combinations thereof. Certain terms have been used in this specification, but they are for illustrative purposes only and do not limit the present invention.

Claims

1. Includes semiconductor processing equipment, image edge detection equipment, wafer transfer equipment and positioning and calibration module, The semiconductor processing apparatus includes a lower cavity in which a first support area is formed and an upper cavity in which a second support area is formed. When the upper cavity and the lower cavity are joined, the wafer is mounted between the first support area and the second support area. A first passage is formed in the peripheral area of ​​the first support area and / or the second support area, and the first passage constitutes a first space. The peripheral area of ​​the wafer is corroded by one or more chemical fluids injected into the first space. The wafer transfer apparatus includes a manipulator and a control device, the control device sets or updates current position setting parameters, and the manipulator transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing apparatus, i.e., to a position corresponding to the current position setting parameters, according to the set or updated current position setting parameters. The image edge detection device converts a sample image of a wafer mounted at a predetermined position and subjected to corrosion into an HLS image based on the current position setting parameter, and obtains the corrosion edge of the wafer by image recognition of the corrosion boundary line between the corroded area and the uncorroded area of ​​the wafer based on the brightness value and color value of the HLS image. The positioning and calibration module calculates the position deviation parameter of the current position setting parameter based on the corrosion edge information of the wafer obtained by image recognition. A wafer positioning system characterized in that the control device obtains updated current position setting parameters by updating the current position setting parameters with the position deviation parameters, and controls the manipulator to move the wafer to a predetermined position on the first support area of ​​the lower cavity, i.e., a position corresponding to the updated current position setting parameters, using the updated current position setting parameters.

2. The positioning and calibration module calculates the position deviation parameter of the current position setting parameter, then determines whether the position deviation parameter falls within a preset position deviation range. If the position deviation parameter falls within the preset position deviation range, it stops updating the current position setting parameter. If the position deviation parameter does not fall within the preset position deviation range, it updates the current position setting parameter using the position deviation parameter. Next, it acquires the corrosion edge of the wafer again using the updated current position setting parameter, then recalculates the position deviation parameter of the updated current position setting parameter, and determines the position corresponding to the updated current position setting parameter. The wafer positioning system according to claim 1, characterized in that it repeats the following steps until the position deviation parameter falls within a preset position deviation range: transporting the wafer to a position corresponding to the current position setting parameter by the manipulator; corroding the edge area of ​​the wafer by the semiconductor processing apparatus; acquiring the corroded edge of the wafer by performing image acquisition and image recognition on the corroded wafer; calculating the position deviation parameter of the current position setting parameter based on the corroded edge information obtained through this image acquisition and image recognition; updating the current position setting parameter based on the calculated position deviation parameter; and transporting the wafer to a position corresponding to the updated current position setting parameter.

3. The wafer positioning system according to claim 1, characterized in that the positioning and calibration module calculates the corrosion width of a plurality of measurement points on the wafer using corrosion edge information of the wafer obtained by image recognition, and calculates the position deviation parameter using the corrosion width of the plurality of measurement points.

4. The position deviation parameter includes a distance deviation in the first direction and a distance deviation in the second direction, and the current position setting parameter includes a position coordinate in the first direction and a position coordinate in the second direction, and the first and second directions are perpendicular. The wafer positioning system according to claim 3, characterized in that the updated position coordinates of the current position setting parameter in the first direction are obtained by using the position coordinates of the current position setting parameter in the first direction and the distance deviation of the position deviation parameter in the first direction, and the updated position coordinates of the current position setting parameter in the second direction are obtained by using the position coordinates of the current position setting parameter in the second direction and the distance deviation of the position deviation parameter in the second direction.

5. The distance deviation in the first direction of the position deviation parameter represents the position deviation in which the center of the wafer and the center of the first support area are misaligned in the first direction. The wafer positioning system according to claim 4, characterized in that the distance deviation in the second direction of the position deviation parameter represents a positioning deviation in which the center of the wafer and the center of the first support area are misaligned in the second direction.

6. The wafer positioning system according to claim 4, characterized in that the plurality of measurement points include a plurality of pairs of measurement points, the first-direction distance deviation of the position deviation parameter corresponds to one or more pairs of measurement points, the straight line connecting the pair of measurement points corresponding to the first-direction distance deviation passes through the center of the wafer, and the first-direction distance deviation is calculated by the difference in corrosion width of each pair of measurement points at the pair of measurement points or multiple pairs of measurement points, or the second-direction distance deviation of the position deviation parameter corresponds to one or more pairs of measurement points, the straight line connecting the pair of measurement points corresponding to the second-direction distance deviation passes through the center of the wafer, and the second-direction distance deviation is calculated by the difference in corrosion width of each pair of measurement points at the pair of measurement points or multiple pairs of measurement points.

7. The wafer positioning system according to claim 6, characterized in that one or more pairs of measurement points corresponding to the distance deviation in the first direction and one or more pairs of measurement points corresponding to the distance deviation in the second direction are superimposed.

8. The wafer positioning system according to claim 4, wherein the position deviation parameter further includes a positioning angle deviation, the current position setting parameter further includes a positioning angle, the updated positioning angle of the current position setting parameter is obtained by the positioning angle of the current position setting parameter and the positioning angle deviation of the position deviation parameter, and the positioning angle deviation of the position deviation parameter refers to the positioning angle deviation between the wafer and the first support area.

9. The positioning angle deviation of the position deviation parameter corresponds to multiple measurement points, and the inclination ratio of the fitting line between the multiple measurement points is calculated based on the difference in corrosion width of a predetermined number of measurement points and the distance between the multiple measurement points, and the positioning angle deviation is obtained from the inclination ratio of the fitting line, or The wafer positioning system according to claim 8, wherein the positioning angle deviation of the position deviation parameter corresponds to one or more pairs of measurement points, each pair of measurement points corresponding to the positioning angle deviation is located on both sides of the positioning notch of the wafer, and the positioning angle deviation is calculated by the difference in corrosion width of each pair of measurement points at one or more pairs of measurement points.

10. A first passage is formed in the peripheral area of ​​the second support area, and one or more chemical fluids flow between the first space and the outside of the semiconductor processing device through the first through-hole formed in the upper cavity, or The wafer positioning system according to claim 1, characterized in that a first passage is formed in the peripheral area of ​​the first support area, the lower cavity includes a first through-hole, and one or more chemical fluids flow between the first space and the outside of the semiconductor processing apparatus through the first through-hole formed in the lower cavity.

11. A wafer positioning method using a system including a semiconductor processing device, an image edge detection device, a wafer transfer device, and a positioning and calibration module, The semiconductor processing apparatus includes a lower cavity in which a first support area is formed and an upper cavity in which a second support area is formed, and when the upper cavity and the lower cavity are joined, the wafer is mounted between the first support area and the second support area, a first passage is formed in the peripheral area of ​​the first support area and / or the second support area, a first space is formed by the first passage, and the peripheral area of ​​the wafer is corroded with one or more chemical fluids injected into the first space, The wafer transfer apparatus includes a manipulator and a control device, the control device sets or updates current position setting parameters, and the manipulator transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing apparatus, i.e., a position corresponding to the current position setting parameters, according to the set or updated current position setting parameters. The image edge detection device obtains the corrosion edge of the wafer by converting a sample image of a wafer mounted at a predetermined position and subjected to corrosion into an HLS image, and by image recognition of the corrosion boundary line between the corroded area and the uncorroded area of ​​the wafer based on the brightness value and color value of the HLS image. The positioning and calibration module includes the step of calculating a position deviation parameter of the current position setting parameter using the corrosion edge information of the wafer obtained by image recognition, The control device obtains updated current position setting parameters by updating the current position setting parameters with the position deviation parameters, and controls the manipulator to move the wafer to a predetermined position on the first support area of ​​the lower cavity, i.e., a position corresponding to the updated current position setting parameters, using the updated current position setting parameters. A wafer positioning method characterized by including the following.

12. The positioning and calibration module calculates the position deviation parameter of the current position setting parameter, then further determines whether the position deviation parameter falls within a preset position deviation range. If the position deviation parameter falls within the preset position deviation range, it stops updating the current position setting parameter. If the position deviation parameter does not fall within the preset position deviation range, it updates the current position setting parameter using the position deviation parameter. Next, it acquires the corrosion edge of the wafer again using the updated current position setting parameter, then recalculates the position deviation parameter of the updated current position setting parameter, and the position deviation corresponding to the updated current position setting parameter is also calculated. The wafer positioning method according to claim 11, further comprising: transporting the wafer by the manipulator to a position corresponding to the current position setting parameter until the difference parameter falls within a pre-set position deviation range; corroding the edge area of ​​the wafer by the semiconductor processing apparatus; acquiring the corroded edge of the wafer by performing image acquisition and image recognition on the wafer on which the corrosion has been performed; calculating a position deviation parameter of the current position setting parameter based on the corroded edge information obtained through this image acquisition and image recognition; updating the current position setting parameter based on the calculated position deviation parameter; and transporting the wafer to a position corresponding to the updated current position setting parameter, and repeating these steps.

13. The wafer positioning method according to claim 11, characterized in that the positioning and calibration module calculates the corrosion width of a plurality of measurement points on the wafer using corrosion edge information of the wafer obtained by image recognition, and calculates the position deviation parameter using the corrosion width of the plurality of measurement points.

14. The position deviation parameter includes a distance deviation in the first direction and a distance deviation in the second direction, and the current position setting parameter includes a position coordinate in the first direction and a position coordinate in the second direction, and the first and second directions are perpendicular. The wafer positioning method according to claim 13, characterized in that the updated position coordinates of the current position setting parameter in the first direction are obtained by using the position coordinates of the current position setting parameter in the first direction and the distance deviation of the position deviation parameter in the first direction, and the updated position coordinates of the current position setting parameter in the second direction are obtained by using the position coordinates of the current position setting parameter in the second direction and the distance deviation of the position deviation parameter in the second direction.

15. The wafer positioning method according to claim 14, characterized in that the plurality of measurement points include a plurality of pairs of measurement points, the distance deviation in the first direction of the position deviation parameter corresponds to one or more pairs of measurement points, the straight line connecting the pair of measurement points corresponding to the distance deviation in the first direction passes through the center of the wafer, and the distance deviation in the first direction is calculated by the difference in corrosion width of each pair of measurement points at the pair of measurement points or multiple pairs of measurement points, or the distance deviation in the second direction of the position deviation parameter corresponds to one or more pairs of measurement points, the straight line connecting the pair of measurement points corresponding to the distance deviation in the second direction passes through the center of the wafer, and the distance deviation in the second direction is calculated by the difference in corrosion width of each pair of measurement points at the pair of measurement points or multiple pairs of measurement points.

16. The position deviation parameter further includes a positioning angle deviation, the current position setting parameter further includes a positioning angle, the updated positioning angle of the current position setting parameter is obtained from the positioning angle of the current position setting parameter and the positioning angle deviation of the position deviation parameter, the positioning angle deviation of the position deviation parameter refers to the positioning angle deviation between the wafer and the first support area, The positioning angle deviation of the position deviation parameter corresponds to multiple measurement points, and the inclination ratio of the fitting line between the multiple measurement points is calculated based on the difference in corrosion width of a predetermined number of measurement points and the distance between the multiple measurement points, and the positioning angle deviation is obtained from the inclination ratio of the fitting line, or The wafer positioning method according to claim 14, wherein the positioning angle deviation of the position deviation parameter corresponds to one or more pairs of measurement points, each pair of measurement points corresponding to the positioning angle deviation is located on both sides of the positioning notch of the wafer, and the positioning angle deviation is calculated by the difference in corrosion width of each pair of measurement points at one or more pairs of measurement points.

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