Imaging device

Abstract

To provide an imaging apparatus capable of expanding a dynamic range by a simple constitution.SOLUTION: A circuit constitution and an operation method of an imaging apparatus can determine an electron saturation state in a charge detection part formed in a pixel and change an operation mode in accordance with a determination result. First, first imaging data are acquired, and if the charge detection part is not saturated, the first imaging data are read out as they are. When the charge detection part is saturated, saturation of the charge detection part is canceled and second image data are acquired and read out.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device and an operation method thereof.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field of one aspect relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes, as an example, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, an operation method thereof, or a manufacturing method thereof. can be cited as an example.

[0003] Note that in this specification etc., the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. Also, a storage device, a display device, an imaging device, and an electronic device may have a semiconductor device.

Background Art

[0004] An oxide semiconductor has been attracting attention as a semiconductor material applicable to a transistor. For example, techniques for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as the oxide semiconductor are disclosed (see Patent Document 1 and Patent Document 2).

[0005] Also, an imaging device having a configuration in which a transistor having an oxide semiconductor is used as part of a pixel circuit is disclosed in Patent Document 3.

Prior Art Documents

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2011-119711 [Overview of the project] [Problems that the invention aims to solve]

[0007] CMOS image sensors are increasingly being incorporated into various devices, and improvements in imaging performance are expected. The dynamic range of current CMOS image sensors is 3 to 4 orders of magnitude (6 This ranges from approximately 0 dB to 80 dB, which is equivalent to five to six orders of magnitude (100 dB) of silver halide film or the human eye. It is desirable to improve the level to (or 120 dB).

[0008] To improve the dynamic range, methods such as switching the charge storage area during imaging or within the pixel Methods for processing analog data have been proposed. However, the former is from an external source Control of this becomes necessary, and a separate means for detecting illuminance, etc., is required. Furthermore, the latter involves the transistor within the pixel. As the number of transistors increases, image degradation due to leakage current and noise in the transistors occurs. This will be a problem.

[0009] Therefore, in one aspect of the present invention, the dynamic range can be widened with a simple configuration. One of the objectives is to provide an imaging device that can adjust the pixel sensitivity after the first image is taken. One of the objectives is to provide an imaging device that can be modified and perform a second imaging. Alternatively, low-power imaging One of the objectives is to provide an imaging device with low power consumption. Alternatively, during the exposure period, the previous frame One of the objectives is to provide an imaging device that reads out data. Alternatively, noise One of the objectives is to provide an imaging device that can capture images with minimal noise. One of its objectives is to provide an imaging device suitable for high-speed operation. Alternatively, high resolution One of the objectives is to provide an imaging device. Alternatively, to provide an imaging device with a high degree of integration. One of the objectives is to provide an imaging device that can capture images in low light conditions. One of the objectives is to provide an imaging device that can be used over a wide temperature range. One of the objectives is to provide an imaging device with a high aperture ratio. To do so. Or, one of the objectives is to provide a highly reliable imaging device. Or, a new One of the objectives is to provide an imaging device, etc. Alternatively, to provide a method for operating the above imaging device. One of the objectives is to provide... or to provide novel semiconductor devices, etc. It will be one of the options.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention relates to an imaging device capable of automatically changing the sensitivity of pixels during imaging. ru.

[0012] One aspect of the present invention comprises a first to sixth transistor, a photoelectric conversion element, and An imaging device having one capacitive element and a second capacitive element, wherein one of the photoelectric conversion elements The electrodes are electrically connected to either the source or the drain of the first transistor, and the first transistor Either the source or drain of the second transistor is connected to the source or drain of the second transistor. One side is electrically connected to the third, and the other side of the source or drain of the first transistor is connected to the third It is electrically connected to either the source or drain of the transistor, and the first transistor The source or drain of the other transistor is electrically connected to the source or drain of the fourth transistor. They are connected in a linear fashion, with the source or drain of the first transistor being connected to the other side of the fifth transistor. The gate electrode is electrically connected to the first transistor, and the other is either the source or the drain. One electrode of the first capacitive element is electrically connected to the source or dot of the fourth transistor. The other end of Rain is electrically connected to one electrode of the second capacitive element, and the fifth transistor Either the source or the drain of the sixth transistor is electrically connected to either the source or the drain of the sixth transistor. They are connected in a specific manner, with the first transistor, the second transistor, the third transistor and the The transistor 4 is characterized by having an oxide semiconductor in the region where the channel is formed. It is an imaging device.

[0013] Oxide semiconductors are composed of In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La). It is preferable to have a fifth transistor and The sixth transistor may also have an oxide semiconductor in the region where the channel is formed.

[0014] The photoelectric conversion element can use selenium or a selenium-containing compound in its photoelectric conversion layer. For example, amorphous selenium or crystalline selenium can be used as the selenium.

[0015] Another aspect of the present invention includes a pixel, a first circuit, a second circuit, a third circuit, and An imaging device having 4 circuits and a 5th circuit, wherein the pixels are electrically connected to the first circuit. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the third circuit. The second circuit is electrically connected to the fourth circuit, and the third circuit is electrically connected to the fifth circuit. The fifth circuit is electrically connected to the pixel, and the pixel receives the first imaging data. It has the function of acquiring second imaging data, and the pixels are either the first imaging data or the second imaging data It has a function to store data in a charge storage unit, and the pixel has a function to store the first imaging data stored in the charge storage unit. The first circuit has a function to transfer the first or second imaging data to the charge detection unit, and the second circuit has a function to transfer the first imaging data to the second The absolute value of the difference between the potential corresponding to the imaging data and the potential corresponding to the reset potential of the charge detection unit. The second circuit has the function of outputting a signal that is added to or subtracted from a reference potential, and the first circuit The third circuit has a function to determine whether or not the charge detection unit is saturated based on the imaging data, and the third circuit is used for the determination. When the charge detection unit is not saturated, the signal that does not acquire the second imaging data is sent to the fifth circuit. The third circuit has the function of outputting to the pixel via a third circuit, and the charge detection unit is saturated by determination. At this time, the saturation of the charge detection unit is relieved, and the signal for acquiring the second imaging data is transmitted via the fifth circuit. The second and fourth circuits have the function of outputting to the pixels, and the first circuit outputs This imaging device is characterized by having the function of converting signals into digital data.

[0016] Another aspect of the present invention is that in the nth frame period (where n is a natural number greater than or equal to 1), A first step is to reset the potential of the charge storage unit, and a second step is to store charge in the charge storage unit. Step 1, a third step to reset the potential of the charge detection unit, and a third step to reset the potential of the charge storage unit. A fourth step involves transferring the signal to the detection unit and reading the signal corresponding to the potential of the charge detection unit. The fifth step is to determine from the signal whether or not the charge detection unit is saturated, and the steps are performed in the order described above. In step 1, if the charge detection unit is determined to be saturated, the potential of the charge storage unit is... A sixth step to reset the charge, a seventh step to store charge in the charge storage unit, and An eighth step involves temporarily increasing the capacity of the detection unit to relieve saturation of the charge detection unit, and the charge The ninth step is to transfer the potential of the storage unit to the charge detection unit, and the above steps are performed in the order described above, and the n+1th step In parallel with the first and second steps in the frame period, the nth frame period The signal corresponding to the potential of the charge detection unit in the 9th step is read out, and the 5th step If the charge detection unit is determined not to be saturated, then in the (n+1)th frame period... In parallel with the first and second steps, the fourth in the nth frame period The operation of the imaging device is characterized by reading out a signal corresponding to the potential of the step charge detection unit. It is a method.

[0017] One aspect of the present invention comprises a first to seventh transistor, a photoelectric conversion element, and An imaging device having one capacitive element, a second capacitive element, and a third capacitive element, One electrode of the power conversion element is electrically connected to either the source or the drain of the first transistor. Connected, with either the source or drain of the first transistor connected to the source of the second transistor. Electrically connected to either the source or drain of the first transistor, and the source or drain The other end of the input is electrically connected to either the source or drain of the third transistor, The source or drain of transistor 1 is connected to the source or drain of transistor 4. One side of the rain is electrically connected, and the other side of the source or drain of the first transistor is The gate electrode of the fifth transistor is electrically connected to the source of the first transistor. The other end of the drain is electrically connected to one electrode of the first capacitive element, and the fourth transistor The source or drain of the first capacitor is electrically connected to one electrode of the second capacitive element, Either the source or drain of transistor 5 is connected to the source or drain of transistor 6. Electrically connected to one side of the rain, the gate of the fourth transistor is connected to the seventh transistor. Either the source or drain of the fourth transistor is electrically connected, and the gate of the fourth transistor is connected to the fourth One electrode of the 3 capacitive elements is electrically connected to the first transistor and the second transistor. The third, fourth, and seventh transistors have channels This imaging device is characterized by having an oxide semiconductor in the region where it is formed.

[0018] Oxide semiconductors are composed of In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La). It is preferable to have a fifth transistor and The sixth transistor may also have an oxide semiconductor in the region where the channel is formed.

[0019] The photoelectric conversion element can use selenium or a selenium-containing compound in its photoelectric conversion layer. For example, amorphous selenium or crystalline selenium can be used as the selenium.

[0020] Another aspect of the present invention includes a pixel, a first circuit, a second circuit, a third circuit, and An imaging device having 4 circuits, wherein each pixel has a charge storage unit and a charge detection unit, The load detection unit is electrically connected to the first capacitive element and the second capacitive element, and the pixel is connected to the first circuit The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the third The first circuit is electrically connected to the second circuit, the second circuit is electrically connected to the fourth circuit, and the third circuit is connected to the drawing. The element is electrically connected, and the pixel has the function of acquiring either first or second imaging data. The pixels have a function to store first imaging data or second imaging data in the charge storage unit. The pixel has charge detection, and the first or second imaging data stored in the charge storage unit is detected. The first circuit has a function to transfer data to the unit, and the first circuit has a potential corresponding to the second imaging data and a charge detection The absolute value of the difference between the reset potential of the section and the corresponding potential is added to or subtracted from the reference potential. The second circuit has the function of outputting a signal, and the second circuit saturates the charge detection unit based on the first imaging data. The third circuit has a function to determine whether or not the charge detection unit is saturated, and the determination indicates that the charge detection unit is not saturated. The device outputs a signal to the pixel that does not conduct electricity between the charge detection unit and one electrode of the second capacitive element. The third circuit has the function of, when the charge detection unit is saturated by determination, the charge detection unit and It has a function of outputting a signal to the pixel that causes conduction between one electrode of the second capacitive element and the other electrode, The pixel has the function of transferring second imaging data from the charge storage unit to the charge detection unit after the determination. The second and fourth circuits convert the signal output by the first circuit into digital data. This imaging device is characterized by having the following function.

[0021] Another aspect of the present invention is that in the nth frame period (where n is a natural number greater than or equal to 1), A first step is to reset the potential of the charge storage unit, and a second step is to store charge in the charge storage unit. Step 1, a third step to reset the potential of the charge detection unit, and a third step to reset the potential of the charge storage unit. A fourth step involves transferring the signal to the detection unit and reading the signal corresponding to the potential of the charge detection unit. The fifth step is to determine from the signal whether or not the charge detection unit is saturated, and the steps are performed in the order described above. In step 1, if it is determined that the charge detection unit is saturated, the capacitance of the charge detection unit is... A sixth step of increasing the potential of the charge detection unit, and a seventh step of resetting the potential of the charge detection unit, The above procedure is followed, and in the fifth step, if it is determined that the charge detection unit is not saturated, The process then proceeds to the seventh step, and in parallel with the fifth through seventh steps, the charge The eighth step is to reset the potential of the storage unit, and the ninth step is to store charge in the charge storage unit. The first step involves performing the above steps in the order described above, and transferring the potential of the charge storage unit to the charge detection unit. This is done in parallel with the first and second steps in the (n+1)th frame period. The signal corresponding to the potential of the charge detection unit in the 10th step during the nth frame period is read. This is an operating method for an imaging device characterized by outputting data. [Effects of the Invention]

[0022] By using one aspect of the present invention, the dynamic range can be widened with a simple configuration. An imaging device can be provided. Alternatively, the pixel sensitivity can be changed after the first imaging, and then... We can provide an imaging device for imaging the eye, or an imaging device with low power consumption. This is possible. Alternatively, an imaging device that reads out data from the previous frame during the exposure period. It can provide an imaging device that can capture images with low noise. We can provide this. Or, we can provide an imaging device suitable for high-speed operation. Alternatively, a high-resolution imaging device can be provided. Alternatively, a highly integrated imaging device can be provided. It can provide an imaging device that can take images in low light conditions. It is possible to provide an imaging device that can be used over a wide temperature range. Alternatively, it is possible to provide an imaging device with a high aperture ratio. Alternatively, a highly reliable imaging device We can provide a suitable location. Or, we can provide a novel imaging device, etc. This can provide a method for operating the above-mentioned imaging device. Alternatively, it can provide a novel semiconductor device, etc. It can be provided.

[0023] Furthermore, one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention In some cases, or depending on the circumstances, it may have effects other than those listed above. Yes. Or, for example, one aspect of the present invention may, depending on the circumstances, These effects may not always be present. [Brief explanation of the drawing]

[0024] [Figure 1] A circuit diagram explaining pixels. [Figure 2] A top view illustrating the imaging device, a circuit diagram of the CDS circuit, and a block diagram of the A / D conversion circuit. [Figure 3] Circuit diagrams of the judgment output circuit and pixel control circuit. [Figure 4] A timing chart illustrating the operation of the judgment output circuit and the pixel control circuit. [Figure 5] A flowchart explaining the operation of the imaging device. [Figure 6]A timing chart explaining the operation of the imaging device. [Figure 7] A timing chart illustrating the operation of the CDS circuit and comparator circuit. [Figure 8] A timing chart explaining the operation of the imaging device. [Figure 9] A diagram illustrating the pixel circuit. [Figure 10] A diagram illustrating the pixel circuit. [Figure 11] A timing chart explaining the operation of the imaging device. [Figure 12] A timing chart explaining the operation of the imaging device. [Figure 13] A diagram illustrating the pixel circuit. [Figure 14] A diagram illustrating the pixel circuit. [Figure 15] A top view and a front view illustrating the configuration of the imaging device. [Figure 16] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 17] A diagram illustrating the operation of the imaging device. [Figure 18] A cross-sectional diagram illustrating the configuration of a photoelectric conversion element. [Figure 19] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 20] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 21] A cross-sectional view illustrating the imaging device. [Figure 22] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 23] A cross-sectional view illustrating the imaging device. [Figure 24] A cross-sectional view illustrating the imaging device. [Figure 25] Cross-sectional and circuit diagrams illustrating the imaging device. [Figure 26] A cross-sectional view illustrating the imaging device. [Figure 27] A cross-sectional view illustrating the imaging device. [Figure 28] A cross-sectional view illustrating the imaging device. [Figure 29]A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 30] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 31] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 32] A diagram illustrating a curved imaging device. [Figure 33] A circuit diagram explaining pixels. [Figure 34] A top view illustrating the imaging device, a circuit diagram of the CDS circuit, and a block diagram of the A / D conversion circuit. [Figure 35] Circuit diagram of the judgment output circuit. [Figure 36] A timing chart illustrating the operation of the judgment output circuit. [Figure 37] A flowchart explaining the operation of the imaging device. [Figure 38] A timing chart explaining the operation of the imaging device. [Figure 39] A timing chart illustrating the operation of the CDS circuit and comparator circuit. [Figure 40] A diagram illustrating the pixel circuit. [Figure 41] A diagram illustrating the pixel circuit. [Figure 42] A timing chart explaining the operation of the imaging device. [Figure 43] A diagram illustrating the pixel circuit. [Figure 44] A diagram illustrating the pixel circuit. [Figure 45] Top view and cross-sectional view illustrating a transistor. [Figure 46] Top view and cross-sectional view illustrating a transistor. [Figure 47] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 48] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 49] Top view and cross-sectional view illustrating the semiconductor layer. [Figure 50] Top view and cross-sectional view illustrating a transistor. [Figure 51]Top view and cross-sectional view illustrating a transistor. [Figure 52] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 53] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 54] Top view and cross-sectional view illustrating a transistor. [Figure 55] A top view illustrating a transistor. [Figure 56] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 57] Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 58] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 59] Cross-sectional TEM image of an a-like OS. [Figure 60] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 61] Perspective and cross-sectional views of the package containing the imaging device. [Figure 62] Perspective and cross-sectional views of the package containing the imaging device. [Figure 63] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0025] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0026] The ordinal numbers "1st" and "2nd" are used for convenience only and do not necessarily indicate the order of processes or layering. It does not indicate order. Therefore, for example, "the first" could be "the second" or "the third." It can be explained by substituting it as appropriate. Also, ordinal numbers as described in this specification, etc. The ordinal numbers used to specify one aspect of the present invention may not always coincide.

[0027] For example, in this specification, etc., if it is explicitly stated that X and Y are connected The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0028] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0029] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0030] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, X and This includes cases where Y is directly connected to it.

[0031] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (D / A conversion circuits, A / D conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.) (etc.), voltage source, current source, switching circuit, amplification circuit (to increase signal amplitude or current amount, etc.) (Incoming circuits, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal One or more generation circuits, memory circuits, control circuits, etc., can be connected between X and Y. As an example, even if another circuit is placed between X and Y, the output from X If a signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes the case where and Y are electrically connected.

[0032] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected) and when X and Y are functionally connected (i.e., X and Y are connected) (When functionally connected with another circuit in between) and when X and Y are directly connected In the case of (that is, when X and Y are connected without another element or circuit in between) and However, this shall be as disclosed in this specification, etc. That is, explicitly stated that they are electrically connected. If it is explicitly stated that it is connected, then Similar information is disclosed in this specification, etc.

[0033] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0034] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope.

[0035] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." It is electrically connected to X via at least a first connection path, and the first connection path is It does not have a second connection path, and the aforementioned second connection path is via a transistor, The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor. The path between ( and ), and the first connection path is a path via Z1, and the transit The drain (or second terminal, etc.) of the terminal is electrically connected to Y via at least a third connection path. They are connected in a manner, and the third connection path does not have the second connection path, and the third The connection path is the path via Z2. This can be expressed as "The transition The source of the starter (or the first terminal, etc.) is connected via Z1 through at least the first connection path. And, electrically connected to X, the first connection path does not have a second connection path, The second connection path has a connection path via a transistor, and the drain of the transistor (or a second terminal, etc.) is connected to Y via Z2 by at least a third connection path. It is expressed as: "They are electrically connected, and the third connection path does not have the second connection path." It is possible. Or, "the source (or first terminal, etc.) of the transistor is less Both are electrically connected to X via Z1 through a first electrical path, and the first electrical The target path does not have a second electrical path, and the second electrical path is the transistor From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor It is an electrical path, and the drain (or second terminal, etc.) of the transistor is at least third The electrical path is electrically connected to Y via Z2, and the third electrical path is , it does not have a fourth electrical path, and the fourth electrical path is the drain of the transistor The electrical pulse from (or the second terminal, etc.) to the source (or the first terminal, etc.) of the transistor It can be expressed as "It is S." Using similar methods of expression as these examples, the circuit configuration By defining the connection path in the transistor, the source (or first terminal) To distinguish between the drain (or second terminal, etc.) and the second terminal, and to determine the technical scope. It is possible.

[0036] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0037] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0038] Note that the words "membrane" and "layer" may differ in some cases or depending on the situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer."

[0039] Generally speaking, electric potential (voltage) is relative, and its relative magnitude from a reference potential is... The size is determined by the degree. Therefore, terms such as "grounding," "GND," and "earth" are used. Even if it is stated, the potential is not necessarily 0 volts. For example, when defining "ground" or "GND" based on the lowest potential in a circuit, Yes, it exists. Alternatively, in a circuit, an intermediate potential can be used as a reference to define "ground" or "GND". In some cases, positive and negative potentials are defined based on that potential. And so it becomes.

[0040] (Embodiment 1) In this embodiment, an imaging device, which is one aspect of the present invention, will be described with reference to the drawings.

[0041] One aspect of the present invention determines the electron saturation state in a charge detection unit provided within a pixel, and determines the determination This is a circuit configuration and operating method for an imaging device that can change its operating mode depending on the result. First, acquire the first imaging data, and if the charge detection unit is not saturated, the first imaging data Read the data as is. If the charge detection unit is saturated, the saturation of the charge detection unit is resolved, and the Acquisition and reading of imaging data from step 2. The first imaging data is an image corresponding to low light. The first image data corresponds to the data itself, and the second image data corresponds to image data that corresponds to high illumination.

[0042] As a result of the above operation, even in low light conditions, noise is reduced and wide dynamic range is maintained. It is possible to acquire images of the range. Furthermore, even when imaging in environments including high light, the bright areas It is possible to maintain the tonal range and obtain images with a wide dynamic range.

[0043] Figure 1 is a circuit diagram of a pixel 10 in an imaging device according to one aspect of the present invention. An example is shown where the transistor is of the n-channel type, but one aspect of the present invention is not limited thereto. It is not fixed, and some transistors may be replaced with p-channel transistors.

[0044] In pixel 10, one electrode of the photoelectric conversion element PD is the source or of transistor 41 It is electrically connected to one of the drains. Either the source or the drain of transistor 41. It is electrically connected to either the source or drain of transistor 42. The other end of the source or drain of transistor 41 is the source or drain of transistor 43. It is electrically connected to one side. The other side of the source or drain of transistor 41 is connected to the transistor The source or drain of transistor 44 is electrically connected. The other end of the drain or the other is electrically connected to the gate of transistor 45. The source or drain of sta 41 is electrically connected to one electrode of capacitive element C1. The source or drain of transistor 44 is connected to one electrode of capacitive element C2. Electrically connected. Either the source or the drain of transistor 45 is connected to the transistor It is electrically connected to either the source or drain of the 46.

[0045] Here, one electrode of the photoelectric conversion element PD, and one of the source or drain of the transistor 41. The charge is applied to node AN, to which either the source or drain of transistor 42 is connected. This will serve as the storage unit. Also, the other side of the source or drain of transistor 41, transistor 4 One of the sources or drains of transistor 3, one of the sources or drains of transistor 44, The gate of the transistor 45 and one electrode of the capacitive element C1 are connected to node FD, which is charged. This will be the detection unit.

[0046] The other electrode of the photoelectric conversion element PD is electrically connected to wiring 71 (VPD). The other side of the source or drain of transistor 42 and the source or drain of transistor 43 The other end is electrically connected to wiring 72 (VRS). The other electrode of capacitive element C1 and The other electrode of the capacitive element C2 is electrically connected to wiring 73 (VSS). Transistor The source or drain of 45 is electrically connected to wiring 74 (VPI). The source or drain of the converter 46 is electrically connected to wiring 91 (OUT1). It can be done.

[0047] In addition, in the connection configuration of each of the above elements, multiple transistors or multiple capacitive elements are electrically connected. This example shows how to share connected wiring, but each is electrically connected to different wiring. That's good too.

[0048] Wiring 71 (VPD), Wiring 72 (VRS), Wiring 73 (VSS), and Wiring 74 (VP I) can function as a power line. For example, wiring 71 (VPD) and Wiring 73 (VSS) can function as a low-voltage power line. Wiring 72 (VRS) ) and wiring 74 (VPI) can be used as high-potential power lines.

[0049] The gate of transistor 41 is electrically connected to wiring 61 (TX). Transistor 4 The gate of transistor 2 is electrically connected to wiring 62 (GWRS). It is electrically connected to wiring 63 (RS). The gate of transistor 44 is connected to wiring 64 ( It is electrically connected to CN). The gate of transistor 46 is electrically connected to wiring 65(SE). It connects to the network.

[0050] Wiring 61 (TX), Wiring 62 (GWRS), Wiring 63 (RS), Wiring 64 (CN) and Wiring 65(SE) is a signal line that controls the conductivity of the transistors to which it is connected. It can be made to function. Note that wiring 63 (RS) and wiring 65 (SE) are controlled on a row-by-row basis. It can be controlled.

[0051] Transistor 41 is a transistor for transferring the potential of node AN to node FD. This allows it to function. Transistor 42 resets the potential of node AN. It can function as a transistor. Transistor 43 is at the potential of node FD. It can be made to function as a transistor for resetting. Transistor 44 is This controls the electrical connection between node FD and capacitive element C2, and distributes the electrons accumulated in node FD. It can function as a transistor for splitting. Transistor 45 is a node It can function as a transistor to produce an output corresponding to the potential of the FD. Transistor 46 can function as a transistor for selecting pixel 10. .

[0052] Note that the above-described configuration of pixel 10 is just one example, and some circuits, some transistors, and some Capacitive elements or some wiring may not be included. Or, they may not be included in the above-mentioned configuration. It may also include circuits, transistors, capacitive elements, wiring, etc. The connection configuration may differ from the one described above.

[0053] Figure 2(A) is a diagram illustrating an imaging device according to one embodiment of the present invention. This imaging device is a matrix A pixel array 11 having pixels 10 arranged in a cubic shape, and a function for driving the pixels 10. Circuit 12 (low driver) and CDS (Correlat) are used to process the output signal of pixel 10. Circuit 13 (CDS circuit) for performing the ed Double Sampling operation, A function to determine whether or not node FD is saturated and the analog data output from circuit 13 A circuit 14 (such as an A / D conversion circuit) that has the function of converting to digital data, and the circuit 14 Circuit 15 (column driver) that has the function of selecting and reading the converted data, and node A circuit 16 (pixel control circuit) that changes the operating mode of a pixel according to whether or not the FD is saturated, It has. Furthermore, a configuration without circuit 13 is also possible.

[0054] Figure 2(B) shows the schematic of circuit 13 connected to one row of the pixel array 11 and circuit 14. This is a block diagram. Circuit 13 consists of transistors 51, 52, and 5 3. The configuration can include capacitive elements C3 and C4. The configuration includes a comparator circuit 17, a determination output circuit 18, and a counter circuit 19. It is possible.

[0055] Transistor 54 functions as a current source circuit. The source of transistor 54 or Wiring 91 (OUT1) is electrically connected to one side of the drain, and the other side of the source or drain A power line is connected to this side. This power line can be, for example, a low-voltage power line. Furthermore, a bias voltage is always applied to the gate of transistor 54.

[0056] In circuit 13, either the source or drain of transistor 51 is connected to transistor 52 It is electrically connected to either the source or the drain of transistor 51. One side of the drain is electrically connected to one electrode of the capacitive element C3. Transistor 52 The other side of the source or drain is electrically connected to the other side of the source or drain of transistor 53. The source or drain of transistor 52 is connected to one side of the capacitive element C4. The electrodes are electrically connected. The source or drain of transistor 52 is connected to wiring 9. It is electrically connected to 2 (OUT2). The other side of the source or drain of transistor 53. The other electrode of the capacitive element C3 is electrically connected to the wiring 91 (OUT1). The source or drain of the converter 51 is, for example, a high-potential power supply to which a reference potential is supplied. It is electrically connected to the line (CDSVDD). The other electrode of the capacitive element C4 is, for example, at a low potential. It is electrically connected to the power line (CDSVSS).

[0057] An example of the operation of circuit 13 when connected to pixel 10 shown in Figure 1 will be explained. First, the transistor Connect the zista 51 and transistor 52. Next, connect the wiring 91 (OUT) from the pixel 10. 1) Output the potential of the imaging data, and connect the reference potential (CDSVDD) to wiring 92 (OUT2). Hold. Then, with transistor 51 non-conductive, wire 91 (OUT1) from pixel 10. Then, a reset potential (here, a potential higher than the potential of the imaging data, for example, the VDD potential) is set. Outputs the following. At this time, wiring 92 (OUT2) is the difference between the potential of the imaging data and the reset potential. The absolute value of the fraction is added to the reference potential (CDSVDD) to obtain the potential. Therefore, the reference potential ( The low-noise potential signal obtained by adding the net imaging data potential to CDSVDD is generated in circuit 1. It can be supplied to 4.

[0058] Note that the reset potential is lower than the potential of the imaging data (for example, the GND potential). In this case, wiring 92 (OUT2) uses the absolute value of the difference between the potential of the imaging data and the reset potential as the reference voltage. This is the potential obtained by subtracting from the position (CDSVDD).

[0059] Furthermore, if transistor 53 is made conductive, a bypass is formed, so wiring 91 (OU The signal from T1 can be directly output to wiring 92 (OUT2).

[0060] In circuit 14, the comparator circuit 17 compares the signal potential input from circuit 13 with the base The refractory potential (REF) is compared. Wiring 92 (OUT2) is connected to the comparator circuit 17. A signal potential corresponding to the first imaging data or the second imaging data is input via this. The first image data is the first exposure data, and it shows whether or not the node FD of pixel 10 is saturated. This is data for making that determination. Furthermore, the second imaging data is acquired according to that determination. This is the data from the second exposure.

[0061] First, when the first imaging data is input, the comparator circuit 17 sends a determination output to the determination output circuit 18. The result is output. The judgment output circuit 18 adjusts the timing of the output to control the comparator circuit 1. It has a function to remove noise output from 7.

[0062] In the comparator circuit 17, the first imaging data saturates the node FD of pixel 10. A determination is made as to whether or not this is true. At this time, the reference potential (REF) input to the comparator circuit 17 This is a constant potential corresponding to the saturation of node FD, and this potential corresponds to the first imaging data. The presence or absence of saturation is determined by comparing it with the signal potential. The signal potential corresponding to the first imaging data bypasses circuit 13 and passes through comparator circuit 1 The configuration is to input to 7, but without bypassing circuit 13, input to comparator circuit 17. That's fine.

[0063] If it is determined that node FD is not saturated, the determination output circuit 18 outputs the second imaging data The signal that is not acquired is output to circuit 16. Therefore, the signal corresponding to the first imaging data The position is input to the comparator circuit 17 via circuit 13. The reference potential input is a ramp wave, and it is compared with the signal potential corresponding to the first imaging data. The result is output to the counter circuit 19. The counter circuit 19 is connected to wiring 94(O The digital data corresponding to the first imaging data is output to UT4).

[0064] If node FD is determined to be saturated, the determination output circuit 18 takes the second imaging data. The signal that is beneficial is output to circuit 16. Circuit 16 also acquires second imaging data for pixel 10. It outputs a signal. The signal potential corresponding to the second imaging data is compared via circuit 13. The input is given to the power supply circuit 17. The reference potential input to the comparator circuit 17 is the lamp. The result of comparing the wave with the signal potential corresponding to the second imaging data is sent to the counter circuit 19. Output. Then, the counter circuit 19 receives the second imaging data via wiring 94 (OUT4). Outputs the corresponding digital data.

[0065] For the determination output circuit 18, for example, the circuit shown in Figure 3(A) can be used. The output terminal of the comparator circuit 17 is electrically connected to the input terminal (IN). Wiring 93 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. Judgment output Circuit 18 is reset by the JRES signal for each selected row, then the comparator circuit The result of the 17th judgment is output to circuit 16.

[0066] For example, the circuit shown in Figure 3(B) can be used for circuit 16. The input terminals of this circuit. Wiring 93 (OUT3) is electrically connected to (IN). Also, the output terminal of the circuit ( There are two OUT lines; one is electrically connected to wiring 61 (TX), and the other is connected to wiring 64 ( It is electrically connected to CN). From this circuit, wiring 61(TX) has terminal TX1 or terminal One of the signals input to child TX2 is output. Also, from this circuit to wiring 64(CN) This outputs one of the signals input to terminal CN1 or terminal CN2. A control signal is input to N, and the signals output from wiring 61 (TX) and wiring 64 (CN) are transmitted. It can also be fixed in place. Note that since circuit 16 has a latching function, when node FD is saturated If it is determined that the condition is met, the signal output from the determination output circuit 18 is held in circuit 16. Therefore, the signal will be retained even if the check is repeated until the last line.

[0067] The circuit described above can be operated according to the timing chart shown in Figure 4. Figure 4 RCK1 / 2 and RCKB1 / 2 shown are inputs to circuit 12 (low driver). The clock signal and the inverted clock signal, JRES are signals input to the circuit in Figure 3(A), GR ES and JENB are signals input to the circuit in Figure 3(B), and EN_CDS is the signal input to circuit 13. The signal SE[1] input to the gate of transistor 53 is connected to wiring 65 of pixel 10 in the first row. The input signal, SE[N], is the signal input to wiring 65 of pixel 10 in the last row.

[0068] The period indicated by frame[n] corresponds to the duration of the nth frame (where n is a natural number greater than or equal to 2). In the nth frame, period 401 is the period for reading the data from the (n-1)th frame, and period 4 02 is the period during which the first imaging data mentioned above is read out and a determination is made, and period 400 is low This is a period during which the driver is not functioning. Also, period 403 in the (n+1)th frame is the nth frame This is the period for retrieving the data from the frame.

[0069] Next, using the flowchart shown in Figure 5 and the timing chart shown in Figure 6, we can apply the following to Figure 1. The operation of the pixel 10 shown will be explained. An imaging apparatus in one aspect of the present invention is a global shutter It operates using a specific method, and within one frame, the operations are: acquisition of the first image data, and determination of the first image data. This can be broadly divided into acquiring the second image data and reading the image data from the previous frame. The acquisition of image data for frame 1 and the reading of image data from the previous frame are performed in parallel.

[0070] Figures 5 and 6 explain the process using an arbitrary nth frame as the reference point. Also, wiring 71 (VP D) and wiring 73 (VSS) are at low potential ("L"), wiring 72 (VRS) and wiring 74 (VPI) is defined as high potential ("H").

[0071] Furthermore, in Figure 6, GWRS is the potential of wiring 62 (GWRS), and RS[1] is the special value of the first row. The potential of wiring 63(RS) in a specific pixel 10, RS[N], is at a specific pixel 10 in the last row. The potential of wiring 63 (RS) is the potential of wiring 64 (CN), and TX is the potential of wiring 61 (TX ) is the potential of node AN at a specific pixel 10 in the first row, AN[1] is the potential of node AN, AN[N] is the potential of node AN at a specific pixel 10 in the last row, and FD[1] is a specific pixel in the first row. The potential of node FD at 10, FD[N] is the potential of node F at a specific pixel 10 in the last row. This is the potential of D.

[0072] First, regarding the acquisition of the first imaging data and the reading of the imaging data acquired in the previous frame... I will explain.

[0073] The imaging mode for the first image data has a relatively long exposure time and wide dynamic range in low-light environments. A mixed-range image can be obtained. On the other hand, because the exposure time is relatively long, in high-light environments... Node FD becomes saturated. Note that in the timing chart in Figure 6, the determination of the first imaging data. This shows the behavior when node FD is saturated.

[0074] At time T1, if GWRS is "H", then AN[1:N] is reset to "H". (The potential of wiring 72 (VRS) is (S1).

[0075] At time T2, if GWRS is "L", then AN[1:N] begins to decrease in accordance with the illuminance. Meru (first exposure, S2).

[0076] At time T3, if RS[1:N] is "H" and CN is "H", then FD[1:N] is It is reset and becomes "H" (potential of wiring 72 (VRS)) (S3). At this time, No A capacitive element C2 is electrically connected to the FD via transistor 44.

[0077] At time T4, if RS[1:N] is "L", CN is "L", and TX is "H", then The electrical connection between the FD and the capacitive element C2 is disconnected, and the node at the time of reset is connected to the capacitive element C2. The potential of FD is maintained. Also, the potential of node AN is transferred to node FD, and node FD The potential begins to decrease (S4).

[0078] At time T5, if TX is set to "L", FD[1:N] is retained. This is the acquisition operation of the imaging data for the first time.

[0079] Here, between times T1 and T3, SE[1] to SE[N] sequentially become "H" for a certain period, and the imaging data determined in the (n - 1)-th frame is read out (S10'). That is, the acquisition operation of the first imaging data of the n-th frame described above and the reading of the imaging data determined in the (n - 1)-th frame are performed in parallel. By reading the imaging data in the next frame in this way, even in the global shutter method, the time allocated for exposure etc. can be lengthened . Therefore, an image with a wide dynamic range and low noise can be acquired even under low illumination conditions.

[0080] FIG. 7(A) is a timing chart for explaining the reading of the imaging data of the first line. SH is the potential supplied to the gate of transistor 52 in circuit 13, CL is the potential supplied to the gate of transistor 51 in circuit 13, REF(RAMP) is the reference potential supplied to comparator circuit 17, OUT2 is the potential of wiring 92(OUT2), and COMP_OUT is the potential of the output terminal of comparator circuit 17.

[0081] In FIG. 6, before time T3, RS[1] to RS[N] sequentially become "H" for a certain period, and node FD is reset, which is an operation accompanying the operation of circuit 13 shown in FIG. 7(A).

[0082] / Next, the determination of the first imaging data and the operations accompanying the determination result will be described.

[0083] Between times T6 and T8, SE[1] through SE[N] sequentially become "H" for a certain period of time, Each time, the first image data is read out, and the presence or absence of node FD saturation is checked for all valid pixels. The judgment is made (S5).

[0084] Figure 7(B) illustrates the timing of the readout of the first imaging data at times T6 to T8. This is a chart. During the readout period of the first imaging data, set EN_CDS to "H" and CL to Set to "H", the signal output from pixel 10 bypasses circuit 13 and goes through the comparator circuit Input to 17. Assume the potential of REF(CONST) is constant and that node FD is saturated. The value should be slightly greater than the potential output to wiring 91 (OUT1). By operating the circuit, the output of the comparator circuit 17 determines whether or not node FD is saturated. This is possible. Note that in Figure 7(B), the node FD of the selected specific pixel 10 is saturated. This indicates the state when the comparator circuit 17 is in operation, and an "L" is output from its output terminal. This is done. Note that by setting EN_CDS to "L" and not bypassing circuit 13, the first imaging day The value of the 'ta' may be read. At this time, "H" will be output from the output terminal of the comparator circuit 17. It will be done.

[0085] At this time, the first imaging data is used to determine whether or not node FD is saturated, and It is not output to the section. Therefore, circuits such as the 15 (column driver) required for external output are not included. The operation of the output circuit may be stopped.

[0086] The result of the first imaging data is output to circuit 16 via the determination output circuit 18. Since all output terminals of the judgment output circuit 18 for each column are connected to wiring 93 (OUT3), If it is determined that the node FD of any one of the pixels 10 is saturated, then circuit 16 The system performs the operation of setting CN to "H" and TX to "H" at the specified time, and the second imaging data Switching to acquisition mode. This completes the determination of the first imaging data and the determination result. It is an accompanying action.

[0087] Next, we will explain how to acquire the second set of imaging data. Note that the imaging mode for the second set of imaging data will also be explained. This method allows for relatively short exposure times and produces images with a wide dynamic range in high-light environments. .

[0088] Regardless of the judgment result of the first imaging data, or before all judgment results are available, the second imaging An exposure operation to acquire data may be performed. For example, as shown in Figure 6, at time T7 Then, set GWRS to "H" and reset AN[1:N] (S6). Then, time T Set GWRS to "L" in step 8 and perform the second exposure by time T10 (S7). Note that 2 For the second exposure, the exposure time is longer than the first exposure to prevent node FD from saturating. To shorten.

[0089] At time T9, before the second exposure is completed, circuit 16 operates to set CN to "H", and Connect the zista 44 to reconnect the node FD and the capacitive element C2 electrically.

[0090] Immediately before time T9, node FD is in an electron-saturated state, i.e., the voltage is 0. In this state, at time T9, the capacitive element C2 retains the potential at the time of node FD's reset. Because they are electrically connected, the stored electrons are divided and the potential of node FD rises (S8). .

[0091] At time T10, when the circuit 16 operates to set CN to "L" and TX to "H", the potential of node AN is transferred to node FD (S9).

[0092] At time T11, when TX is set to "L", FD[1:N] is held. This is the operation for acquiring the second imaging data. Also, the second imaging data is read out as the imaging data of the n-th frame in the (n + 1)-th frame (S10).

[0093] FIG. 8 is a timing chart when it is determined that there is no saturation of node FD due to the first imaging data. When none of the nodes FD of all the pixels 10 are saturated, the circuit 16 does not perform the operation of setting CN and TX to "H". That is, it does not switch to the mode of acquiring the second imaging data. Therefore, the data acquired as the first imaging data is read out as it is. When it is determined that there is no saturation of node FD, the operation of setting GRS to "H" at times T7 to T8 may be disabled, and the second exposure may not be performed. As described above, the imaging device according to an aspect of the present invention operates in a global shutter system. Therefore, when it is determined that even one of the nodes FD of all the pixels 10 is saturated, it switches to the mode of acquiring the second imaging data, and the second imaging data is acquired for all the pixels 10.

[0094] As described above, the imaging device according to an aspect of the present invention operates in a global shutter system. Therefore, when it is determined that even one of the nodes FD of all the pixels 10 is saturated, it switches to the mode of acquiring the second imaging data, and the second imaging data is acquired for all the pixels 10.

[0095] By the above operation, the second imaging data can be automatically acquired as necessary, and the gradation of the bright part can be maintained even in imaging of a field where light and darkness are mixed. That is, an image with a wide dynamic range can be acquired. Also, noise is reduced even under low illuminance conditions. It is possible to obtain images with a wide dynamic range that maintain tonal gradation with minimal exposure to light.

[0096] Pixel 10 may have the configuration shown in Figure 9. Pixel 10 shown in Figure 9 is a photoelectric conversion element PD The orientation in which it is connected is different from that of pixel 10 shown in Figure 1. Pixel 10 shown in Figure 9 is the same as the one in Figure 11. Timing chart (with acquisition of second imaging data) or timing chart in Figure 12 (second It can be operated according to (2) without acquiring imaging data. At this time, wiring 71 (V PD) and wiring 74 (VPI) are high potential ("H"), wiring 72 (VRS), wiring 73 ( The VSS (Voltage-Sensitive State) is set to low potential ("L").

[0097] In this case, nodes AN and FD become saturated with electrons upon reset, resulting in high illuminance. Nodes AN and FD will be in a state of electron deficiency. Therefore, as shown in Figure 1 above... The potentials of nodes AN and FD change in the opposite direction to the description of the operation of pixel 10 shown. do.

[0098] Furthermore, pixel 10 may have the configuration shown in Figures 10(A) and (B). Figure 10(A) shows a tiger This configuration does not include the inverter 42. In this configuration, the potential of the wiring 71 (VPD) is set to a high potential. By doing so, the potential of node AN can be reset. Figure 10(B) shows the transistor The ZISTA 45 is configured so that either the source or the drain is connected to wiring 91 (OUT).

[0099] Furthermore, the transistor used in pixel 10 is as shown in Figures 13(A) and (B), A configuration in which back gates are provided on transistors 41 to 46 may also be used. Figure 13(A This configuration applies a constant potential to the back gate, allowing the threshold voltage to be controlled. In Figure 13(A), as an example, wiring 71 (VPD) is supplied with a low potential by the back gate. The example shows connection to either wire 73 (VSS) or wire 75 (VSS2), but either one is acceptable. It may also be configured to connect to a single wire. Also, Figure 13(B) is the same as the front gate. The configuration applies a potential to the back gate, increasing the on-current and decreasing the off-current. This can be done. Also, to ensure that the desired transistor has appropriate electrical characteristics, Figure 1 A configuration combining the configurations shown in 3(A) and Figure 13(B) may also be used. Some transistors may not have a gate. Also, see Figures 9, 10(A), and (B). The configurations of 13(A) and (B) can be combined as needed.

[0100] Pixel 10 has multiple transistors 43 to 46, as shown in Figure 14. It may also be a shared configuration. In Figure 14, multiple pixels in the vertical direction use transistors 43 to The example shows a configuration in which the Rangista 46 is shared, but multiple horizontal or horizontal-vertical configurations are also shown. It may be shared by pixels. With this configuration, the transients that each pixel possesses It can reduce the number of items.

[0101] Furthermore, Figure 14 shows a configuration in which transistors 43 to 46 are shared by four pixels. As shown, it may also be a form shared by 2 pixels, 3 pixels, or 5 or more pixels. The configurations in Figure 9, Figure 10(A), (B), and Figure 13(A), (B) can be arbitrarily chosen. They can be combined.

[0102] Furthermore, an imaging device according to one aspect of the present invention has a pixel array 11 and circuits 12 to 16 A laminated structure with substrate 35 can be formed. For example, Figure 15(A) can be placed on top of the pixel array 11. When Figure 15(B) is a top view of the substrate 35, the front view shown in Figure 15(C) is as follows: A stacked configuration of the pixel array 11 and the substrate 35 can be used. With this configuration, Transistors suitable for each element can be used, and the area of ​​the imaging device can be reduced. This is possible. Note that the circuit layout in Figure 15(B) is just one example, and other layouts are also possible. It's okay to be out.

[0103] Circuits 12 to 16 are designed to achieve both high-speed operation and a CMOS circuit configuration, using silicon It is preferable to fabricate it using a transistor (hereinafter referred to as a Si transistor). For example, if the substrate 35 is a silicon substrate, the above circuit can be formed on the silicon substrate. Furthermore, the pixel array 11 uses an oxide semiconductor transistor (hereinafter referred to as OS transistor). It is preferable to manufacture using a stool. Note that some of the components of circuits 12 to 16 The transistors may be placed on the same plane as the pixel array 11.

[0104] A specific example of the configuration of an imaging device according to one aspect of the present invention will be described with reference to the drawings. Figure 16 (A) The cross-sectional view shows the photoelectric conversion element PD and transistor 4 in pixel 10 shown in Figure 1. 1. This shows an example of a specific connection configuration for transistor 43 and capacitive element C1. Figure 16(A) shows transistors 42, 44, 45, and Transistors 46 and capacitive element C2 are not shown. Transistors 41 to 4 6 and the capacitive elements C1 and C2 are provided in layer 1100, and the photoelectric conversion element PD is provided in layer 1200. It is possible.

[0105] In the cross-sectional view described in this embodiment, the wiring, electrodes and contact plug (conductor 8 1) Although they are shown as individual elements, when they are electrically connected They may also be provided as the same element. Furthermore, the wiring and electrodes are connected via the conductor 81. The configuration described is just one example; in some cases, the electrodes may be directly connected to the wiring.

[0106] On each element is an insulating layer 82 having the function of a protective film, interlayer insulating film, or planarizing film and An insulating layer 83, etc., is provided. For example, the insulating layer 82 and insulating layer 83, etc. are silicon oxide films. Inorganic insulating films such as silicon oxide nitride films can be used. Alternatively, acrylic resin, Organic insulating films such as polyimide resin may be used. Insulating layer 82 and insulating layer 83 etc. The top surface is treated with CMP (Chemical Mechanical Polish) as needed. It is preferable to perform a flattening treatment using the ing method or similar methods.

[0107] In addition, if some of the wiring shown in the drawings is not provided, or if there is wiring or other elements not shown in the drawings, Rangings and other components may be included in each layer. Additionally, layers not shown in the drawings may be included. Yes, it is. Also, some of the layers shown in the drawing may not be included.

[0108] The transistors 41 to 46, which are components of the pixel 10, have a low off-current. It is preferable to use an OS transistor. OS transistors have extremely low off-current characteristics. Because it has this feature, the dynamic range of imaging can be expanded. Pixel 10 shown in Figure 1 In this circuit configuration, when the intensity of light incident on the photoelectric conversion element PD is large, node AN and The potential of the FD node decreases. Transistors using oxide semiconductors have extremely low off-current. Because the current is low, even when the gate potential is extremely small, the current corresponding to the gate potential is positive. It can reliably output. Therefore, the range of illuminance that can be detected, i.e. It can widen the dynamic range.

[0109] Also, transistors 41, 42, 43 and 44 Its low off-current characteristics allow for the maximum period during which charge can be held at nodes AN and FD. This allows for longer operation. Therefore, all pixels can be used without complicating the circuit configuration or operating method. A global shutter system that simultaneously performs charge accumulation operations can be applied. An imaging device according to one aspect of the present invention can also be operated using a rolling shutter method.

[0110] The operation method of the imaging device will be explained using Figures 17(A), (B), and (C). In (A), (B), and (C), "E" is the period during which exposure can be performed, and "R" is the readout period. This refers to the period during which the operation can be performed. Also, n is any nth frame (n is a natural number greater than or equal to 2). This refers to the nth frame. Also, n-1 is the frame immediately preceding the nth frame, n+ 1 represents the frame immediately following the nth frame. Also, Line[1] represents pixel array 1 The first row of 1, Line[M] is the Mth row of the pixel array 11 (in Figure 17, M is 4 or greater). It means (a natural number).

[0111] Figure 17(A) is a schematic diagram illustrating the operation of the rolling shutter system. The shutter method is an operation method in which exposure and data reading are performed sequentially for each row. Because the imaging is not simultaneous, image distortion occurs when imaging moving objects.

[0112] Figure 17(B) is a schematic diagram illustrating the operation of a typical global shutter system. The Balshatter method is an operation that exposes all pixels simultaneously and then reads out the data row by row. This is the law. Therefore, even when imaging moving objects, distortion-free images can be obtained.

[0113] Figure 17(C) is a schematic diagram illustrating an operating method applied to an imaging device according to one embodiment of the present invention. In this operation method, all pixels are simultaneously exposed in the nth frame, and in the (n+1)th frame, The data acquired in n frames will be read. Therefore, the same data within one frame period Because frame exposure and readout are not performed, unlike conventional global shutter systems, readout is... The exposure time is not limited by the increase in exposure time. Therefore, the exposure time can be extended. It is possible.

[0114] OS transistors are more electrically charged than transistors that use silicon in the active region or active layer. Because the temperature dependence of the characteristic changes is small, it can be used over an extremely wide temperature range. Therefore, imaging devices and semiconductor devices having OS transistors are used in automobiles, aircraft, and space. It is also suitable for installation on aircraft and other vehicles.

[0115] Furthermore, OS transistors have a higher drain breakdown voltage than Si transistors. In photoelectric devices using selenium-based materials as the photoelectric conversion layer, avalanche multiplication is utilized to It is preferable to operate it by applying a relatively high voltage (for example, 10V or higher). By combining an OS transistor with a photoelectric conversion element that uses a selenium-based material as the photoelectric conversion layer... This makes it possible to create a highly reliable imaging device.

[0116] In Figure 16(A), each transistor is shown as having a back gate, As shown in Figure 16(B), it may also be a configuration without a back gate. As shown in (C), only some transistors, for example transistor 41, have a back gate. It may be in a form that has such a configuration. The back gate is provided opposite to the transit It may be electrically connected to the front gate of the tailgate. Alternatively, the tailgate may be electrically connected to the rear gate. A fixed potential different from that of the back gate may be supplied. This configuration can also be applied to other pixel configurations described in this embodiment.

[0117] The photoelectric conversion element PD provided in layer 1200 can be of various forms. Figure 16(A) illustrates a configuration in which a selenium-based material is used in the photoelectric conversion layer 561. Photoelectric converters (PDs) using ion-based materials have the characteristic of high external quantum efficiency for visible light. Furthermore, selenium-based materials have a high light absorption coefficient, which offers the advantage of making the photoelectric conversion layer 561 thinner. It possesses. In photoelectric converters (PDs) using selenium-based materials, amplification is greatly increased by avalanche doubling. This allows for a highly sensitive sensor. In other words, by using a selenium-based material in the photoelectric conversion layer 561... By having this, a sufficient photocurrent can be obtained even if the pixel area is reduced. Therefore, Photoelectric converters (PDs) using ion-based materials are also suitable for imaging in low-light environments. .

[0118] As selenium-based materials, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be obtained by heat-treating amorphous selenium after film formation. By making the crystal grain size smaller than the pixel pitch, the variation in characteristics between pixels can be reduced. This is possible. Furthermore, crystalline selenium has better spectral sensitivity to visible light and light absorption than amorphous selenium. It has the characteristic of having a high coefficient.

[0119] In Figure 16(A), the photoelectric conversion layer 561 is shown as a single layer, but as shown in Figure 18(A) As such, a hole injection blocking layer 568 is made on the light-receiving surface side using gallium oxide, cerium oxide, or In- Ga-Zn oxide or the like may be provided. Alternatively, as shown in Figure 18(B), electrode 566 A nickel oxide or antimony sulfide layer may be provided on the side as an electron injection blocking layer 569. Alternatively, as shown in Figure 18(C), the hole injection blocking layer 568 and the electron injection blocking layer 56 A configuration including 9 is also possible. Note that, as shown in Figures 1 and 9, the photoelectric transformer in pixel 10 The orientation of the connection of the PD element can be different. Therefore, Figure 18(A) The hole injection blocking layer 568 and the electron injection blocking layer 569 shown in Figure 18(C) are swapped. It may be possible.

[0120] The photoelectric conversion layer 561 may be a layer containing a copper, indium, and selenium compound (CIS). i. Or, a layer containing a copper, indium, gallium, and selenium compound (CIGS). This is also good. CIS and CIGS utilize avalanche multiplication, similar to selenium monolayers. A photoelectric conversion element can be formed.

[0121] A photoelectric conversion element PD using a selenium-based material has electrodes 56 formed from, for example, a metal material. A configuration can be provided in which a photoelectric conversion layer 561 is located between 6 and the light-transmitting conductive layer 562. Furthermore, CIS and CIGS are p-type semiconductors, and the sulfidation of n-type semiconductors is necessary to form a junction. Cadmium or zinc sulfide may be provided in contact with the material.

[0122] In Figure 16(A), the translucent conductive layer 562 and the wiring 71 are in direct contact, but in Figure 19 As shown in (A), the two may be connected via wiring 88. Also, as shown in Figure 16(A In this configuration, the photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are not separated between the pixel circuits. However, as shown in Figure 19(B), a configuration in which the circuits are separated may also be used. In this configuration, an insulating partition 567 is provided in the region that does not have electrodes 566, and a photoelectric conversion layer 561 It is preferable to prevent cracks from forming in the translucent conductive layer 562, as shown in Figure 19(C). Alternatively, a configuration without a partition wall 567 may be used, as shown in (D).

[0123] Furthermore, electrodes 566 and wiring 71, etc., may be multilayered. For example, as shown in Figure 20(A) In addition, the electrode 566 is made of two layers, conductive layer 566a and conductive layer 566b, and the wiring 71 is made of conductive layer It can consist of two layers: 71a and a conductive layer 71b. In the configuration shown in Figure 20(A), For example, conductive layers 566a and 71a may be formed using a low-resistance metal or the like, and conductive layer 566b and the conductive layer 71b are selected from metals or other materials that have good contact characteristics with the photoelectric conversion layer 561. It is preferable to form it in this way. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. It can be done. Also, some metals can be galvanically treated by contact with the translucent conductive layer 562. This can occur. Even if such a metal is used for the conductive layer 71a, the conductive layer 71b may be involved. This can prevent galvanic corrosion.

[0124] For example, the conductive layers 566b and 71b may be made of molybdenum or tungsten. It is possible to do so. In addition, conductive layers 566a and 71a may contain, for example, aluminum. Lamination can be used, such as sandwiching titanium or aluminum between layers of titanium.

[0125] Furthermore, as shown in Figure 20(B), the translucent conductive layer 562 and the wiring 71 are conductor 81 and wiring The connection may be made via 88. Alternatively, the insulating layer 82, etc., may be configured as a multi-layer structure. Example For example, as shown in Figure 20(B), the insulating layer 82 has insulating layer 82a and insulating layer 82b Furthermore, if the etching rates of insulating layer 82a and insulating layer 82b are different, the conductor 81 This will result in a step. Other insulating layers used in interlayer insulating films and planarizing films are multilayered. In some cases, the conductor 81 will also have a step. Here, the insulating layer 82 is two layers. Although an example has been shown, the insulating layer 82 and other insulating layers may consist of three or more layers.

[0126] The partition wall 567 can be formed using an inorganic insulator or an insulating organic resin. Wall 567 provides light shielding for transistors, etc., and / or the area of ​​the light-receiving part per pixel. It may be colored black or other colors to confirm its identity.

[0127] Furthermore, photoelectric conversion elements (PDs) use a pin-like structure with an amorphous silicon film or a microcrystalline silicon film. Diode elements such as type diodes may also be used.

[0128] For example, Figure 21 shows an example in which a pin-type thin-film photodiode is used as the photoelectric conversion element PD. The photodiode consists of an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type semiconductor layer. The semiconductor layer 563 of type i is stacked in order. It is preferable to use silicon. Also, p-type semiconductor layer 563 and n-type semiconductor layer 5 65 contains amorphous silicon or microcrystalline silicon containing dopants that impart each conductivity type. Recon and other materials can be used. A photodiode using amorphous silicon as the photoelectric conversion layer. It has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0129] In the photoelectric conversion element PD shown in Figure 21, the n-type semiconductor layer 565 that acts as the cathode is The configuration is such that the electrode 566 has an electrical connection with the transistor 41. The p-type semiconductor layer 563, acting as a node, is electrically connected to the wiring 71 via the wiring 88. It has.

[0130] Furthermore, the anode and cathode of the photoelectric conversion element PD and the electrode layer and wiring are respectively By reversing the connection configuration, the circuit can be configured according to the circuit diagram shown in Figure 9.

[0131] In either case, the photoelectric conversion element PD is configured such that the p-type semiconductor layer 563 becomes the light-receiving surface. It is preferable to form a p-type semiconductor layer 563 as a light-receiving surface, which is a photoelectric conversion element. This allows for an increase in the output current of the PD (Photon Detector).

[0132] Furthermore, the configuration of the photoelectric conversion element PD having the form of a pin-type thin-film photodiode, and The connection configuration of the photoelectric conversion element PD and wiring is as shown in the examples in Figures 22(A), (B), and (C). It may be present. Note that the configuration of the photoelectric conversion element PD and the connection method between the photoelectric conversion element PD and the wiring are as follows: These are not the only forms; other forms are also acceptable.

[0133] Figure 22(A) shows the translucent conductive layer 562 in contact with the p-type semiconductor layer 563 of the photoelectric conversion element PD. The configuration includes the translucent conductive layer 562 acting as an electrode, and the output of the photoelectric conversion element PD. The current can be increased.

[0134] The translucent conductive layer 562 contains, for example, indium tin oxide, silicon-containing indium tin oxide. Indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, aluminum Contains zinc oxide, tin oxide, fluorine-containing tin oxide, antimony-containing tin oxide, graphene, Graphene oxide and the like can be used. Also, the light-transmitting conductive layer 562 is not limited to a single layer, It may be a stacking of different films.

[0135] Figure 22(B) shows that the translucent conductive layer 562 and the wiring 71 are in contact via the conductor 81 and the wiring 88. This is a continuation of the configuration. Furthermore, the p-type semiconductor layer 563 and wiring 71 of the photoelectric conversion element PD are conductive. It can also be configured to be connected via body 81 and wiring 88. See Figure 22(B). In this configuration, the light-transmitting conductive layer 562 may be omitted.

[0136] Figure 22(C) shows an opening where a p-type semiconductor layer 563 is exposed in the insulating layer covering the photoelectric conversion element PD. A section is provided, and the light-transmitting conductive layer 562 covering the opening and the wiring 71 have an electrical connection. It is structured.

[0137] Furthermore, as shown in Figure 23, the photoelectric conversion element PD has a silicon substrate 600 as the photoelectric conversion layer. A photodiode can also be used.

[0138] The photoelectric conversion element PD formed using the aforementioned selenium-based material or amorphous silicon is a thin film. It is manufactured using common semiconductor fabrication processes such as lithography and etching. This can be done. Also, selenium-based materials have high resistance, and as shown in Figure 16(A), photoelectric transformation The switching layer 561 can also be configured not to be separated between circuits. Therefore, one aspect of the present invention The imaging device has a high yield and can be manufactured at low cost. On the other hand, the silicon substrate When forming a photodiode with 600 as the photoelectric conversion layer, polishing and bonding processes are required. This requires highly complex processes such as [specific steps / methods].

[0139] Furthermore, an imaging device according to one aspect of the present invention is provided in which a silicon substrate 600 on which a circuit is formed is stacked This configuration may also be used. For example, as shown in Figure 24(A), an active region may be placed on the silicon substrate 600. A layer 1400 having transistors 610 and 620 is a pixel circuit An overlapping configuration is possible. Figure 24(B) is a cross-sectional view of the transistor in the channel width direction. It corresponds to this.

[0140] Here, in Figures 24(A) and (B), the Si transistor is shown as an example of a fin-type configuration. However, a planar type may also be used, as shown in Figure 25(A). Or, Figure 25(B) As shown, the transistor may have an active layer 650 made of a silicon thin film. The active layer 650 is made of polycrystalline silicon or SOI (Silicon on Insulation). It can be a single crystal silicon of type r).

[0141] The circuit formed on the silicon substrate 600 has the function of reading out the signal output by the pixel circuit and the It can have functions such as signal conversion processing, for example, as shown in the circuit diagram in Figure 25(C). The configuration can include a CMOS inverter as shown. Transistor 610(nc The gates of the h-type transistor and transistor 620 (p-channel type) are electrically connected. One of the sources or drains of one transistor is connected to the source or drain of the other transistor. It is electrically connected to one of the drains. Also, the source or drain of both transistors The other end of each input is electrically connected to a separate wire.

[0142] The circuits formed on the silicon substrate 600 are shown, for example, in Figures 2(A) and 15(B). This corresponds to circuits 12, 13, 14, 15, 16, etc.

[0143] Furthermore, the silicon substrate 600 is not limited to bulk silicon substrates, but also germanium, silicon, and Lumanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphate It is also possible to use substrates made of gallium nitride or organic semiconductors.

[0144] Here, as shown in Figures 23 and 24(A) and (B), a transistor having an oxide semiconductor The region where the zista is formed and the Si device (Si transistor or Si photodiode) An insulating layer 80 is provided between the region where (D) is formed and the region where (D) is formed.

[0145] Water in the insulating layer provided near the active regions of transistors 610 and 620 The element terminates the dangling bond of silicon. Therefore, the hydrogen is in transistor 6. This has the effect of improving the reliability of transistors 10 and 620. On the other hand, transistor 4 Hydrogen in the insulating layer located near the oxide semiconductor layer, which is the first active layer, is in the oxide semiconductor It is one of the factors that generate carriers in the layer. Therefore, the hydrogen is used in transistor 41, etc. This can sometimes lead to a decrease in reliability. Therefore, when using silicon-based semiconductor materials... One layer has transistors, and the other layer has transistors made of oxide semiconductors. When stacking layers, an insulating layer 80 is provided between them to prevent hydrogen diffusion. Preferably, the insulating layer 80 traps hydrogen in one layer, thereby enabling the transistor 6 The reliability of transistors 10 and 620 can be improved. Also, from one layer to the other By suppressing the diffusion of hydrogen into the other layer, the reliability of transistors such as transistor 41 is also improved. It is possible.

[0146] Examples of insulating layer 80 include aluminum oxide, aluminum oxide nitride, and gallium oxide. Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxide Hafnium nitride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0147] In configurations like those shown in Figures 24(A) and (B), the circuits formed on the silicon substrate 600 (e.g., For example, the drive circuit, the transistor 41, and the photoelectric conversion element PD are formed to overlap. This allows for an increase in the density of pixels. In other words, the resolution of the imaging device can be increased. It can be increased. For example, imaging with a pixel count of 4K2K, 8K4K, or 16K8K. It is suitable for use in the device. Note that the transistor 45 and transistors of the pixel 10 Transistor 46 is formed with Si transistors, transistor 41, transistor 42, and The configuration shall have overlapping regions with components such as 43, transistor 44, and photoelectric conversion element PD. It's also possible.

[0148] Furthermore, an imaging device according to one aspect of the present invention can have the configuration shown in Figure 26. The imaging device is a modified version of the imaging device shown in Figure 24(A), and includes an OS transistor and Si This diagram illustrates an example of a CMOS inverter constructed using transistors.

[0149] Here, the Si transistor 620 provided in layer 1400 is of the p-channel type. Furthermore, the OS transistor 610 provided in layer 1100 is of the n-channel type. By providing only p-channel transistors on the silicon substrate 600, well formation and n-channel transistors can be achieved. This eliminates the need for processes such as impurity layer formation.

[0150] The imaging device shown in Figure 26 is an example in which selenium or the like is used as the photoelectric conversion element PD, but Figure 21 and Similarly, a configuration using a pin-type thin-film photodiode may also be used.

[0151] In the imaging apparatus shown in Figure 26, the transistor 610 is a transistor formed in layer 1100 It can be manufactured using the same process as the st 41 and transistor 43. The manufacturing process for the imaging device can be simplified.

[0152] Furthermore, as shown in Figure 27, an imaging device according to one aspect of the present invention is formed on a silicon substrate 660 A pixel composed of a photoelectric conversion element PD and an OS transistor formed on it. This configuration may be used in which a silicon substrate 600 on which a circuit is formed is bonded together. By adopting this configuration, the effective performance of the photoelectric conversion element PD formed on the silicon substrate 660 This makes it easier to increase the surface area. Furthermore, it makes it easier to miniaturize the circuits formed on the silicon substrate 600. By integrating these Si transistors to a high degree of density, we can provide high-performance semiconductor devices. ru.

[0153] Furthermore, as a modified example of Figure 27, as shown in Figure 28, an OS transistor and a Si transistor are used. The circuit may also be constructed using a zista. With this configuration, the silicon base This makes it easier to improve the effective area of ​​the photoelectric conversion element PD formed on the plate 660. The circuit formed on the silicon substrate 600 is highly integrated using miniaturized Si transistors. This enables the provision of high-performance semiconductor devices.

[0154] In the configuration shown in Figure 28, a Si transistor is formed on the silicon substrate 600 and on top of it A CMOS circuit can be constructed using the formed OS transistor. Because it has an extremely low off-current, it can be used to construct a CMOS circuit with extremely low static leakage current. It is possible.

[0155] The configuration of the transistors and photoelectric conversion elements in the imaging device in this embodiment is as follows: This is just one example. Therefore, for example, any of transistors 41 to 46, Alternatively, one or more transistors may be constructed with silicon or the like in their active region or active layer. It is also possible to utilize both or either transistor 610 and transistor 620. It can also be constructed as a transistor having an oxide semiconductor layer in the polarity layer.

[0156] Figure 29(A) is a cross-sectional view of an example of an imaging device with a color filter and the like added. The cross-sectional view shows a portion of the region having a pixel circuit for 3 pixels. The photoelectric conversion element PD is An insulating layer 2500 is formed on the layer 1200 that is formed. The insulating layer 2500 is visible to light. In contrast, highly transparent silicon oxide films can be used. Also, passivation A configuration in which silicon nitride films are laminated as the film may also be used. Alternatively, as the anti-reflective film, A configuration in which dielectric films such as humic acid are stacked may also be used.

[0157] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 is on top It has the function of preventing the mixing of colors of light passing through the color filter. The light-shielding layer 2510 is made of aluminum Metal layers such as um and tungsten, or dielectrics that function as an anti-reflective coating with the said metal layers. A configuration in which multiple films are stacked can be used.

[0158] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. It can be configured as follows. Also, a color filter 2530 (color filter 25 30a, color filter 2530b, color filter 2530c) are formed. , color filter 2530a, color filter 2530b and color filter 2530 c can represent R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0159] A light-transmitting insulating layer 2560 or the like can be provided on the color filter 2530. ru.

[0160] Also, as shown in Figure 29(B), instead of the color filter 2530, the optical conversion layer 255 You may also use 0. With this configuration, images can be obtained in various wavelength ranges. It can be used as an imaging device.

[0161] For example, if a filter that blocks light with wavelengths below visible light is used in the optical conversion layer 2550, infrared It can be used as an imaging device. Furthermore, the optical conversion layer 2550 blocks light with wavelengths below near-infrared. By using a filter, it can be made into a far-infrared imaging device. Also, the optical conversion layer 2550 If a filter that blocks light with a wavelength equal to or longer than that of visible light is used, an ultraviolet imaging device can be obtained. .

[0162] Also, if a scintillator is used for the optical conversion layer 2550, an imaging device that can obtain an image visualizing the intensity of radiation, such as an X-ray imaging device, can be obtained. When radiation such as X-rays passing through a subject enters the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. Then, image data is acquired by detecting the light with the photoelectric conversion element PD. Further, an imaging device having such a configuration may be used for a radiation detector or the like. When radiation such as X-rays passing through a subject enters the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. Then, image data is acquired by detecting the light with the photoelectric conversion element PD. Further, an imaging device having such a configuration may be used for a radiation detector or the like. When radiation such as X-rays passing through a subject enters the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. Then, image data is acquired by detecting the light with the photoelectric conversion element PD. Further, an imaging device having such a configuration may be used for a radiation detector or the like. When radiation such as X-rays passing through a subject enters the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence.

[0163] A scintillator contains a substance that emits visible light or ultraviolet light by absorbing the energy when irradiated with radiation such as X-rays or gamma rays. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO dispersed in resin or ceramics can be used. A scintillator contains a substance that emits visible light or ultraviolet light by absorbing the energy when irradiated with radiation such as X-rays or gamma rays. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO dispersed in resin or ceramics can be used. A scintillator contains a substance that emits visible light or ultraviolet light by absorbing the energy when irradiated with radiation such as X-rays or gamma rays. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO dispersed in resin or ceramics can be used.

[0164] In a photoelectric conversion element PD using a selenium-based material, since radiation such as X-rays can be directly converted into electric charges, a configuration that does not require a scintillator can also be adopted. In a photoelectric conversion element PD using a selenium-based material, since radiation such as X-rays can be directly converted into electric charges, a configuration that does not require a scintillator can also be adopted.

[0165] Also, as shown in FIG. 29(C), a microlens array 2540 may be provided on the color filter 2530a, the color filter 2530b, and the color filter 2530c. Light passing through each lens of the microlens array 2540 passes through the color filter directly below and is irradiated onto the photoelectric conversion element PD. Also, as shown in FIG. 29(D), light Light passing through each lens of the microlens array 2540 passes through the color filter directly below and is irradiated onto the photoelectric conversion element PD. Also, as shown in FIG. 29(D), light A microlens array 2540 may be provided on the light conversion layer 2550. See Figure 29(A The region other than layer 1200 shown in (B), (C), and (D) is defined as layer 1600.

[0166] Figure 30 shows a pixel 10 according to one aspect of the present invention and a microlens array 2 shown in Figure 29(C). This figure illustrates specific stacking configurations such as 540. Figure 30 shows the pixels shown in Figure 24(A) This is an example using the configuration shown in Figure 28. Figure 31 also shows an example using the pixel configuration shown in Figure 28.

[0167] In this way, the photoelectric conversion element PD, the circuit of the pixel 10, and the drive circuit each interact with each other. Because it can be configured to have an overlapping region, the imaging device can be miniaturized. can.

[0168] Furthermore, as shown in Figures 30 and 31, a diffraction grating is located above the microlens array 2540. A configuration with 1500 is also possible. Image of the subject through the diffraction grating 1500 (diffraction image) The image is captured into a pixel, and the input image (image of the subject) is calculated from the captured image at the pixel. It can be configured. Also, by using a diffraction grating 1500 instead of a lens, the imaging device Installation costs can be reduced.

[0169] The diffraction grating 1500 can be formed from a translucent material. For example, silicone oxide Inorganic insulating films such as silicon oxide nitride films can be used. Alternatively, acrylic resin can be used. Organic insulating films such as lipids and polyimide resins may be used. Alternatively, the above inorganic insulating film and It may also be laminated with an insulating film.

[0170] Furthermore, the diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. Yes, it is possible. It can also be formed using lithography and etching processes. Furthermore, it can also be formed using nanoimprint lithography or laser scribing. ru.

[0171] A gap X may be provided between the diffraction grating 1500 and the microlens array 2540. X can be 1 mm or less, preferably 100 μm or less. This spacing can also be empty space. Alternatively, a light-transmitting material may be provided as a sealing layer or adhesive layer. For example, nitrogen or Inert gases such as noble gases can be contained within that space. Alternatively, acrylic resin, Epoxy resin or polyimide resin may be provided at the intervals. Alternatively, silicone resin may be used. A liquid such as oil may be provided. Note that if the microlens array 2540 is not provided... Alternatively, a gap X may be provided between the color filter 2530 and the diffraction grating 1500.

[0172] Furthermore, the imaging device may be curved as shown in Figures 32(A1) and 32(B1). Figure 32(A1) shows the imaging device curved in the direction of the dashed line X1-X2 in the figure. This is shown. Figure 32(A2) shows the area indicated by the dashed line X1-X2 in Figure 32(A1). This is a cross-sectional view. Figure 32(A3) shows the area indicated by the dashed line Y1-Y2 in Figure 32(A1). This is a cross-section.

[0173] Figure 32(B1) shows the imaging device curved in the direction of the dashed line X3-X4 in the figure, and The diagram shows the curved state in the direction of the dashed line Y3-Y4. Figure 32(B2) is a diagram. This is a cross-sectional view of the area indicated by the dashed line X3-X4 in 32(B1). Figure 32(B3) is This is a cross-sectional view of the area indicated by the dashed line Y3-Y4 in Figure 32(B1).

[0174] By curving the imaging device, image field curvature and astigmatism can be reduced. This facilitates the optical design of lenses and other components used in combination with imaging devices. For example, Because the number of lenses required for aberration correction can be reduced, semiconductor devices using imaging devices can be miniaturized. It can be easily made lighter and more compact. Furthermore, it can improve the quality of captured images. Cut.

[0175] In this embodiment, one aspect of the present invention has been described. Or, other embodiments may be described. In this section, one aspect of the present invention will be described. However, this aspect of the present invention is not limited to these. It is not possible. In other words, various aspects of the invention are described in this embodiment and other embodiments. Therefore, one aspect of the present invention is not limited to a specific aspect. For example, one aspect of the present invention and An example of its application to an imaging device has been shown, but one aspect of the present invention is not limited thereto. In some cases, or depending on the circumstances, one aspect of the present invention may not be applied to an imaging device. This is also possible. For example, one aspect of the present invention may be applied to a semiconductor device having a different function. Example For example, in one aspect of the present invention, the channel formation region and source-drain region of a transistor Although examples of cases having oxide semiconductors have been shown, one aspect of the present invention is not limited thereto. In some cases, or depending on the circumstances, various transitions in one aspect of the present invention The channel formation region of a transistor, or the source-drain region of a transistor, etc. The present invention may have various semiconductors. Depending on the circumstances, the present invention may be used in some cases or situations. Various transistors, channel formation regions of transistors, or transistors in one embodiment The source and drain regions of a converter are, for example, made of silicon, germanium, or silicon gel. Manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphate, It may have at least one of the following: gallium nitride, or an organic semiconductor. Or, for example... For example, depending on the circumstances, or depending on the situation, various transitions in one aspect of the present invention The channel formation region of a transistor, or the source-drain region of a transistor. These do not necessarily have to contain an oxide semiconductor.

[0176] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0177] (Embodiment 2) In this embodiment, an imaging device different from that of Embodiment 1 will be described with reference to the drawings. Detailed explanations of parts common to the imaging device described in Embodiment 1 will be omitted.

[0178] One aspect of the present invention determines the electron saturation state in a charge detection unit provided within a pixel, and determines the determination This is a circuit configuration and operating method for an imaging device that can change its operating mode depending on the result. First, acquire the first imaging data, and if the charge detection unit is not saturated, check the capacity of the charge detection unit. The control is performed without changing the quantity value. Also, if the charge detection unit is saturated, the capacitance of the charge detection unit is controlled. The control is performed to increase the value. After these controls are performed individually for all pixels, the second The system acquires and reads out imaging data. The data was acquired without changing the capacitance value of the charge detection unit. The second set of imaging data corresponds to data for low light conditions. Furthermore, the capacitance value of the charge detection unit was increased. The second set of acquired imaging data corresponds to high-light-dependent data.

[0179] As a result of the above operation, even in low light conditions, noise is reduced and wide dynamic range is maintained. It is possible to acquire images of the range. Furthermore, even when imaging in environments including high light, the bright areas It is possible to maintain the tonal range and obtain images with a wide dynamic range.

[0180] Figure 33 is a circuit diagram of a pixel 20 in an imaging device according to one embodiment of the present invention. In some cases, an example is shown where the transistor is of the n-channel type, but one aspect of the present invention is this It is not limited to this, and some transistors may be replaced with p-channel transistors.

[0181] In pixel 20, one electrode of the photoelectric conversion element PD is the source of transistor 741 or It is electrically connected to one side of the drain. The source or drain of transistor 741 One end is electrically connected to either the source or drain of transistor 742. The source or drain of transistor 741, the other of which is the source or drain of transistor 743. Electrically connected to one side of the rain. The other side of the source or drain of transistor 741. It is electrically connected to either the source or drain of transistor 744. The source or drain of transistor 741 is electrically connected to the gate of transistor 745. The source or drain of transistor 741 is connected to one side of capacitive element C71. The electrodes are electrically connected. The source or drain of transistor 744 is connected to the other side. It is electrically connected to one electrode of the element C72. The source or destination of transistor 745. One side of the rain is electrically connected to either the source or drain of transistor 746. The gate of transistor 744 is connected to either the source or the drain of transistor 747. These are electrically connected. The gate of transistor 744 is connected to one electrode of the capacitive element C73. It is electrically connected.

[0182] Here, one electrode of the photoelectric conversion element PD, the source or drain of the transistor 741 Node AN to which one of the sources or drains of transistor 742 is connected This will serve as a charge storage unit. Also, the other side of the source or drain of transistor 741, Either the source or drain of transistor 743, and either the source or drain of transistor 744. On the other hand, the gate of transistor 745 and one electrode of capacitive element C71 are connected. The FD is used as the charge detection unit. Also, the gate of transistor 744, transistor 747 Node C is connected to either the source or drain of the capacitor and one electrode of the capacitive element C73. N is the signal holding unit.

[0183] The other electrode of the photoelectric conversion element PD is electrically connected to wiring 771 (VPD). The other side of the source or drain of transistor 742 and the source or drain of transistor 743 The other end of Rain is electrically connected to wiring 772 (VRS). The other end of capacitive element C1 is electrically connected to wiring 772 (VRS). The electrodes, the other electrode of capacitive element C72 and the other electrode of capacitive element C73 are connected to wiring 773(V It is electrically connected to SS). The source or drain of transistor 745 is connected to the other. Electrically connected to line 774 (VPI). Source or drain of transistor 746. The other end is electrically connected to wiring 791 (OUT1).

[0184] In addition, in the connection configuration of each of the above elements, multiple transistors or multiple capacitive elements are electrically connected. This example shows how to share connected wiring, but each is electrically connected to different wiring. That's good too.

[0185] Wiring 771 (VPD), Wiring 772 (VRS), Wiring 773 (VSS), and Wiring 77 4(VPI) can function as a power line. For example, wiring 771(VP D) and wiring 773 (VSS) can function as low-voltage power lines. Wiring 772 (VRS) and 774 (VPI) can be used as high-voltage power lines. can.

[0186] The gate of transistor 741 is electrically connected to wiring 761 (TX). The gate of transistor 742 is electrically connected to wiring 762 (GWRS). Transistor 74 The gate of transistor 3 is electrically connected to wiring 763 (RS). It is electrically connected to wiring 764(SE). The gate of transistor 747 is connected to wiring 7 It is electrically connected to 65(SE2). In addition to the source or drain of transistor 747. This is electrically connected to wiring 793 (OUT3).

[0187] Wiring 761 (TX), Wiring 762 (GWRS), Wiring 763 (RS), Wiring 764 (SE) ) and wiring 765(SE2) control the conduction of the transistors to which they are connected. It can function as a signal line. Note: Wiring 763 (RS), Wiring 764 (SE) And wiring 765 (SE2) can be controlled row by row.

[0188] Transistor 741 is a transistor for transferring the potential of node AN to node FD. This allows it to function. Transistor 742 resets the potential of node AN. It can function as a transistor for that purpose. Transistor 743 is node FD It can function as a transistor to reset the potential. 744 is a transistor for controlling the electrical connection between node FD and capacitive element C72. It can function as such. Transistor 745 outputs according to the potential of node FD. It can function as a transistor for performing this task. Transistor 746 is used for pixels. It can function as a transistor for selecting 20. Transistor 747 This can be used as a transistor to maintain the potential of node CN.

[0189] Note that the above-described configuration of pixel 20 is just one example, and some circuits, some transistors, and some Capacitive elements or some wiring may not be included. Or, they may not be included in the above-mentioned configuration. It may also include circuits, transistors, capacitive elements, wiring, etc. The connection configuration may differ from the one described above.

[0190] Figure 34(A) is a diagram illustrating an imaging device according to one embodiment of the present invention. This imaging device is a matrix A pixel array 21 having pixels 20 arranged in a rix pattern, and a function to drive the pixels 20. Circuit 22 (low driver) and CDS (Correll) are used to process the output signal of pixel 20. Circuit 23 (CDS circuit) for performing the TED Double Sampling operation and A function to determine whether or not node FD is saturated, and to control the operation mode of the pixels according to the determination result. A device that controls functions and converts analog data output from circuit 23 into digital data. A circuit 24 (such as an A / D conversion circuit) that has the ability to select and read the data converted by circuit 24. It has a circuit 25 (column driver) that has a function to remove the column. Note that circuit 23 is not provided. It can also be configured in a different way.

[0191] Figure 34(B) shows the schematic of circuit 23 connected to one row of the pixel array 21 and circuit 24 This is a block diagram. Circuit 23 consists of transistor 751, transistor 752, and transistor The configuration can include a st 753, a capacitive element C74, and a capacitive element C75. Furthermore, circuit 24 includes a comparator circuit 27, a determination output circuit 28, and a counter circuit 29. This configuration can be implemented.

[0192] Transistor 754 functions as a current source circuit. Alternatively, wiring 791 (OUT1) is electrically connected to one side of the drain, and the source or drain A power line is connected to the other end of the wire. This power line can be, for example, a low-voltage power line. Furthermore, a bias voltage is always applied to the gate of transistor 754. ru.

[0193] In circuit 23, either the source or drain of transistor 751 is connected to transistor 7 It is electrically connected to either the source or drain of transistor 52. Alternatively, one of the drains is electrically connected to one electrode of the capacitive element C74. Transis The source or drain of transistor 752 is the other of the source or drain of transistor 753. One side is electrically connected to the other, either the source or the drain of transistor 752. Electrically connected to one electrode of sub-C75. Source or slave of transistor 752. The other end of the transistor is electrically connected to wiring 792 (OUT2). The other electrode of the drain or spool and the other electrode of the capacitive element C74 are connected to wiring 791 (OUT1). It is electrically connected to the source or drain of transistor 751, for example, the base It is electrically connected to the high-potential power line (CDSVDD) to which the near-potential is supplied. Capacitive element C7 The other electrode of 5 is electrically connected to, for example, a low-voltage power line (CDSVSS).

[0194] An example of the operation of circuit 23 when connected to pixel 20 shown in Figure 33 will be explained. First, the tra Connect transistor 751 and transistor 752. Next, connect the wiring 791 from pixel 20. The potential of the imaging data is output to (OUT1), and the reference potential (CDS) is output to wiring 792 (OUT2). Hold VDD). Then, wire 79 from pixel 20 as non-conductive, leaving transistor 751 non-conductive. Set the reset potential to 1 (OUT1) (here, a potential higher than the potential of the imaging data, e.g., VD The output is set to the D potential. At this time, wiring 792 (OUT2) is the potential of the imaging data and The absolute value of the difference in reset potentials is added to the reference potential (CDSVDD) to obtain the resulting potential. This is a low-noise method where the net imaging data potential is added to the reference potential (CDSVDD). A potential signal can be supplied to circuit 24.

[0195] Note that the reset potential is lower than the potential of the imaging data (for example, the GND potential). In this case, wiring 792 (OUT2) is based on the absolute value of the difference between the potential of the imaging data and the reset potential. This is the potential obtained by subtracting it from the potential (CDSVDD).

[0196] Also, if transistor 753 is made conductive, a bypass is formed, so wiring 791( The signal from OUT1 can be directly output to wiring 792 (OUT2).

[0197] In circuit 24, the comparator circuit 27 compares the signal potential input from circuit 23 with the base The refractory potential (REF) is compared. Wiring 792 (OUT2) is connected to comparator circuit 27. A signal potential corresponding to the first or second imaging data is input via this. Here, the first imaging data is the first exposure data, and the saturation of node FD at pixel 20 is present. This is data used to determine if there is nothing present. The second imaging data is acquired according to this determination. This is the data from the second exposure.

[0198] First, when the first imaging data is input, the comparator circuit 27 sends a determination output to the determination output circuit 28. The result is output. The judgment output circuit 28 adjusts the timing of the output to control the comparator circuit 2 It has a function to remove noise output from 7.

[0199] In the comparator circuit 27, the first imaging data saturates the node FD of pixel 20. A determination is made as to whether or not this is true. At this time, the reference potential (REF) input to the comparator circuit 27 This is a constant potential corresponding to the saturation of node FD, and this potential corresponds to the first imaging data. The presence or absence of saturation is determined by comparing it with the signal potential. The signal potential corresponding to the first imaging data bypasses circuit 23 and passes through comparator circuit 2 The configuration is to input to 7, but without bypassing circuit 23, input to comparator circuit 27. That's fine.

[0200] If it is determined that node FD is not saturated, the determination output circuit 28 outputs the capacitance value of node FD. A signal that does not change is output to the pixel. Specifically, a signal that does not conduct to transistor 744 The voltage is output to wiring 793 (OUT3), and the corresponding potential is held at node CN of pixel 20. In this case, the capacity value of the node FD does not change.

[0201] If node FD is determined to be saturated, the determination output circuit 28 outputs the capacitance value of node FD. The signal to be increased is output to the pixel. Specifically, the potential through which transistor 744 conducts is The output is sent to wiring 793 (OUT3), and the corresponding potential is held at node CN of pixel 20. As capacitive element C72 is electrically connected to node FD, the capacitance value of node FD increases. do.

[0202] After performing the above operation for all valid pixels, reset the node FD and proceed to the second imaging. The data is acquired. The signal potential corresponding to the second imaging data is compared via circuit 23. This is input to circuit 27. At this time, the reference potential (RE) input to comparator circuit 27 is input. F) is a ramp wave, and the result is countered by comparing it with the signal potential corresponding to the second imaging data. - Output to circuit 29. Then, the counter circuit 29 outputs to wiring 794 (OUT4). It outputs digital data corresponding to the image data.

[0203] For the determination output circuit 28, for example, the circuit shown in Figure 35 can be used. The input of this circuit The output terminal of the comparator circuit 27 is electrically connected to terminal (IN). Wiring 793 (OUT3) is electrically connected to the output terminal (OUT) of the circuit. After path 28 is reset by the JRES signal for each selected row, comparator circuit 2 The result of the judgment in step 7 is output to wiring 793 (OUT3). A control signal is input to terminal GCN. Furthermore, it is possible to fix the signal output to wiring 793 (OUT3).

[0204] The circuit shown in Figure 35 can be operated according to the timing chart shown in Figure 36. RCK1 / 2 and RCKB1 / 2 shown in Figure 36 are input to circuit 22 (low driver). The clock signal and the inverted clock signal, JRES and JENB, are entered into the circuit shown in Figure 35. The signal being powered, EN_CDS, is the signal input to the gate of transistor 753 in circuit 23. SE[1] is the signal input to wiring 764 of pixel 20 in the first row, and SE[N] is the signal input to wiring 764 of the last row. The signal SE2[1] input to wiring 764 of pixel 20 is connected to wiring 765 of pixel 20 in the first row. The signal input to SE2[N] is the signal input to wiring 765 of pixel 20 in the last row. ru.

[0205] The period indicated by frame[n] corresponds to the duration of the nth frame (where n is a natural number greater than or equal to 2). In the nth frame, period 401 is the period for reading the data from the (n-1)th frame, and period 4 02 is the period during which the first imaging data mentioned above is read out and a determination is made, and period 400 is low This is a period during which the driver is not functioning. Also, period 403 in the (n+1)th frame is the nth frame This is the period for retrieving the data from the frame.

[0206] Next, using the flowchart shown in Figure 37 and the timing chart shown in Figure 38, The operation of the pixel 20 shown in 33 will be described. An imaging apparatus in one aspect of the present invention is global It operates in a shutter mode, and the operation within one frame is the acquisition of the first imaging data, the first imaging data It can be broadly divided into the determination, acquisition of the second imaging data, and reading the imaging data from the previous frame. Oh, the acquisition of the first image data and the reading of the image data from the previous frame are performed in parallel. ru.

[0207] Figures 37 and 38 are explained using an arbitrary nth frame as the reference. Also, wiring 771 (VPD) and wiring 773 (VSS) are low potential ("L"), wiring 772 (VRS) and Wiring 774 (VPI) is set to high potential ("H").

[0208] Also, in Figure 38, GWRS is the potential of wiring 762 (GWRS), and RS[1] is the first row. The potential of wiring 763(RS) in a specific pixel 20, RS[N] is the specific pixel in the last row. The potential of wiring 763(RS) in 20, CN[1] is at a specific pixel 20 in the first row. The potential of node CN, CN[N] is the potential of node CN at a specific pixel 20 in the last row, T X is the potential of wiring 761(TX), and AN[1] is node A at a specific pixel 20 in the first row. The potential of N, AN[N] is the potential of node AN at a specific pixel 20 in the last row, FD[1] is the potential of node FD at a specific pixel 20 in the first row, and FD[N] is a specific pixel in the last row. This is the potential of node FD at point 20.

[0209] First, regarding the acquisition of the first imaging data and the reading of the imaging data acquired in the previous frame... I will explain.

[0210] The first imaging data is data used to distinguish the illuminance (low or high illumination) of the object being imaged. In the first imaging mode for the imaging data, only the capacitive element C71 is connected to node FD. Because imaging is performed at low capacitance values, the node FD saturates in high-illumination environments. Therefore, By determining whether or not the node FD is saturated, the illuminance of the object being imaged can be identified. In the timing chart of Figure 38, the first row of the first imaging data is node F. This shows the behavior when D is not saturated, and the Nth line (last line) shows when node FD is saturated. This shows the action to take when the person is present.

[0211] At time T1, if GWRS is "H", then AN[1:N] is reset to "H". (The potential of wiring 772 (VRS) is (S1).

[0212] At time T2, if GWRS is "L", then AN[1:N] begins to decrease in accordance with the illuminance. Meru (first exposure, S2).

[0213] At time T3, if RS[1:N] is "H" and CN[1:N] is "H", then FD[ [1:N] is reset to "H" (potential of wiring 772 (VRS)) (S3). At that time, the capacitive element C72 is electrically connected to node FD via transistor 744. To set CN[1:N] to "H", wire 765(SE2)[1:N] must be set to "H". Transistor 747 is activated as "H", and the input signal of terminal GCN of the determination output circuit 28 is set to "H "That's all you need to do."

[0214] At time T4, if SE2[1:N] is "H" and CN[1:N] is "L", then the traction control is Since transistor 744 becomes non-conductive, the electrical connection between node FD and capacitive element C72 is broken. It is rejected. Note that in order to set CN[1:N] to "L", the judgment output circuit 28 must be reset. And terminal GCN should be set to "L". Note that SE2[1:N] should be set to "L" after time T4. If transistor 747 is made non-conductive, then CN[1:N] is due to the capacitive element C73, etc. It is retained.

[0215] Also, at time T4, if RS[1:N] is "L" and TX is "H", then, The potential of node AN is transferred to node FD, and the potential of node FD begins to decrease (S4).

[0216] At time T5, if TX is set to "L", then FD[1:N] is retained. This is the end of the first part. This is the operation for acquiring image data (1).

[0217] Here, between time T1 and T3, SE[1] to SE[N] sequentially have a certain period of "H" Then, the imaging data confirmed in the (n-1)th frame is read out (S10'). In other words, The acquisition operation of the first imaging data in the nth frame and the imaging data confirmed in the (n-1)th frame. Data readout is performed in parallel. By reading out the imaging data in the next frame in this way... In a global shutter system, it is possible to increase the time allocated to exposure and other processes. Therefore, it is possible to acquire images with a wide dynamic range and low noise even under low light conditions. It is possible.

[0218] Figure 39(A) is a timing chart explaining the readout of the first row of imaging data. H is the potential supplied to the gate of transistor 752 in circuit 23, and CL is the potential supplied to circuit 23. The potential supplied to the gate of transistor 751, REF (RAMP), is a composite The reference potential supplied to circuit 27, OUT2 is the potential of wiring 792 (OUT2), COMP _OUT is the potential at the output terminal of comparator circuit 27.

[0219] In Figure 38, RS[1] to RS[N] sequentially become "H" for a certain period of time before time T3. The node FD is reset, which is due to the operation of circuit 23 shown in Figure 39(A). It is an action.

[0220] Next, we will explain the determination of the first imaging data and the actions taken based on the determination result.

[0221] Between times T6 and T8, SE[1] through SE[N] sequentially become "H" for a certain period of time, Each time, the first image data is read out, and the saturation of node FD is calculated for all 20 valid pixels. The presence or absence of the item is determined (S5).

[0222] Figure 39(B) illustrates the timing of the readout of the first imaging data at times T6 to T8. This is a queuing chart. During the readout period of the first imaging data, set EN_CDS to "H" and CL Let this be "H", and the signal output from pixel 20 bypasses circuit 23 and goes through the comparator circuit Input to path 27. Assume the potential of REF(CONST) is constant and node FD is saturated. Sometimes, the value should be slightly greater than the potential output to wiring 791 (OUT1). By operating it in this way, the output of the comparator circuit 27 determines whether or not node FD is saturated. This can be determined. Note that in Figure 39(B), the node FD of the selected specific pixel 20 is shown. This indicates the state when the system is saturated, and the output terminal of the comparator circuit 27 shows "L". The output is as follows. Note that if EN_CDS is set to "L" and circuit 23 is not bypassed, the first image is taken Image data may be read out. At this time, the output terminal of the comparator circuit 27 will show "H". The following will be output.

[0223] At this time, the first imaging data is used to determine whether or not node FD is saturated, and It is not output to the section. Therefore, circuits such as the 25 (column driver) required for external output are not available. The operation of the output circuit may be stopped.

[0224] The determination result of the first imaging data is read via the determination output circuit 28. The output is displayed in pixel 20. Here, the result of the determination is entered into node CN of pixel 20. Therefore, the wiring 765(SE2) on the same line is changed in accordance with the timing of outputting the judgment result. Let the fixed period be "H".

[0225] In pixel 20, where node FD is determined not to be saturated, "L" is input to node CN. Therefore, transistor 744 does not conduct. Consequently, the capacitive element C71 is connected to node FD. The only thing that is electrically connected is that the capacitance value of node FD does not change. Pixel 20 is set to an imaging mode suitable for imaging in low light conditions.

[0226] In pixel 20, where node FD is determined to be saturated, "H" is input to node CN. Therefore, transistor 744 conducts. Consequently, the capacitive element C71 and The capacitive element C72 is electrically connected, and the capacitance value of node FD increases (S6 ). In other words, the pixel 20 is set to an imaging mode suitable for imaging at high illumination. This completes the determination of the first imaging data and the actions taken based on the determination result.

[0227] Next, we will explain how to acquire the second set of imaging data.

[0228] The exposure operation to acquire the second set of imaging data may be performed before all the judgment results are available. For example, as shown in Figure 38, if GWRS is set to "H" at time T7, then AN[1:N] Reset (S7). Then, set GWRS to "L" at time T8, and continue until time T10. A second exposure is performed (S8). The duration of the second exposure is the same as the duration of the first exposure. That's fine. Alternatively, you can make it shorter than the first exposure time.

[0229] If RS[1:N] is "H" at time T9 before the second exposure is finished, then FD[1:N The voltage is reset to "H" (potential of wiring 772 (VRS)) (S9).

[0230] At time T10, if wiring 761(TX) is set to "H", then the potential of node AN is Transferred to floppy disk (S10).

[0231] At time T11, if wiring 761(TX) is set to "L", then FD[1:N] is held. This completes the acquisition of the second imaging data. Furthermore, this second imaging data is the second In the n+1th frame, the image data for the nth frame is read out (S11).

[0232] Through the above operation, the imaging mode for the second image data can be set for every 20 pixels. Even when imaging a field of view with a mix of light and dark areas, the tonal range is maintained, resulting in images with a wide dynamic range. You can obtain it.

[0233] Pixel 20 may have the configuration shown in Figure 40. The pixel 20 shown in Figure 40 is a photoelectric conversion element. The orientation in which the PD is connected is different from that of pixel 20 shown in Figure 33. Pixel 20 shown in Figure 40 is different from that shown in Figure 4. It can be operated according to the timing chart of 2. At this time, wiring 771 (VP D) and wiring 774 (VPI) are high potential ("H"), wiring 772 (VRS), wiring 77 3(VSS) is set to low potential ("L").

[0234] In this case, nodes AN and FD become saturated with electrons upon reset, resulting in high illuminance. Nodes AN and FD will be in an electron-deficient state. Therefore, see Figure 33 above. The potentials of nodes AN and FD are changed in the opposite direction to the description of the operation of pixel 20 shown. To transform.

[0235] Furthermore, pixel 20 may have the configuration shown in Figures 41(A) and (B). Figure 41(A) shows a tra This configuration does not include the inverter 742. In this configuration, the potential of the wiring 771 (VPD) is increased. By setting the potential, the potential of node AN can be reset. Figure 41(B) shows Configuration in which either the source or drain of the transistor 745 is connected to wiring 791(OUT). That is the case.

[0236] Furthermore, the transistor used in pixel 20 is as shown in Figures 43(A) and (B), A configuration in which a back gate is provided on transistor 741 or transistor 747 is also possible. (Figure 43) (A) is a configuration in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. In Figure 43(A), as an example, the back gate supplies a low potential to wiring 771 (VP D) An example of connecting to wiring 773 (VSS) or wiring 775 (VSS2) is shown. Alternatively, it may be configured to connect to just one of the wires. Also, Figure 43(B) shows the front gate The configuration applies the same potential to the back gate as to the on-current, increasing the on-current and off-current. The current can be reduced. Also, the desired transistor will have appropriate electrical characteristics. Alternatively, a configuration combining the structures shown in Figures 43(A) and 43(B) may be used. Oh, it's also acceptable to have transistors that don't have a back gate. Also, see Figures 40 and 41. The configurations of A), (B), and 43(A), (B) can be combined as needed. Cut.

[0237] Pixel 20 is composed of multiple transistors 743 to 747, as shown in Figure 44. It can also be a form that is shared in its basic form. In Figure 44, transistor 743 is used for multiple pixels in the vertical direction. The example illustrates a configuration that shares transistor 747, but in the horizontal or horizontal-vertical direction It may be shared by multiple pixels. With this configuration, the amount of each pixel has This can reduce the number of transistors required.

[0238] Furthermore, Figure 44 shows a configuration in which transistors 743 to 747 are shared by four pixels. Although this is illustrated, there may also be forms that are shared by 2 pixels, 3 pixels, or 5 or more pixels. The configurations in Figure 40, Figure 41(A), (B), and Figure 43(A), (B) are as follows: It can be combined in any way you like.

[0239] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0240] (Embodiment 3) In this embodiment, a transient having an oxide semiconductor that can be used in one aspect of the present invention The sta will be explained using drawings. Note that in the drawings of this embodiment, for clarity, Some elements are enlarged, reduced, or omitted in the illustration for illustrative purposes.

[0241] Figures 45(A) and (B) show a top view and a cross-sectional view of a transistor 101 according to one embodiment of the present invention. Yes. Figure 45(A) is a top view, and the cross section is in the direction of the dashed line B1-B2 shown in Figure 45(A). This corresponds to Figure 45(B). Also, the cross section in the direction of the dashed line B3-B4 shown in Figure 45(A) is This corresponds to Figure 47(A). Also, the direction of the dashed line B1-B2 is the channel length direction, and the dashed line B The 3-B4 direction is referred to as the channel width direction.

[0242] The transistor 101 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 150, oxide semiconductor layer 130, conductive layer 140, and insulating layer 1 in contact with conductive layer 150 60, conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175 , and also, if necessary, the insulating layer 180 may be given the function of a planarizing film. .

[0243] Here, the conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0244] Furthermore, region 231 shown in Figure 45(B) is the source region, region 232 is the drain region, and region 2 Region 33 can function as a channel-forming region. Regions 231 and 232 are guided The conductive layer 140 and the conductive layer 150 are in contact with each other, and the conductive layer 140 and the conductive layer 150 By using a conductive material that readily bonds with oxygen, the resistance of regions 231 and 232 can be reduced. It is possible.

[0245] Specifically, the oxide semiconductor layer 130 and the conductive layer 140 and conductive layer 150 come into contact with each other. Oxygen vacancies occur within the oxide semiconductor layer 130, and these oxygen vacancies remain within the oxide semiconductor layer 130. Due to interactions with hydrogen that is either distilled or diffused from the outside, regions 231 and 232 have low resistance. It becomes an n-type resistance.

[0246] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner. Also, "electrode layer" can be replaced with "wiring." can.

[0247] Furthermore, the diagram illustrates an example in which the conductive layer 170 is formed of two layers, conductive layer 171 and conductive layer 172. However, it may be a single layer or a stack of three or more layers. This configuration will be explained in this embodiment. This can also be applied to other transistors.

[0248] Furthermore, although the diagram shows examples where the conductive layer 140 and conductive layer 150 are formed as a single layer, two or more layers are also shown. The above stacking may also be used. This configuration is also applicable to other transistors described in this embodiment. can.

[0249] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 45(C) and (D). Figure 45(C) is a top view of transistor 102, and the dashed line C shown in Figure 45(C) The cross-section in the direction of 1-C2 corresponds to Figure 45(D). Also, the dashed line C3 shown in Figure 45(C) -The cross-section in the C4 direction corresponds to Figure 47(B). Also, the dashed line C1-C2 direction is channeled The direction of the channel length and the direction of the dashed line C3-C4 are referred to as the channel width direction.

[0250] The transistor 102 has an insulating layer 160 that acts as a gate insulating film and a gate electrode layer. Except for the fact that it does not coincide with the edge of the conductive layer 170 which acts as a transistor, it is the same as transistor 101. It has the following configuration. The structure of transistor 102 is such that conductive layer 140 and conductive layer 150 are insulated Because it is broadly covered by the edge layer 160, the conductive layer 140 and conductive layer 150 and conductive layer 170 It has the characteristic of high resistance between the terminals and low gate leakage current.

[0251] Transistors 101 and 102 have conductive layers 170 and 140 and This is a top gate structure having a region where the electrochemical layer 150 overlaps. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacity. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high It is easy to form transistors.

[0252] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 45(E) and (F). Figure 45(E) is a top view of transistor 103, and the dashed line D shown in Figure 45(E) The cross-section in the 1-D2 direction corresponds to Figure 45(F). Also, the dashed line D3 shown in Figure 45(E) -The cross-section in the D4 direction corresponds to Figure 47(A). Also, the dashed line D1-D2 direction is channeled The direction of the channel length and the direction of the dashed line D3-D4 are referred to as the channel width direction.

[0253] Transistor 103 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A material semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, and an insulating layer 160 in contact with The conductive layer 170, the oxide semiconductor layer 130, the insulating layer 160, and the insulating layer covering the conductive layer 170 are all connected. Edge layer 175, insulating layer 180 in contact with insulating layer 175, insulating layer 175 and insulating layer 180 A conductive layer 140 is electrically connected to the oxide semiconductor layer 130 through an opening provided therein. It also has a conductive layer 150. Furthermore, an insulating layer 180, a conductive layer 140, and a conductive layer may be added as needed. It may have an insulating layer (planarized film) in contact with 150.

[0254] Here, the conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0255] Furthermore, region 231 shown in Figure 45(F) is the source region, region 232 is the drain region, and region 2 Region 33 can function as a channel-forming region. Regions 231 and 232 are absolute It is in contact with the edge layer 175, and if, for example, an insulating material containing hydrogen is used as the insulating layer 175, the region Regions 231 and 232 can be made to have lower resistance.

[0256] Specifically, the process up to forming the insulating layer 175 generates in regions 231 and 232 The interaction between the oxygen deficiency and the hydrogen diffusing from the insulating layer 175 to regions 231 and 232 As a result of this action, regions 231 and 232 become low-resistance n-type. Note that this is an insulating material containing hydrogen. Materials such as silicon nitride and aluminum nitride can be used.

[0257] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 46(A) and (B). i. Figure 46(A) is a top view of transistor 104, and the dashed line E shown in Figure 46(A) The cross-section in the direction of 1-E2 corresponds to Figure 46(B). Also, the dashed line E3 shown in Figure 46(A) -The cross-section in the E4 direction corresponds to Figure 47(A). Also, the dashed line E1-E2 direction is channeled The direction of the channel length and the direction of the dashed line E3-E4 are referred to as the channel width direction.

[0258] Transistor 104 has conductive layers 140 and 150 at the edges of oxide semiconductor layer 130. Except for the fact that it is in contact with the other element in a way that covers it, it has the same configuration as transistor 103.

[0259] Furthermore, regions 331 and 334 shown in Figure 46(B) are the source region, region 332 and Region 335 can function as a drain region, and region 333 can function as a channel-forming region. .

[0260] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. Similar to method 2, the resistance can be reduced.

[0261] Furthermore, regions 334 and 335 are regions 231 and region 335 in transistor 103. Similar to region 232, resistance can be reduced. Note that region 334 in the channel length direction And when the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate The on-current does not decrease significantly due to the contribution of the electric field. Therefore, regions 334 and 33 In some cases, the resistance reduction of component 5 is not performed.

[0262] Transistors 103 and 104 have conductive layers 170 and 140 and It is a self-aligned structure in which the electrolytic layer 150 does not have any overlapping regions. The lampistor has extremely low parasitic capacitance between the gate electrode layer and the source and drain electrode layers. Therefore, it is suitable for high-speed operation applications.

[0263] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 46(C) and (D). Figure 46(C) is a top view of transistor 105, and the dashed line F shown in Figure 46(C) The cross-section in the 1-F2 direction corresponds to Figure 46(D). Also, the dashed line F3 shown in Figure 46(C) -The cross-section in the F4 direction corresponds to Figure 47(A). Also, the dashed line F1-F2 direction is channeled The direction of the channel length and the direction of the dashed line F3-F4 are referred to as the channel width direction.

[0264] Transistor 105 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, oxide semiconductor layer 130, conductive layer 141, insulating layer 160 in contact with conductive layer 151 And, a conductive layer 170 in contact with the insulating layer 160, an oxide semiconductor layer 130, a conductive layer 141, and a conductive layer. An insulating layer 175 that is in contact with layer 151, insulating layer 160 and conductive layer 170, and an insulating layer 175 that is in contact with The insulating layer 180 and the insulating layer 175 and the insulating layer 180 are conductive through openings provided in them. Conductive layers 142 and 15 are electrically connected to layer 141 and conductive layer 151, respectively. It has 2. It also comes into contact with the insulating layer 180, the conductive layer 142 and the conductive layer 152 as needed. It may have an insulating layer or the like.

[0265] Here, conductive layers 141 and 151 are in contact with the upper surface of the oxide semiconductor layer 130, and the sides The configuration is designed so that it does not come into contact with anything.

[0266] The transistor 105 has conductive layers 141 and 151, and insulating layers 175 and The insulating layer 180 has an opening, and the conductive layer 14 is accessible through the opening. It has conductive layers 142 and 152 that are electrically connected to conductive layer 151 and conductive layer 151, respectively. It has the same configuration as transistor 101, except for the following point. Conductive layer 140 (conductive layer 141 The conductive layer 142) can be used as a source electrode layer, and the conductive layer 150 (conductive Layer 151 and conductive layer 152 can be used as drain electrode layers.

[0267] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 46(E) and (F). Figure 46(E) is a top view of transistor 106, and the dashed line G shown in Figure 46(E) The cross-section in the 1-G2 direction corresponds to Figure 46(F). Also, the dashed line G3 shown in Figure 46(A) -The cross-section in the G4 direction corresponds to Figure 47(A). Also, the dashed line G1-G2 direction is channeled. The direction of the channel length and the direction of the dashed line G3-G4 are referred to as the channel width direction.

[0268] Transistor 106 has an insulating layer 120 that is in contact with the substrate 115 and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer in contact with the insulating layer 160. Layer 170, insulating layer 120, oxide semiconductor layer 130, conductive layer 141, conductive layer 151, insulating An insulating layer 175 in contact with layer 160, conductive layer 170, and an insulating layer 180 in contact with insulating layer 175. Through openings provided in the insulating layer 175 and the insulating layer 180, the conductive layer 141 and the conductive It has conductive layers 142 and 152 that are electrically connected to layer 151, respectively. If necessary, an insulating layer (planarized film) in contact with the insulating layer 180, conductive layer 142, and conductive layer 152. They may also have, etc.

[0269] Here, conductive layers 141 and 151 are in contact with the upper surface of the oxide semiconductor layer 130, and the sides The configuration is designed so that it does not come into contact with anything.

[0270] Transistor 106 has conductive layers 141 and 151, except that the transistor It has the same configuration as Ta 103. The conductive layer 140 (conductive layer 141 and conductive layer 142) is - It can be used as an electrode layer, conductive layer 150 (conductive layer 151 and conductive layer 15 2) can be used as a drain electrode layer.

[0271] In the configuration of transistors 105 and 106, conductive layer 140 and conductive layer 1 Since 50 is not in contact with the insulating layer 120, oxygen in the insulating layer 120 enters the conductive layer 140. Furthermore, it becomes less likely for the conductive layer 150 to absorb acid, and acid from the insulating layer 120 into the oxide semiconductor layer 130 This makes it easier to supply raw materials.

[0272] Regions 231 and 232 in transistor 103, transistor 104 and Regions 334 and 335 in the lampistor 106 form oxygen vacancies and improve conductivity. Impurities may be added to enhance the properties. These impurities may form oxygen vacancies in the oxide semiconductor layer. For example, phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helical Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more elements selected from zinc and carbon may be used. Methods of adding include plasma treatment, ion implantation, ion doping, and plasma treatment. Methods such as Merjohn ion implantation can be used.

[0273] When the above elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bonds between elements and oxygen are broken, and an oxygen vacancy is formed. Due to the interaction between elementary defects and hydrogen remaining in or later added in the oxide semiconductor layer, The conductivity of the semiconductor layer can be increased.

[0274] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of impurity elements, oxygen vacancies are formed. Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor It can be formed. Here, an oxide semiconductor that has been made conductive is called an oxide conductor. Furthermore, oxide conductors, like oxide semiconductors, are translucent.

[0275] Oxide conductors are degenerate semiconductors in which the conduction band edge and the Fermi level coincide or nearly coincide. It is presumed that there is an oxide conductor layer, a source electrode layer and a drain electrode layer. The contact with the conductive layer that functions is ohmic contact, and the oxide conductive layer and the source electrode layer This reduces the contact resistance with the conductive layer that functions as the drain electrode layer.

[0276] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 48(A), (B), (C), (D), (E) ), (F) shown are cross-sectional views in the channel length direction, and the channels shown in Figures 47(C) and (D) As shown in the cross-sectional view in the width direction, a conductive layer 173 is placed between the oxide semiconductor layer 130 and the substrate 115. It may be provided. The conductive layer may be used as a second gate electrode layer (back gate). This allows for increasing the on-current and controlling the threshold voltage. (See Figure 48(A)) In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is acid The width of the conductive layer 173 may be shorter than that of the conductive layer 170. It can be made shorter than the width.

[0277] To increase the ON current, for example, the conductive layer 170 and conductive layer 173 are set to the same potential, double It can be driven as a gate transistor. Also, to control the threshold voltage, A constant potential different from that of the conductive layer 170 should be supplied to the conductive layer 173. To make 73 at the same potential, for example, as shown in Figure 47(D), conductive layer 170 and conductive layer 1 73 can be electrically connected via the contact hole.

[0278] Furthermore, in transistors 101 to 106 in Figures 45 and 46, acid Although an example where the oxide semiconductor layer 130 is a single layer is shown, the oxide semiconductor layer 130 is stacked. This is also acceptable. The oxide semiconductor layer 130 of transistors 101 to 106 is shown in Figure 49. (B), (C) or Figure 49(D), (E) can be replaced with the oxide semiconductor layer 130 shown. It is possible.

[0279] Figure 49(A) is a top view of the oxide semiconductor layer 130, and Figures 49(B) and (C) show the two-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130, which is constructed in three layers. Figures 49(D) and (E) show the three-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130.

[0280] In oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c, Oxide semiconductor layers with different compositions can be used.

[0281] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 50(A) and (B). Figure 50(A) is a top view of transistor 107, and the dashed line H shown in Figure 50(A) The cross-section in the 1-H2 direction corresponds to Figure 50(B). Also, the dashed line H3 shown in Figure 50(A) -The cross-section in the H4 direction corresponds to Figure 52(A). Also, the dashed line H1-H2 direction is channeled. The direction in the longitudinal direction, and the direction of the dashed line H3-H4, are referred to as the channel width direction.

[0282] Transistor 107 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layer 140 and conductive layer 150, and the laminate, conductive layer 140 and conductive layer 15 The oxide semiconductor layer 130c in contact with 0, and the insulating layer 160 in contact with the oxide semiconductor layer 130c , conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and an insulating layer 175 in contact with It has an insulating layer 180 and, if necessary, a planarizing film as a functional You may add the ability.

[0283] In transistor 107, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The point is that it is a semiconductor layer 130c), and conductive layer 140 and conductive layer 150 and insulating layer 160 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between them, It has the same configuration as the Ranjista 101.

[0284] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 50(C) and (D). Figure 50(C) is a top view of transistor 108, and the dashed line I shown in Figure 50(C) The cross-section in the direction of 1-I2 corresponds to Figure 50(D). Also, the dashed line I3 shown in Figure 50(C) -The cross-section in the I4 direction corresponds to Figure 52(B). Also, the dashed line I1-I2 direction is channel The direction in the longitudinal direction, and the direction of the dashed line I3-I4, are referred to as the channel width direction.

[0285] The transistor 108 has an insulating layer 160 and an oxide semiconductor layer 130c, with the edges connected to the conductive layer 17. It differs from transistor 107 in that its terminals do not coincide with the zero point.

[0286] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 50(E) and (F). Figure 50(E) is a top view of transistor 109, and the dashed line J shown in Figure 50(E) is the same as the line J The cross-section in the direction of 1-J2 corresponds to Figure 50(F). Also, the dashed line J3 shown in Figure 50(E) -The cross-section in the J4 direction corresponds to Figure 52(A). Also, the dashed line J1-J2 direction is channel The direction in the longitudinal direction, and the direction of the dashed line J3-J4, are referred to as the channel width direction.

[0287] The transistor 109 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and an acid in contact with the stack. A oxide semiconductor layer 130c, an insulating layer 160 in contact with the oxide semiconductor layer 130c, and an insulating layer 16 A conductive layer 170 in contact with 0, the laminate, oxide semiconductor layer 130c, insulating layer 160 and conductive An insulating layer 175 covering the electrical layer 170, an insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and conductive layer 14 which is electrically connected to the laminate through an opening provided in the insulating layer 180. It has a conductive layer 150 and an insulating layer 180, conductive layer 140 and as needed. The conductive layer 150 may have an insulating layer (planarized film) or the like in contact with it.

[0288] In transistor 109, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 103, except that it is a physical semiconductor layer 130c.

[0289] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 51(A) and (B). Figure 51(A) is a top view of transistor 110, and the dashed line K shown in Figure 51(A) The cross-section in the 1-K2 direction corresponds to Figure 51(B). Also, the dashed line K3 shown in Figure 51(A) -The cross-section in the K4 direction corresponds to Figure 52(A). Also, the dashed line K1-K2 direction is the channel. The direction in the longitudinal direction, along the dashed line K3-K4, is referred to as the channel width direction.

[0290] In transistor 110, the oxide semiconductor layer 130 is divided into two regions 331 and 332. In region 333, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 104, except that it is a solid semiconductor layer (130c).

[0291] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 51(C) and (D). i. Figure 51(C) is a top view of transistor 111, and the dashed line L shown in Figure 51(C) The cross-section in the 1-L2 direction corresponds to Figure 51(D). Also, the dashed line L3 shown in Figure 51(C) -The cross-section in the L4 direction corresponds to Figure 52(A). Also, the dashed line L1-L2 direction is channel The direction in the longitudinal direction, and the direction of the dashed line L3-L4, are referred to as the channel width direction.

[0292] The transistor 111 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layers 141 and 151, and the laminate, conductive layer 141 and conductive layer 15 A 1 oxide semiconductor layer 130c in contact with 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , conductive layer 170 in contact with insulating layer 160, said lamination, conductive layer 141, conductive layer 151, oxidation A semiconductor layer 130c, an insulating layer 160, and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer The insulating layer 180 is in contact with 175, and the openings provided in the insulating layer 175 and the insulating layer 180 Conductive layers 142 and 151 are electrically connected through conductive layer 141 and conductive layer 151, respectively. It has a conductive layer 152. Additionally, an insulating layer 180, a conductive layer 142, and a conductive layer 1 may be provided as needed. It may have an insulating layer (planarized film) or the like in contact with 52.

[0293] In transistor 111, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The fact that it is a semiconductor layer 130c), and that it is a conductive layer 141 and a conductive layer 151 and an insulating layer 16 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between it and 0, It has the same configuration as transistor 105.

[0294] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 51(E) and (F). Figure 51(E) is a top view of transistor 112, and the dashed line M shown in Figure 51(E) The cross-section in the 1-M2 direction corresponds to Figure 51(F). Also, the dashed line M3 shown in Figure 51(E) -The cross-section in the M4 direction corresponds to Figure 52(A). Also, the dashed line M1-M2 direction is the channel. The direction in the longitudinal direction, and the direction of the dashed line M3-M4, are referred to as the channel width direction.

[0295] Transistor 112 is located in regions 331, 332, 334, and 335. The oxide semiconductor layer 130 consists of two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b). At point 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide Except for the fact that it is a monocrystalline semiconductor layer 130b and an oxide semiconductor layer 130c, transistor 106 and They have a similar configuration.

[0296] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 53(A), (B), (C), (D), (E) ), (F) shown are cross-sectional views in the channel length direction, and the channels shown in Figures 52(C) and (D) As shown in the cross-sectional view in the width direction, a conductive layer 173 is placed between the oxide semiconductor layer 130 and the substrate 115. It may be provided. The conductive layer may be used as a second gate electrode layer (back gate). This allows for further increases in on-current and control of the threshold voltage. (See Figure 53) In the cross-sectional views shown in A), (B), (C), (D), (E), and (F), the conductive layer 173 The width may be shorter than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be shorter than that of the conductive layer 1 The width can be shorter than 70.

[0297] Furthermore, a transistor according to one aspect of the present invention has the configuration shown in Figures 54(A) and 54(B) It is also possible. Figure 54(A) is a top view, and Figure 54(B) is shown in Figure 54(A). These are cross-sectional views corresponding to the dashed lines N1-N2 and N3-N4. See Figure 54. In the top view (A), some elements have been omitted for clarity.

[0298] The transistor 113 shown in Figures 54(A) and 54(B) is connected to substrate 115 and substrate 11 5. An insulating layer 120 on top of the insulating layer 120, and an oxide semiconductor layer 130 on top of the insulating layer 120 (oxide semiconductor layer 130 a) oxide semiconductor layer 130b, oxide semiconductor layer 130c) and oxide semiconductor layer 130 in contact And conductive layers 140 and 150 are arranged with a gap between them, and an oxide semiconductor layer 130 It has an insulating layer 160 in contact with c and a conductive layer 170 in contact with the insulating layer 160. The semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 are on the transistor 113. The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and insulating layer 12 are provided on 190. It is located in an opening that reaches 0.

[0299] The configuration of transistor 113 is, compared to the configurations of the other transistors mentioned above, source Because the overlapping region between the conductor that serves as the electrode or drain electrode and the conductor that serves as the gate electrode is small. Therefore, parasitic capacitance can be reduced. Consequently, transistor 113 can operate at high speed. It is suitable as an element for circuits that require it. The top surface of transistor 113 is shown in Figure 54(B). As shown, CMP (Chemical Mechanical Polishing) It is preferable to flatten the surface using methods such as the law, but a configuration that does not flatten the surface is also possible.

[0300] Furthermore, the conductive layer 140 (source electrode layer) and conductive in a transistor according to one aspect of the present invention Layer 150 (drain electrode layer) is shown in the top view (oxide semiconductor layer 1) in Figures 55(A) and (B). 30. Only conductive layers 140 and 150 are shown in the figure. The width of the oxide semiconductor layer (W O S The width of conductive layer 140 and conductive layer 150 is greater than (W SD Even if a long gap is formed And it may be formed in a short form. OS ≥W SD (W SD is W OS By doing the following, The gate electric field is more easily applied to the entire oxide semiconductor layer 130, affecting the electrical characteristics of the transistor. It can be improved. Also, as shown in Figure 55(C), the conductive layer 140 and the conductive layer 150 may be formed only in the region that overlaps with the oxide semiconductor layer 130.

[0301] In one embodiment of the present invention, a transistor (transistors 101 to 113) is Even in the misaligned configuration, the conductive layer 170, which is the gate electrode layer, is an insulating layer, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via 160, and the on current is This can be improved. Such a transistor structure is called a surrounded channel This is called an (s-channel) structure.

[0302] Furthermore, a transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In a transistor having the oxide semiconductor layer 130, the two or three layers of material By appropriately selecting the material, an electric current can be passed through the oxide semiconductor layer 130b. The current flowing through the conductive layer 130b reduces the effects of interfacial scattering, resulting in a high on-current. This is possible. Therefore, by increasing the thickness of the oxide semiconductor layer 130b, the on-current can be improved. This may occur.

[0303] With the above configuration, the electrical characteristics of the transistor can be improved.

[0304] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. This can be done.

[0305] (Embodiment 4) In this embodiment, the components of the transistor shown in Embodiment 2 will be described in detail. This will be done.

[0306] For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate with an insulated surface, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a structure in which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed on the silicon substrate can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate having a (110) plane as the plane orientation of the surface on which the transistor is formed. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. This can be done. This can be done. This can be done. This can be done. - This can be done. This can be done. - This can be done. This can be done. This can be done. This can be done. This can be done.

[0307] The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115. In addition, it can play a role in supplying oxygen to the oxide semiconductor layer 130. Therefore, The margin layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. It is more preferable that the insulating layer is an insulating film. The insulating layer 120 is converted to oxygen atoms as measured by the TDS method. The calculated amount of oxygen released is 1.0 × 10 19 atoms / cm 3 It is preferable that the above conditions are met. Note that the surface temperature of the film during the above TDS analysis should be between 100°C and 700°C, or 10 The temperature range is 0°C to 500°C. Also, the substrate 115 is a substrate on which other devices are formed. In this case, the insulating layer 120 also functions as an interlayer insulating film. In that case, the surface is flat. It is preferable to perform a planarization treatment using methods such as CMP to make the surface flat.

[0308] For example, the insulating layer 120 contains aluminum oxide, magnesium oxide, silicon oxide, and oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide oxide insulating films such as lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , nitrous oxide such as silicon nitride, silicon nitride, aluminum nitride, aluminum nitride A dielectric insulating film or a mixture thereof can be used. Furthermore, a lamination of the above materials is also possible. That's fine.

[0309] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130 a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked sequentially from the insulating layer 120 side. This section will primarily explain the details of the case where it has a three-layer structure.

[0310] In the case of a single layer oxide semiconductor layer 130, the oxide semiconductor layer 13 shown in this embodiment You can use the layer corresponding to 0b.

[0311] Furthermore, if the oxide semiconductor layer 130 consists of two layers, the oxide semiconductor layer 13 shown in this embodiment... The layer corresponding to 0a and the layer corresponding to the oxide semiconductor layer 130b are arranged in order from the insulating layer 120 side. A stacked layer can be used. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be swapped with 130b.

[0312] Furthermore, if there are four or more oxide semiconductor layers 130, for example, as described in this embodiment... The configuration involves adding another oxide semiconductor layer to the three-layer oxide semiconductor layer 130. It is possible.

[0313] For example, the oxide semiconductor layer 130b contains the oxide semiconductor layer 130a and the oxide semiconductor layer Acids with a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than body layer 130c. Ion semiconductors are used. Electron affinity is the energy difference between the vacuum level and the top of the valence band (ions). From the potential, the energy difference between the lower end of the conduction band and the upper end of the valence band (energy gap) It can be calculated by subtracting (P).

[0314] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. It contains one or more metallic elements, for example, the energy at the lower end of the conduction band is the oxide semiconductor layer 13 Greater than 0b, at least 0.05eV, 0.07eV, 0.1eV, or 0.15eV. If present, it approaches the vacuum level within the range of 2eV, 1eV, 0.5eV, or 0.4eV. It is preferable to form it with an oxide semiconductor.

[0315] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 A channel is formed in the oxide semiconductor layer 130b, which has the lowest energy at the lower end of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It could also be said that it has an area in which it functions.

[0316] Furthermore, the oxide semiconductor layer 130a contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, the interface when the oxide semiconductor layer 130b and the insulating layer 120 are in contact In comparison, interface states are formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. This becomes less likely to occur. The interface level may form a channel, so the transistor The key voltage may fluctuate. Therefore, an oxide semiconductor layer 130a is provided. This can reduce variations in electrical characteristics such as the threshold voltage of transistors. Furthermore, the reliability of the transistor can be improved.

[0317] Furthermore, the oxide semiconductor layer 130c contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact. Compared to the interface in the case of [the other case], the interface between oxide semiconductor layer 130b and oxide semiconductor layer 130c This reduces the likelihood of carrier scattering. Therefore, an oxide semiconductor layer 130c is provided. This allows for an increase in the field-effect mobility of the transistor.

[0318] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c contain Al, Ti, Ga Ge, Y, Zr, Sn, La, Ce, or Hf are used in a material higher than the oxide semiconductor layer 130b. Materials containing the atoms in a specific ratio can be used. Specifically, materials with an atomic ratio of 1.5 times or more are preferred. The ratio should be at least twice, and more preferably at least three times. The aforementioned elements bond strongly with oxygen. Therefore, it has the function of suppressing the occurrence of oxygen vacancies in the oxide semiconductor layer. The monocrystalline semiconductor layer 130a and the oxide semiconductor layer 130c are more acidic than the oxide semiconductor layer 130b. It can be said that primary defects are less likely to occur.

[0319] Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. Preferably, it contains both In and Zn. To reduce variations in the electrical characteristics of the transistors, stabilizers were added along with them. It is preferable to include it.

[0320] Stabilizers include Ga, Sn, Hf, Al, or Zr. The stabilizers are lanthanides such as La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0321] For example, as oxide semiconductors, indium oxide, tin oxide, gallium oxide, zinc oxide, I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxides, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Materials, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn Oxides can be used.

[0322] Here, for example, In-Ga-Zn oxide is a substance whose main components are In, Ga, and Zn. It means oxide. It may also contain metal elements other than In, Ga, and Zn. Furthermore, in this specification, a film composed of In-Ga-Zn oxide is also referred to as an IGZO film. .

[0323] Also, InMO3(ZnO) m Materials represented as (m>0, and m is not an integer) It may be included. Note that M is one selected from Ga, Y, Zr, La, Ce, or Nd. This indicates a metallic element or multiple metallic elements. Also, In2SnO5(ZnO) n (n>0, and You may also use materials represented by n (where n is an integer).

[0324] Furthermore, the oxide semiconductor layer 130b is composed of oxide semiconductor layer 130a and oxide semiconductor layer 130 It is desirable to have a higher indium content than carbon. In oxide semiconductors, heavy metals are primarily used for the s-railway. The pathway contributes to carrier conduction, and by increasing the In content, more s-trajectories are formed. Because the pathways overlap, oxides with a composition where In is greater than M are those with In equal to or less than M. Compared to the oxide that forms the final product, it has higher mobility. Therefore, it is incorporated into the oxide semiconductor layer 130b. By using oxides with a high zinc content, transistors with high field-effect mobility can be realized. It is possible.

[0325] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more. The oxide semiconductor layer 1 is 0 nm or less, more preferably 5 nm to 25 nm. The thickness of 30b is 3 nm to 200 nm, preferably 5 nm to 150 nm. Furthermore, the thickness of the oxide semiconductor layer 130c is preferably 10 nm or more and 100 nm or less. The wavelength is 1 nm to 50 nm, preferably 2 nm to 30 nm, and more preferably The thickness shall be between 3 nm and 15 nm. In addition, the oxide semiconductor layer 130b shall be oxide semiconductor layer 13 A thickness greater than 0c is preferable.

[0326] In order to impart stable electrical characteristics to a transistor with an oxide semiconductor layer as its channel, The impurity concentration in the oxide semiconductor layer is reduced, making the oxide semiconductor layer intrinsic (type i) or substantially Making it intrinsic is effective. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is The degree is 1 x 10 19 / cm 3 Less than 1 × 10 15 / cm 3 Less than 1 ×10 13 / cm 3 Being less than, or 1 × 10 8 / cm 3 It is less than 1 × 10 -9 / cm 3 This refers to something that is greater than or equal to the above.

[0327] Furthermore, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metals other than the main component are present. Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, making them carrier-dense. This increases the degree of the problem. Furthermore, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. These impurity levels can act as traps, potentially degrading the electrical characteristics of the transistor. Therefore, oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide semiconductor layer It is preferable to reduce the impurity concentration in the 130c layer and at each interface.

[0328] To make an oxide semiconductor layer intrinsically or substantially intrinsically, SIMS (Secondary The hydrogen concentration estimated by ion mass spectrometry analysis is 2 ×10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 below, Better 1 × 10 19 atoms / cm 3 More preferably 5 × 10 18 a toms / cm 3 The following, 1 × 10 17 atoms / cm 3 It has an area that is greater than or equal to Control it so that it does not exceed 5 × 10. Also, the nitrogen concentration is 5 × 10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm3 The following, 5 × 10 16 atoms / cm 3 Control the region to have a range greater than or equal to the above.

[0329] Furthermore, high concentrations of silicon and carbon can reduce the crystallinity of the oxide semiconductor layer. In order to avoid reducing the crystallinity of the oxide semiconductor layer, the silicon concentration should be 1 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 It is less than 1 × 10 18 atoms / cm 3 The region is controlled to have a range of the above. Also, the carbon concentration 1 x 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 less than More preferably 1 × 10 18 atoms / cm 3 Less than 6 × 10 17 ato ms / cm 3 Control the region to have a range greater than or equal to the above.

[0330] Furthermore, as mentioned above, a transient using a highly purified oxide semiconductor layer in the channel formation region The off-current of the sta is extremely small. For example, if the voltage between the source and drain is 0.1V, 5 When set to V or approximately 10V, the off-current per channel width of the transistor is several It becomes possible to reduce the level to yA / μm or even a few zA / μm.

[0331] Since silicon-containing insulating films are often used as gate insulating films for transistors, For the reasons stated above, the region that becomes the channel of the oxide semiconductor layer is the transistor of one aspect of the present invention. It can be said that a structure that does not come into contact with the gate insulating film is preferable. When a channel is formed at the interface between the oxide semiconductor layer and the oxide semiconductor layer, carrier scattering occurs at the interface. This can lead to a decrease in the field-effect mobility of the transistor. From this perspective as well, oxidation It is preferable to keep the channel region of the semiconductor layer away from the gate insulating film.

[0332] Therefore, the oxide semiconductor layer 130 is divided into oxide semiconductor layer 130a and oxide semiconductor layer 130b By using a stacked structure of oxide semiconductor layer 130c, channels are formed in oxide semiconductor layer 130b. A transistor can be formed that has high field-effect mobility and stable electrical characteristics. It can form a ta.

[0333] Band structure of oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In this structure, the energy at the lower end of the conduction band changes continuously. This is because the oxide semiconductor layer 1 By making the compositions of 30a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c similar, This can also be understood from the fact that oxygen readily diffuses between them. Therefore, oxide semiconductor layer 130a The oxide semiconductor layer 130b and oxide semiconductor layer 130c are laminates of layers with different compositions. However, it can also be said that it is continuous in terms of physical properties, and in the drawing, each interface of the laminate It is represented by a dotted line.

[0334] The oxide semiconductor layers 130, which are stacked with a common main component, are not simply stacked one layer at a time. Continuous junctions (in this case, U-shaped junctions where the energy at the lower end of the conduction band changes continuously between each layer) The structure is prepared so that a well structure (U-shaped well) is formed. That is, each layer If impurities that form defect levels such as trap centers or recombination centers are present at the interface A layered structure is formed in such a way. If impurities are mixed between the layers of the stacked oxide semiconductor layers, When this occurs, the continuity of the energy band is lost, and carriers are trapped or re-established at the interface. It disappears due to the combination.

[0335] For example, oxide semiconductor layer 130a and oxide semiconductor layer 130c have In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, 1:9: 6. In-Ga-Zn oxide, G, with ratios such as 1:10:1 or nearby values ​​(atomic ratio). Use Ga-Zn oxide with a:Zn = 10:1 or nearby values ​​(atomic ratio). This is possible. Also, the oxide semiconductor layer 130b has In:Ga:Zn=1:1:1, 2: 1:3, 5:5:6, 3:1:2, 4:2:3, 4:2:4.1 or their neighboring values ​​( In-Ga-Zn oxides (in terms of atomic ratio, etc.) can be used. When film deposition is performed using as a sputtering target, the oxide semiconductor layer 130a and acid are deposited. The atomic ratio of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is not necessarily the same. do not have.

[0336] In the oxide semiconductor layer 130, the oxide semiconductor layer 130b becomes a well, and channel The energy is formed in the oxide semiconductor layer 130b. The oxide semiconductor layer 130 has energy at the lower end of the conduction band. Because the ghee changes continuously, it can also be called a U-shaped well. Channels formed through configuration can also be called embedded channels.

[0337] Furthermore, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, and the silicon oxide film, etc. Near the interface with the insulating layer, trap levels can form due to impurities and defects. Due to the presence of the semiconductor layer 130a and the oxide semiconductor layer 130c, the oxide semiconductor layer 13 This allows us to move 0b away from the trap level.

[0338] However, the energy at the lower end of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c - When the difference between this and the energy at the lower end of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductive layer 130b may exceed the energy difference and reach the trap level. When it is trapped in a trap level, a negative charge is generated at the insulating layer interface, and the transistor The threshold voltage shifts in the positive direction.

[0339] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c contain: It is preferable that the crystalline portion is included. In particular, using a crystal oriented along the c-axis allows for the creation of transistors. It can impart stable electrical properties. Furthermore, crystals oriented along the c-axis are resistant to distortion. This can improve the reliability of semiconductor devices using flexible substrates.

[0340] Conductive layer 140 acting as source electrode layer and conductive layer 1 acting as drain electrode layer 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and a single layer or laminate of a material selected from the alloy of the metal material can be used. Typical examples include Ti, which readily combines with oxygen, and materials that allow for relatively high subsequent processing temperatures. For these reasons, it is preferable to use W, which has a high melting point. Also, low-resistance Cu or Cu-M Lamination of alloys such as n and the above materials may also be used. Transistor 105, Transistor 1 06. In transistors 111 and 112, for example, the conductive layer 141 and The conductive layer 151 is made of W, and the conductive layers 142 and 152 are made of a laminated film of Ti and Al, etc. It is possible to be there.

[0341] The above material has the property of extracting oxygen from the oxide semiconductor layer. Therefore, when in contact with the above material... In some regions of the oxide semiconductor layer, oxygen is desorbed from the oxide semiconductor layer, forming an oxygen vacancy. The region becomes noticeably affected when the small amount of hydrogen contained in the membrane combines with the oxygen deficiency. It is converted to n-type. Therefore, the n-type region is the source or drain of the transistor. It can be made to work in this way.

[0342] Furthermore, when W is used in conductive layers 140 and 150, even if nitrogen is doped... Good. By doping with nitrogen, the property of extracting oxygen can be moderately weakened, resulting in an n-type. This prevents the transformed region from expanding into the channel region. Also, the conductive layer 140 The conductive layer 150 is stacked with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By causing contact, it is possible to prevent the n-type region from expanding into the channel region. It is possible. As for the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc., can be used.

[0343] The insulating layer 160, which acts as a gate insulating film, contains aluminum oxide, magnesium oxide, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, acid Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. These may be included as impurities.

[0344] Furthermore, an example of the laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, oxygen It contains nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide, and oxide Preferably contains silicon or silicon oxide nitride.

[0345] Hafnium oxide and aluminum oxide are compared to silicon oxide and silicon oxide-nitride. It has a high dielectric constant. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 is Because it can be made larger, the leakage current due to tunnel current can be reduced. That is, This makes it possible to realize transistors with low current. Furthermore, a crystalline oxide can be used. Hafnium has a higher dielectric constant compared to hafnium oxide, which has an amorphous structure. Therefore, in order to create a transistor with a small off-current, hafnium oxide, which has a crystalline structure, is used. It is preferable to use [this]. Examples of crystal structures include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0346] Furthermore, the insulating layer 120 and insulating layer 160 that are in contact with the oxide semiconductor layer 130 are made of nitrogen oxide It is preferable to use a film with low emission levels. An insulating layer and an oxide semiconductor with high nitrogen oxide emission levels are preferable. When conductors come into contact, the energy level density may increase due to nitrogen oxides. Insulating layer 120 And the insulating layer 160 is, for example, a silicon oxide nitride film that emits a small amount of nitrogen oxides. An oxide insulating layer such as an aluminum oxide nitride film can be used.

[0347] Silicon oxiditride films with low nitrogen oxide emissions are used in the TDS method. This is a membrane where the amount of ammonia released is greater than the amount of ammonia discharged, typically when the amount of ammonia released is 1 × 10⁻⁶. 18 cm -3 The above 5 x 10 19 cm -3 The following applies. Note that the amount of ammonia released is from the membrane. By heat treatment to a surface temperature of 50°C to 650°C, preferably 50°C to 550°C This shall be the amount of release.

[0348] By using the above oxide insulating layer as the insulating layer 120 and insulating layer 160, the transient This makes it possible to reduce the threshold voltage shift of the transistor and the variation in the transistor's electrical characteristics. This can be reduced.

[0349] The conductive layer 170 acting as the gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W It can be used. Furthermore, alloys of the above materials or conductive nitrides of the above materials may also be used. Furthermore, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials Layers of materials are also possible. Typical examples include tungsten and tungsten and titanium nitride layers. Laminated layers of tungsten and tantalum nitride can be used. Also, low-resistance Cu can be used. Alternatively, using alloys such as Cu-Mn or laminates of the above materials with alloys such as Cu or Cu-Mn. This may also be the case. In this embodiment, the conductive layer 171 is made of tantalum nitride, and the conductive layer 172 is made of tungsten A conductive layer 170 is formed using [a specific method / tool].

[0350] The insulating layer 175 may be made of a silicon nitride film or an aluminum nitride film containing hydrogen. This is possible. Transistors 103, 104, and 2 shown in Embodiment 2 In transistors 106, 109, 110, and 112: By using a hydrogen-containing insulating film as the insulating layer 175, a portion of the oxide semiconductor layer is converted to n-type. It is possible. In addition, the nitride insulating film also acts as a blocking film for moisture, etc. This can improve the reliability of the transistor.

[0351] Furthermore, an aluminum oxide film can also be used as the insulating layer 175. In particular, the embodiment Transistors 101, 102, 105, and 2 shown in state 2 In transistors 107, 108, and 111, the insulating layer 175 contains oxide It is preferable to use a luminium film. The aluminum oxide film contains impurities such as hydrogen and water. It has a high barrier effect that prevents both aluminum oxide and oxygen from permeating the membrane. The nium film contains impurities such as hydrogen and water during and after the transistor fabrication process. Prevention of contamination into the oxide semiconductor layer 130, prevention of oxygen release from the oxide semiconductor layer, insulating layer 1 It is suitable for use as a protective film that prevents the unnecessary release of oxygen from 20°C. Furthermore, it is also possible to diffuse the oxygen contained in the aluminum oxide film into the oxide semiconductor layer. ru.

[0352] Furthermore, it is preferable that an insulating layer 180 is formed on the insulating layer 175. This includes magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride Cone, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, rayon oxide Using an insulating film containing one or more of tantalum, neodymium oxide, hafnium oxide, and tantalum oxide This is possible. Furthermore, the insulating layer may be a laminate of the above-mentioned materials.

[0353] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than its stoichiometric composition. This is preferable. Oxygen released from the insulating layer 180 passes through the insulating layer 160 to the oxide semiconductor Since it can diffuse into the channel-forming region of layer 130, it can form a shape in the channel-forming region. The oxygen deficiency that has occurred can be compensated for by oxygen. Therefore, a stable transistor Electrical properties can be obtained.

[0354] Miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization degrades the electrical characteristics of transistors, particularly the channel width. When it shrinks, the on-current decreases.

[0355] In transistors 107 to 112 of one aspect of the present invention, a channel is formed An oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b, The channel-forming layer and the gate insulating film are not in contact. This suppresses carrier scattering at the interface with the insulating film, thus reducing the on-voltage of the transistor. The flow can be increased.

[0356] Furthermore, in a transistor according to one aspect of the present invention, as described above, the oxide semiconductor layer 130 is A gate electrode layer (conductive layer 170) is formed so as to electrically surround the width direction of the fiber. Therefore, for the oxide semiconductor layer 130, in addition to the gate electric field from the direction perpendicular to the top surface, the side A gate electric field is applied from a direction perpendicular to it. That is, the entire channel formation layer A gate electric field is applied, which expands the effective channel width, and therefore the on current is further increased. It can be improved.

[0357] Furthermore, in one aspect of the present invention, the oxide semiconductor layer 130 is a two- or three-layer transistor. This involves forming an oxide semiconductor layer 130b on an oxide semiconductor layer 130a in which a channel is formed. This has the effect of making it difficult for interfacial states to form. Furthermore, oxidation in one aspect of the present invention In a transistor with three semiconductor layers 130, the oxide semiconductor layer 130b is an intermediate layer in the three-layer structure. By positioning it as a layer, it has the added benefit of eliminating the influence of impurities from above and below. Therefore, in addition to improving the on-current of the transistor as described above, the threshold voltage stabilization is also important. This allows for the reduction of the S value (subthreshold value). Therefore, the gate The current can be reduced when the voltage VG is 0V, thereby reducing power consumption. This stabilizes the threshold voltage of the transistor, thereby improving the long-term reliability of semiconductor devices. It can be made possible. Furthermore, the transistor according to one aspect of the present invention has electrical characteristics that improve with miniaturization. Because degradation is suppressed, it can be said that it is suitable for forming highly integrated semiconductor devices.

[0358] The various films described in this embodiment, such as metal films, semiconductor films, and inorganic insulating films, are typically spalled. It can be formed by the condensate method or plasma CVD, but other methods, such as thermal CVD, can also be used. It may also be formed by law. An example of the thermal CVD method is MOCVD (Metal Organic Compounds). nic Chemical Vapor Deposition (NIC) method and ALD (Atom Examples include the IC Layer Deposition method.

[0359] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0360] Furthermore, in the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the contents of the chamber are processed By using atmospheric pressure or reduced pressure, the reaction is carried out near or on the substrate, causing the deposit to be deposited on the substrate. Film deposition may be performed.

[0361] The ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber and supplying the raw material gas for the reaction to the chamber. - The material is introduced and reacted with, and this process is repeated to form a film. Along with the raw material gas, an inert gas is also used. Argon or nitrogen may be introduced as a carrier gas. For example, two or more types The raw material gases may be supplied to the chamber in sequence. In this case, multiple types of raw material gases must not be mixed. As described above, after the reaction of the first raw material gas, an inert gas is introduced, and then the second raw material gas is introduced. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the A second raw material gas may be introduced. The first raw material gas is adsorbed and reacts with the surface of the substrate to form the first layer. A film is formed, and a second raw material gas introduced later is adsorbed and reacts, causing the second layer to form on top of the first layer. The layers are stacked to form a thin film. This process is repeated while controlling the gas introduction sequence until the desired thickness is achieved. By repeating the process several times, a thin film with excellent step coverage can be formed. The thickness of the thin film is Because it can be adjusted by the number of times the injection is repeated, precise film thickness adjustment is possible. It is suitable for fabricating miniature FETs.

[0362] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-Ga -When forming a Zn-O film, trimethylindium (In(CH3)3), trimethyl Tilgarium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) are used. This is possible. It is not limited to these combinations, and trimethylgallium can be substituted with triethyl Lugarium (Ga(C2H5)3) can also be used, and diethyl can be used instead of dimethylzinc. Zinc (Zn(C2H5)2) can also be used.

[0363] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and Liquids containing hafnium precursors (such as hafnium alkoxide or tetrakisdimethylamide) Fnium (TDMAH, Hf[N(CH3)2]4) and tetrakis (ethylmethylamide) (The raw material gas is a vaporized hafnium amide such as hafnium, and ozone is used as an oxidizer.) Two types of gases (O3) are used.

[0364] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: a raw material gas obtained by vaporizing (such as) and H2O as an oxidizing agent. The materials include tris(dimethylamide)aluminum, triisobutylaluminum, and Luminium tris(2,2,6,6-tetramethyl-3,5-heptanedione), etc. There is.

[0365] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Roloticilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are supplied. It is supplied and reacted with the adsorbed material.

[0366] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 gas and H Two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. Gas may be used.

[0367] For example, an oxide semiconductor layer, such as In-Ga-Zn-O, can be deposited using an ALD (Alternating Dead Lens) deposition system. When forming a layer, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are sequentially introduced to form a GaO layer, and further Subsequently, Zn(CH3)2 gas and O3 gas are introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. These gases can be used to create In-Ga-O layers and In-Zn layers. A mixed compound layer such as an O layer or a Ga-Zn-O layer may be formed. Alternatively, instead of O3 gas... H2O gas obtained by bubbling with an inert gas such as Ar may be used, but it does not contain H. It is preferable to use O3 gas, which does not contain oxygen.

[0368] A counter-target sputtering system can also be used to deposit oxide semiconductor layers. The film deposition method using the opposing target sputtering apparatus is called VDSP (vapor It can also be called a precipitate (SP).

[0369] By depositing an oxide semiconductor layer using a counter-target sputtering apparatus, Plasma damage during the deposition of oxide semiconductor layers can be reduced. Therefore, in the film... This can reduce oxygen deficiency. Furthermore, by using a counter-target sputtering apparatus... This enables film deposition at low pressure, thus reducing the impurity concentration in the deposited oxide semiconductor layer (e.g., For example, it can reduce hydrogen, noble gases (such as argon), and water.

[0370] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0371] (Embodiment 5) The following describes the structure of an oxide semiconductor layer that can be used in one aspect of the present invention. .

[0372] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0373] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0374] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0375] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned (crystalline oxide semiconductor), polycrystalline oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l Examples include oxide semiconductors and amorphous oxide semiconductors. ru.

[0376] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. It can be divided into conductors and crystalline oxide semiconductors. As for crystalline oxide semiconductors, there are single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0377] Amorphous structures are generally isotropic and lack heterogeneous structures, representing a metastable state of atomic arrangement. It is not fixed, the bonding angle is flexible, and it has short-range order but not long-range order. It is said that...

[0378] Conversely, stable oxide semiconductors can be made into completely amorphous (completely amorphous) materials. It cannot be called an oxide semiconductor (rphous). Also, it is not isotropic (for example, in a minute region) Oxide semiconductors that have a periodic structure cannot be called perfectly amorphous oxide semiconductors. On the other hand, a-like OS is not isotropic but has an unstable structure with voids (also called porous structures). It is a structure. In terms of instability, a-like OS is an amorphous oxide in terms of its physical properties. It's similar to a semiconductor.

[0379] <caac-os> First, let me explain CAAC-OS.

[0380] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0381] CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 56(A), a peak appears near 31° at the diffraction angle (2θ). Since the 'k' is attributed to the (009) plane of the InGaZnO4 crystal, CAAC-OS The crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also called the surface to be formed). It can be confirmed that it is facing in a direction approximately perpendicular to the top surface. Note that 2θ is 31° In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak is due to a crystal structure classified as space group Fd-3m. Therefore, CAAC -OS preferably does not show the peak.

[0382] On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when this is done, no clear peak appears, as shown in Figure 56(B). On the other hand, single crystal InGaZ When φ scan is performed on nO4 with 2θ fixed near 56°, the result is as shown in Figure 56(C). Six peaks are observed that belong to a crystal plane equivalent to the (110) plane. Therefore, X Structural analysis using RD revealed that CAAC-OS has irregular orientations in its a-axis and b-axis. This can be confirmed.

[0383] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 56(D) (control) is observed. This is also called a limited-field electron diffraction pattern. A diffraction pattern may appear. This diffraction pattern includes In The spot contains a location originating from the (009) plane of the GaZnO4 crystal. Therefore, the electron rotation Depending on the circumstances, the pellets contained in CAAC-OS may have c-axis orientation, and the c-axis may be the surface to be formed. Alternatively, it can be seen that it is oriented in a direction approximately perpendicular to the upper surface. On the other hand, for the same sample, on the sample surface Figure 56(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly. As shown in Figure 56(E), a ring-shaped diffraction pattern can be observed. Therefore, the probe Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of peridotites in CAAC-OS. It can be seen that the a-axis and b-axis of the net do not have orientation. Note that in Figure 56(E) The ring is caused by the (010) and (100) planes of the InGaZnO4 crystal, among other things. It is thought that the second ring in Figure 56(E) is caused by the (110) plane, etc. It's possible.

[0384] Furthermore, a transmission electron microscope (TEM) A composite image of the bright-field image and diffraction pattern of CAAC-OS obtained by (croscope) analysis. When observing a high-resolution TEM image (also known as a TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are not visible. Also called "Nandaly." ) There are cases where it is not possible to clearly confirm this. Therefore, CAAC -OS can be said to be less prone to the decrease in electron mobility caused by grain boundaries.

[0385] Figure 57(A) shows a high-resolution T of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The EM image is shown. For observing high-resolution TEM images, spherical aberration correction is required. The aberration correction function was used. High-resolution analysis was performed using the spherical aberration correction function. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. This can be observed.

[0386] From Figure 57(A), we can see that the pellet is a region in which metal atoms are arranged in layers. Yes, it is possible. It has been found that the size of a single pellet can be 1 nm or larger, or even 3 nm or larger. Therefore, pellets are called nanocrystals (nc). It is also possible to use CAAC-OS with CANC(C-Axis Aligned nan It can also be called an oxide semiconductor containing ocrystals. The pellet is CAAC -Reflects the unevenness of the surface or top surface of the OS, and the surface or top surface of the CAAC-OS It becomes parallel to the plane.

[0387] Furthermore, Figures 57(B) and 57(C) show CAAC observed from a direction approximately perpendicular to the sample surface. -Shows a Cs-corrected high-resolution TEM image of the OS plane. Figures 57(D) and 57(E) are shown. These are images obtained by image processing Figure 57(B) and Figure 57(C), respectively. The following describes the image processing. Let's explain the method. First, Figure 57(B) is converted to the Fast Fourier Transform (FFT). The FFT image is obtained by performing a Fourier Transform (FFT) process. Next, the acquisition In the resulting FFT image, with the origin as the reference point, 2.8 nm -1 from 5.0nm -1 Leave the range between Next, the masked FFT image is subjected to the inverse Fast Fourier Transform (IFFT: By processing the image (Inverse Fast Fourier Transform), The processed image is obtained. The image obtained in this way is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and is a grid image. This shows the array.

[0388] In Figure 57(D), areas where the grid arrangement is disordered are indicated by dashed lines. The area enclosed by the dashed lines is It is a single pellet. The dotted line indicates the connection point between the pellets. The dashed line indicates a hexagonal shape, showing that the pellet is hexagonal. The shape of the net is not always a regular hexagon; it is often a non-regular hexagon.

[0389] In Figure 57(E), a dotted line separates one region with a aligned grid arrangement from another region with a aligned grid arrangement. As shown, even near the dotted line, a clear grain boundary cannot be confirmed. Connecting the surrounding grid points to a central grid point creates a distorted hexagon, or a pentagon and / or heptagon. Shapes and other features can be formed. That is, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. It can be seen that CAAC-OS has a dense atomic arrangement in the ab plane. Due to the absence of certain elements, or because the substitution of metal elements changes the bond distance between atoms, This is thought to be because it allows for distortion to be tolerated.

[0390] As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, CA AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an anchored crystal. ru.

[0391] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. Because it can decrease due to the generation of defects or other factors, from the opposite perspective, CAAC-OS It can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0392] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0393] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers A can become a source of emissions. For example, oxygen vacancies in oxide semiconductors can trap carriers and In some cases, it may become a carrier source by capturing hydrogen.

[0394] CAAC-OS, with its low impurity and oxygen vacancies, is an oxide semiconductor with a low carrier density. Specifically, 8 x 10 11 cm -3 Less than 1 × 10 11 cm -3 Less than, More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 The above career It can be made into a high-density oxide semiconductor. Such an oxide semiconductor can be made into a high-purity intrinsic or It is essentially a high-purity, intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and defects. It has a low energy level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0395] <nc-os> Next, I will explain nc-OS.

[0396] This section describes the case of analyzing nc-OS using XRD. For example, for nc-OS When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. In other words, nc-OS crystals do not have orientation.

[0397] Furthermore, for example, nc-OS having an InGaZnO4 crystal is thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, Figure 58 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. Furthermore, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample (na The beam electron diffraction pattern is shown in Figure 58(B). From Figure 58(B), a ring-shaped region is visible. Multiple spots are observed within. Therefore, nc-OS has a probe diameter of 50 nm. Order is not confirmed by irradiating with an electron beam, but when an electron beam with a probe diameter of 1 nm is irradiated... Order can be confirmed by having them shoot.

[0398] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 58(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. This may occur. Therefore, in the range of thickness less than 10 nm, nc-OS is ordered. It can be seen that there is a region with high fissure, i.e., a crystal. Furthermore, the crystals are oriented in various directions. Therefore, there are also regions where a regular electron diffraction pattern is not observed.

[0399] Figure 58(D) shows the Cs-corrected elevation of the cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. High-resolution TEM images are shown. nc-OS refers to areas indicated by auxiliary lines in the high-resolution TEM image. As shown, there are regions where the crystalline structure can be observed and regions where the crystalline structure cannot be clearly observed. It has a region and a crystal portion contained in nc-OS, with a size of 1 nm to 10 nm. Yes, and they are often between 1 nm and 3 nm in size. Oxide semiconductors with a wavelength greater than 0 nm and less than or equal to 100 nm are called microcrystalline oxide semiconductors (micro It is sometimes called a crystalline oxide semiconductor. nc-OS is useful, for example, when grain boundaries cannot be clearly identified in high-resolution TEM images. There is a possibility that the nanocrystals share the same origin as the pellets in CAAC-OS. Therefore, the crystalline portion of nc-OS may be referred to as a pellet in the following text.

[0400] Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from oxide semiconductors.

[0401] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS is used. Oxides containing RANC (Random Aligned nanocrystals) semiconductors, or containing NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0402] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0403] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0404] Figure 59 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 59(A) is This is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Figure 59(B ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation These are high-resolution cross-sectional TEM images. From Figures 59(A) and 59(B), a-like OS It can be seen that, from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. The bright regions show a change in shape after electron irradiation. Furthermore, the bright regions are either porous or low-density. It is presumed to be in the degree range.

[0405] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0406] As samples, prepare a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0407] First, high-resolution cross-sectional TEM images are obtained for each sample. All of them have a crystalline portion.

[0408] Furthermore, the unit cell of the InGaZnO4 crystal has three In-O layers, and Ga-Zn- It is known to have a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the spacing between the grid planes of the (009) plane (also called the d value). It is approximately [value], and from crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, Below, areas where the spacing of the grid stripes is between 0.28 nm and 0.30 nm are represented as InGaZn. This was considered to be the crystalline portion of O4. Note that the lattice fringes correspond to the ab-plane of the InGaZnO4 crystal. ru.

[0409] Figure 60 shows an example of investigating the average size of the crystalline regions (22 to 30 locations) in each sample. The length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 60, a-like The crystalline portion of the OS grows larger in proportion to the cumulative amount of electrons irradiated during TEM image acquisition, etc. It can be seen that, as shown in Figure 60, the size is about 1.2 nm in the initial stages of TEM observation. The crystal region (also called the initial nucleus) is then transformed into an electron (e - The cumulative radiation dose was 4.2 × 10⁻⁶ 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 1.9 nm. On the other hand, nc -OS and CAAC-OS are defined as the cumulative electron dose from the start of electron irradiation being 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. (Figure 60) Furthermore, regardless of the cumulative electron irradiation dose, the size of the crystal region in nc-OS and CAAC-OS is, It can be seen that they are approximately 1.3 nm and 1.8 nm, respectively. TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. Electron beam irradiation conditions The acceleration voltage is 300kV and the current density is 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0410] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. It is clear that the structure is unstable.

[0411] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density will be between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are difficult to deposit into film.

[0412] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's how it is. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] , the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also , for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0413] Note that when there is no single crystal of the same composition, the density corresponding to the single crystal in the desired composition can be estimated by combining single crystals with different compositions at an arbitrary ratio. The density corresponding to the single crystal in the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor takes various structures and each has various characteristics. In addition, the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, CAAC-OS. The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0414]

[0415]

[0416] (Embodiment 6) In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The imaging device configuration according to one aspect of the present invention can be used for the image sensor chip.

[0417] Figure 61(A) is a perspective view of the top side of the package containing the image sensor chip. The package consists of a package substrate 810 for fixing the image sensor chip 850, and The device includes a bar glass 820 and an adhesive 830 for bonding the two together.

[0418] Figure 61(B) is a perspective view of the bottom of the package. On the bottom of the package, It has a BGA (Ball Grid Array) configuration with 840 solder balls as bumps. Yes. Note that this applies not only to BGA, but also to LGA (Land grid array) and PGA (P You could also use something like `in Grid Array`.

[0419] Figure 61(C) shows the package with some of the cover glass 820 and adhesive 830 omitted. This is a perspective view of the package, and Figure 61(D) is a cross-sectional view of the package substrate. An electrode pad 860 is formed on 810, and the electrode pad 860 and bump 840 are connected -Electrically connected via hole 880 and land 885. Electrode pad 860 The electrodes of the image sensor chip 850 are electrically connected by the wire 870. It is.

[0420] Figure 62(A) shows a camera with an image sensor chip housed in a lens-integrated package. This is a perspective view of the top side of the camera module. The camera module is an image sensor. Package substrate 811, lens cover 821, and lens 835 for fixing the top 851 It has the following features. Also, between the package substrate 811 and the image sensor chip 851 An IC chip 890 is also provided, which has functions such as a drive circuit and a signal conversion circuit for the image device. It has a configuration as a SiP (System in Package).

[0421] Figure 62(B) is a perspective view of the lower side of the camera module. Package substrate 8 The bottom and four sides of 11 are provided with mounting lands 841 for the QFN (Quad f It has a lat no-lead package configuration. Note that this configuration is just one example. Yes, it can be a QFP (Quad flat package) or the aforementioned BGA, etc. stomach.

[0422] Figure 62(C) shows the module with the lens cover 821 and part of the lens 835 omitted. This is a perspective view of the frame, and Figure 62(D) is a cross-sectional view of the camera module. A portion of 41 is used as an electrode pad 861, and the electrode pad 861 is an image sensor chip The electrodes of the pin 851 and IC chip 890 are electrically connected by wire 871. It is.

[0423] By housing the image sensor chip in the package described above, printed circuit boards, etc. This makes implementation easier, allowing image sensor chips to be integrated into various semiconductor devices and electronic equipment. It is possible.

[0424] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0425] (Embodiment 7) An imaging device according to one aspect of the present invention, and a semiconductor device including the imaging device, can be used. As an electronic device, it includes a display device, a personal computer, and an image storage device equipped with a recording medium. Devices or image playback devices, mobile phones, game consoles including portable models, mobile data terminals, e-book terminals In addition, cameras such as video cameras and digital still cameras, goggle-type displays (head Mounted display), navigation system, sound playback device (car audio, de Digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, Examples include automated teller machines (ATMs) and vending machines. These electronic devices An example is shown in Figure 63.

[0426] Figure 63(A) shows a surveillance camera, which has a housing 951, a lens 952, a support part 953, etc. One component for acquiring images in the said surveillance camera is an imaging device according to one aspect of the present invention. The device can be equipped with such equipment. Note that "surveillance camera" is a common term and does not specify its intended use. It's not a camera. For example, a device that functions as a surveillance camera is a camera, or a video camera. It is also called Ra.

[0427] Figure 63(B) shows a video camera, comprising a first housing 971, a second housing 972, a display unit 973, It has an operation key 974, a lens 975, a connecting part 976, etc. Operation key 974 and lens 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. It exists. One aspect of the present invention is a component for acquiring images in the video camera. It can be equipped with an imaging device.

[0428] Figure 63(C) shows a digital camera, consisting of a housing 961, a shutter button 962, and a microphone 9 It has components 63, a light-emitting unit 967, a lens 965, etc. Images are acquired with this digital camera. One component for this purpose may be an imaging device according to one embodiment of the present invention.

[0429] Figure 63(D) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 33, it has operating buttons 935, a crown 936, a camera 939, etc. The display unit 932 is It may be a touch panel. It is one of the components for acquiring images on the information terminal. The present invention may be provided with an imaging device according to one embodiment of the present invention.

[0430] Figure 63(E) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control keys 907, Stylus 908, Camera It has 909, etc. Note that the portable game console shown in Figure 63(E) has two display units 903 It has a display unit 904, but the number of display units that a portable game console has is not limited to this. It is not possible. The present invention is one of the components for acquiring images in the portable game console. The device can be equipped with an imaging device of the form.

[0431] Figure 63(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows for the input and output of information. One aspect of the present invention is a component for acquiring images in the mobile data terminal. It can be equipped with an imaging device.

[0432] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of Symbols]

[0433] 10 pixels 11-pixel array 12 circuits 13 circuits 14 circuits 15 circuits 16 circuits 17 Comparator Circuit 18. Judgment Output Circuit 19 Counter Circuit 20 pixels 21-pixel array 22 circuits 23 circuits 24 circuits 25 circuits 27 Comparator Circuit 28. Judgment Output Circuit 29 Counter Circuit 35 circuit boards 41 Transistors 42 transistors 43 transistors 44 transistors 45 transistors 46 transistors 51 Transistors 52 transistors 53 Transistors 54 transistors 61 Wiring 62 Wiring 63 Wiring 64 Wiring 65 Wiring 71 Wiring 71a Conductive layer 71b Conductive layer 72 Wiring 73 Wiring 74 Wiring 75 Wiring 80 Insulating layer 81 Conductors 82 Insulating layer 82a Insulating layer 82b Insulating layer 83 Insulating layer 88 Wiring 91 Wiring 92 Wiring 93 Wiring 94 Wiring 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 106 transistors 107 transistors 108 transistors 109 transistors 110 transistors 111 transistors 112 transistors 113 Transistors 115 circuit boards 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide Semiconductor Layer 130c oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive layer 171 Conductive layer 172 Conductive layer 173 Conductive layer 175 Insulating layer 180 Insulating layer 190 Insulating layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 400 period 401 period 402 period 403 period 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor layer 564 Semiconductor layer 565 Semiconductor layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 568 Hole injection blockage layer 569 Electron injection blocking layer 600 silicon substrate 610 transistors 620 transistors 650 active layer 660 silicon substrate 741 transistors 742 transistors 743 transistors 744 transistors 745 transistors 746 transistors 747 transistors 751 transistors 752 transistors 753 Transistors 754 transistors 761 Wiring 762 Wiring 763 Wiring 764 Wiring 765 Wiring 771 Wiring 772 Wiring 773 Wiring 774 Wiring 775 Wiring 791 Wiring 792 Wiring 793 Wiring 794 Wiring 810 Package Substrate 811 Package substrate 820 Cover Glass 821 Lens Cover 830 Adhesive 835 lens 840 Bump 841 Land 850 Image Sensor Chips 851 Image Sensor Chip 860 Electrode Pads 861 Electrode Pads 870 wire 871 Wire 880 Through Hole 885 Rand 890 IC chip 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 909 Camera 911 cabinet 912 Display section 919 Camera 931 cabinet 932 Display section 933 Wristband 935 buttons 936 Crown 939 Camera 951 cabinet 952 Lens 953 Support part 961 cabinet 962 Shutter button 963 Mike 965 lens 967 Light-emitting part 971 cabinet 972 cabinets 973 Display section 974 Operation Keys 975 lens 976 Connection part 1100 layers 1200 layers 1400 layers 1500 diffraction grating 1600 layers 2500 Insulating layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filters 2530a color filter 2530b color filter 2530c color filter 2540 Microlens Array 2550 Optical Conversion Layer 2560 Insulating layer

Claims

1. It comprises a photoelectric conversion element formed on a silicon substrate, a capacitive element, a first transistor, and a second transistor. When the anode of the photoelectric conversion element, which is positioned on the light-receiving surface side of the photoelectric conversion element, is positioned upward, the capacitive element, the first transistor, and the second transistor have a region positioned below the anode. The cathode of the photoelectric conversion element is electrically connected to either the source or the drain of the first transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The source or drain of the first transistor is electrically connected to the capacitive element in an imaging device, A first conductive layer having a function as one electrode of the capacitive element and having a region on its upper surface that is in contact with the first insulating layer, A second conductive layer having the function of the other electrode of the capacitive element and having a region on its lower surface that is in contact with the second insulating layer, A third conductive layer is electrically connected to the anode and has a region on its upper surface that is in contact with the first insulating layer, A fourth conductive layer is electrically connected to the anode via the third conductive layer and functions as wiring to control the potential of the anode, A fifth conductive layer having a function as a first signal line electrically connected to the gate of the first transistor, and having a region on its lower surface that is in contact with the second insulating layer, A sixth conductive layer having a function as a second signal line electrically connected to the gate of the second transistor, and having a region on its lower surface that is in contact with the second insulating layer, A hafnium oxide layer having a region positioned above the light-receiving surface, A light-shielding layer having a region positioned above the light-receiving surface via the hafnium oxide layer, The array comprises a microlens array having a region positioned above the light-shielding layer, The source or drain of the first transistor, the other of which is electrically connected to the first conductive layer, Either the source or the drain of the second transistor is electrically connected to the first conductive layer. The fourth conductive layer has a region located below the third conductive layer, The third conductive layer overlaps with the light-shielding layer. An imaging device wherein the fourth conductive layer overlaps with the light-shielding layer.

2. It comprises a photoelectric conversion element formed on a silicon substrate, a capacitive element, a first transistor, and a second transistor. When the anode of the photoelectric conversion element, which is positioned on the light-receiving surface side of the photoelectric conversion element, is positioned upward, the capacitive element, the first transistor, and the second transistor have a region positioned below the anode. The cathode of the photoelectric conversion element is electrically connected to either the source or the drain of the first transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The source or drain of the first transistor is electrically connected to the capacitive element in an imaging device, A first conductive layer having a function as one electrode of the capacitive element and having a region on its upper surface that is in contact with the first insulating layer, A second conductive layer having the function of the other electrode of the capacitive element and having a region on its lower surface that is in contact with the second insulating layer, A third conductive layer is electrically connected to the anode and has a region on its upper surface that is in contact with the first insulating layer, A fourth conductive layer is electrically connected to the anode via the third conductive layer and functions as wiring to control the potential of the anode, A fifth conductive layer having a function as a first signal line electrically connected to the gate of the first transistor, and having a region on its lower surface that is in contact with the second insulating layer, A sixth conductive layer having a function as a second signal line electrically connected to the gate of the second transistor, and having a region on its lower surface that is in contact with the second insulating layer, A hafnium oxide layer having a region positioned above the light-receiving surface, A light-shielding layer having a region positioned above the light-receiving surface via the hafnium oxide layer, A color filter having a region positioned above the light-shielding layer, The system includes a microlens array having a region positioned above the color filter, The source or drain of the first transistor, the other of which is electrically connected to the first conductive layer, Either the source or the drain of the second transistor is electrically connected to the first conductive layer. The fourth conductive layer has a region located below the third conductive layer, The third conductive layer overlaps with the light-shielding layer. An imaging device wherein the fourth conductive layer overlaps with the light-shielding layer.

3. It comprises a photoelectric conversion element formed on a silicon substrate, a capacitive element, a first transistor, and a second transistor. When the anode of the photoelectric conversion element, which is positioned on the light-receiving surface side of the photoelectric conversion element, is positioned upward, the capacitive element, the first transistor, and the second transistor have a region positioned below the anode. The cathode of the photoelectric conversion element is electrically connected to either the source or the drain of the first transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The source or drain of the first transistor is electrically connected to the capacitive element in an imaging device, A first conductive layer having a function as one electrode of the capacitive element and having a region on its upper surface that is in contact with the first insulating layer, A second conductive layer having the function of the other electrode of the capacitive element and having a region on its lower surface that is in contact with the second insulating layer, A third conductive layer is electrically connected to the anode and has a region on its upper surface that is in contact with the first insulating layer, A fourth conductive layer is electrically connected to the anode via the third conductive layer and functions as wiring to control the potential of the anode, A fifth conductive layer having a function as a first signal line electrically connected to the gate of the first transistor, and having a region on its lower surface that is in contact with the second insulating layer, A sixth conductive layer having a function as a second signal line electrically connected to the gate of the second transistor, and having a region on its lower surface that is in contact with the second insulating layer, A hafnium oxide layer having a region positioned above the light-receiving surface, A light-shielding layer having a region positioned above the light-receiving surface via the hafnium oxide layer, The array comprises a microlens array having a region positioned above the light-shielding layer, The source or drain of the first transistor, the other of which is electrically connected to the first conductive layer, Either the source or the drain of the second transistor is electrically connected to the first conductive layer. The fourth conductive layer has a region located below the third conductive layer, The third conductive layer overlaps with the light-shielding layer. The fourth conductive layer overlaps with the light-shielding layer. The channel formation region of the first transistor overlaps with the region of the anode that does not overlap with the light-shielding layer. The imaging device wherein the channel formation region of the second transistor overlaps with a region of the anode that does not overlap with the light-shielding layer.

4. It comprises a photoelectric conversion element formed on a silicon substrate, a capacitive element, a first transistor, and a second transistor. When the anode of the photoelectric conversion element, which is positioned on the light-receiving surface side of the photoelectric conversion element, is positioned upward, the capacitive element, the first transistor, and the second transistor have a region positioned below the anode. The cathode of the photoelectric conversion element is electrically connected to either the source or the drain of the first transistor. The source or drain of the first transistor is electrically connected to the source or drain of the second transistor. The source or drain of the first transistor is electrically connected to the capacitive element in an imaging device, A first conductive layer having a function as one electrode of the capacitive element and having a region on its upper surface that is in contact with the first insulating layer, A second conductive layer having the function of the other electrode of the capacitive element and having a region on its lower surface that is in contact with the second insulating layer, A third conductive layer is electrically connected to the anode and has a region on its upper surface that is in contact with the first insulating layer, A fourth conductive layer is electrically connected to the anode via the third conductive layer and functions as wiring to control the potential of the anode, A fifth conductive layer having a function as a first signal line electrically connected to the gate of the first transistor, and having a region on its lower surface that is in contact with the second insulating layer, A sixth conductive layer having a function as a second signal line electrically connected to the gate of the second transistor, and having a region on its lower surface that is in contact with the second insulating layer, A hafnium oxide layer having a region positioned above the light-receiving surface, A light-shielding layer having a region positioned above the light-receiving surface via the hafnium oxide layer, A color filter having a region positioned above the light-shielding layer, The system includes a microlens array having a region positioned above the color filter, The source or drain of the first transistor, the other of which is electrically connected to the first conductive layer, Either the source or the drain of the second transistor is electrically connected to the first conductive layer. The fourth conductive layer has a region located below the third conductive layer, The third conductive layer overlaps with the light-shielding layer. The fourth conductive layer overlaps with the light-shielding layer. The channel formation region of the first transistor overlaps with the region of the anode that does not overlap with the light-shielding layer. The imaging device wherein the channel formation region of the second transistor overlaps with a region of the anode that does not overlap with the light-shielding layer.

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