Semiconductor equipment

Abstract

To provide a semiconductor device with excellent connection reliability.SOLUTION: A semiconductor device 1 includes: a semiconductor element 10 where a first electrode 11 to a third electrode 13 are provided; an insulating base material 21 where penetration holes 31 and 32 from which the first electrode and the third electrode are exposed; wires 40 and 50 that are electrically connected to the first electrode and the third electrode through the penetration holes; a wiring member (conductive adhesive layer 63) that is electrically connected to the second electrode; a first terminal (press-fit terminal 70) that is connected to the wire 40 and has elasticity; a second terminal (press-fit terminal 80) that is connected to the wiring member and has elasticity; and a fixing member 100 that fixes the first terminal and the second terminal while electrically insulating therebetween. The wire 40 has a first concave part (via wire 41) that is recessed toward the semiconductor element. The first terminal has a first convex part (bowl-like part 71). The first terminal and the second terminal sandwich, in a lamination direction, a laminated body 130 including the wiring member, the semiconductor element, the insulating base material by the elasticity.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, as a semiconductor device, a semiconductor element is attached to a resin film such as polyimide via an adhesive layer, and wiring is formed on the surface opposite to the adhesive layer of the resin film (see, for example, Patent Document 1). Terminals such as bus bars are soldered to the wiring of this semiconductor device.

Prior Art Documents

Patent Documents

[0003] <00Q0016]]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device, the solder connecting the wiring and the terminal may contain voids. Voids reduce connection reliability.

[0005] An object of this disclosure is to provide a semiconductor device capable of obtaining excellent connection reliability.

Means for Solving the Problems

[0006] According to one embodiment of the present disclosure, a semiconductor element having a first surface and a second surface opposite to the first surface, with a first electrode provided on the first surface and a second electrode provided on the second surface; an insulating substrate mounted on the first surface of the semiconductor element, having a third surface in contact with the first surface and a fourth surface opposite to the third surface, with a through hole formed therein through which the first electrode is exposed; wiring disposed on the fourth surface of the insulating substrate and electrically connected to the first electrode through the through hole; a wiring member provided on the second surface of the semiconductor element and electrically connected to the second electrode; and the wiring A semiconductor device is provided, comprising: a first terminal connected to a wire and having elasticity; a second terminal connected to the wiring member and having elasticity; and a fixing member that fixes the first terminal and the second terminal while electrically insulating them from each other, wherein the wiring has a fifth surface that contacts the first terminal, the fifth surface has a first recess that is recessed toward the semiconductor element, the first terminal has a first protrusion that fits into the first recess and contacts the fifth surface, and the first terminal and the second terminal elastically sandwich a laminate including the wiring member, the semiconductor element, the insulating substrate and the wiring in the stacking direction. [Effects of the Invention]

[0007] According to this disclosure, excellent connectivity reliability can be obtained. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] This is a circuit diagram showing a semiconductor device according to an embodiment. [Figure 3] This is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] This is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] This is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] This is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0009] Embodiments of this disclosure will be described in detail below with reference to the attached drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numerals to avoid redundant explanations. In this disclosure, the X1-X2 direction, Y1-Y2 direction, and Z1-Z2 direction are mutually orthogonal directions. The plane including the X1-X2 direction and the Y1-Y2 direction is described as the XY plane, the plane including the Y1-Y2 direction and the Z1-Z2 direction is described as the YZ plane, and the plane including the Z1-Z2 direction and the X1-X2 direction is described as the ZX plane. For convenience, the Z1-Z2 direction is considered the up and down direction, with the Z1 side being the upper side and the Z2 side being the lower side. Planar view means viewing the object from the Z1 side, and planar shape means the shape of the object as viewed from the Z1 side. However, semiconductor devices can be used upside down or arranged at any angle.

[0010] [Configuration of semiconductor device] First, the cross-sectional configuration of the semiconductor device according to this embodiment will be described. Figure 1 is a cross-sectional view showing the semiconductor device according to this embodiment.

[0011] As shown in Figure 1, the semiconductor device 1 according to this embodiment includes a semiconductor element 10 and a flexible wiring substrate 20. For example, the semiconductor element 10 can be a device using silicon (Si) or silicon carbide (SiC). Alternatively, the semiconductor element 10 can be a device using gallium nitride (GaN) or gallium arsenide (GaAs). For example, the semiconductor element 10 can be an active semiconductor element (e.g., a silicon chip such as a CPU), an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a diode. The semiconductor element 10 is a semiconductor element with electrodes on its front and back surfaces. The planar shape of the semiconductor element 10 can be any shape and size. For example, the planar shape of the semiconductor element 10 is formed in a rectangular shape. The thickness of the semiconductor element 10 can be, for example, about 50 μm to 500 μm.

[0012] The semiconductor element 10 has one surface 10A and another surface 10B opposite to the surface 10A. The semiconductor element 10 also has a main body 15, an electrode 11, an electrode 12, and an electrode 13. Electrodes 11 and 13 are provided on one surface 10A, and electrode 12 is provided on the other surface 10B. For example, electrodes 11, 12, and 13 can be a source electrode, a drain electrode, and a gate electrode, respectively.

[0013] Electrodes 11, 12, and 13 (hereinafter sometimes collectively referred to as "electrodes") can be made from materials such as aluminum (Al) or copper (Cu), or alloys containing at least one metal selected from these metals. If necessary, a surface treatment layer may be formed on the surface of the electrodes. Examples of surface treatment layers include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by stacking Ni and Au layers in that order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by stacking Ni, Pd, and Au layers in that order). For these Au, Ni, and Pd layers, for example, metal layers formed by electroless plating (electroless plated metal layers) can be used. Furthermore, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0014] The flexible wiring board 20 comprises an insulating substrate 21, an insulating adhesive layer 22, and a wiring layer 25. The insulating substrate 21 has one surface 21A and another surface 21B opposite to the first surface 21A. The adhesive layer 22 is provided on the first surface 21A, and the wiring layer 25 is provided on the other surface 21B. The adhesive layer 22 may be provided over the entire surface 21A. The wiring layer 25 is laminated on the other surface 21B. The wiring layer 25 comprises a seed layer 23 and a metal layer 24.

[0015] As the insulating substrate 21, for example, a resin film can be used. As the material of the resin film, insulating resins such as polyimide resin, polyethylene resin, and epoxy resin can be used. The insulating substrate 21 is, for example, flexible. Here, flexibility refers to the property of being able to be bent or flexed. The planar shape of the insulating substrate 21 can be any shape and any size. The planar shape of the insulating substrate 21 is formed in a rectangular shape, for example. The thickness of the insulating substrate 21 can be, for example, about 50 μm to 100 μm.

[0016] The semiconductor element 10 is adhered to one surface 21A of the insulating substrate 21 by an adhesive layer 22. One surface 10A of the semiconductor element 10 faces one surface 21A of the insulating substrate 21. Through holes 31 through which the electrode 11 is exposed and through holes 32 through which the electrode 13 is exposed are formed in the insulating substrate 21 and the adhesive layer 22. One surface 21A of the insulating substrate 21 contacts one surface 10A of the semiconductor element 10 through the adhesive layer 22. In the present disclosure, the state of contacting through an adhesive layer or a conductive adhesive layer may be simply referred to as "contacting".

[0017] As the material of the adhesive layer 22, for example, adhesives such as epoxy-based, polyimide-based, and silicone-based adhesives can be used. As the thickness of the adhesive layer 22, for example, it can be set to about 20 μm to 40 μm.

[0018] A plurality of sets of the electrode 11 and the through hole 31 may be provided, and the same number of sets of the electrode 13 and the through hole 32 as the sets of the electrode 11 and the through hole 31 may be provided.

[0019] The wiring layer 25 has a wiring 40 connected to the electrode 11 through the through hole 31 and a wiring 50 connected to the electrode 13 through the through hole 32.

[0020] The wiring 40 includes a via wiring 41 filled in the through hole 31 and a wiring pattern 42 formed on the other surface 21B of the insulating substrate 21. The wiring 40 has one surface 40A and the other surface 40B opposite to the one surface 40A. One surface 40A of the wiring 40 contacts the other surface 21B of the insulating substrate 21, the inner surface of the through hole 31, and the surface of the electrode 11 exposed from the through hole 31. The other surface 40B of the wiring 40 has a surface 41B provided on the via wiring 41 and a surface 42B provided on the wiring pattern 42. The surface 41B of the via wiring 41 is a concave surface that recesses toward the semiconductor element 10 so as to enter the through hole 31 from the surface 42B of the wiring pattern 42. The via wiring 41 recesses toward the semiconductor element 10. The via wiring 41 is an example of the first recess.

[0021] The wiring 50 includes via wiring 51 filled in the through hole 32 and a wiring pattern 52 formed on the other surface 21B of the insulating substrate 21. The wiring 50 has one surface 50A and the other surface 50B opposite to the surface 50A. The one surface 50A of the wiring 50 is in contact with the other surface 21B of the insulating substrate 21, the inner surface of the through hole 32, and the surface of the electrode 13 exposed from the through hole 32. The other surface 50B of the wiring 50 has a surface 51B provided on the via wiring 51 and a surface 52B provided on the wiring pattern 52. The surface 51B of the via wiring 51 is a concave surface that recesses toward the semiconductor element 10 so as to enter the through hole 32 from the surface 52B of the wiring pattern 52. The via wiring 51 is recessed toward the semiconductor element 10.

[0022] The seed layer 23 covers the other surface 21B of the insulating substrate 21 and the inner surfaces of the through holes 31 and 32. The seed layer 23 is formed to continuously cover the other surface 21B of the insulating substrate 21, the inner surfaces of the through holes 31 and 32, and the surfaces of the electrodes exposed at the bottom of the through holes 31 and 32. A metal film (sputtered film) formed by sputtering can be used as the seed layer 23. As a seed layer 23 formed by sputtering, for example, a two-layer metal film can be used in which a Ti layer made of titanium (Ti) and a Cu layer made of copper (Cu) are sequentially laminated on the other surface 21B of the insulating substrate 21 and the inner surfaces of the through holes 31 and 32. In this case, the thickness of the Ti layer can be, for example, about 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 1000 nm. The Ti layer functions as an adhesion layer to improve the adhesion between the insulating substrate 21 and electrodes and the seed layer 23. Furthermore, the Ti layer functions as a metal barrier layer that suppresses the diffusion of copper from the Cu layer, etc., to the insulating substrate 21, etc. In addition to Ti, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used as materials for the metal film that functions as such an adhesion layer and metal barrier layer.

[0023] For example, copper or a copper alloy can be used as the material for the metal layer 24. For example, a metal layer formed by electroplating (electroplated metal layer) can be used as the metal layer 24.

[0024] The semiconductor device 1 further includes lead terminals 60, press-fit terminals 70, press-fit terminals 80, press-fit terminals 90, a fixing member 100, and a sealing material 110.

[0025] The lead terminal 60 is formed, for example, from a lead frame. The material of the lead terminal 60 is, for example, copper (Cu). The electrodes 12 of the semiconductor element 10 are bonded to the lead terminal 60 by a conductive adhesive layer 63. The lead terminal 60 has one surface 60A and the other surface 60B opposite to the surface 60A. A recess 61 is formed on one surface 60A of the lead terminal 60. The recess 61 is formed, for example, by half-etching. The depth of the recess 61 is approximately equal to the sum of the thickness of the semiconductor element 10 and the thickness of the conductive adhesive layer 63. The semiconductor element 10 is mounted in the recess 61. A recess 62 is formed on the other surface 60B of the lead terminal 60. The recess 62 is formed, for example, by half-etching. The recess 62 is formed in a position that overlaps with the semiconductor element 10 in a plan view. The conductive adhesive layer 63 is, for example, a solder layer or a sintered metal layer. The conductive adhesive layer 63 may be composed of a conductive paste. One side 60A of the lead terminal 60 is in contact with the other side 10B of the semiconductor element 10 via the conductive adhesive layer 63. The lead terminal 60 is an example of a wiring member. The recess 61 is an example of a third recess. The recess 62 is an example of a second recess.

[0026] The lead terminal 60 is provided so as to be covered by the sealing material 110. A portion of the lead terminal 60 may be exposed from the sealing material 110. On the other surface 60B of the lead terminal 60, a protrusion 65 that forms a recess 62 is provided on the outer circumference. The side surface of the protrusion 65 forms the inner surface of the recess 62. By providing the protrusion 65, it is possible to prevent the press-fit terminal 80 from coming loose. In addition, the strength of the seal can be improved by increasing the surface area in contact between the lead terminal 60 and the sealing material 110. Also, in Figure 1, the protrusion that forms a recess 61 is not shown on the outer circumference in the direction of X1 on one surface 60A, but a protrusion may be provided.

[0027] The press-fit terminal 70 is made of metal and is elastic. The material of the press-fit terminal 70 is, for example, copper (Cu). The press-fit terminal 70 includes a bowl-shaped portion 71 and a base portion 72 connected to the bowl-shaped portion 71. The press-fit terminal 70 has one surface 70A and the other surface 70B opposite to the surface 70A. The surface 70A of the press-fit terminal 70 has a surface 71A provided on the bowl-shaped portion 71 and a surface 72A provided on the base portion 72. The surface 71A of the bowl-shaped portion 71 is a convex surface that protrudes toward the semiconductor element 10 from the surface 72A of the base portion 72. The bowl-shaped portion 71 protrudes toward the semiconductor element 10. The surface 71A of the bowl-shaped portion 71 contacts the surface 41B of the via wiring 41, and the bowl-shaped portion 71 fits into the concave via wiring 41 and contacts the wiring 40. The press-fit terminal 70 is an example of a first terminal, and the bowl-shaped portion 71 is an example of a first convex portion.

[0028] The press-fit terminal 80 is made of a material such as copper (Cu). It is metallic and elastic. The press-fit terminal 80 includes a bowl-shaped portion 81 and a base portion 82 connected to the bowl-shaped portion 81. The press-fit terminal 80 has one surface 80A and the other surface 80B opposite to the surface 80A. The surface 80A of the press-fit terminal 80 has a surface 81A provided on the bowl-shaped portion 81 and a surface 82A provided on the base portion 82. The surface 81A of the bowl-shaped portion 81 is a convex surface that protrudes toward the semiconductor element 10 from the surface 82A of the base portion 82. The bowl-shaped portion 81 protrudes toward the semiconductor element 10. The surface 81A of the bowl-shaped portion 81 contacts the surface 60B of the lead terminal 60, and the bowl-shaped portion 81 fits into the recess 62 and contacts the lead terminal 60. The press-fit terminal 80 is an example of a second terminal, and the bowl-shaped portion 81 is an example of a second protrusion.

[0029] The base portion 72 of the press-fit terminal 70 and the base portion 82 of the press-fit terminal 80 extend substantially parallel to each other toward the X1 side when viewed from the semiconductor element 10. The fixing member 100 fixes the press-fit terminals 70 and 80 while electrically insulating them from each other. The fixing member 100 has an insulating member 101 and a tightening member 102. The insulating member 101 is provided between the other end of the base portion 72 and the other end of the base portion 82 and contacts the surfaces 72A of the base portion 72 and the surface 82A of the base portion 82. For example, a polyimide layer or insulating paper can be used as the insulating member 101. The tightening member 102 tightens the press-fit terminal 70, the insulating member 101 and the press-fit terminal 80 while sandwiching them. The tightening member 102 includes, for example, an insulating bolt and nut.

[0030] The press-fit terminal 90 is made of metal and is elastic. The material of the press-fit terminal 90 is, for example, copper (Cu). The press-fit terminal 90 includes a bowl-shaped portion 91 and a base portion 92 connected to the bowl-shaped portion 91. The press-fit terminal 90 has one surface 90A and the other surface 90B opposite to the surface 90A. The surface 90A of the press-fit terminal 90 has a surface 91A provided on the bowl-shaped portion 91 and a surface 92A provided on the base portion 92. The surface 91A of the bowl-shaped portion 91 is a convex surface that protrudes toward the semiconductor element 10 from the surface 92A of the base portion 92. The bowl-shaped portion 91 protrudes toward the semiconductor element 10. The surface 91A of the bowl-shaped portion 91 contacts the surface 51B of the via wiring 51, and the bowl-shaped portion 91 fits into the concave via wiring 51 and contacts the wiring 50. The base portion 92 of the press-fit terminal 90 extends towards X2 when viewed from the semiconductor element 10.

[0031] The press-fit terminals 70 and 80 are fixed by the fixing member 100 to form the terminal member 120. In the terminal member 120, the distance between the surface 71A of the bowl-shaped portion 71 and the surface 81A of the bowl-shaped portion 81 is greater than when the laminate 130, which includes the lead terminal 60, conductive adhesive layer 63, semiconductor element 10, adhesive layer 22, insulating substrate 21, and wiring 40, is provided between them due to the elastic deformation of the press-fit terminals 70 and 80. Therefore, when the laminate 130 is provided between the surface 71A of the bowl-shaped portion 71 and the surface 81A of the bowl-shaped portion 81, the press-fit terminals 70 and 80 elastically sandwich the laminate 130 in the lamination direction.

[0032] The sealing material 110 seals the laminate 130, press-fit terminals 70, 80, and 90. The sealing material 110 seals at least the portion where the press-fit terminal 70 and the wiring 40 come into contact with each other, and the portion where the press-fit terminal 80 and the lead terminal 60 come into contact with each other. As the material for the sealing material 110, for example, mold resin or underfill resin can be used.

[0033] The electrode 11 of the semiconductor element 10 is electrically connected to the press-fit terminal 70. The electrode 12 of the semiconductor element 10 is electrically connected to the lead terminal 60 and the press-fit terminal 80. The electrode 13 of the semiconductor element 10 is electrically connected to the press-fit terminal 90.

[0034] Here, the circuit configuration of the semiconductor device 1 according to the embodiment will be described. Figure 2 is a circuit diagram showing the semiconductor device according to the embodiment.

[0035] As shown in Figure 2, electrode 11 of semiconductor element 10 is electrically connected to terminal P 151 via press-fit terminal 70. Electrode 12 of semiconductor element 10 is electrically connected to terminal N 152 via lead terminal 60 and press-fit terminal 80. Electrode 13 of semiconductor element 10 is electrically connected to control terminal 153 via press-fit terminal 90. Terminal P 151 is the positive input terminal, and terminal N 152 is the negative input terminal. Therefore, currents flow in opposite directions through press-fit terminals 70 and 80.

[0036] [Manufacturing method for semiconductor devices] Next, a method for manufacturing a semiconductor device according to the embodiment will be described. Figures 3 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. In the following description, a so-called multi-cavity manufacturing method will be described, in which the part that will become a composite of the semiconductor element 10 and the flexible wiring substrate 20 is manufactured all at once, and then the composite is made into individual pieces. For the sake of convenience in the explanation, the parts that will ultimately become each component of the semiconductor device 1 will be denoted by the reference numeral of the final component.

[0037] First, as shown in Figure 3(a), a large insulating substrate 21 having one surface 21A and the other surface 21B is prepared. The large insulating substrate 21 has, for example, a plurality of individual regions in which composites are formed arranged in a matrix. Here, the individual regions are regions that are ultimately cut along predetermined cutting lines to become individual pieces, each becoming an individual composite. The number of individual regions that the large insulating substrate 21 has is not particularly limited. An insulating adhesive layer 22 is provided on one surface 21A of the insulating substrate 21, covering the entire surface 21A.

[0038] Next, as shown in Figure 3(b), through-holes 31 and 32 are formed at required locations in the insulating substrate 21 and the adhesive layer 22, penetrating the insulating substrate 21 and the adhesive layer 22 in the thickness direction. The through-holes 31 and 32 can be formed, for example, by laser processing using a CO2 laser or UV-YAG laser, or by punching. For example, through-hole 31 is formed on the X1 side of through-hole 32.

[0039] Next, as shown in Figure 3(c), the semiconductor element 10 is bonded to the insulating substrate 21 with the adhesive layer 22. At this time, one side 10A of the semiconductor element 10 is positioned opposite one side 21A of the insulating substrate 21, and the electrodes 11 and 13 are aligned so that they overlap the through-hole 31 and the through-hole 32 in a plan view.

[0040] Next, as shown in Figure 4(a), a wiring layer 25 including a seed layer 23 and a metal layer 24 is formed on the other surface 21B of the insulating substrate 21. The wiring layer 25 can be formed, for example, by a semi-additive method.

[0041] Specifically, the seed layer 23 is formed to cover the entire other surface 21B of the insulating substrate 21 and the entire inner surfaces of the through holes 31 and 32. The seed layer 23 can be formed, for example, by sputtering or electroless plating. For example, when forming the seed layer 23 by sputtering, first, a Ti layer is formed by depositing titanium by sputtering to cover the other surface 21B of the insulating substrate 21 and the inner surfaces of the through holes 31 and 32. Then, a Cu layer is formed by depositing copper on the Ti layer by sputtering. This allows for the formation of a two-layer seed layer 23 (Ti layer / Cu layer). Alternatively, when forming the seed layer 23 by electroless plating, for example, a seed layer 23 consisting of a Cu layer (single-layer structure) can be formed by electroless copper plating.

[0042] Next, a plating resist layer (not shown) is formed on the seed layer 23, with openings provided in the areas where the wiring layer 25 will be formed, i.e., the areas where the wirings 40 and 50 will be formed. Subsequently, a metal layer 24 made of copper or the like is formed in the openings of the plating resist layer by an electroplating method that uses the seed layer 23 as a plating power supply path. After that, the plating resist layer is removed. Next, the seed layer 23 is removed by wet etching using the metal layer 24 as a mask. In this way, a wiring layer 25 including the seed layer 23 and the metal layer 24 can be formed. The wiring layer 25 has wirings 40 and 50. The flexible wiring substrate 20 is composed of an insulating substrate 21, an adhesive layer 22, and a wiring layer 25.

[0043] In addition, a lead terminal 60 is prepared separately from the flexible wiring board 20. For example, a lead terminal 60 is prepared in which a recess 61 is formed on one surface 60A and a recess 62 is formed on the other surface 60B by half-etching of a metal plate. The depth of the recess 61 is approximately the same as the sum of the thickness of the semiconductor element 10 and the thickness of the conductive adhesive layer 63.

[0044] After the wiring layer 25 is formed, a conductive adhesive layer 63 is provided on the other surface 10B of the semiconductor element 10, as shown in Figure 4(b). The conductive adhesive layer 63 is left in an uncured state. Next, the lead terminals 60 are joined to the electrodes 12 using the conductive adhesive layer 63. The conductive adhesive layer 63 is cured during this joining process. In addition, the adhesive layer 22 of the flexible wiring board 20 is placed on one surface 60A of the lead terminals 60.

[0045] In this way, the laminate 130 can be manufactured. Note that the division of the large insulating substrate 21 can be done, for example, after the formation of the wiring layer 25 (see Figure 4(a)) and before the application of the conductive adhesive layer 63 (see Figure 4(b)).

[0046] In addition to the laminate 130, a terminal member 120 having a press-fit terminal 70, a press-fit terminal 80, and a fixing member 100 is prepared, as shown in Figure 5(a). The press-fit terminal 70 includes a bowl-shaped portion 71 and a base portion 72 connected to the bowl-shaped portion 71. The press-fit terminal 80 includes a bowl-shaped portion 81 and a base portion 82 connected to the bowl-shaped portion 81. The distance between the surface 71A of the bowl-shaped portion 71 and the surface 81A of the bowl-shaped portion 81 is smaller when the laminate 130 is not provided between the surface 71A of the bowl-shaped portion 71 and the surface 81A of the bowl-shaped portion 81 than when the laminate 130 is provided.

[0047] Then, as shown in Figure 5(b), the terminal member 120 is fixed to the laminate 130. Specifically, the press-fit terminals 70 and 80 are elastically deformed, and the surface 71A of the bowl-shaped portion 71 is brought into contact with the other surface 40B of the wiring 40, and the surface 81A of the bowl-shaped portion 81 is brought into contact with the other surface 60B of the lead terminal 60, while the terminal member 120 is moved toward the laminate 130 from the X2 side of the laminate 130. Then, when the bowl-shaped portion 71 fits into the concave via wiring 41 and the bowl-shaped portion 81 fits into the recess 62 of the lead terminal 60, the movement of the terminal member 120 is stopped. In this way, the bowl-shaped portion 71 fits into the concave via wiring 41 and the bowl-shaped portion 81 fits into the recess 62.

[0048] Next, as shown in Figure 6, the press-fit terminal 90 is positioned so that the bowl-shaped portion 91 fits into the concave via wiring 51, and then sealed with the sealing material 110.

[0049] In this way, the semiconductor device 1 according to the embodiment can be manufactured.

[0050] In the semiconductor device 1 according to this embodiment, the surface 71A of the bowl-shaped portion 71 contacts the surface 41B of the via wiring 41, and the bowl-shaped portion 71 fits into the concave via wiring 41 and contacts the wiring 40. Also, the surface 81A of the bowl-shaped portion 81 contacts the surface 60B of the lead terminal 60, and the bowl-shaped portion 81 fits into the recess 62 and contacts the lead terminal 60. Then, the press-fit terminals 70 and 80 elastically sandwich the laminate 130 in the stacking direction. As a result, the wiring 40 and the press-fit terminal 70 make firm contact with each other, and the lead terminal 60 and the press-fit terminal 80 make firm contact with each other. Therefore, according to this embodiment, excellent connection reliability can be obtained. Furthermore, the terminal member 120 can be firmly mechanically fixed to the laminate 130 without using a bonding material such as solder.

[0051] Furthermore, the sealing material 110 seals at least the portion where the press-fit terminal 70 and the wiring 40 come into contact with each other, and the portion where the press-fit terminal 80 and the lead terminal 60 come into contact with each other. Therefore, excellent stability is obtained in the contact between the wiring 40 and the press-fit terminal 70, and in the contact between the lead terminal 60 and the press-fit terminal 80. In this respect as well, according to this embodiment, excellent connection reliability can be obtained, and the terminal member 120 can be firmly mechanically fixed to the laminate 130.

[0052] Furthermore, the base 72 of the press-fit terminal 70 and the base 82 of the press-fit terminal 80 extend substantially parallel to each other toward the X1 side when viewed from the semiconductor element 10. Therefore, the length of the press-fit terminals 70 and 80 can be shortened, thereby reducing the inductance.

[0053] Furthermore, when current flows from terminal P 151 to terminal N 152, current flows from X2 to X1 in press-fit terminal 70, and from X1 to X2 in press-fit terminal 80. Therefore, loop inductance is possible. Also, in this embodiment, the distance between press-fit terminal 70 and press-fit terminal 80 is at most approximately the sum of the thickness of the semiconductor element 10, the thickness of the flexible wiring board 20, and the thickness of the portion of the lead terminal 60 where the recess 62 is formed. Therefore, the magnetic field generated around press-fit terminal 70 and the magnetic field generated around press-fit terminal 80 tend to cancel each other out, and inductance can be reduced.

[0054] Furthermore, the wiring layer 25 can be formed on the other surface 21B of the insulating substrate 21 with fine and high precision by a semi-additive method. Therefore, high dimensional accuracy can be achieved, and connections such as external connection terminals can be easily made. The wiring layer 25 can also be formed on the other surface 21B of the insulating substrate 21 by a subtractive method. In addition, by bonding the semiconductor element 10 to one surface 21A of the insulating substrate 21 with an adhesive layer 22, the position of the semiconductor element 10 can be fixed with respect to the insulating substrate 21 and the wiring layer 25. Therefore, according to this embodiment, excellent positional accuracy and connection reliability can be obtained.

[0055] Note that a recess 61 does not necessarily have to be formed on one side 60A of the lead terminal 60. However, if a recess 61 is formed, the overall thickness of the semiconductor device 1 can be reduced.

[0056] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of symbols]

[0057] 1 Semiconductor device 10 Semiconductor devices 10A, 10B, 21A, 21B, 40A, 40B, 41B, 42B, 50A, 50B, 51B, 52B, 60A, 60B, 70A, 70B, 71A, 72A, 80A, 80B, 81A, 82A, 90A, 90B, 91A, 92A side 11, 12, 13 electrodes 20 Flexible Wiring Boards 21 Insulating substrate 22 Adhesive layer 25 wiring layer 31, 32 Through holes 40, 50 wiring Via wiring 41, 51 42, 52 wiring patterns 60 lead terminals 61, 62 recess 70, 80, 90 press-fit terminals 71, 81, 91 Bowl-shaped part 72, 82, 92 base 100 Fixing member 101 Insulating material 102 Fastening member 110 Sealing material 120 Terminal component 130 Laminate

Claims

1. A semiconductor element having a first surface and a second surface opposite to the first surface, wherein a first electrode is provided on the first surface and a second electrode is provided on the second surface, An insulating substrate mounted on the first surface of the semiconductor element, having a third surface in contact with the first surface and a fourth surface opposite to the third surface, and having a through hole formed therein through which the first electrode is exposed, A wiring is arranged on the fourth surface of the insulating substrate and electrically connected to the first electrode through the through hole, A wiring member provided on the second surface of the semiconductor element and electrically connected to the second electrode, A first terminal, which is elastic and connected to the aforementioned wiring, A second terminal, which is connected to the aforementioned wiring member and has elasticity, A fixing member that fixes the first terminal and the second terminal while electrically insulating them from each other, It has, The wiring has a fifth surface that contacts the first terminal, The fifth surface has a first recess that is recessed toward the semiconductor element, The first terminal has a first protrusion that fits into the first recess and contacts the fifth surface, The first and second terminals elastically sandwich a laminate including the wiring member, the semiconductor element, the insulating substrate, and the wiring in the stacking direction.

2. The wiring member has a sixth surface that contacts the second surface of the semiconductor element and a seventh surface opposite to the sixth surface, and the seventh surface has a second recess that is recessed toward the semiconductor element. The semiconductor device according to claim 1, wherein the second terminal has a second protrusion that fits into the second recess and contacts the wiring member.

3. The semiconductor device according to claim 1 or 2, further comprising a sealing material that seals at least the portion where the first terminal and the wiring come into contact with each other, and the portion where the second terminal and the wiring member come into contact with each other.

4. The semiconductor device according to claim 1 or 2, wherein currents flow in opposite directions through the wiring and the wiring member.

5. The semiconductor device according to claim 1 or 2, wherein the wiring member has lead terminals.

6. The semiconductor device according to claim 1 or 2, having a conductive adhesive layer that joins the second electrode and the wiring member to each other.

7. The second electrode and the wiring member are joined together by a conductive adhesive layer, The sixth surface of the wiring member has a third recess that is approximately equal to the sum of the thickness of the semiconductor element and the thickness of the conductive adhesive layer. The semiconductor device according to claim 2, wherein the semiconductor element is mounted in the third recess.

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