Insulated-gate bipolar transistor

Abstract

To provide an IGBT capable of reducing the turn-on voltage and reducing the switching loss.SOLUTION: An IGBT includes: an n-type drift layer 3; an n-type accumulation layer 4 provided on the upper surface of the drift layer and having higher impurity concentration than the drift layer; a base layer provided on the upper surface of the accumulation layer; a gate electrode 11a embedded, through a gate insulating film 10a, inside a striped gate trench 9a penetrating the base layer and the accumulation layer; and a dummy electrode 11b embedded, through a dummy insulating film 10b, inside a dummy trench 9b provided to face the gate trench across the base layer and the accumulation layer. The base layer has a p-type active base region 5a and a p-type floating base region 5b arranged alternately in the extending direction of the gate trench, and an n-type base isolation region 5c isolating the active base region and the floating base region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a trench-gate type insulated-gate bipolar transistor (IGBT). [Background technology]

[0002] Trench-gate IGBTs can achieve high channel density and reduced on-voltage. Furthermore, by separating the p-type base layer into an active base region connected to the emitter potential and a floating base region at a floating potential using a gate trench, carrier injection is promoted, thereby reducing the IGBT's on-voltage. During turn-off, holes in the carriers accumulated in the floating base region are extracted through the extraction path at the bottom of the gate trench, resulting in poor turn-off characteristics.

[0003] Patent Document 1 discloses a structure in which a floating base region with a floating potential and an active base region connected to the emitter potential are alternately arranged in the direction of extension of the mesa within a stripe-shaped mesa extending along a gate trench. Current density and saturation current can be easily adjusted by adjusting the width of the mesa in the direction of extension of the emitter region located above the active base region, as well as by adjusting the distance from the floating base region and the width of the floating base region. In addition, the on-voltage can be reduced by the injection enhancement (IE) effect of the floating base region. During turn-off, hole extraction paths can be formed not only at the bottom of the gate trench but also on the trench sides between the floating base region and the active base region within the mesa, reducing the potential change of the floating base region and suppressing turn-off losses. However, during turn-on, it becomes difficult to form hole extraction paths between the floating base region and the active base region, making it difficult to control the turn-on speed.

[0004] Patent Document 2 discloses a structure in which the base region is separated by a gate trench and a dummy trench connected to the emitter potential. A first base region is provided between the gate trenches, a second base region between the dummy trenches, and a floating base region between the gate trenches and the dummy trenches. The first and second active base regions are connected to the emitter potential, and the floating base region is at a floating potential. In the ON state, the ON voltage is reduced by the IE effect of the floating base region. During turn-off, hole extraction paths are formed around the gate trench and the dummy trench, and during the turn-on process, the extraction path around the dummy trench remains. Therefore, by making the potential change of the floating base region gentle during the switching process, switching losses can be improved.

[0005] In the structure disclosed in Patent Document 2, when an n-type storage layer with a higher concentration than the drift layer is provided below the base region, the on-voltage due to the floating base region can be reduced. However, it becomes difficult to form hole extraction paths, and the voltage change rate dV / dt and loss control during switching deteriorate. Therefore, Patent Document 3 discloses a structure that eliminates the floating base region and connects it to the emitter potential. Also, the Miller capacitance C between the gate and collector GC and the gate-emitter input capacitance C GE Adjusting the ratio through surface cell arrangement is difficult and makes it hard to accommodate different application needs (e.g., dV / dt control). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2000-183340 [Patent Document 2] Patent No. 5987990 [Patent Document 3] Japanese Patent Publication No. 2020-191439 [Overview of the project] [Problems that the invention aims to solve]

[0007] In view of the above-mentioned problems, the present invention aims to provide an insulated-gate bipolar transistor that can reduce on-voltage and reduce switching losses. [Means for solving the problem]

[0008] One aspect of the present invention includes (a) a drift layer of a first conductivity type, (b) a storage layer of a first conductivity type having a higher impurity concentration than the drift layer, (c) a base layer provided on the upper surface of the storage layer, (d) a gate electrode embedded inside a stripe-shaped gate trench penetrating the base layer and the storage layer via a gate insulating film, (e) a dummy electrode embedded inside a stripe-shaped dummy trench penetrating the base layer and the storage layer via a dummy insulating film, and (f) a component provided on the upper part of the base layer with a higher impurity concentration than the drift region. The gist of this invention is an insulated-gate bipolar transistor comprising an emitter region of a first conductivity type with a pure concentration, a base layer having an active base region of a second conductivity type with an emitter region on top connected to the emitter potential, a floating base region of a second conductivity type set to a floating potential, and a separation region of a first conductivity type separating the active base region and the floating base region, wherein in a mesa where a gate trench and a dummy trench are adjacent, the active base region and the floating base region are alternately arranged in the direction of extension of the gate trench, separated by the separation region. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an insulated-gate bipolar transistor that can reduce on-voltage and reduce switching losses. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic plan view showing an example of the arrangement of the base region of the IGBT according to the embodiment. [Figure 2] This is a schematic cross-sectional view taken from the direction of line AA in Figure 1. [Figure 3] This is a schematic cross-sectional view taken from the direction of line BB in Figure 1. [Figure 4]This is a schematic perspective view illustrating the hole extraction path of the IGBT according to the embodiment. [Figure 5] This is a schematic cross-sectional view showing an example of an IGBT in Comparative Example 1. [Figure 6] This is a schematic cross-sectional view showing an example of an IGBT in Comparative Example 2. [Figure 7] This is a circuit diagram showing an example of a circuit for measuring the switching characteristics of an IGBT. [Figure 8] This figure shows an example of the relationship between the voltage change rate and gate resistance of an IGBT according to the embodiment. [Figure 9] This figure shows an example of the relationship between the switching loss and gate resistance of an IGBT according to the embodiment. [Figure 10] This figure shows another example of the relationship between the voltage change rate and gate resistance of an IGBT according to the embodiment. [Figure 11] This figure shows another example of the relationship between the switching loss and gate resistance of an IGBT according to the embodiment. [Figure 12] This figure shows an example of the turn-on waveform of the IGBT according to the embodiment. [Figure 13] This figure shows another example of the turn-on waveform of the IGBT according to the embodiment. [Figure 14] This table shows an example of the evaluation results of the IGBT according to the embodiment. [Figure 15] This is a schematic plan view showing another example of the arrangement of the source region of the IGBT according to the embodiment. [Figure 16] This is a schematic plan view showing another example of the arrangement of the base region of the IGBT according to the embodiment. [Figure 17] This is a schematic cross-sectional view taken from the direction of line CC in Figure 16. [Figure 18] This is a schematic plan view showing another example of the arrangement of the base region of the IGBT according to the embodiment. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following description. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly. In the following explanation, the case where the first conductivity type is n-type and the second conductivity type, which is the opposite, is p-type will be explained as an example. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, the + and - attached to n and p mean that they are semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - attached, respectively. However, even if two semiconductor regions are attached to the same n, this does not mean that the impurity concentrations of each semiconductor region are exactly the same.

[0013] Figure 1 is a schematic plan view showing the arrangement of the base layer (5a, 5b), base separation region 5c, and trenches (9a, 9b) of an IGBT according to the first embodiment of the present invention. As shown in Figure 1, the trenches (9a, 9b) consist of a striped gate trench 9a and a striped dummy trench 9b arranged parallel to the gate trench 9a in a plan view. The gate trenches 9a and dummy trenches 9b are arranged alternately, and the base layer (5a, 5b) and base separation region 5c are provided between the gate trenches 9a and dummy trenches 9b. In the base layer (5a, 5b) and base separation region 5c, in a plan view, the active base region 5a and the floating base region 5b are arranged alternately in the direction in which the trenches (9a, 9b) extend, and the active base region 5a and the floating base region 5b are separated by the base separation region 5c. In other words, in a mesa where a gate trench 9a and a dummy trench 9b are adjacent, the active base region 5a and the floating base region 5b are alternately arranged via a base separation region 5c. In a direction perpendicular to the extension direction of the trenches (9a,9b), the active base region 5a faces the adjacent active base region 5a across the gate trench 9a, and faces the floating base region 5b across the dummy trench 9b. Alternatively, the active base region 5a may be arranged so as to face the floating base region 5b across the dummy trench 9b, and also face the floating base region 5b across the gate trench 9a. The position of the active base region 5a projected in a direction perpendicular to the extension direction of the trenches (9a,9b) is contained within the floating base region 5b.

[0014] As shown in FIG. 1, an emitter region 6 and a low-resistance base connection region 7 are selectively provided above the active base region 5a. Both the emitter region 6 and the low-resistance base connection region 7 are provided so as to contact the opposing side surfaces of the gate trench 9a and the dummy trench 9b, respectively. The base isolation region 5c is arranged to face the low-resistance base connection region 7 through the active base region 5a in the extending direction of the trench (9a, 9b). That is, in the extending direction of the trench (9a, 9b), the low-resistance base connection region 7 is provided so as to cover both sides of the emitter region 6, and is closer to the base isolation region 5c than the emitter region 6. In FIG. 1, two emitter regions 6 sandwiched by the low-resistance base connection region 7 are arranged in the extending direction of the trench (9a, 9b). The number of emitter regions 6 is not limited, and may be three or more, or may be single. Also, neither the emitter region 6 nor the low-resistance base connection region 7 is provided in the floating base region 5b. A contact region is formed so as to partially contact the emitter region 6 and be included in the low-resistance base connection region 7, and an emitter electrode 13 is formed in ohmic contact with the semiconductor surface therein.

[0015] FIG. 2 is a cross-sectional view taken in a direction orthogonal to the extending direction of the trench (9a, 9b), and FIG. 3 is a cross-sectional view taken in the extending direction of the trench (9a, 9b). As shown in FIGS. 2 and 3, an n-type accumulation layer 4 having a higher impurity concentration than the drift layer 3 is provided on the upper surface of the drift layer 3 of the first conductivity type (n - -type), and a base layer (5a, 5b) and a base isolation region 5c are arranged on the upper surface of the accumulation layer 4. The base layer (5a, 5b) has an active base region 5a of the second conductivity type (p-type) and a floating base region 5b of p-type. The base isolation region 5c is of the first conductivity type (n-type). The n-type base isolation region 5c has an impurity concentration not less than the impurity concentration of the drift layer 3 and not more than the impurity concentration of the accumulation layer 4. For example, the impurity concentration is about 3×10 13 cm -3 for the drift layer 3, and 5×10 15 cm -3 or more and 1×10 17 cm -3 or less for the accumulation layer 4, preferably 1×1016 cm -3 The above is 1 x 10 17 cm -3 The range is as follows: Above the active base region 5a, n has a higher impurity concentration than the drift layer 3. + The emitter region 6 of type 5a and the p region with a higher impurity concentration than the active base region 5a + A low-resistance base connection region 7 is provided. As shown in Figure 1, the emitter region 6 and the low-resistance base connection region 7 are alternately provided in the direction in which the trenches (9a, 9b) extend in parallel. The emitter region 6 and the low-resistance base connection region 7 are connected to the emitter potential. In other words, the active base region 5a is connected to the emitter potential via the low-resistance base connection region 7. The floating base region 5b is set to the floating potential.

[0016] Trenches (9a, 9b) are provided that penetrate the storage layer 4 from the upper surfaces of the base layers (5a, 5b) and the base isolation region 5c. The base layers (5a, 5b), the base isolation region 5c, and the storage layer 4 are in contact with the sides of each trench (9a, 9b), and a portion of the drift layer 3 is also in contact with them. As shown in Figure 2, a gate insulating film 10a is provided on the bottom and sides of the gate trench 9a. A gate electrode 11a connected to the gate potential via the gate insulating film 10a is embedded inside the gate trench 9a. A dummy insulating film 10b is provided on the bottom and sides of the dummy trench 9b. A dummy electrode 11b connected to the emitter potential via the dummy insulating film 10b is embedded inside the dummy trench 9b.

[0017] As the gate insulating film 10a and dummy insulating film 10b, in addition to silicon dioxide (SiO2) film, a single-layer film of any one of the following can be used: silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these. As the material for the gate electrode 11a and dummy electrode 11b, for example, a polysilicon layer (doped polysilicon layer) to which impurities such as phosphorus (P) or boron (B) are added at a high impurity concentration can be used.

[0018] As shown in Figures 2 and 3, interlayer insulating films 12 are placed on the gate electrode 11a and the dummy electrode 11b, respectively. The interlayer insulating film 12 extends to cover the floating base region 5b and the base separation region 5c. An emitter electrode 13 is provided so as to cover the interlayer insulating film 12. As shown in Figures 2 and 3, the emitter electrode 13 is in physical contact with the emitter region 6 and the low-resistance base connection region 7 through contact holes formed between the interlayer insulating films 12. A silicon oxide film doped with boron (B) and phosphorus (P) (BPSG) is used as the interlayer insulating film 12. The interlayer insulating film 12 may also be a silicon oxide film doped with phosphorus (P) (PSG), an undoped SiO2 film that does not contain phosphorus (P) or boron (B) and is called "NSG", a silicon oxide film doped with boron (B) (BSG), a Si3N4 film, etc. A multilayer film of these may also be used. The emitter electrode 13 is, for example, made of nickel silicide (NiSi x It can be composed of a film, titanium nitride (TiN) film, titanium (Ti) film, aluminum (Al) film, or aluminum-silicon (Al-Si) film.

[0019] An n-type field stop layer (FS layer) 2 is placed on the lower surface of the drift layer 3, and p +A collector region 1 of a specific type is arranged. A collector electrode 14 is arranged on the lower surface of the collector region 1. As the collector electrode 14, for example, a single layer film made of gold (Au) or a metal film stacked in the order of Ti, nickel (Ni), and Au can be used. The IGBT according to this embodiment can be realized using a silicon (Si) semiconductor substrate as the basis and using a normal semiconductor device manufacturing process.

[0020] During operation of the IGBT according to this embodiment, for example, with the emitter electrode 13 at ground potential, a positive voltage is applied to the collector electrode 14. When a positive voltage above a threshold, for example +15V, is applied to the gate electrode 11a, an inversion layer (channel) is formed on the surface of the active base region 5a, which is the interface between the gate insulating film 10a of the gate trench 9a and the active base region 5a. Using electrons supplied to the drift layer 3 via the inversion layer as the base current, a bipolar transistor composed of a p-type active base region 5a, an n-type storage region 4 / drift layer 3 / FS layer 2, and a p-type collector region 1 operates. When the IGBT is turned on in this way, in the ON state, current flows from the collector electrode 14 to the emitter electrode 13 via the collector region 1, FS layer 2, drift layer 3, storage layer 4, the inversion layer of the active base region 5a, and the emitter region 6. If the voltage applied to the gate electrode 11a is below the threshold, an inversion layer is not formed in the active base region 5a, and therefore no current flows from the collector electrode 14 to the emitter electrode 13.

[0021] In the IGBT according to this embodiment, the floating base region 5b is at a floating potential, and even in the ON state, no inversion layer is formed in the floating base region 5b in contact with the gate trench 9a. Furthermore, since the dummy electrode 11b of the dummy trench 9b is electrically connected to the emitter potential, no inversion layer is formed on the surface of the active base region 5a in contact with the side surface of the dummy trench 9b. Therefore, the channel density of the IGBT can be reduced, and hole extraction can be suppressed. Moreover, since an n-type storage layer 4 is provided below the p-type active base region 5a, the accumulation of holes in the drift layer 3 is promoted. As a result, the ON voltage can be reduced.

[0022] In the ON state of the IGBT according to this embodiment, as shown in Figure 4, the base separation region 5c in contact with the side surface of the dummy trench 9b and the drift layer 3 in contact with the bottom surface have extraction paths Hp on A is formed. Holes accumulated in the floating base region 5b are drawn through the extraction path Hp on It is drawn through to the low-resistance base connection region 7 of the active base region 5a. Also, when a negative voltage below the threshold voltage, for example -15V, is applied to the gate electrode 11a to turn it off, an inversion layer that becomes a p-type channel is formed on the surface of the base isolation region 5c in contact with the side surface of the gate trench 9a. Therefore, as shown in Figure 4, the extraction path Hp is drawn along the side surface of the gate trench 9a to the base isolation region 5c. off A structure is formed. As a result, the excess holes accumulating in the floating base region 5b are drawn through the extraction path Hp during turn-on. on It can be extracted via the extraction path Hp off It can be withdrawn via this. Thus, in the IGBT according to this embodiment, the potential change of the floating base region 5b can be suppressed and made gradual during the switching process, making it possible to easily control the voltage change dV / dt and prevent an increase in switching losses.

[0023] Furthermore, in the IGBT according to this embodiment, the gate-collector capacitance C can be adjusted by adjusting the distance between the active base region 5a and the floating base region 5b that sandwich the base separation region 5c. GC and C GE The value can be easily adjusted. Voltage change dV / dt can also be easily controlled, making it applicable to a wide range of applications. Furthermore, the IGBT according to this embodiment can achieve low switching loss under a wide range of fixed drive conditions, such as gate resistance in hard switching. Therefore, it can be used in a wide range of applications, such as when there are current capability limitations on the gate drive circuit while meeting noise specifications, or when only the IGBT of the power element needs to be replaced.

[0024] As an example, in the structure of the IGBT according to the embodiment, the impurity concentration of the storage layer 4 is set to 9 × 10 15 cm -3and 9×10 16 cm -3 The turn-on characteristics of each were evaluated. In addition, as Comparative Examples 1 and 2, IGBTs with the structures shown in Figures 5 and 6 were fabricated and their turn-on characteristics were evaluated. As shown in Figures 5 and 6, in Comparative Examples 1 and 2, the base layers (5a, 5b, 55) are provided on the upper surface of the storage layer 4. The p-type active base region 5a, the p-type floating base region 5b, and the p-type intermediate region 55 of the base layers (5a, 5b, 55) are defined by striped trenches (9a, 9b) and formed in a striped pattern. The active base region 5a is provided between the gate trenches 9a, and the emitter region 6 is provided separately in contact with the side walls of each of the opposing gate trenches 9a. The floating base region 5b is provided between the gate trench 9a and the dummy trench 9b. The intermediate region 55 is provided between the dummy trenches 9b. In Comparative Example 1, as shown in Figure 5, the emitter region 6, the active base region 5a, and the intermediate region 55 are each physically connected to the emitter electrode 13 through an opening in the interlayer insulating film 12, and the floating base region 5b is at a floating potential. On the other hand, as shown in Figure 6, in Comparative Example 2, in addition to the emitter region 6, the active base region 5a, and the intermediate region 55, the floating base region 5b is also physically connected to the emitter electrode 13 through an opening in the interlayer insulating film 12 and connected to the emitter potential.

[0025] Figure 7 shows the measurement circuit used to evaluate the turn-on characteristics of the IGBT. As shown in Figure 7, a freewheeling diode Di is connected in antiparallel to the transistor under test Tr. A pulse signal is applied to the gate electrode of the transistor under test Tr from the gate drive circuit via the gate resistor Rg. The transistors under test Tr used in the example, comparative example 1, and comparative example 2 were all manufactured in the same way, except for the arrangement of the surface region, including the area of ​​the active base region 5a and the area of ​​the floating base region 5b and the base isolation region 5c or intermediate region 55 in the minimum configuration unit, and their maximum ratings were also the same.

[0026] Figures 8 and 9 show the impurity concentration n of the storage layer 4. SC 9 x 10 15 cm -3In this case, the voltage change dV / dt of each transistor Tr measured in the example, comparative example 1, and comparative example 2. on and switching loss (E on +E rr ) and gate resistor Rg on This shows the relationship with switching loss (E on +E rr ) is the turn-on loss E of the transistor under test Tr. on and the reverse recovery loss E of the freewheeling diode Di rr It is expressed as the sum of the following, as shown in Figure 8: voltage change dV / dt on When driving while suppressing the voltage to 5kV / μs or less, the gate resistance Rg in Example and Comparative Example 2 on The gate resistance Rg should be approximately 16Ω or higher, as in Comparative Example 1. on The impedance must be in the range of approximately 8Ω or higher. Switching loss (E on +E rr ) is as shown in Figure 9, gate resistor Rg on In the range of approximately 16Ω or more, the example is smaller than Comparative Examples 1 and 2. In Comparative Examples 1 and 2, the gate resistance Rg on If the impedance is in the range of 8Ω to 12Ω, the switching loss (E on +E rr ) becomes smaller than in the example.

[0027] Figures 10 and 11 show the impurity concentration n in the storage layer 4. SC 9 x 10 16 cm -3 In this case, the voltage change dV / dt of each transistor Tr measured in the example, comparative example 1, and comparative example 2. on and switching loss (E on +E rr ) and gate resistor Rg on The relationship is shown in Figure 10, as shown in the voltage change dV / dt on When driving while suppressing the voltage to 5kV / μs or less, the gate resistance Rg in this example... on The gate resistance Rg should be approximately 16Ω or higher in Comparative Example 1 and Comparative Example 2. on The impedance must be in the range of approximately 10Ω or more. Switching loss (E on +E rr) is as shown in Figure 11, gate resistor Rg on In the range of approximately 16Ω or more, the example is smaller than Comparative Examples 1 and 2. In Comparative Examples 1 and 2, the gate resistance Rg on The voltage changes in dV / dt in the range of approximately 8Ω to 10Ω. on Although it will be greater than 5kV / μs, the switching loss (E on +E rr ) is smaller than in the example. As shown in Figures 8 to 11, in Comparative Example 1 and Comparative Example 2, the switching loss (E) is smaller than in the example. on +E rr ) can reduce the gate resistor Rg on The range decreases as the impurity concentration of the storage layer 4 increases. Thus, according to the structure of the IGBT according to the embodiment, a wide range of fixed gate resistance Rg on Switching loss (E on +E rr This makes it possible to reduce )

[0028] Figure 12 shows the impurity concentration n in the storage layer 4. SC 9 x 10 16 cm -3 For example, the gate resistor Rg on The turn-on waveforms of the example and comparative example 1 when the resistance is 16 ohms are shown. As shown in Figure 12, the gate voltage V of comparative example 1 GE The waveform shows a hump during the rising edge of the gate-emitter capacitance charge period. This hump is caused by the potential of the floating base region 5b shown in Figure 5. On the other hand, the gate voltage V of the embodiment GE In the waveform, the hump is suppressed, and the turn-on voltage change dV / dt on The switching speed increases, and the switching loss (E on +E rr ) can be reduced. Switching loss (E on +E rr The value was 20.8 mJ in the example and 27.1 mJ in Comparative Example 1.

[0029] Figure 13 shows the impurity concentration n in the storage layer 4. SC 9 x 10 16 cm -3As the voltage change dV / dt on shows the turn-on waveforms of the example and Comparative Example 1 when it is 5 kV / μs. The switching losses (E on + E rr ) were of the same degree, but the gate voltage change dV GE / dt of the example became lower. Thus, the gate drive circuit of the example can lower the requirement for the peak gate current compared with Comparative Example 1.

[0030] FIG. 14 shows the evaluation results of the example, Comparative Example 1, and Comparative Example 2 for the cases where the impurity concentration of the accumulation layer 4 is 9×10 16 cm -3 and 9×10 15 cm -3 . As shown in the table of FIG. 14, when the impurity concentration of the accumulation layer 4 is as low as 9×10 15 cm -3 , the on-voltage Von is 1.715 V for the example, 1.695 V and 1.836 V for Comparative Example 1 and Comparative Example 2, respectively. The switching losses (E on + E on + E rr ) at the same voltage change dV / dt of 5 kV / μs are 24.99 mJ / pulse for the example, 20.27 mJ / pulse and 26.95 mJ / pulse for Comparative Example 1 and Comparative Example 2, respectively. Both the on-voltage and the voltage change are intermediate values between the example and Comparative Example 1 and Comparative Example 2. When the impurity concentration of the accumulation layer 4 is 9×10 16 cm -3 , for the on-voltage Von, the example is 1.56 V, Comparative Example 1 and Comparative Example 2 are 1.513 V and 1.604 V, respectively, and the example is an intermediate value between Comparative Example 1 and Comparative Example 2. On the other hand, the switching losses (E on + E on + E rr ) at the same voltage change dV / dt of 5 kV / μs are 20.8 mJ / pulse for the example and 20.1 mJ / pulse for both Comparative Example 1 and Comparative Example 2, and the example is equivalent to Comparative Example 1 and Comparative Example 2. However, as shown in FIGS. 9, 11, and 12, at the same gate resistance Rg on , the switching losses (E on + Err The embodiment shows that the dimensions of the example are smaller than those of Comparative Examples 1 and 2. In the IGBT according to the embodiment, it is possible to reduce switching losses while suppressing the on-voltage.

[0031] As described above, both the emitter region 6 and the low-resistance base connection region 7, which are located above the active base region 5a, are in contact with the opposing sides of the gate trench 9a and the dummy trench 9b, respectively. However, the arrangement of the emitter region 6 and the low-resistance base connection region 7 is not limited. For example, as shown in Figure 15, in a plan view, the two emitter regions 6 may be arranged such that only one side of each is in contact with the side wall of the gate trench 9a, while the other sides are covered by the low-resistance base connection region 7, which is in contact with the respective sides of the gate trench 9a and the dummy trench 9b. In Figure 15, two emitter regions 6 are arranged in the low-resistance base connection region 7, but there may be three or more emitter regions 6, or there may be a single emitter region 6.

[0032] As shown in Figure 16, multiple dummy trenches 9b, for example two, may be arranged adjacent to each other between gate trenches 9a. The base layers (5b, 5d) between adjacent dummy trenches 9b comprise a p-type floating base region 5b and a p-type drawn base region 5d. The base isolation region 5c is an n-type semiconductor layer. In the stretching direction of the dummy trench 9b, drawn base regions 5d and floating base regions 5b are alternately provided via the base isolation region 5c. The active base region 5a between the gate trench 9a and the dummy trench 9b faces the floating base region 5b between the dummy trenches 9b. The floating base region 5b between the gate trench 9a and the dummy trench 9b faces the drawn base region 5d between the dummy trenches 9b. As shown in Figure 17, the drawn base region 5d is separated from the floating base region 5b by the base isolation region 5c. At the top of the pulled-out base region 5d, p is physically connected to the emitter electrode 13 through a contact hole opening in the interlayer insulating film 12. + A low-resistance base connection region 7 of the type is provided. In this way, the extraction base region 5d is connected to the emitter potential.

[0033] In the ON state of the IGBT according to this embodiment, as shown in Figure 16, the extraction path Hp is located in the base separation region 5c that is in contact with the side surface of the dummy trench 9b. on A hole is formed. Holes accumulated in the floating base region 5b between the gate trench 9a and the dummy trench 9b are drawn out through the extraction path Hp facing the gate trench 9b. on Holes are drawn through to the low-resistance base connection region 7 of the active base region 5a. Holes accumulated in the floating base region 5b between the dummy trenches 9b are drawn through the extraction path Hp facing the adjacent dummy trench 9b. on The extraction is performed through this path to the low-resistance base connection region 7 of the extraction base region 5d. Thus, the extraction path Hp is formed on the side of the dummy trench 9b. on As the density increases, the excess holes accumulating in the floating base region 5b are drawn into the extraction paths Hp on both sides of the dummy trench 9b. on It can be efficiently extracted via this route. Also, in the off state, the extraction path Hp is located on the side of the gate trench 9a. off This is formed. As a result, during the IGBT switching process, the potential change in the floating base region 5b can be suppressed and made gradual, making it easier to control the voltage change dV / dt and preventing an increase in switching losses.

[0034] Furthermore, as shown in Figure 18, multiple gate trenches 9a, for example two gate trenches 9a, may be arranged adjacent to each other between the dummy trenches. The floating base region 5b sandwiched between the adjacent gate trenches 9a faces the active base region 5a sandwiched between the gate trenches 9a and the dummy trenches 9b. The active base region 5a sandwiched between the adjacent gate trenches 9a faces the floating base region 5b sandwiched between the gate trenches 9a and the dummy trenches 9b. In the ON state of the IGBT, an extraction path Hp is located on the side of the dummy trench 9b. on In addition, in the off state, an extraction path Hp is formed on the side of the gate trench 9a. off A pulling path Hp is formed. off It is formed not only between the gate trench 9a and the dummy trench 9b, but also between the gate trench 9a, and the extraction path Hp offThe density increases. Therefore, holes remaining in the floating base region 5b in the off state are extracted via the extraction path Hp off This allows for efficient extraction. As a result, during the IGBT switching process, the potential change in the floating base region 5b can be suppressed and made gradual, making it easier to control the voltage change dV / dt and preventing an increase in switching losses.

[0035] (Other embodiments) Although the present invention has been described by the embodiments disclosed above, the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the invention. It should be assumed that various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0036] In the first and second embodiments described above, silicon (Si) was used as the semiconductor substrate material, but the semiconductor material is not limited and may be a wide-bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). Furthermore, it is not limited to a single IGBT, but may be a reverse-conducting IGBT integrated with a freewheeling diode.

[0037] As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined solely by the inventive features relating to the claims that are reasonable based on the above description. [Explanation of symbols]

[0038] 1 Collector area 2. Field Stop Layer (FS Layer) 3 Drift Layer 4 Accumulation layer (5a,5b) Base layer 5a Active base region 5b Floating base region 5c Base isolation region 5d Pull-out base area 6. Emitter region 7. Low-resistance base connection area 9a Gate Trench 9b Dummy Trench 10a gate insulating film 10b Dummy insulating film 11a Terminal 11b Dummy electrode 12 Interlayer insulating film 13. Emitter electrode 14 Collector electrode

Claims

1. A first conductive drift layer, A first conductivity type storage layer is provided on the upper surface of the drift layer and has a higher impurity concentration than the drift layer, A base layer provided on the upper surface of the aforementioned storage layer, A gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer via a gate insulating film, A dummy electrode is embedded inside a stripe-shaped dummy trench that penetrates the base layer and the storage layer, via a dummy insulating film, An emitter region of a first conductivity type having a higher impurity concentration than the drift layer is provided above the base layer, Equipped with, The base layer comprises a second conductivity type active base region having the emitter region at its upper part and connected to the emitter potential, a second conductivity type floating base region set to a floating potential, and a first conductivity type base separation region separating the active base region and the floating base region. In a mesa where the gate trench and the dummy trench are adjacent, the active base region and the floating base region are alternately arranged in the extending direction of the gate trench, with the base separation region in between. The active base region faces other floating base regions across a trench which is the gate trench or the dummy trench, The floating base region faces the other active base region across the trench. An insulated gate bipolar transistor characterized by the following features.

2. The insulated gate bipolar transistor according to claim 1, characterized in that the active base region faces the other floating base region across the trench which is the dummy trench.

3. The insulated-gate bipolar transistor according to claim 1, characterized in that the active base region faces the other floating base region across the trench, which is the gate trench.

4. A first conductive drift layer, A first conductivity type storage layer is provided on the upper surface of the drift layer and has a higher impurity concentration than the drift layer, A base layer provided on the upper surface of the aforementioned storage layer, A gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer via a gate insulating film, A dummy electrode is embedded inside a stripe-shaped dummy trench that penetrates the base layer and the storage layer, via a dummy insulating film, An emitter region of a first conductivity type having a higher impurity concentration than the drift layer is provided above the base layer, Equipped with, The base layer comprises a second conductivity type active base region having the emitter region at its upper part and connected to the emitter potential, a second conductivity type floating base region set to a floating potential, and a first conductivity type base separation region separating the active base region and the floating base region. In a mesa where the gate trench and the dummy trench are adjacent, the active base region and the floating base region are alternately arranged in the extending direction of the gate trench, with the base separation region in between. An insulated gate bipolar transistor characterized in that the impurity concentration of the base isolation region is greater than or equal to the impurity concentration of the drift layer and less than or equal to the impurity concentration of the storage layer.

5. The impurity concentration in the base separation region is 1 × 10 １６ cm －３ The above 1 x 10 １７ cm －３ The insulated gate type bipolar transistor according to claim 4, characterized in that it is as follows.

6. A first conductive drift layer, A first conductivity type storage layer is provided on the upper surface of the drift layer and has a higher impurity concentration than the drift layer, A base layer provided on the upper surface of the aforementioned storage layer, A gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer via a gate insulating film, A dummy electrode is embedded inside a stripe-shaped dummy trench that penetrates the base layer and the storage layer, via a dummy insulating film, An emitter region of a first conductivity type having a higher impurity concentration than the drift layer is provided above the base layer, Equipped with, The base layer comprises a second conductivity type active base region having the emitter region at its upper part and connected to the emitter potential, a second conductivity type floating base region set to a floating potential, and a first conductivity type base separation region separating the active base region and the floating base region. In a mesa where the gate trench and the dummy trench are adjacent, the active base region and the floating base region are alternately arranged in the extending direction of the gate trench, with the base separation region in between. The base layer further comprises a second conductivity type extraction base region connected to the emitter potential and lacking the emitter region, In a mesa where the dummy trenches are adjacent to each other, the insulated gate bipolar transistor is characterized in that the drawn-out base region and the floating base region are alternately arranged in the direction of extension of the dummy trenches, with the base isolation region in between.

7. An insulated gate bipolar transistor according to any one of claims 1 to 6, characterized in that the emitter region and a low-resistance base connection region of a second conductivity type having a higher impurity concentration than the active base region are selectively provided in contact with each other above the active base region.

8. The insulated gate bipolar transistor according to claim 7, characterized in that both the emitter region and the low-resistance base connection region are in contact with the dummy trench and the gate trench.

9. In a plan view, the emitter region has only one side in contact with the gate trench. The insulated-gate bipolar transistor according to claim 7, characterized in that the low-resistance base connection region is in contact with the dummy trench and the gate trench so as to cover the other side of the emitter region.

10. The insulated gate bipolar transistor according to claim 7, characterized in that, in the extension direction of the gate trench, the low-resistance base connection region is positioned closer to the base isolation region than to the emitter region.

11. In the other mesa portion provided with the other active base region, the other active base region and the other floating base region are alternately arranged in the direction of extension of the trench, via other base isolation regions, as described in Claim 1.

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