Semiconductor device and method for manufacturing a semiconductor device

Abstract

This semiconductor device comprises: a semiconductor chip; a metal block that has a first surface and a second surface that is on the reverse side from the first surface, the first surface being bonded to the semiconductor chip by means of a bonding material; and a lead electrode that is bonded to the second surface of the metal block. The surface of the lead electrode that is on the reverse side from the surface that is bonded to the metal block has a plurality of recesses / protrusions.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a structure in a semiconductor device in which a pad portion and a conductive spacer are joined. The joining of the pad portion and the spacer is performed, for example, by ultrasonic bonding or the like.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device such as a power semiconductor device, a semiconductor chip may be joined to a wiring member such as a lead electrode. As a method of joining a lead electrode and a semiconductor chip, for example, there is a method of discharging molten metal onto one main surface of the semiconductor chip. Further, there is a method in which a joining material and a lead electrode are arranged on a semiconductor chip pre-joined to a circuit pattern on an insulating substrate and reflowed. In such a method of joining a lead electrode and a semiconductor chip, the joining area is larger than a method of forming a circuit by joining a metal wire and a semiconductor chip. Therefore, an increase in current and an extension of life are expected.

[0005] However, the above method requires heating the entire semiconductor device during the process of joining the lead electrodes to the top surface of the semiconductor chip. This may cause the bonding material at the joint between the pre-bonded semiconductor chip and the insulating substrate to remelt. In this case, re-inspection of the joint on the back of the semiconductor chip may be necessary. Furthermore, when solder is used as the bonding material between the back of the semiconductor chip and the insulating substrate, there is a problem in that the back electrodes of the semiconductor chip diffuse into the solder, reducing the bonding strength.

[0006] On the other hand, to avoid the above-mentioned problems, it is conceivable to join the semiconductor chip and the lead electrode by applying ultrasonic vibrations, that is, to use ultrasonic bonding. However, there is a problem in that if the top surface of the semiconductor chip is used as the part to be joined by ultrasonic bonding, the semiconductor chip may be damaged, making ultrasonic bonding unsuitable.

[0007] This disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress damage to semiconductor chips during ultrasonic bonding. [Means for solving the problem]

[0008] The semiconductor device according to this disclosure comprises a semiconductor chip, a metal block having a first surface and a second surface opposite to the first surface, the first surface of which is bonded to the semiconductor chip with a bonding material, and a lead electrode bonded to the second surface of the metal block, wherein a plurality of irregularities are formed on the surface of the lead electrode opposite to the surface bonded to the metal block, and recesses are formed on the surface of the lead electrode opposite to the surface bonded to the metal block, and the plurality of irregularities are formed on the bottom surface of the recesses. The semiconductor device according to this disclosure comprises a semiconductor chip, a metal block having a first surface and a second surface opposite to the first surface, the first surface of which is bonded to the semiconductor chip with a bonding material, and a lead electrode bonded to the second surface of the metal block, wherein a plurality of irregularities are formed on the surface of the lead electrode opposite to the surface bonded to the metal block, and the metal block has an aluminum layer bonded to the lead electrode and a copper layer bonded to the semiconductor chip.

[0009] A method for manufacturing a semiconductor device according to this disclosure involves joining a semiconductor chip and the first surface of a metal block having a first surface and a second surface opposite to the first surface with a bonding material, and then ultrasonic vibration is applied from the surface of the lead electrode opposite to the metal block to ultrasonically bond the second surface of the metal block and the lead electrode. A recess is formed on the side of the lead electrode opposite to the side joined to the metal block, and the ultrasonic bonding mark of the ultrasonic bonding is formed on the bottom surface of the recess. ru. [Effects of the Invention]

[0010] In the semiconductor device and method for manufacturing the semiconductor device described herein, damage to the semiconductor chip during ultrasonic bonding can be suppressed by ultrasonic bonding between the metal block and the lead electrode. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of the semiconductor device according to Embodiment 1. [Figure 2] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 3] This is a diagram illustrating another example of ultrasonic bonding marks. [Figure 4] This is a cross-sectional view of the semiconductor device according to Embodiment 2. [Figure 5] This is a cross-sectional view of the semiconductor device according to Embodiment 3. [Figure 6] This is a cross-sectional view of the semiconductor device according to Embodiment 4. [Figure 7] This is a cross-sectional view of the semiconductor device according to Embodiment 5. [Modes for carrying out the invention]

[0012] Semiconductor devices and methods for manufacturing semiconductor devices according to each embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repetition of the description may be omitted.

[0013] Embodiment 1. Figure 1 is a cross-sectional view of the semiconductor device 100 according to Embodiment 1. Figure 2 is a plan view of the semiconductor device 100 according to Embodiment 1. Figure 1 shows a typical configuration of the junctions of the semiconductor chip 20, metal block 24, and lead electrodes of the semiconductor device 100. Note that the semiconductor device 100 is simplified in Figure 1, and for example, wires which are signal lines electrically connected to the semiconductor chip 20, signal terminals, etc., are omitted.

[0014] The semiconductor device 100 is, for example, a power semiconductor device. In the semiconductor device 100, a case 10 is provided on a base plate 12. The base plate 12 is made of a material with excellent thermal conductivity, such as aluminum alloy or copper. An insulating substrate 14 is joined to the area of ​​the upper surface of the base plate 12 surrounded by the case 10 by a bonding material such as solder or soft solder. The insulating substrate 14 has an insulating layer made of a ceramic or resin with excellent thermal conductivity, such as aluminum nitride or silicon nitride, and circuit patterns 16 provided on both sides of the insulating layer. The circuit patterns 16 are made of aluminum alloy, copper, etc. Figure 1 shows the circuit patterns 16 provided on the upper surface of the insulating layer of the insulating substrate 14.

[0015] The semiconductor chip 20 has a substrate, an electrode 20a provided on the upper surface of the substrate, and an electrode 20b provided on the lower surface of the substrate. The electrode 20b of the semiconductor chip 20 is joined to the circuit pattern 16 using a joining material 18. The joining material 18 is, for example, solder, soft solder, or the like. The semiconductor chip 20 is, for example, an IGBT, diode, reverse-conducting IGBT, etc. made of a silicon (Si) material. The semiconductor chip 20 may also be a MOSFET or Schottky diode formed of a material having a larger bandgap than Si, such as silicon carbide (SiC) or gallium nitride (GaN). The number of semiconductor chips 20 on the insulating substrate 14 is not limited. Depending on the application of the semiconductor device 100, the necessary number or type of semiconductor chips 20 may be mounted.

[0016] The metal block 24 has a first surface and a second surface opposite to the first surface. The first surface is joined to the electrode 20a of the semiconductor chip 20 with a joining material 22. The joining material 22 is solder, soft solder, or the like. The metal block 24 is formed of a metal having excellent thermal conductivity and a low electrical resistance value, such as copper or aluminum. Not limited to this, the metal block 24 may be any metal having desired properties.

[0017] The lower surface of the lead electrode 26 formed of metal is joined to the second surface of the metal block 24. The joining of the lead electrode 26 and the metal block 24 is ultrasonic bonding. The metal block 24 and the lead electrode 26 are joined without an intervening joining material. A plurality of irregularities 50 are formed on the surface of the lead electrode 26 opposite to the surface joined to the metal block 24. The plurality of irregularities 50 are ultrasonic bonding marks. The plurality of irregularities 50 are formed at positions that overlap the metal block 24 in a plan view within the lead electrode 26.

[0018] The ultrasonic bonding mark is also called an ultrasonic vibration application mark. The shapes of the plurality of concavities and convexities 50 that are ultrasonic bonding marks differ depending on the tip shape and vibration direction of the ultrasonic vibration tool 60. For example, by applying a reciprocating vibration in a single direction to the upper surface of the lead electrode 26, as shown in FIG. 2, an applied mark in which parallel concavities and convexities are continuous can be formed as the plurality of concavities and convexities 50. Also, depending on the tip shape of the ultrasonic vibration tool 60, a plurality of square pyramids may be continuously formed as the plurality of concavities and convexities 50. FIG. 3 is a diagram for explaining another example of the ultrasonic bonding mark. In the example of FIG. 3, the plurality of concavities and convexities 50a are arranged in two directions. The plurality of concavities and convexities 50a are formed, for example, in a range of 4 mm × 8 mm. The width of each concavity and convexity included in the plurality of concavities and convexities 50a is, for example, about 0.1 mm to 10 mm.

[0019] A plurality of metal blocks 24 may be joined to one semiconductor chip 20. The ultrasonic bonding marks are formed in a number corresponding to the number of metal blocks 24. In the example of FIG. 2, two metal blocks 24 are joined to one semiconductor chip 20.

[0020] The lead electrode 26 may be formed by extending an external electrode 28 pre-inserted into the case 10 up to the semiconductor chip 20. The lead electrode 26 may be joined to the external electrode 28 provided in the case 10 in advance by soldering, laser welding, ultrasonic bonding, or the like. Also, a part of the lead electrode 26 may be connected to the circuit pattern 16 by ultrasonic bonding, soldering, laser welding, or the like to form a circuit. Also, one lead electrode 26 may be joined across a plurality of metal blocks 24 on a plurality of semiconductor chips 20.

[0021] Next, the assembly procedure for the semiconductor device 100 in this embodiment is shown below. First, the circuit pattern 16 of the insulating substrate 14 and the semiconductor chip 20, and the semiconductor chip 20 and the first surface of the metal block 24 are joined using bonding materials 18 and 22 such as solder, solder paste, or soft solder. In the joining process, the bonding materials 18 and 22 are first mounted on the circuit pattern 16 and on the semiconductor chip 20. Generally, solder is often used as the bonding material 18 and 22. The bonding material 18 and 22, such as solder paste, may be mounted by screen printing or applied using a dispenser. Next, the semiconductor device 100 is heated to a temperature exceeding the melting point of the bonding materials 18 and 22 to perform the joining.

[0022] The metal block 24 and the semiconductor chip 20 may be joined simultaneously in the process of joining the semiconductor chip 20 to the circuit pattern 16. Alternatively, the semiconductor chip 20 and the metal block 24 may be joined after the semiconductor chip 20 has been joined to the circuit pattern 16. In this case, the bonding material 22 may be placed on the semiconductor chip 20 by screen printing or dispensing, the metal block 24 may be placed on the bonding material 22, and then the bonding material 22 may be locally heated by laser heating or hot air heating to complete the joining. This can prevent the bonding material 18 from melting again.

[0023] Next, the case 10 is joined to the base plate 12. In this step, first, a silicone-based or epoxy-based adhesive is applied to the joining surface of the case 10 to the base plate 12. Then, the case 10 is fitted into the base plate 12 to which the semiconductor chip 20 and insulating substrate 14 are joined, and a load is applied to the case 10 to make the case 10 and the base plate 12 tightly bonded. The case 10 and the base plate 12 may be fastened together with tapping screws or the like. Alternatively, the adhesive may be heated and solidified while the case 10 and the base plate 12 are fixed with a clamping jig or the like.

[0024] Next, the lead electrode 26 is placed on the second surface of the metal block 24. Then, as shown in Figure 1, ultrasonic vibration is applied from the side of the lead electrode 26 opposite to the metal block 24 to ultrasonically bond the second surface of the metal block 24 and the lead electrode 26. The lead electrode 26 is pressed by an ultrasonic vibration tool 60 from the side opposite to the side in contact with the metal block 24. By applying ultrasonic vibration while being pressed with a constant load, the lead electrode 26 and the metal block 24 are bonded together.

[0025] Next, in order to form a signal circuit for controlling the semiconductor chip 20, control electrodes on the semiconductor chip 20 and external signal terminals are connected by wire using ultrasonic bonding. Generally, aluminum or other materials with high thermal and electrical conductivity are often used for the wire.

[0026] Next, the case 10 is sealed with a sealing resin. Silicone gel or epoxy resin is often used as the sealing resin. However, any resin with the desired physical properties such as elastic modulus, heat resistance, adhesion, and coefficient of thermal expansion can be used as the sealing resin. Next, the semiconductor device 100 is placed in a curing furnace or the like to cure the sealing resin, and the necessary curing is performed to complete the shape of the semiconductor device 100. After that, electrical characteristics and other tests are performed, and the semiconductor device 100 is completed.

[0027] In this embodiment, a metal block 24 is placed between the semiconductor chip 20 and the lead electrode 26. By ultrasonically bonding the metal block 24 and the lead electrode 26, damage to the semiconductor chip 20 during ultrasonic bonding can be suppressed. In other words, since the upper surface of the semiconductor chip 20 does not become the bonding area for ultrasonic bonding, damage to the semiconductor chip 20 can be suppressed even when ultrasonic vibrations are applied while applying pressure to the lead electrode 26. As a result, in this embodiment, ultrasonic bonding can be applied when forming a circuit between the lead electrode 26 and the semiconductor chip 20, and it is not necessary to heat the entire semiconductor device 100. Therefore, remelting of the bonding area between the pre-bonded semiconductor chip 20 and the insulating substrate 14 can be suppressed. Consequently, re-inspection of the bonding area on the back surface of the semiconductor chip 20 can be avoided, and the semiconductor device 100 can be manufactured at a low cost. In addition, a decrease in bonding strength on the back surface of the semiconductor chip 20 can be suppressed.

[0028] As described above, the semiconductor chip 20 may be formed from a wide-bandgap semiconductor. Wide-bandgap semiconductors include, for example, silicon carbide, gallium nitride-based materials, or diamond. According to this embodiment, even when the semiconductor chip 20 is formed from a wide-bandgap semiconductor and a high current flows through it, a decrease in junction strength can be suppressed, and a decrease in the reliability of the semiconductor device 100 can be suppressed.

[0029] The modifications described above can be appropriately applied to the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments. Since the semiconductor device and method for manufacturing the semiconductor device according to the following embodiments have many similarities with Embodiment 1, the differences from Embodiment 1 will be the focus of this explanation.

[0030] Embodiment 2. Figure 4 is a cross-sectional view of the semiconductor device 200 according to Embodiment 2. The structure of the metal block 224 and the lead electrode 226 of the semiconductor device 100 of Embodiment 1 differs from that of the semiconductor device 100 of Embodiment 1. Other configurations are the same as those of Embodiment 1. A mating portion for mating with the lead electrode 226 is formed on the second surface of the metal block 224. Specifically, a convex portion 224a is formed on the second surface of the metal block 224, and a concave portion 226a is formed on the lower surface of the lead electrode 226. With the convex portion 224a of the metal block 224 fitted into the concave portion 226a of the lead electrode 226, the metal block 224 and the lead electrode 226 are ultrasonically bonded. As a result, the flat upper surface of the convex portion 224a of the metal block 224 and the flat bottom of the concave portion 226a of the lead electrode 226 are ultrasonically bonded.

[0031] In this embodiment, the metal block 224 and the lead electrode 226 are fitted together, making it easy to position the lead electrode 226 horizontally even if the lead electrode 226 is not fixed before joining. Furthermore, the horizontal positioning accuracy of the lead electrode 226 can be improved, enabling the stable manufacture of the semiconductor device 200.

[0032] Furthermore, the shapes of the protrusions 224a and recesses 226a are not limited as long as the metal block 224 and the lead electrode 226 can be fitted together. Alternatively, the recess may be formed in the metal block 224 and the protrusion may be formed in the lead electrode 226.

[0033] Embodiment 3. Figure 5 is a cross-sectional view of the semiconductor device 300 according to Embodiment 3. The semiconductor device 300 differs from the semiconductor device 100 of Embodiment 1 in the structure of the lead electrode 326. The other configurations are the same as those of Embodiment 1. A recess 327 is formed on the surface of the lead electrode 326 opposite to the surface joined to the metal block 24. Multiple irregularities 50, which are ultrasonic bonding marks, are formed on the bottom surface of the recess 327.

[0034] In this embodiment, since a recess 327 is formed on the upper surface of the lead electrode 326, the scattering of metal debris generated when ultrasonically bonding the lead electrode 26 and the metal block 24 can be suppressed. Therefore, the semiconductor device 300 can be manufactured stably. It is preferable that the depth of the recess 327 is greater than the maximum depth of the multiple irregularities 50. This enhances the effect of suppressing the scattering of metal debris. The maximum depth of the multiple irregularities 50 is, for example, 0.5 mm to 0.8 mm.

[0035] Furthermore, the width of the recess 327 may be wider than the width of the region of the lead electrode 326 that is in contact with the metal block 24. The area of ​​the recess 327 may also be wider than the area of ​​the region of the lead electrode 326 that is in contact with the metal block 24. This ensures that sufficient area of ​​the ultrasonic bonding portion is secured even when the recess 327 is formed.

[0036] Embodiment 4. Figure 6 is a cross-sectional view of a semiconductor device 400 according to Embodiment 4. The structure of the metal block 424 of the semiconductor device 400 differs from that of the semiconductor device 100 of Embodiment 1. The other configurations are the same as those of Embodiment 1. The metal block 424 has a copper layer 424a bonded to the semiconductor chip 20 with a bonding material 22, and an aluminum layer 424b ultrasonically bonded to the lead electrode 26. The metal block 424 is a clad material formed, for example, by applying pressure to the surfaces of a copper material and an aluminum material and rolling them together.

[0037] In this embodiment, the presence of a soft aluminum layer 424b on a portion of the metal block 424 mitigates damage to the semiconductor chip 20 caused by ultrasonic vibrations during ultrasonic bonding of the lead electrode 26 and the metal block 424. On the other hand, aluminum is less likely to form intermetallic compounds with bonding materials 22 such as solder. The presence of a copper layer 424a on the surface to be bonded with the semiconductor chip 20 and the bonding material 22 allows for easy bonding of the semiconductor chip 20 and the metal block 424. Therefore, the semiconductor device 400 can be manufactured stably. Note that the metal block 424 only needs to have a copper layer 424a and an aluminum layer 424b. For example, another metal layer may be provided between the copper layer 424a and the aluminum layer 424b.

[0038] Embodiment 5. Figure 7 shows an embodiment. 5 This is a cross-sectional view of the semiconductor device 500. The thickness b of the metal block 524 of the semiconductor device 500 is greater than or equal to the thickness of the portion of the lead electrode 26 that is joined to the metal block 524. The other configurations are the same as those of Embodiment 1. For example, if the thickness of the lead electrode 26 is 0.6 mm, then the thickness b of the metal block 524 is 0.6 mm or more. In this embodiment, in the process of ultrasonically bonding the lead electrode 26 and the metal block 524, there is a metal block 524 that is thicker than the lead electrode 26 between the semiconductor chip 20 and the lead electrode 26. This further suppresses damage to the semiconductor chip 20 when ultrasonic vibration is applied to the lead electrode 26 while applying pressure. Therefore, the semiconductor device 500 can be manufactured stably.

[0039] The technical features described in each embodiment may be used in combination as appropriate. [Explanation of symbols]

[0040] 10 Case, 12 Base plate, 14 Insulating substrate, 16 Circuit pattern, 18 Bonding material, 20 Semiconductor chip, 20a, 20b Electrodes, 22 Bonding material, 24 Metal block, 26 Lead electrode, 28 External electrode, 50, 50a Concave and concave, 60 Ultrasonic vibration tool, 100, 200 Semiconductor device, 224 Metal block, 224a Convex part, 226 Lead electrode, 226a Concave, 300 Semiconductor device, 326 Lead electrode, 327 Concave, 400 Semiconductor device, 424 Metal block, 424a Copper layer, 424b Aluminum layer, 500 Semiconductor device, 524 Metal block

Claims

1. Semiconductor chips and A metal block having a first surface and a second surface opposite to the first surface, wherein the first surface is joined to the semiconductor chip with a bonding material, A lead electrode joined to the second surface of the metal block, Equipped with, Multiple irregularities are formed on the surface of the lead electrode opposite to the surface joined to the metal block. A recess is formed on the surface of the lead electrode opposite to the surface joined to the metal block. The semiconductor device is characterized in that the plurality of irregularities are formed on the bottom surface of the recesses.

2. The semiconductor device according to claim 1, characterized in that the width of the recess is wider than the width of the region of the lead electrode that is in contact with the metal block.

3. The semiconductor device according to claim 1, characterized in that the depth of the recess is greater than the maximum depth of the plurality of irregularities.

4. Semiconductor chips and A metal block having a first surface and a second surface opposite to the first surface, wherein the first surface is joined to the semiconductor chip with a bonding material, A lead electrode joined to the second surface of the metal block, Equipped with, Multiple irregularities are formed on the surface of the lead electrode opposite to the surface joined to the metal block. The semiconductor device is characterized in that the metal block has an aluminum layer bonded to the lead electrode and a copper layer bonded to the semiconductor chip.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that the thickness of the metal block is equal to or greater than the thickness of the portion of the lead electrode that is joined to the metal block.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that the semiconductor chip is formed of a wide-bandgap semiconductor.

7. The semiconductor device according to claim 6, characterized in that the wide bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that a fitting portion for fitting with the lead electrode is formed on the second surface of the metal block.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that the plurality of irregularities are ultrasonic bonding marks.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that the metal block and the lead electrode are joined without an intervening bonding material.

11. After joining a semiconductor chip and the first surface of a metal block having a first surface and a second surface opposite to the first surface with a bonding material, ultrasonic vibration is applied from the side of the lead electrode opposite to the metal block to ultrasonically bond the second surface of the metal block and the lead electrode. A recess is formed on the surface of the lead electrode opposite to the surface joined to the metal block. A method for manufacturing a semiconductor device, characterized in that the ultrasonic bonding marks of the ultrasonic bonding are formed on the bottom surface of the recess.

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