Multi-gate transistors and switches for transceivers.

Abstract

Multiple gate electrodes (8a, 8b, 8c) are formed on a semiconductor layer (2,3) between the source electrode (5) and the drain electrode (6). An insulating film (9a, 9b) covers the semiconductor layer (2,3) and the multiple gate electrodes (8a, 8b, 8c). Each of the multiple gate electrodes (8a, 8b, 8c) has an overhang on the source side and a drain side. The source-side overhang of the gate electrode (8a) closest to the source electrode (5) and the drain-side overhang of the gate electrode (8c) closest to the drain electrode (6) are designated as the first overhang (10a). The overhangs other than the first overhang (10a) are designated as the second overhang (10b). A cavity (11) exists between the second overhang (10b) and the semiconductor layer (2,3) because the insulating film (9a, 9b) does not completely fill the space. The space between the first overhang portion (10a) and the semiconductor layers (2,3) is filled with insulating film (9a,9b), so there is no cavity (11).

Description

[Technical Field]

[0001] This disclosure relates to a multi-gate transistor and a switch for a transceiver. [Background technology]

[0002] In typical communication transceivers, a switch composed of a FET or HEMT, which is a voltage-controlled device capable of high-speed switching, is used to switch between transmission and reception paths. To suppress signal quality degradation when passing through the switch, it is required that signal leakage in the off-state path is small and signal loss in the on-state path is small. Furthermore, transceivers for mobile base stations and radar applications may require high allowable transmission power characteristics of around 10 to 50W.

[0003] To minimize signal degradation (insertion loss) during signal passage, it is necessary to reduce the attenuation due to parasitic resistance Ron within the transistor when it is switched on, and to reduce signal leakage through the drain-source capacitance Coff of the transistor when it is switched off (increase isolation).

[0004] In a transistor with a fixed structure, increasing the gate width reduces Ron, and decreasing the gate width reduces Coff. Thus, Ron and Coff have a trade-off relationship, and Ron × Coff, which is an indicator of switch performance, is determined by the transistor structure. A transistor structure that can reduce Ron × Coff is advantageous for switches used in transceivers.

[0005] Allowable transmit power refers to the input power at which the insertion loss of a switch begins to increase when the input power to the switch is increased. To increase the allowable transmit power, it is necessary to suppress power leakage in the switch transistor in the off state for the desired large input power. This power leakage occurs because, as the input power increases, the voltage amplitude between the gate and source or gate and drain of the switch transistor gradually increases, and eventually the maximum value of these voltage amplitudes exceeds the transistor's threshold voltage, or the minimum value of the voltage amplitude exceeds the breakdown voltage, causing the transistor to transition from the off state to the on state. To suppress leakage, it is effective to set the switch control voltage so that the potential difference between the gate and source or gate and drain is large within a range that is not affected by the breakdown voltage. Therefore, communication equipment that outputs high power (around 10 to 50 W) employs switches using GaN devices, which can be expected to have high allowable transmit power due to their high voltage resistance characteristics.

[0006] However, when the switch for a transceiver with an output of 10-50W is configured with a single-stage GaN device SW arm, a large negative voltage of several tens of volts is required as the gate control voltage Vc. When this negative voltage is applied to the gate from the SW arm's control terminal through a high resistance (>1kΩ) with the voltages at both ends of the SW arm, i.e., source and drain, set to 0V, the reverse bias gate leakage current flowing from drain to gate or from source to gate is larger compared to a GaAs switch. The gate leakage current tends to increase as the reverse bias voltage increases. Therefore, this gate leakage current flowing through the high resistance can cause the voltage at the gate terminal to rise, or if the current suction capability (maximum current that the circuit can absorb) of the CMOS control circuit that outputs the high-resistance control voltage Vc is smaller than the leakage current flowing from the gate terminal of the GaN switch to the output terminal of the control circuit, the output voltage of the control circuit will rise due to the incoming current.

[0007] CMOS control circuits that output tens of volts require a special process that includes high-voltage elements with a voltage rating of tens of volts or more, making it impossible to apply inexpensive general-purpose processes. Furthermore, high-voltage elements increase the size of the elements, thus increasing the chip area of ​​the CMOS control circuit. To increase the current-sinking capacity, it is necessary to increase the size of the Nch MOSFET elements and lower the resistance of the FETs, which further increases the area and consequently the cost.

[0008] To improve the allowable transmission power while reducing the negative voltage applied to the SW arm's control terminal, a widely used technique involves stacking multiple transistors vertically to create a multi-stage configuration for the SW arm, which is in the off state during transmission. Since the cooldown (Coff) of each transistor in the multi-stage configuration is connected in series, the overall Coff of the multi-stage configuration becomes smaller, and isolation can also be increased. To suppress the increase in chip area associated with multi-stage configuration, multi-gate transistors such as dual-gate, triple-gate, and quad-gate transistors are widely used.

[0009] Increasing the number of transistors stacked vertically improves the allowable transmit power while lowering the control voltage during the off state, but it increases the on-resistance by the number of stacked transistors, leading to a problem of increased insertion loss. To address this, a structure has been proposed in which capacitance is provided between the gate and source and between the gate and drain at both ends of the multi-gate structure transistor (see, for example, Patent Document 1). This capacitance allows sufficient allowable transmit power characteristics to be obtained even at low control voltages. Therefore, the desired allowable transmit power can be obtained with fewer stacked transistors for the same control voltage, thus suppressing the decrease in insertion loss. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2007-73815 [Overview of the project] [Problems that the invention aims to solve]

[0011] In conventional multi-gate transistors, each gate is T-shaped, and the underside of the overhang portion of all T-shaped gates is embedded with an insulating film, resulting in parasitic capacitance. Because the parasitic capacitance between the gate and source and between the gate and drain of all gates becomes large, the drain-source capacitance Coff of the transistor in the OFF state also becomes large. As a result, there was a problem of poor isolation characteristics.

[0012] This disclosure was made to solve the problems described above, and its purpose is to provide a transistor and a switch for a transceiver that can improve isolation characteristics while obtaining sufficient allowable transmit power characteristics. [Means for solving the problem]

[0013] The multigate transistor according to this disclosure comprises a semiconductor layer, a source electrode and a drain electrode formed on the semiconductor layer, a plurality of gate electrodes formed on the semiconductor layer between the source electrode and the drain electrode, and an insulating film covering the semiconductor layer, the source electrode, the drain electrode, and the plurality of gate electrodes, wherein each of the plurality of gate electrodes has an overhang on the source side and a drain side, the overhang on the source side of the gate electrode closest to the source electrode and the overhang on the drain side of the gate electrode closest to the drain electrode are designated as a first overhang, and the overhangs other than the first overhang are designated as a second overhang, the space between the second overhang and the semiconductor layer is not completely filled by the insulating film and a cavity exists, and the space between the first overhang and the semiconductor layer is filled by the insulating film and no cavity exists. [Effects of the Invention]

[0014] In the present disclosure, the eaves portion on the source side of the gate electrode closest to the source electrode and the eaves portion on the drain side of the gate electrode closest to the drain electrode are defined as the first eaves portion, and the eaves portion other than the first eaves portion is defined as the second eaves portion. There is a cavity between the second eaves portion and the semiconductor layer and it is not completely filled with an insulating film, while there is no cavity between the first eaves portion and the semiconductor layer as it is filled with an insulating film. As a result, isolation characteristics can be improved while obtaining sufficient allowable transmission power characteristics.

Brief Description of the Drawings

[0015] [Figure 1] It is a diagram showing a transceiver according to Embodiment 1. [Figure 2] It is a diagram showing a switch for a transceiver according to Embodiment 1. [Figure 3] It is a diagram showing a modified example of the switch for a transceiver according to Embodiment 1. [Figure 4] It is a cross-sectional view showing a multi-gate transistor according to Embodiment 1. [Figure 5] It is a diagram for explaining the operation of the multi-gate transistor. [Figure 6] It is a diagram showing a multi-gate transistor and a CMOS control circuit according to Embodiment 1. [Figure 7] It is a cross-sectional view showing a transistor and a CMOS control circuit according to Comparative Example 1. [Figure 8] It is a cross-sectional view showing a multi-gate transistor according to Comparative Example 2. [Figure 9] It is a diagram showing isolation according to the presence or absence of a cavity. [Figure 10] It is a cross-sectional view showing a multi-gate transistor according to Embodiment 2. [Figure 11] It is a cross-sectional view showing a multi-gate transistor according to Embodiment 3. [Figure 12] It is a cross-sectional view showing a multi-gate transistor according to Embodiment 4.

Modes for Carrying Out the Invention

[0016] A multi-gate transistor and a switch for a transceiver according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repetition of the description may be omitted.

[0017] Embodiment 1 Figure 1 shows a transceiver according to Embodiment 1. The transmitting amplifier TX amplifies the signal TXin and outputs the signal TXout. The receiving amplifier RX amplifies the signal RXin input from the antenna ANT and outputs the signal RXout. The switch SW is an SPDT (Single-Pole Double-Throw) switch with three terminals (P1, P2, P3), and either the transmitting amplifier TX or the receiving amplifier RX is connected to the antenna ANT. The signal TXout is transmitted from the antenna ANT via the switch SW and the bandpass filter BPF.

[0018] Figure 2 shows a switch for a transceiver according to Embodiment 1. A transistor Tra, which constitutes the series arm of the transmitting side, is connected between terminal P1 and terminal P2, to which the signal TXout from the transmitting amplifier TX is input. A transistor Trb, which constitutes the series arm of the receiving side, is connected between terminal P1 and terminal P3. A transistor Trc, which constitutes the parallel arm of the transmitting side, is connected between the ground point and terminal P2. A transistor Trd, which constitutes the parallel arm of the receiving side, is connected between the ground point and terminal P3. Terminals P1 and ANT, terminal P2 and transmitting amplifier TX, and terminal P3 and receiving amplifier RX are DC isolated by a series capacitance (not shown). The bias voltages of the source and drain terminals of transistors Tra, Trb, Trc, and Trd are set to 0V because they are connected to the ground point via a high-resistance element (>1kΩ) connected between the drain and source of each transistor. A control voltage V is applied to the control terminals of transistors Trb and Trc. RX A voltage is applied, and through a resistor, a bias voltage is supplied to the gate terminal of each transistor. Control terminals of transistors Tra,Trd V TX The control voltage V C1A voltage is applied. For example, if transistors Tra, Trb, Trc, and Trd are normally-on type, then during transmission, the control terminal V TX A voltage (V) approximately equal to the drain voltage and source voltage. C1 Apply 0V to turn on transistors Tra and Trd, and the control terminal V RX This includes a negative voltage V below the transistor threshold voltage Vth. C2 Apply the voltage to set transistors Trb and Trc to the off state. Note that in Figure 2, one of the parallel arms is connected to ground, but it is not limited to ground and can be set to any power supply voltage (Vd). In that case, the drain voltage and source voltage of each arm will be Vd, and Vd should be applied to the control terminal of the transistor to be turned on, and the control voltage should be set so that the potential difference between the gate and source and the gate and drain of the control terminal to be turned off is less than or equal to the threshold voltage Vth.

[0019] To achieve a high allowable transmit power of approximately 1 to 50W, the key factors in the path from the transmitting amplifier TX to the antenna ANT, i.e., the path from terminal P2 to terminal P1, are the current tolerance of the series-arm transistor Tra in the ON state and the power level at which the parallel-arm transistor Trc can maintain its OFF state. At the same time, in the path from the antenna ANT to the receiving amplifier RX, i.e., the path from terminal P1 to terminal P3, the key factor is the power level at which the series-arm transistor Trb can maintain its OFF state to prevent power leakage to the receiving side. Therefore, multi-gate transistors (described later) with feedforward capacitance Cff connected to both ends are applied to the series-arm transistor Trb on the receiving side and the parallel-arm transistor Trc on the transmitting side.

[0020] Figure 3 shows a modified example of the transceiver switch according to Embodiment 1. The parallel arm transistors Trc and Trd are omitted. Typically, a parallel arm is provided to improve isolation, but if the desired isolation characteristics for the switch can be achieved with the isolation of the series arm, a configuration without a parallel arm may be adopted. In this case, a multi-gate transistor (described later) with feedforward capacitors Cff connected to both ends is applied to the series arm transistor Trb on the receiving side.

[0021] Figure 4 is a cross-sectional view showing a multi-gate transistor according to Embodiment 1. A buffer layer 2 and a barrier layer 3 are sequentially stacked on a substrate 1 as semiconductor layers. The substrate 1 is made of SiC or Si, but may also be sapphire or GaN. In the case of a GaN HEMT, the buffer layer 2 is generally made of GaN and the barrier layer 3 is made of AlGaN. However, if the substrate 1 is Si, the buffer layer 2 may be an AlGaN / GaN superlattice. A two-dimensional electron gas is generated at the interface between the buffer layer 2 and the barrier layer 3.

[0022] n-type ohmic contact layers 4a and 4b are formed by injecting silicon into a portion of the buffer layer 2 and barrier layer 3. A source electrode 5 and a drain electrode 6 are formed on the ohmic contact layers 4a and 4b, respectively. Wiring electrodes 7a and 7b are formed on the source electrode 5 and drain electrode 6, respectively. The source electrode 5 and drain electrode 6 are made of TiAl. The wiring electrodes 7a and 7b are made of Ti / Au.

[0023] Three gate electrodes 8a, 8b, and 8c are formed on the barrier layer 3 between the source electrode 5 and the drain electrode 6. The gate electrodes 8a, 8b, and 8c are constructed by laminating Au on top of a metal with a low work function, such as Pd, Pt, or Ni, to reduce resistance.

[0024] The surfaces of the barrier layer 3 and the gate electrodes 8a, 8b, and 8c are covered with insulating films 9a and 9b. The insulating films 9a and 9b are made of SiNx, but may also be SiOx or Al2O3. Note that while Si3N4 is a typical silicon nitride film and SiO2 is a typical silicon oxide film, SiNx and SiOx may also have different composition ratios.

[0025] Each of the gate electrodes 8a, 8b, and 8c has a Y-shaped branch at the top of the gate, with a thin central tip in contact with the barrier layer 3 and overhangs extending from that tip towards the source and drain sides, respectively. The source-side overhang of gate electrode 8a closest to the source electrode 5 and the drain-side overhang of gate electrode 8c closest to the drain electrode 6 are designated as the first overhang portion 10a. The overhang portions other than the first overhang portion 10a are designated as the second overhang portion 10b.

[0026] The lower overhang length Xa of the first eaves portion 10a, which branches in a Y-shape from the narrow gate end in the center of the portion in contact with the barrier layer 3, is shorter than the lower overhang length Xb of the second eaves portion 10b. Since Xb / Yb > 1 for the distance Yb ​​from the surface of the barrier layer 3 to the lower end of the second eaves portion 10b, insulating films 9a and 9b are less likely to be deposited between the second eaves portion 10b and the substrate 1, and a cavity 11 is formed. On the other hand, the distance Ya between the lower end of the first eaves portion 10a and the surface of the barrier layer 3 is Xa / Ya < 1, the space between the eaves 10a and the barrier layer 3 is easily filled with insulating films 9a and 9b, and Ya is about the same as the combined thickness of the insulating films 9a and 9b deposited on the barrier layer 3 and the insulating films 9a and 9b deposited on the gate electrode surface, so no cavity 11 exists. As a result, a portion of the feedforward capacitance Cff is formed between the first overhang portion 10a and the ohmic contact layer 4a via the parasitic capacitance generated between the first overhang portion 10a and the barrier layer 3. Similarly, a portion of the feedforward capacitance Cff is formed between the first overhang portion 10a and the ohmic contact layer 4b. Furthermore, the spaces between the first overhang portion 10a and the source electrode 5 or drain electrode 6, and between the first overhang portion 10a and a portion of the wiring electrode 7a or 7b are filled with insulating films 9a and 9b, thereby forming the entire Cff together with a portion of the aforementioned Cff.

[0027] Figure 5 is a diagram illustrating the operation of a multi-gate transistor. The operation of a multi-gate transistor with three gate electrodes 8a, 8b, and 8c can be explained by a switch arm formed by stacking three transistors Tr1, Tr2, and Tr3 vertically. These three transistors are assumed to have the same structure and dimensions, and their gate-source capacitance Cgs and gate-drain capacitance Cgd are the same for all of them. Consider the case where the input signal frequency is high and the gate-source capacitance Cgs and gate-drain capacitance Cgd of each transistor cannot be ignored. The drain-source voltage of the multi-gate transistor is distributed equally among the three vertically stacked transistors Tr1, Tr2, and Tr3.

[0028] In the case of a symmetric gate transistor, since capacitances Cgs and Cgd are the same, a voltage Vgi = Vc ± Vdm / (2 × 3) is generated at the gate. Vc is the control voltage, and Vdm is the voltage amplitude at the node where transistor Tr1 is connected to terminal P1 via a series arm. During transmission, if the maximum value of this voltage Vgi exceeds the transistor's threshold voltage Vth, the transistor switches from OFF to ON, and the signal input to switch SW from terminal P2 leaks to the ground terminal via transistors Tr1, Tr2, and Tr3, causing a sharp decrease in the transmitted power output from antenna ANT. Similarly, if the minimum value of voltage Vgi falls below the breakdown voltage, the transistor switches from OFF to ON, causing a sharp decrease in the transmitted power output from antenna.

[0029] Typically, the control voltage Vc is set sufficiently high relative to the breakdown voltage to prevent component failure. In this case, the maximum value of the voltage Vgi is determined by the potential difference between the control voltage Vc and the threshold voltage Vth, and the allowable transmit power Po is Po = 2 × [3 × (Vc - Vth)]. 2 The result is / Zo. Vth is the threshold voltage of transistors Tr1, Tr2, and Tr3, respectively. Zo is the characteristic impedance of the transmission line 13 connected between the antenna ANT and terminal P1 of the switch SW.

[0030] Since the feed-forward capacitances Cff are formed at both ends of the multi-gate transistor of this embodiment, the transistors Tr1 and Tr3 at both ends have asymmetric gates. For a GaN transistor with a symmetric gate, Cgs and Cgd per 1 mm of the total gate width are about several hundred fF / mm. The Cff of this embodiment is about 100 fF / mm per 1 mm of the total gate width when the overhang length Xa under the first eaves portion 10a is 0.8 μm, the distance Ya between the end under the first eaves portion 10a and the surface of the barrier layer 3 is 1 μm, and the insulating films 9a and 9b are made of Si3N4 with a dielectric constant of 7.8. The gate-source capacitance of transistor Tr3 is Cgs + Cff > Cgd, and the gate-source impedance is smaller than the gate-drain impedance. Therefore, the voltage generated between the gate and source of Tr3 by the RF current flowing through these capacitances is Vgi < Vc ± Vdm / (2×3). Similarly, the gate-drain capacitance of transistor Tr1 is Cgd + Cff > Cgs, and the gate-drain impedance is smaller than the gate-source impedance. Therefore, the voltage generated between the gate and drain of Tr1 by the RF current flowing through these capacitances is Vgi < Vc ± Vdm / (2×3). If the transistors Tr1 and Tr3 at both ends are in the OFF state, the signal cannot pass through. Therefore, a larger allowable transmission power can be obtained compared to the case where there is no feed-forward capacitance Cff for the same control voltage Vc.

[0031] FIG. 6 is a diagram showing a multi-gate transistor and a CMOS control circuit according to Embodiment 1. Feed-forward capacitances Cff are provided at both ends of the multi-gate transistor Trm of Embodiment 1. The CMOS control circuit 14 supplies an output voltage high level V OH (≈0 V) to the gate of the multi-gate transistor Trm during reception, that is, when the parallel transistors are on, and supplies an output voltage low level V OL (≈control voltage Vc below Vth) during transmission, that is, when the parallel transistors are off. The CMOS control circuit 14 has a CMOSFET composed of an NchMOSFET and a PchMOSFET. The output voltage is VOL The amount of current (sink current) that an NchMosefFET can absorb at that time is called its current sink capacity.

[0032] Next, the effects of this embodiment will be explained in comparison with Comparative Examples 1 and 2. Figure 7 is a cross-sectional view showing the transistor and CMOS control circuit according to Comparative Example 1. The single-gate transistor Trs of Comparative Example 1 does not have a feedforward capacitance Cff. The output voltage of the CMOS control circuit 14 is V OL At this time, the drain-gate or source-gate gate leakage current of the single-gate transistor Trs is transmitted from the output terminal Vo of the CMOS control circuit 14 through the Nch MOSFET to a negative voltage V ss It flows towards the power supply. The gate leakage current causes the control terminal V of the SW arm. RX A potential difference is generated across the high resistance (>1kΩ) connected between the gate of transistor Trs, so the potential at the gate terminal is the control terminal V RX The voltage supplied to the device becomes higher than the current drawn in. Furthermore, if the incoming leakage current increases beyond the current suction capacity of the CMOS control circuit 14, the output voltage V of the CMOS control circuit 14 will be affected by the resistance of the ON-state NchMOSFET. OL The voltage increases significantly. In order to supply the desired bias voltage to the gate terminal of Trs from the CMOS control circuit 14, the negative voltage V of the CMOS control circuit 14 increases by the amount that the leakage current increases and the output voltage rises. ss Lower V OL The output voltage level needs to be lowered to the negative side. In the case of the single gate in Comparative Example 1, in order to achieve the allowable transmit power of 50W (=47dBm), the negative voltage V ss Because the voltage needs to be lowered below -40V, transistors with a voltage rating of 40V or higher must be used as NchMOSFETs and PchMOSFETs. This requires a special process, and inexpensive general-purpose processes cannot be applied. In addition, high-voltage elements have larger dimensions, which increases the chip area of ​​the CMOS control circuit.

[0033] In the case of a single gate without feedforward capacitance, as in Comparative Example 1, the allowable transmit power is approximately 43 dBm (≒20 W) at a control voltage of -40 V. With a quintuple gate, an allowable transmit power of 47 dBm or more can be achieved even at a control voltage of -10 V. In contrast, by adding feedforward capacitance Cff as in this embodiment, an allowable transmit power of 47 dBm or more can be achieved even with a triple gate at a control voltage of -10 V. Therefore, when selecting a process for the CMOS control circuit, it is not necessary to require transistor options with high voltage resistance of several tens of volts, and a relatively low-cost process can be used. Furthermore, since the feedforward capacitance is formed under the overhang of the gate electrode, a separate process for forming a parallel plate capacitance as feedforward capacitance is unnecessary. In addition, since the desired allowable transmit power can be obtained with a small number of gate electrodes stacked vertically, the decrease in insertion loss can be suppressed.

[0034] Figure 8 is a cross-sectional view showing a multi-gate transistor according to Comparative Example 2. In Comparative Example 2, each gate electrode 8a, 8b, and 8c is T-shaped. Therefore, the underside of the overhang portion of all gate electrodes 8a, 8b, and 8c is embedded by insulating films 9a and 9b, resulting in parasitic capacitance. As the gate-source parasitic capacitance and gate-drain parasitic capacitance of all gates become large, the drain-source capacitance Coff of the transistor in the switched-off state also becomes large. As a result, the isolation characteristics deteriorate.

[0035] In contrast, in this embodiment, there is a cavity 11 between the second overhang portion 10b and the barrier layer 3. Therefore, the parasitic capacitance between the second overhang portion and the barrier layer is reduced, and the gate-source capacitance Cgs and gate-drain capacitance Cgd become smaller, thus reducing the drain-source capacitance Coff of the transistor in the OFF state. As a result, the isolation characteristics of the SW arm in the OFF state at the same operating frequency are improved.

[0036] Figure 9 shows the isolation depending on the presence or absence of a cavity. It can be seen that when there is a cavity 11 between the second overhang portion 10b and the barrier layer 3, the isolation is improved compared to when there is no cavity 11.

[0037] Furthermore, the space between the first overhang portion 10a and the barrier layer 3 is filled with insulating films 9a and 9b, so there is no cavity 11. Consequently, feedforward capacitance Cff is generated at both ends of the multi-gate structure transistor, between the gate and source and between the gate and drain. This feedforward capacitance Cff allows for sufficient allowable transmit power characteristics to be obtained even at low control voltages. Therefore, the desired allowable transmit power can be obtained with a small number of gate electrodes stacked vertically for the same control voltage, thus suppressing a decrease in insertion loss.

[0038] Furthermore, the cross-sectional shape of each of the gate electrodes 8a, 8b, and 8c is Y-shaped. This makes it easier for a cavity 11 to form between the overhang portion of the gate electrodes 8a, 8b, and 8c and the barrier layer 3. As a result, the capacities Cgs and Cgd can be reduced.

[0039] Furthermore, insulating films 9a and 9b are difficult to deposit under the overhang portion of a T-type gate electrode, and even if they are deposited, they do not form a very good film, which causes problems in ensuring the uniformity and reliability of capacitances Cgs and Cgd. In contrast, insulating films 9a and 9b can be deposited under the overhang portion of a Y-type gate electrode using ALD or the like with almost the same film thickness depending on the gate shape.

[0040] Furthermore, in the case of a T-type gate electrode, the length of the overhang portions at both ends of the multi-gate is made longer than the other overhang portions to create a difference from the parasitic capacitance of the other overhang portions. In contrast, in the case of a Y-type gate electrode, a cavity 11 is easily formed below the overhang portion. Therefore, the first overhang portion 10a at both ends of the multi-gate is made shorter than the second overhang portion 10b to make it easier to fill with insulating films 9a and 9b. By adjusting the length of the overhang portions in this way, it is possible to form capacitance at both ends of the multi-gate while forming a cavity 11 below the second overhang portion 10b and reducing the capacitance.

[0041] Furthermore, when an external feedforward capacitance is connected to the end of the gate electrode, the impedance between the gate and source or gate and drain will differ between the part near the capacitance and the part far from it due to the effects of parasitic inductance and parasitic resistance. In contrast, in this embodiment, a feedforward capacitance Cff is formed on the overhang portion of the gate electrode, so even if the gate width is long, the impedance between the gate and source or gate and drain appears to be the same at any position on the gate electrode, thus providing a uniform effect.

[0042] In this embodiment, a triple-gate transistor having three gate electrodes 8a, 8b, and 8c was used, but the same effect can be obtained with other multi-gate structures such as dual-gate, quadruple-gate, and quintuple-gate transistors.

[0043] Furthermore, although this embodiment uses an SPDT switch with one transmit port and one receive port as an example, similar effects can be achieved with one or more transmit ports or two or more receive ports. In addition, although a GaN transistor was used in this embodiment, similar effects can be achieved using a GaAs MESFET.

[0044] Embodiment 2 Figure 10 is a cross-sectional view showing a multi-gate transistor according to Embodiment 2. The insulating film 9c is embedded between the first overhang portion 10a and the barrier layer 3. The insulating film 9c is formed before the gate electrodes 8a, 8b, and 8c are formed. By adjusting the dielectric constant and thickness of the insulating film 9c, the capacitance value of the feedforward capacitance Cff can be set to a desired value. It is preferable that the dielectric constant of the insulating film 9c is higher than the dielectric constant of the insulating films 9a and 9b that cover the parts other than the area between the first overhang portion 10a and the barrier layer 3. For example, when Ta2O5 is used for the insulating film 9c, the relative dielectric constant is about 20 to 25, and the capacitance of the feedforward capacitance Cff can be increased by about three times compared to Si3N4 with a dielectric constant of 7.8. Other configurations and effects are the same as in Embodiment 1.

[0045] Embodiment 3 Figure 11 is a cross-sectional view showing a multi-gate transistor according to Embodiment 3. The height of the second overhang portion 10b from the barrier layer 3 is greater than the height of the first overhang portion 10a. The distance Yb ​​between the lower side of the upper electrode protruding from the adjacent gate electrode side of the second overhang portion and the barrier layer 3 is greater than the combined thickness of the insulating films 9a and 9b deposited on the barrier layer 3 and the insulating films 9a and 9b deposited on the gate electrode surface. As a result, a cavity 11 is formed between the second overhang portion and the barrier layer 3 without being filled with insulating films 9a and 9b, thus reducing parasitic capacitance and decreasing Cgs and Cgd, and further reducing the drain-source capacitance Coff of the multi-gate transistor Trm. Other configurations and effects are the same as in Embodiment 1.

[0046] Embodiment 4 Figure 12 is a cross-sectional view showing a multi-gate transistor according to Embodiment 4. The length of the second overhang portion 10b is longer than in Embodiment 1. As a result, the insulating films 9a and 9b covering the second overhang portion 10b of adjacent gate electrodes 8a, 8b, and 8c are connected. Therefore, the amount of insulating film 9a and 9b that enters between the second overhang portion 10b and the barrier layer 3 is reduced, which widens the cavity 11 and further reduces parasitic capacitance. The other configurations and effects are the same as in Embodiment 1. [Explanation of Symbols]

[0047] 1 Substrate, 2 Buffer layer, 3 Barrier layer, 4a,4b Ohmic contact layers, 5 Source electrode, 6 Drain electrode, 8a,8b,8c Guard gate, 9a,9b,9c Insulating film, 10a First overhang, 10b Second overhang, 11 Cavity, ANT Antenna, RX Receiver amplifier, Tra,Trb,Trc,Trd Transistors, Trm Multi-gate transistor, TX Transmitter amplifier

Claims

1. Semiconductor layer, Source electrode and drain electrode formed on the semiconductor layer, A plurality of gate electrodes formed on the semiconductor layer between the source electrode and the drain electrode, The semiconductor layer and the insulating film covering the plurality of gate electrodes are provided, Each of the aforementioned plurality of gate electrodes has an overhang portion on the source side and the drain side, The source-side overhang portion of the gate electrode closest to the source electrode and the drain-side overhang portion of the gate electrode closest to the drain electrode are designated as the first overhang portion. The portion of the awning other than the first awning portion is designated as the second awning portion. A cavity exists between the second overhang portion and the semiconductor layer. A multi-gate transistor characterized in that the space between the first overhang portion and the semiconductor layer is filled with the insulating film, so that no void exists.

2. Each of the aforementioned plurality of gate electrodes has a Y-shaped cross-sectional shape. The multi-gate transistor according to claim 1, characterized in that the first overhang portion is shorter than the second overhang portion.

3. The insulating film comprises a first insulating film embedded between the first overhang portion and the semiconductor layer, and a second insulating film covering the portion other than the space between the first overhang portion and the semiconductor layer. The multi-gate transistor according to claim 1 or 2, characterized in that the dielectric constant of the first insulating film is higher than the dielectric constant of the second insulating film.

4. The multi-gate transistor according to claim 1 or 2, characterized in that the height of the second overhang portion from the semiconductor layer is greater than the height of the first overhang portion.

5. The multi-gate transistor according to claim 1 or 2, characterized in that the insulating film covering the second overhang portion of an adjacent gate electrode is connected.

6. A transistor in the series arm on the transmitting side, connected between the antenna and the transmitting amplifier, The antenna and the receiving amplifier are connected to a series arm transistor on the receiving side, A switch for a transceiver, characterized in that the multi-gate transistor described in claim 1 or 2 is used as the transistor of the series arm on the receiving side.

7. A transistor in the transmitting side's parallel arm, connected between the ground point and the transmitting amplifier, The system further comprises a transistor of a parallel arm on the receiving side connected between the ground point and the receiving amplifier, The switch for a transceiver according to claim 6, characterized in that the multi-gate transistor is used as the transistor of the parallel arm on the transmitting side.

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