Package structure for low-capacity TVS

Abstract

To provide a package structure for a low-capacity transient-voltage-suppression (TVS) device.SOLUTION: A package structure 100 comprises a first lead frame 102 including a die pad 108 and a chip stack 110 coupled to the first lead frame 102. The chip stack 110 includes a transient-voltage- suppression (TVS) device 114 coupled to the die pad 108, a conductive wafer 116 that is a solder wafer coupled to the TVS device 114, and a glass passivation palette (GPP) device 118 coupled to the conductive wafer 116.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor devices, and more particularly, to a package structure for low-capacitance transient voltage suppression (TVS) devices.

Background Art

[0002] Packaging of integrated circuits is usually the final step in semiconductor device manufacturing. During packaging, a semiconductor die representing the core of the semiconductor device is placed into a housing that protects the die from physical damage and corrosion. For example, semiconductor dies are generally mounted on a copper substrate using solder alloy reflow, conductive epoxy, etc. The mounted semiconductor die is then often encapsulated within a plastic or epoxy compound.

[0003] As the power requirements of semiconductor devices increase, there is a need for larger semiconductor dies, sometimes referred to as "large area semiconductor dies," to provide correspondingly higher current handling levels. In some cases, such as for TVS diode applications, multiple large area dies must be connected in series in a stacked configuration to provide a sufficiently high breakdown voltage. However, ever-larger semiconductor dies, such as those used in surface mount c-type (SMC) packages, have too large a solder-void ratio. The present disclosure is provided at least in part to address this drawback.

Summary of the Invention

[0004] This summary is provided to introduce selected concepts in a simplified form and these concepts are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is this summary intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] In some embodiments, the package structure may include a first lead frame containing a die pad and a chip stack coupled to the first lead frame. The chip stack may include a transient voltage suppression (TVS) device coupled to the die pad, a conductive wafer coupled to the TVS device, and a glass passivation pallet (GPP) device coupled to the conductive wafer.

[0006] In some embodiments, the semiconductor package may comprise a first lead frame including die pads, and a chip stack coupled to the first lead frame, the chip stack including a solder wafer sandwiched between a transient voltage suppression (TVS) chip and a glass passivation pallet (GPP) chip.

[0007] In some embodiments, a method for forming a package structure may include the steps of providing a first lead frame including a die pad, and coupling a chip stack to the first lead frame. The chip stack may include a transient voltage suppression (TVS) device coupled to the die pad, a solder wafer coupled to the TVS device, and a glass passivation pallet (GPP) device coupled to the solder wafer. [Brief explanation of the drawing]

[0008] The attached drawings illustrate an exemplary approach of this disclosure, including a practical application of the principles of this disclosure, as shown below.

[0009] [Figure 1] This is a side view of a semiconductor package according to an embodiment of the present disclosure.

[0010] [Figure 2] This is a top view of the first lead frame of a semiconductor package according to an embodiment of the present disclosure.

[0011] [Figure 3]This is a side view of the first lead frame of a semiconductor package according to an embodiment of the present disclosure.

[0012] [Figure 4] This is a top view of a clip of a semiconductor package according to an embodiment of the present disclosure.

[0013] [Figure 5] This is a side view of a clip of a semiconductor package according to an embodiment of the present disclosure.

[0014] [Figure 6] This is a top view of a glass passivation process (GPP) chip of a semiconductor package according to an embodiment of this disclosure.

[0015] [Figure 7] This is a side view of a GPP chip in a semiconductor package according to an embodiment of the present disclosure.

[0016] [Figure 8] This is a flowchart of the method according to the embodiment of this disclosure.

[0017] The drawings are not necessarily to scale. The drawings are for illustrative purposes only and are not intended to depict any specific parameter of the disclosure. The drawings are intended to illustrate a typical embodiment of the disclosure and should therefore not be considered limiting. In the drawings, similar reference numerals represent similar elements.

[0018] Furthermore, certain elements in parts of the figures may be omitted for clarity of explanation, or may not be shown to scale. Sectional views may be in the form of “slice” or “close-up” sections, and certain background lines that would be visible in a “true” section may be omitted for clarity of explanation. In addition, some reference numerals may be omitted in certain drawings for clarity. [Modes for carrying out the invention]

[0019] Here, the devices, packages, and methods according to the present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the systems and methods are shown. However, the devices, packages, and methods may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the devices, packages, and methods to those skilled in the art.

[0020] One recent development direction regarding power semiconductor discrete packaging is faster recovery capability. To improve this capability, embodiments of the present disclosure are directed to low-capacity and high-power TVS SMC products manufactured in-line. More specifically, the package structure of the present disclosure reduces the electrical capacitance value of the chip by using a glass passivation process (GPP) chip. GPP chips have relatively low capacitance values and high reliability characteristics. To avoid the solder-void ratio problem inherent in larger SMC packages, embodiments of the present disclosure include a stack structure in which the first chip is a GPP chip and the second chip is a planar transient voltage suppression (TVS) chip. The third chip may be a solder wafer sandwiched between the first chip and the second chip. By replacing the solder paste with a solder wafer, the void region of the stack can be eliminated.

[0021] In some embodiments, the package structure may include a lead frame with grooved pads, thereby increasing the solder retention rate. Further, the package structure may include improved clips for increased heat dissipation and faster recovery capability.

[0022] Referring to FIG. 1, an exemplary embodiment of a semiconductor device or package structure 100 according to the present disclosure is shown. The exemplary package structure (hereinafter, "structure") 100 may include a first lead frame 102 and a second lead frame 104. The first lead frame 102 may have a first end 105 and a second end 106. Although not shown, the first end 105 may be coupled to a substrate, a PCB, etc. The second end 106 may include a die pad 108 that is coupled to a chip stack 110 by solder 112. In other embodiments, the die pad 108 is attached to the chip stack 110 using conductive epoxy or another suitable material. Although not limiting, the first lead frame 102 and the second lead frame 104 may be made of a conductive material (e.g., copper, copper alloy, silver, etc.) and may be configured to provide an electrical connection between the die pad 108 and a circuit to which the structure 100 will be connected.

[0023] In some embodiments, the chip stack 110 may include a TVS device / chip 114 coupled to the die pad 108, a conductive wafer 116 coupled to the TVS device 114, and a glass passivation pallet (GPP) device 118 coupled to the conductive wafer 116. In some embodiments, the conductive wafer 116 is a solder wafer. As shown, the GPP device 118 may be coupled to a clip 120 by solder 122. The clip 120 may be coupled to the second lead frame 104 by solder 124. In some embodiments, the clip 120 is a conductive material (e.g., copper, copper alloy, silver, etc.) that provides a direct electrical path between the substrate, the die pad 108, and the first lead frame 102 and the second lead frame 104. Further shown, the structure 100 may include a encapsulation 128 (e.g., an epoxy compound) that surrounds the chip stack 110 and the clip 120. In some embodiments, the first lead frame 102 and the second lead frame 104 may extend outside the encapsulation 128.

[0024] Herein, with reference to Figures 2 and 3, a first lead frame 102 according to an embodiment of the present disclosure will be described in more detail. As shown, the second end 106 of the first lead frame 102, including the first surface 132 opposite the second surface 134, may be generally planar. A die pad 108 is bonded to the first surface 132. In some embodiments, the die pad 108 may include one or more grooves 136. As shown, each groove 136 includes a pair of walls 140 defining a U-shaped or V-shaped cross-sectional profile. The grooves 136 allow solder 112 to enter, thereby improving the adhesion between the chip stack 110 and the die pad 108 during thermal cycling. Furthermore, the grooves 136 reduce stress accumulation during thermal cycling. Although two grooves 136 are shown in a window frame configuration, it should be understood that the number and configuration of the grooves 136 are not limiting. As further shown, the first lead frame 102 may include a locking hole 138 and a pair of corner notches 139, which provide flexibility to the first lead frame 102.

[0025] The clip 120 according to an embodiment of the present disclosure will now be described in more detail with reference to Figures 4 and 5. As shown, the clip 120 may include a first contact area 142 at a first end 143 and a second contact area 144 at a second end 145. In some embodiments, the first contact area 142 is generally planar to increase contact with the GPP device 118. The second contact area 144 may extend generally perpendicular to the first contact area 142. The second contact area 144 may be electrically connected to a second lead frame 104. As further shown, the clip 120 may further include a pair of clip gates 146 on both sides.

[0026] The GPP device 118 according to an embodiment of this disclosure will now be described in more detail with reference to Figures 6 and 7. As shown, the GPP device 118 may comprise a passivation layer 150, which may be a chip glass region, and a mesa region 152. A dicing region 156 surrounds the mesa region 152. In an exemplary embodiment, the passivation layer 150 may be electrically connected to a clip 120 by solder 122 (not shown).

[0027] With reference to Figure 8, a method 200 for forming a package structure according to an embodiment of the present disclosure is described. In block 201, the method 200 may include a step of providing a first lead frame including a die pad. In block 202, the method 200 may include a step of coupling a chip stack to the first lead frame, wherein the chip stack includes a TVS device coupled to the die pad, a solder wafer coupled to the TVS device, and a GPP device coupled to the solder wafer.

[0028] In some embodiments, in block 203, method 200 may optionally include the steps of coupling a clip to a GPP device and connecting a second lead frame to the clip. In some embodiments, the method may include the step of providing a coating (e.g., epoxy) around the chip stack and the clip, wherein the first and second lead frames extend outside the coating. In some embodiments, the method may include the step of providing a first solder between the TVS device and the die pad, wherein the first solder extends into the grooves of the die pad. In some embodiments, the method may include the steps of connecting a first contact area of ​​the clip to the GPP device by a second solder and connecting a second contact area of ​​the clip to the second lead frame by a third solder.

[0029] Although exemplary Method 100 is described above as a series of actions or events, the Disclosure is not limited by the shown ordering of such actions or events unless otherwise specified. For example, some actions may, according to the Disclosure, be performed in a different order and / or concurrently with other actions or events, apart from those illustrated and / or described herein. Furthermore, not all described actions or events may be necessary to implement the method relating to the Disclosure. In addition, Method 100 may be implemented in relation to the formation and / or processing of structures illustrated and described herein, as well as in relation to other structures not illustrated.

[0030] When used herein, an element or step described in the singular and beginning with the word "a" or "an" shall not be understood to exclude multiple elements or steps unless explicitly stated otherwise. Furthermore, any reference to "one embodiment" in this disclosure is not intended to be construed as excluding the existence of additional embodiments that further incorporate the described features.

[0031] The use of “including,” “comprising,” or “having” and their variations herein means that they encompass the items listed thereafter, their equivalents, and any additional items. Therefore, the terms “including,” “comprising,” or “having” and their variations are open-ended and may be used interchangeably herein.

[0032] As used herein, the phrases “at least one,” “one or more,” and “and / or” are open-ended expressions and can be both conjunctive and disjunctive in use. For example, the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” and “A, B, and / or C” mean A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0033] References to all directions (e.g., proximal, distal, upper, lower, upward, downward, left, right, transverse, longitudinal, front, back, apex, bottom, upward, downward, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used solely for identification purposes to aid the reader's understanding of this disclosure. References to directions do not impose limitations, in particular, on the location, orientation, or use of this disclosure. References to connections (e.g., attachment, joining, connection, and joint) should be interpreted broadly and, unless otherwise indicated, may include intermediate members between sets of elements and relative movement between elements. Accordingly, references to connections do not necessarily imply that two elements are directly connected to each other and in a fixed relationship.

[0034] Furthermore, the identification terms (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority, but are used to distinguish one feature from another. The drawings are for illustrative purposes only, and the dimensions, locations, order, and relative sizes reflected in the drawings accompanying this specification may vary.

[0035] Furthermore, the terms “substantial” or “effectively” and “approximately” can be used interchangeably in some embodiments and may be described using any relative scale acceptable to those skilled in the art. For example, these terms can serve as a comparison to a baseline parameter to indicate a deviation that can provide the intended function. Although not restrictive, deviations from the baseline parameter may be, for example, less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.

[0036] The foregoing description of exemplary embodiments is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosure to the exact forms disclosed. Many variations and modifications are possible in view of the disclosure. The scope of the disclosure is intended to be limited not by this detailed description, but rather by the claims appended to this specification. Future applications claiming priority to this application may claim the disclosed subject matter in different modes and may generally include any set of one or more limitations disclosed or otherwise demonstrated herein.

Claims

1. A first lead frame including a die pad, A chip stack coupled to the first lead frame, wherein the chip stack is A transient voltage suppression (TVS) device coupled to the die pad, A conductive wafer coupled to the TVS device, A glass passivation process (GPP) device directly bonded to the TVS device using a solder layer, wherein the GPP device extends throughout the entire TVS device, and The clip attached to the GPP device, The second lead frame connected to the clip and Including a chip stack, Equipped with, The aforementioned clip is A first contact area connected to the GPP device, The second contact region connected to the second lead frame and Includes, The first contact area has a first width, The package structure wherein the clip extends to a second width greater than the first width between the first contact area and the second contact area.

2. The aforementioned clip is A set of clip gates positioned between the first contact area and the second contact area to expand the width of the clip. The package structure according to claim 1, further comprising:

3. The package structure according to claim 1, further comprising a covering that surrounds the chip stack and the clip, wherein the first lead frame and the second lead frame extend to the outside of the covering.

4. The package structure according to claim 1 or 3, further comprising a first solder between the TVS device and the die pad.

5. The package structure according to claim 4, wherein the die pad includes a groove, and the first solder extends within the groove.

6. The package structure according to claim 5, wherein the groove includes a set of walls defining a U-shaped or V-shaped contour.

7. The package structure according to any one of claims 4 to 6, wherein the clip includes a first contact area and a second contact area, the first contact area being connected to the GPP device by a second solder, and the second contact area being connected to the second lead frame by a third solder.

8. The package structure according to any one of claims 1 to 7, wherein the conductive wafer is sandwiched between the TVS device and the GPP device.

9. A first lead frame including a die pad, A chip stack coupled to the first lead frame, the chip stack includes a solder wafer sandwiched between a transient voltage suppression (TVS) chip and a glass passivation process (GPP) chip, the GPP chip being directly bonded to the TVS chip using the solder wafer and extending across the entire TVS chip, The clip attached to the GPP chip, The second lead frame connected to the clip and Equipped with, The aforementioned clip is A first contact area connected to the GPP chip, The second contact region connected to the second lead frame and Includes, The first contact area has a first width, The clip extends to a second width greater than the first width between the first contact area and the second contact area. Semiconductor package.

10. The semiconductor package according to claim 9, wherein the TVS chip is bonded to the die pad by a first solder.

11. The aforementioned clip is A set of clip gates positioned between the first contact area and the second contact area to expand the width of the clip. The semiconductor package according to claim 10, further comprising:

12. The semiconductor package according to claim 9, further comprising a covering that surrounds the chip stack and the clip, wherein the first lead frame and the second lead frame extend outward from the covering.

13. The semiconductor package according to claim 10 or 11, wherein the die pad includes a groove, the first solder extends within the groove, and the groove includes a set of walls defining a U-shaped or V-shaped contour.

14. The semiconductor package according to any one of claims 11 to 13, wherein the clip includes a first contact region and a second contact region, the first contact region being connected to the GPP chip by a second solder, and the second contact region being connected to the second lead frame by a third solder.

15. The step of providing a first lead frame including a die pad, In the step of coupling the chip stack to the first lead frame, the chip stack is: A transient voltage suppression (TVS) device coupled to the die pad, The solder wafer coupled to the TVS device, A glass passivation process (GPP) device is directly bonded to the TVS device using the aforementioned solder wafer, wherein the GPP device extends throughout the entire TVS device, and Stages including, The steps include attaching the clip to the GPP device, The steps include: connecting the second lead frame to the clip, Equipped with, The aforementioned clip is A first contact area connected to the GPP device, The second contact region connected to the second lead frame and Includes, The first contact area has a first width, A method for forming a package structure in which the clip extends to a second width greater than the first width between the first contact area and the second contact area.

16. The aforementioned clip is A set of clip gates positioned between the first contact area and the second contact area to expand the width of the clip, The method according to claim 15, further comprising:

17. The method according to claim 15, further comprising the step of providing a cover around the chip stack and the clip, wherein the first lead frame and the second lead frame extend to the outside of the cover.

18. The method according to claim 15 or 17, further comprising the step of providing a first solder between the TVS device and the die pad, wherein the first solder extends into a groove of the die pad.

19. The method according to any one of claims 15, 17, or 18, further comprising the steps of connecting a first contact area of ​​the clip to the GPP device by a second solder, and connecting the second contact area of ​​the clip to the second lead frame by a third solder.

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