Semiconductor chips and semiconductor devices

Abstract

To provide a semiconductor chip and a semiconductor device capable of suppressing the occurrence of thermal runaway.SOLUTION: A semiconductor chip according to an embodiment has a first electrode, a semiconductor layer, a second electrode, a third electrode, and a metal layer. The semiconductor layer includes a first portion, a second portion, and a third portion located between the first portion and the second portion. The semiconductor layer is provided on the first electrode. The second electrode is provided on the first portion. The third electrode is located on the second portion. The metal layer is located below the first electrode and below the third portion. The lower surface of the metal layer is located below the lower surface of the first electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor chips and semiconductor devices. [Background technology]

[0002] Semiconductor chips such as diodes, metal oxide semiconductor field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs) are used in applications such as power conversion. It is desirable for semiconductor chips to be resistant to thermal runaway. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-158180 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor chip and a semiconductor device that can suppress the occurrence of thermal runaway. [Means for solving the problem]

[0005] The semiconductor chip according to the embodiment comprises a first electrode, a semiconductor layer, a second electrode, a third electrode, and a metal layer. The semiconductor layer includes a first portion, a second portion, and a third portion located between the first portion and the second portion. The semiconductor layer is provided on the first electrode. The second electrode is provided on the first portion. The third electrode is provided on the second portion. The metal layer is provided below the first electrode and located below the third portion. The lower surface of the metal layer is located below the lower surface of the first electrode. [Brief explanation of the drawing]

[0006] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor chip according to the first embodiment. [Figure 2] FIG. 2(a) is a bottom view showing a semiconductor chip according to the first embodiment. FIG. 2(b) is a top view showing a semiconductor chip according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 5] FIG. 5(a) is a cross-sectional view showing a semiconductor device including a semiconductor chip according to a reference example. FIG. 5(b) is a cross-sectional view showing a semiconductor device including a semiconductor chip according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a semiconductor chip according to the second embodiment. [Figure 7] FIG. 7(a) is a bottom view showing a semiconductor chip according to the first embodiment. FIG. 7(b) is a top view showing a semiconductor chip according to the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a plan view showing a semiconductor device according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor chip according to a modification of the second embodiment. [Figure 11] FIG. 11(a) is a bottom view showing a semiconductor chip according to a modification of the second embodiment. FIG. 11(b) is a top view showing a semiconductor chip according to a modification of the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to a modification of the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a semiconductor chip according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a semiconductor device according to the third embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Please note that the drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of the parts, are not necessarily identical to those of reality. Furthermore, even when representing the same part, the dimensions and ratios may differ between drawings. Furthermore, in this specification and each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n, n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] (First Embodiment) Figure 1 is a cross-sectional view showing a semiconductor chip according to the first embodiment. Figure 2(a) is a plan view showing a semiconductor chip according to the first embodiment. Figure 2(b) is a bottom view showing a semiconductor chip according to the first embodiment. Figure 1 corresponds to the II cross-sectional view in Figures 2(a) and 2(b). The semiconductor chip 1 according to the first embodiment is a diode. As shown in Figures 1, 2(a), and 2(b), the semiconductor chip 1 according to the first embodiment comprises a semiconductor layer 10, a cathode electrode 21k (first electrode), an anode electrode 22a (second electrode), an anode electrode 23a (third electrode), and a metal layer 30.

[0009] The embodiment will be described using the XYZ Cartesian coordinate system. The direction from the cathode electrode 21k toward the semiconductor layer 10 will be defined as the Z direction (first direction). The direction perpendicular to the Z direction will be defined as the X direction (second direction). The direction perpendicular to both the X and Z directions will be defined as the Y direction. Here, the direction from the cathode electrode 21k toward the semiconductor layer 10 will be referred to as "up," and the opposite direction will be referred to as "down." These directions are based on the relative positional relationship between the cathode electrode 21k and the semiconductor layer 10, and are unrelated to the direction of gravity.

[0010] As shown in Figure 1, the cathode electrode 21k is provided on the lower side of the semiconductor chip 1. The semiconductor layer 10 is provided on top of the cathode electrode 21k. The semiconductor layer 10 includes a first portion 10a, a second portion 10b, and a third portion 10c. In Figure 1, the first portion 10a to the third portion 10c are shown by a dashed line. The third portion 10c is located between the first portion 10a and the second portion 10b. The direction from the first portion 10a to the second portion 10b is perpendicular to the Z direction. In the illustrated example, the direction from the first portion 10a to the second portion 10b is parallel to the X direction.

[0011] As shown in Figures 1 and 2(a), the anode electrodes 22a and 23a are provided on the first portion 10a and the second portion 10b of the semiconductor layer 10, respectively. The anode electrodes 22a and 23a are separated from each other. The direction from anode electrode 22a to anode electrode 23a is parallel to the direction from the first portion 10a to the second portion 10b and perpendicular to the Z direction.

[0012] As shown in Figure 1, the semiconductor layer 10 is more specifically n - Type (first conductivity type) cathode region 11k (first semiconductor region) and p + The shape (second conductivity type) includes an anode region 12a (second semiconductor region). - Cathode region 11k and p + The shaped anode region 12a is provided in the first part 10a to the third part 10c. -The V-shaped cathode region 11k is electrically connected to the cathode electrode 21k. p + The V-shaped anode region 12a is n - provided on a part of the V-shaped cathode region 11k and is electrically connected to the anode electrode 22a and the anode electrode 23a. A plurality of p that are separated from each other + shaped anode regions 12a may be provided under the anode electrode 22a and under the anode electrode 23a, respectively.

[0013] As shown in FIGS. 1 and 2(b), the metal layer 30 is provided under the cathode electrode 21k and is located under the third portion 10c. The metal layer 30 is in contact with the cathode electrode 21k and is electrically connected to the cathode electrode 21k. The lower surface of the metal layer 30 is located below the lower surface of the cathode electrode 21k. That is, the metal layer 30 protrudes downward from the cathode electrode 21k. The metal layer 30 is aligned with the gap between the anode electrode 22a and the anode electrode 23a in the Z direction.

[0014] n - A pn junction is formed between the V-shaped cathode region 11k and the p + shaped anode region 12a. When a positive voltage is applied to the anode electrode 22a or the anode electrode 23a with respect to the cathode electrode 21k, a current flows through the semiconductor chip 1. When a positive voltage is applied to the cathode electrode 21k with respect to the anode electrodes 22a and 23a, the current stops, and a depletion layer spreads from the pn junction to the n - shaped cathode region 11k and the p + shaped anode region 12a.

[0015] FIGS. 3 and 4 are cross-sectional views showing the semiconductor device according to the first embodiment. FIG. 3 corresponds to the III-III cross-sectional view of FIG. 4. FIG. 4 corresponds to the IV-IV cross-sectional view of FIG. 3. As shown in Figures 3 and 4, the semiconductor device 100 according to the first embodiment comprises a semiconductor chip 1, a lead frame 41 (first metal member), a lead frame 42 (second metal member), a lead frame 43 (third metal member), an insulating member 45, a bonding layer 51 (first bonding layer), a bonding layer 52 (second bonding layer), and a bonding layer 53 (third bonding layer).

[0016] The semiconductor chip 1 is bonded to the lead frame 41 via a bonding layer 51. The cathode electrode 21k and the metal layer 30 of the semiconductor chip 1 are electrically connected to the lead frame 41. The upper surface of the lead frame 41 is flat along the X-Y plane. Therefore, the distance between the lead frame 41 and the metal layer 30 is shorter than the distance between the lead frame 41 and the cathode electrode 21k.

[0017] The lead frame 42 is bonded to the anode electrode 22a via a bonding layer 52 and is electrically connected to the anode electrode 22a. The lead frame 43 is bonded to the anode electrode 23a via a bonding layer 53 and is electrically connected to the anode electrode 23a. The lead frame 43 is separate from the lead frame 42. Alternatively, one lead frame may be provided on the anode electrodes 22a and 23a. In that case, the anode electrodes 22a and 23a are electrically connected to one lead frame via bonding layers 52 and 53, respectively.

[0018] The insulating member 45 is provided around the semiconductor chip 1 and seals the semiconductor chip 1. As shown in Figure 4, a portion of each lead frame is not covered by the insulating member 45 and is exposed to the outside so that it can be electrically connected to other devices. As illustrated, the lower surface of lead frame 41, the upper surface of lead frame 42, and the upper surface of lead frame 43 may be exposed to the outside and not covered by the insulating member 45.

[0019] An example of the materials used for each component is described below. The semiconductor layer 10 contains a semiconductor material. The semiconductor material is silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as a p-type impurity.

[0020] The cathode electrode 21k, anode electrode 22a, and anode electrode 23a contain a metal such as titanium, aluminum, or copper. The metal layer 30 contains any metal. To increase the thermal conductivity of the metal layer 30, it is preferable that the metal layer 30 contains one or more selected from the group consisting of silver and copper. The metal layer 30 is formed, for example, by plating. The lead frames 41-43 contain a metal such as copper. The insulating member 45 contains an insulating resin such as polyimide. The bonding layers 51-53 contain solder containing tin or the like. Lead-free solder is preferred as the solder. In addition to tin, the solder may also contain silver or copper or the like.

[0021] The advantages of the first embodiment will be explained. According to the semiconductor chip 1 of this embodiment, external electrical circuits can be connected to the anode electrodes 22a and 23a, respectively. For example, in an electrical circuit that uses two rectifier diodes, one semiconductor chip 1 can be used as two rectifier diodes. Also, when the semiconductor chip 1 is used as a protection diode for electrostatic discharge, each of multiple electrical circuits can be protected by one semiconductor chip 1. Alternatively, below the anode electrodes 22a and 23a, the p + By providing the anode regions 12a, the semiconductor chip 1 can also be used as a bidirectional diode.

[0022] When the semiconductor chip 1 is operating, current flows from the anode electrode 22a or anode electrode 23a to the cathode electrode 21k, generating heat in the semiconductor layer 10. The heat generated in the semiconductor layer 10 is transferred to the cathode electrode 21k, anode electrode 22a, or anode electrode 23a and discharged from the semiconductor chip 1. The heat discharged from the semiconductor chip 1 is transferred to the lead frames 41-43 shown in Figures 3 and 4 and discharged from the semiconductor device 100.

[0023] In semiconductor chip 1, the first portion 10a and the second portion 10b are located below the anode electrode 22a and the anode electrode 23a, respectively. Therefore, the heat generated in the first portion 10a and the second portion 10b is efficiently dissipated from the anode electrode 22a and the anode electrode 23a, respectively. On the other hand, the third portion 10c is located below the gap between the anode electrode 22a and the anode electrode 23a. Therefore, the heat generated in the third portion 10c is less easily dissipated from the semiconductor layer 10 compared to the heat generated in the first portion 10a and the second portion 10b.

[0024] When the temperature of a portion of the semiconductor layer 10 rises, the electrical resistance of that portion decreases. This decrease in electrical resistance allows more current to flow through that portion, generating further heat. The repeated cycle of increased heat generation and decreased electrical resistance ultimately destroys the semiconductor chip 1; in other words, thermal runaway occurs. If the temperature of the third portion 10c rises, thermal runaway may occur in the third portion 10c, potentially destroying the semiconductor chip 1.

[0025] Figure 5(a) is a cross-sectional view showing a semiconductor device equipped with a semiconductor chip according to a reference example. Figure 5(b) is a cross-sectional view showing a semiconductor device equipped with a semiconductor chip according to an embodiment. The semiconductor chip 1a shown in Figure 5(a) is a reference example and does not have a metal layer 30. Multiple voids V exist in the bonding layer 51. The voids V are caused by air bubbles contained in the solder paste, which is the material of the bonding layer 51. The thermal conductivity of the voids V is lower than that of the bonding layer 51. Therefore, the presence of voids V hinders heat dissipation from the semiconductor layer 10. In particular, if the voids V are located below the third portion 10c, heat dissipation from the third portion 10c is hindered, and the temperature of the third portion 10c tends to rise even further.

[0026] The semiconductor chip 1 according to this embodiment includes a metal layer 30. The metal layer 30 is provided below the cathode electrode 21k and is located below the third portion 10c. When the semiconductor chip 1 is mounted on the lead frame 41, the voids V in the solder paste are pushed out laterally or crushed by the metal layer 30. As shown in Figure 5(b), the density of voids V in the bonding layer 51 below the third portion 10c is reduced by providing the metal layer 30. As a result, heat is more easily dissipated from the third portion 10c through the metal layer 30 and the bonding layer 51, and thermal runaway of the semiconductor chip 1 can be suppressed.

[0027] In the example shown in Figure 5(b), a portion of the bonding layer 51 is located between the lead frame 41 and the metal layer 30 in the Z direction. Another portion of the bonding layer 51 is not located between the lead frame 41 and the metal layer 30 in the Z direction. The density of voids V in the aforementioned portion of the bonding layer 51 is smaller than the density of voids V in the aforementioned other portion of the bonding layer 51.

[0028] The thicker the metal layer 30, the lower the density of voids V under the third portion 10c, and the easier it is for heat to dissipate from the third portion 10c. On the other hand, if the metal layer 30 is too thick, the semiconductor chip 1 becomes unstable when mounted. For this reason, as shown in Figure 5(b), the thickness T1 of the metal layer 30 is preferably greater than 0.1 times and less than 0.5 times the thickness T2 of the bonding layer 51. The thickness is a dimension in the Z direction.

[0029] More preferably, from the viewpoint of the stability of the semiconductor chip 1 during mounting, the effect of reducing the density of voids V, and the heat dissipation performance of the metal layer 30, the thickness T1 of the metal layer 30 is greater than 0.1 times and less than 0.2 times the thickness T2 of the bonding layer 51. In particular, if the metal layer 30 includes one or more selected from the group consisting of copper and silver, the thermal conductivity of the metal layer 30 can be made sufficiently higher than the thermal conductivity of the bonding layer 51. Even if the effect of reducing the density of voids V by the metal layer 30 is small, heat dissipation from the third portion 10c through the metal layer 30 can be promoted, and thermal runaway of the semiconductor chip 1 can be suppressed.

[0030] The metal layer 30 may be provided under a portion of the first portion 10a or under a portion of the second portion 10b. The metal layer 30 is not provided under any other portion of the first portion 10a or any other portion of the second portion 10b. The wider the width W of the metal layer 30 shown in Figure 1, the better the heat conduction between the third portion 10c and the lead frame 41. The width is the dimension in the direction from the first portion 10a to the second portion 10b.

[0031] On the other hand, if the width W is too small or too wide, the effect of pushing the void V laterally during the mounting of the semiconductor chip 1 will decrease. For this reason, it is preferable that the width W is greater than 0.5 times and less than 2.0 times the distance D between the anode electrode 22a and the anode electrode 23a. The distance is the dimension in the direction from the first part 10a to the second part 10b. The distance D corresponds to the width of the third part 10c.

[0032] Furthermore, it is preferable that the metal layer 30 extends to the end face of the semiconductor chip 1, as shown in Figure 2(b). In the illustrated example, in the Y direction, the position of the end face of the metal layer 30 is the same as the position of the end face of the semiconductor chip 1. When the metal layer 30 extends to the end face of the semiconductor chip 1, the voids V can be pushed to the end of the bonding layer 51 when the semiconductor chip 1 is bonded to the lead frame 41. The bubbles contained in the voids V are released to the outside of the bonding layer 51, and the voids V disappear. This further reduces the density of voids V in the bonding layer 51 and further suppresses thermal runaway of the semiconductor chip 1.

[0033] (Second Embodiment) Figure 6 is a cross-sectional view showing a semiconductor chip according to the second embodiment. Figure 7(a) is a plan view showing a semiconductor chip according to the second embodiment. Figure 7(b) is a bottom view showing a semiconductor chip according to the second embodiment. Figure 6 corresponds to the VI-VI cross-sectional view in Figures 7(a) and 7(b). The semiconductor chip 2 according to the second embodiment is a MOSFET. As shown in Figures 6, 7(a), and 7(b), the semiconductor chip 2 according to the second embodiment comprises a semiconductor layer 10, a gate electrode 20, a drain electrode 21d (first electrode), a source electrode 22s (second electrode), a gate pad 23g (third electrode), and a metal layer 30.

[0034] As shown in Figure 6, the drain electrode 21d is located on the underside of the semiconductor chip 2. The semiconductor layer 10 is located on top of the drain electrode 21d. Similar to semiconductor chip 1, in semiconductor chip 2, the semiconductor layer 10 includes a first portion 10a to a third portion 10c. In Figure 6, the first portion 10a to the third portion 10c are indicated by dashed lines.

[0035] As shown in Figures 6 and 7(a), the source electrode 22s and gate pad 23g are located on the first portion 10a and the second portion 10b, respectively. The source electrode 22s and gate pad 23g are separated from each other. As shown in Figures 6 and 7(b), the metal layer 30 is located below the drain electrode 21d and below the third portion 10c. In the Z direction, the metal layer 30 is aligned with the gap between the source electrode 22s and the gate pad 23g.

[0036] The semiconductor layer 10 is, more specifically, n - P-type drift region 11d (first semiconductor region), p-type base region 12b (second semiconductor region), n + Shape source region 13s (third semiconductor region), and n + Includes a drain region 14d. + The drain region 14d is provided above the drain electrode 21d and is electrically connected to the drain electrode 21d. - The shape of the drift region 11d is n+ It is located above the drain region 14d. - The shape of the drift region 11d is n + It is electrically connected to the drain electrode 21d via the drain region 14d. - Shape drift regions 11d and n + The drain region 14d is provided in the first part 10a to the third part 10c.

[0037] The p-shaped base region 12b has n in the first part 10a and the third part 10c. - It is located above the shape drift region 11d. + The p-type source region 13s is provided on the p-type base region 12b in the first portion 10a. The gate electrode 20 faces the p-type base region 12b via the gate insulating layer 20a.

[0038] The source electrode 22s consists of a p-type base region 12b and n + The gate electrode is electrically connected to the source region 13s. A gate insulating layer 20a is provided between the gate electrode 20 and the source electrode 22s, so the gate electrode 20 and the source electrode 22s are electrically isolated. The gate pad 23g is electrically connected to the gate electrode 20. An insulating layer 20b is provided between the semiconductor layer 10 and the gate pad 23g, so the semiconductor layer 10 and the gate pad 23g are electrically isolated.

[0039] p-type base region 12b, n + Each of the p-shaped source region 13s and gate electrode 20 extends in the Y direction, and multiple p-shaped base regions are provided in the X direction. The source electrode 22s consists of multiple p-shaped base regions 12b and multiple n-shaped base regions. + The gate pad 23g is electrically connected to the source region 13s. The gate pad 23g is electrically connected to multiple gate electrodes 20.

[0040] In the illustrated example, the semiconductor chip 2 has a trench gate structure in which the gate electrode 20 is surrounded by the semiconductor layer 10 in the XY plane. The semiconductor chip 2 may also have a planar gate structure in which the gate electrode 20 is provided on top of the semiconductor layer 10. In either structure, the gate electrode 20 is located between the semiconductor layer 10 and the source electrode 22s.

[0041] With a positive voltage applied to the drain electrode 21d relative to the source electrode 22s, a voltage above a threshold is applied to the gate electrode 20. This forms a channel (inversion layer) in the p-type base region 12b, and the semiconductor chip 2 turns on. Electrons flow through the channel from the source electrode 22s to the drain electrode 21d. When the voltage applied to the gate electrode 20 falls below the threshold, the channel in the p-type base region 12b disappears, and the semiconductor chip 2 turns off.

[0042] Figure 8 is a cross-sectional view showing a semiconductor device according to the second embodiment. Figure 9 is a plan view showing a semiconductor device according to the second embodiment. As shown in Figures 8 and 9, the semiconductor device 200 according to the second embodiment comprises a semiconductor chip 2, a lead frame 41 (first metal member), a lead frame 42 (second metal member), a bonding wire 43a (third metal member), a lead terminal 43b, an insulating member 45, and bonding layers 51 to 53. In Figure 9, the insulating member 45 is shown by a dashed line.

[0043] The semiconductor chip 2 is bonded to the lead frame 41 via a bonding layer 51. The drain electrode 21d and metal layer 30 of the semiconductor chip 2 are electrically connected to the lead frame 41. The lead frame 42 is bonded to the source electrode 22s via a bonding layer 52 and is electrically connected to the source electrode 22s. One end of the bonding wire 43a is bonded to the gate pad 23g, and the other end of the bonding wire 43a is bonded to the lead terminal 43b. The gate pad 23g is electrically connected to the lead terminal 43b via the bonding wire 43a.

[0044] The structure of the semiconductor device 200 is not limited to the illustrated example. Instead of the bonding wires 43a and lead terminals 43b, a single lead frame 43 may be bonded to the gate pad 23g via a bonding layer 53, similar to the semiconductor device 100. Instead of the lead frame 42, bonding wires and lead terminals may be provided.

[0045] The insulating member 45 is provided around the semiconductor chip 2 and seals the semiconductor chip 2. A portion of each lead frame and a portion of the lead terminal 43b are not covered by the insulating member 45 and are exposed to the outside.

[0046] The gate electrode 20 contains a conductive material such as polysilicon. The gate insulating layer 20a and insulating layer 20b contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21d, source electrode 22s, and gate pad 23g contain a metal such as titanium, aluminum, or copper. The bonding wire 43a contains a metal such as aluminum. The lead terminal 43b contains a metal such as copper.

[0047] In the semiconductor chip 2 and semiconductor device 200 according to the second embodiment, the heat generated in the third portion 10c is less easily dissipated from the semiconductor layer 10 compared to the heat generated in the first portion 10a and the second portion 10b. The semiconductor chip 2, like the semiconductor chip 1, includes a metal layer 30. The metal layer 30 is provided below the drain electrode 21d and is located below the third portion 10c. As a result, similar to the first embodiment, heat is more easily dissipated from the third portion 10c, and thermal runaway of the semiconductor chip 2 can be suppressed.

[0048] In semiconductor chip 2, as with semiconductor chip 1, the thickness of the metal layer 30 is preferably greater than 0.1 times the thickness of the bonding layer 51 and less than 0.5 times. More preferably, the thickness of the metal layer 30 is greater than 0.1 times the thickness of the bonding layer 51 and less than 0.2 times. Furthermore, the width W of the metal layer 30 shown in Figure 6 is preferably greater than 0.5 times the distance D between the source electrode 22s and the gate pad 23g and less than 2.0 times.

[0049] (modified version) Figure 10 is a cross-sectional view showing a semiconductor chip according to a modified example of the second embodiment. Figure 11(a) is a plan view showing a semiconductor chip according to a modified example of the second embodiment. Figure 11(b) is a bottom view showing a semiconductor chip according to a modified example of the second embodiment. Figure 10 corresponds to the XX cross-sectional view in Figures 11(a) and 11(b). As shown in Figures 10 and 11(a), the modified semiconductor chip 2a differs from semiconductor chip 2 in that it includes multiple source electrodes 22s and a metal layer 31.

[0050] The semiconductor layer 10 includes a plurality of first portions 10a, second portions 10b, third portions 10c, and fourth portions 10d. The third portion 10c is located between the plurality of first portions 10a and second portions 10b. The fourth portion 10d is located between the first portions 10a.

[0051] Multiple source electrodes 22s are provided on multiple first portions 10a, and are spaced apart from each other in the X direction. One of the multiple source electrodes 22s is part of a plurality of p-shaped base regions 12b and multiple n + It is electrically connected to a portion of the p-type source region 13s. Another of the multiple source electrodes 22s is connected to another portion of the multiple p-type base regions 12b and multiple n-type base regions. + It is electrically connected to another part of the shape source region 13s.

[0052] As shown in Figures 10 and 11(b), the metal layer 31 is located beneath the drain electrode 21d and below the fourth portion 10d. The metal layer 31 is aligned with the gap between the source electrodes 22s in the Z direction. The other components of semiconductor chip 2a are the same as those of semiconductor chip 2.

[0053] Figure 12 is a cross-sectional view showing a modified semiconductor device according to the second embodiment. As shown in Figure 12, in the modified semiconductor device 210, the cathode electrode 21k, metal layer 30, and metal layer 31 are electrically connected to the lead frame 41. Multiple lead frames 42 are electrically connected to multiple source electrodes 22s via multiple bonding layers 52.

[0054] The other components of the semiconductor device 210 are the same as those of the semiconductor device 200. The material of the metal layer 31 can be the same as the material of the metal layer 30.

[0055] In the modified semiconductor chip 2a, multiple source electrodes 22s are provided, spaced apart from each other. Heat generated in the fourth portion 10d, located below the gaps between the source electrodes 22s, is less easily dissipated from the semiconductor layer 10 compared to the heat generated in the first portion 10a and the second portion 10b. By providing the metal layer 31, the density of voids V in the junction layer 51 below the fourth portion 10d can be reduced when mounting the semiconductor chip 2a. This makes it easier for heat to be dissipated from the fourth portion 10d, thereby suppressing thermal runaway of the semiconductor chip 2a.

[0056] (Third embodiment) Figure 13 is a cross-sectional view showing a semiconductor chip according to the third embodiment. The semiconductor chip 3 according to the third embodiment is an IGBT. The semiconductor chip 3 according to the third embodiment shown in Figure 13 comprises a semiconductor layer 10, a gate electrode 20, a collector electrode 21c (first electrode), an emitter electrode 22e (second electrode), a gate pad 23g (third electrode), and a metal layer 30.

[0057] The collector electrode 21c and emitter electrode 22e can be configured in the same way as the drain electrode 21d and source electrode 22s. The collector electrode 21c is provided on the lower side of the semiconductor chip 3. The semiconductor layer 10 is provided on top of the collector electrode 21c.

[0058] The semiconductor layer 10 in the semiconductor chip 3 is n + An n-type buffer region 14b is provided in place of the n-type drain region 14d, and p+ It differs from the semiconductor layer 10 in semiconductor chip 2 in that it further includes a collector region 15c. In semiconductor chip 3, n + The shape of the source region 13s is n + It functions as a shape emitter region 13e.

[0059] p + The n-type collector region 15c is provided on the collector electrode 21c and is electrically connected to the collector electrode 21c. The n-type buffer region 14b is p + It is located above the shape collector region 15c. - The n-shaped drift region 11d is located on top of the n-shaped buffer region 14b. The p-shaped base region 12b is n - It is located above the shape drift region 11d. + The p-type source region 13s is provided on the p-type base region 12b. The gate electrode 20 faces the p-type base region 12b via a gate insulating layer 20a.

[0060] The emitter electrode 22e and gate pad 23g are provided on the first portion 10a and the second portion 10b, respectively. The emitter electrode 22e consists of a plurality of p-type base regions 12b and a plurality of n + The emitter region 13e is electrically connected. The gate pad 23g is electrically connected to multiple gate electrodes 20.

[0061] With a positive voltage applied to the collector electrode 21c relative to the emitter electrode 22e, a voltage above the threshold is applied to the gate electrode 20. This forms a channel (inversion layer) in the p-type base region 12b, and the semiconductor chip 3 turns on. Electrons pass through the channel from the emitter electrode 22e to n - The electrons flow into the drift region 11d. Depending on the flow of electrons, holes move from the collector electrode 21c to n - It flows into the shape drift region 11d. - Electrons and holes accumulate in the drift region 11d, causing conductivity modulation, and n -The electrical resistance of the p-type drift region 11d decreases significantly. When the voltage applied to the gate electrode 20 falls below the threshold, the channel in the p-type base region 12b disappears, and the semiconductor chip 3 turns off.

[0062] Figure 14 is a cross-sectional view showing a semiconductor device according to the third embodiment. The configuration of the semiconductor device 300 according to the third embodiment shown in Figure 14 is the same as that of the semiconductor device 200, except that a semiconductor chip 3 is provided instead of semiconductor chip 2.

[0063] According to the third embodiment, similar to the second embodiment, heat can be easily dissipated from the third portion 10c of the semiconductor chip 3, thereby suppressing thermal runaway of the semiconductor chip 3.

[0064] In semiconductor chip 3, as with semiconductor chip 1, the thickness of the metal layer 30 is preferably greater than 0.1 times the thickness of the bonding layer 51 and less than 0.5 times. More preferably, the thickness of the metal layer 30 is greater than 0.1 times the thickness of the bonding layer 51 and less than 0.2 times. Furthermore, the width W of the metal layer 30 shown in Figure 13 is preferably greater than 0.5 times the distance D between the emitter electrode 22e and the gate pad 23g and less than 2.0 times.

[0065] Regarding the embodiments described above, the relative levels of impurity concentrations between each semiconductor region can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between each semiconductor region can also be confirmed using SCM. The impurity concentration in each semiconductor region can be measured by secondary ion mass spectrometry (SIMS).

[0066] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of symbols]

[0067] 1,1a,2,2a,3: Semiconductor chip, 10: Semiconductor layer, 10a: First part, 10b: Second part, 10c: Third part, 10d: Fourth part, 11d: n - Shape drift region, 11k:n - Cathode region shape, 12a:p + 12b: p-type anode region, 13e: n-type base region + Shape emitter region, 13s:n + Source area, 14b:n buffer area, 14d:n + Shaped drain region, 15c:p + Shape: Collector region, 20: Gate electrode, 20a: Gate insulating layer, 20b: Insulating layer, 21c: Collector electrode, 21d: Drain electrode, 21k: Cathode electrode, 22s: Source electrode, 22a: Anode electrode, 22e: Emitter electrode, 22s: Source electrode, 23a: Anode electrode, 23g: Gate pad, 30,31: Metal layer, 41~43: Lead frame, 43a: Bonding wire, 43b: Lead terminal, 45: Insulating material, 51~53: Bonding layer, 100,200,210,300: Semiconductor device, D: Distance, T1,T2: Thickness, V: Void

Claims

1. First electrode and A semiconductor layer provided on the first electrode, comprising a first part, a second part, and a third part interposed between the first part and the second part, A second electrode provided on the first portion, A third electrode is provided on the second portion and is separated from the second electrode, A metal layer provided below the first electrode, located below the third portion, with its lower surface positioned below the lower surface of the first electrode, Equipped with, The metal layer is further provided below a portion of the first portion and below a portion of the second portion, but is not provided below another portion of the first portion and below another portion of the second portion. The lower surface of the metal layer is located on the side of the direction toward the first electrode in the direction toward the first electrode from the semiconductor layer, The aforementioned metal layer is provided along the direction in which the gap between the second electrode and the third electrode extends, in a semiconductor chip.

2. The aforementioned semiconductor layer is A first semiconductor region of a first conductivity type provided in the first part, the second part, and the third part, A second semiconductor region of a second conductivity type is provided in the first portion and located on the first semiconductor region, Includes, The first semiconductor region is electrically connected to the first electrode, The semiconductor chip according to claim 1, wherein the second semiconductor region is electrically connected to the second electrode.

3. The gate electrode further comprises the second semiconductor region facing the gate insulating layer, The semiconductor layer further includes a third semiconductor region of a first conductivity type provided on the second semiconductor region, The third semiconductor region is electrically connected to the second electrode, The semiconductor chip according to claim 2, wherein the gate electrode is electrically connected to the third electrode.

4. The aforementioned metal layer comprises one or more selected from the group consisting of copper and silver. The semiconductor chip according to claim 1, wherein the metal layer is provided linearly along the gap between the second electrode and the third electrode.

5. A semiconductor chip according to any one of claims 1 to 4, A first metal member bonded to the first electrode and the metal layer via a first bonding layer, A second metal member joined to the second electrode, A third metal member joined to the aforementioned third electrode, A semiconductor device equipped with the following features.

6. The semiconductor device according to claim 5, wherein the distance between the first metal member and the metal layer is shorter than the distance between the first metal member and the first electrode.

7. The semiconductor device according to claim 5, wherein the thickness of the metal layer is less than 0.5 times the thickness of the first bonding layer.

8. A portion of the first bonding layer is located between the first metal member and the metal layer. Another part of the first bonding layer is not located between the first metal member and the metal layer. The semiconductor device according to claim 5, wherein the density of voids in the portion of the first bonding layer is smaller than the density of voids in the other portion of the first bonding layer.

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