Semiconductor device having a dummy pad and method for forming the same

Abstract

In a particular aspect, a semiconductor device includes a device layer, a dummy pad, a dielectric structure extending vertically between the device layer and the dummy pad, and an interconnect structure extending vertically between the device layer and the dielectric structure, wherein the dielectric structure, the interconnect structure, and the dummy pad are superimposed.

Description

Technical Field

[0001] This disclosure relates to three-dimensional (3D) memory devices and methods of manufacturing the same.

Background Art

[0002] Electrostatic discharge (ESD) is a sudden discharge of static electricity. ESD can occur when a charged body touches an electronic device. ESD can damage semiconductor devices, for example, if not protected during the manufacture and packaging of semiconductor devices. One way to prevent damage caused by ESD is to use an ESD protection circuit (also known as an ESD circuit) that diverts the flow of ESD current by providing a low impedance path.

Summary of the Invention

[0003] In one aspect, a semiconductor device includes a device layer, a dummy pad, a dielectric structure extending vertically between the device layer and the dummy pad, and an interconnect structure extending vertically between the device layer and the dielectric structure. The dielectric structure, the interconnect structure, and the dummy pad are overlapped.

[0004] In some embodiments, the semiconductor device further includes a semiconductor layer between the dummy pad and the interconnect structure. In some embodiments, the dielectric structure includes a separation structure within the semiconductor layer.

[0005] In some embodiments, the lateral dimension of the separation structure is larger than the lateral dimension of the dummy pad.

[0006] In some embodiments, the semiconductor device further includes a first via contact that contacts the interconnect structure and is separated from the dummy pad by the separation structure.

[0007] In some embodiments, the first via contact includes tungsten.

[0008] In some embodiments, the semiconductor device further includes a second via contact that contacts a dummy pad and extends vertically. In some embodiments, the dielectric structure includes a dielectric layer between the second via contact and the interconnect structure.

[0009] In some embodiments, the second via contact is isolated from the interconnection structure by a dielectric layer.

[0010] In some embodiments, the second via contact contains tungsten.

[0011] In some embodiments, the semiconductor device further includes a bonding interface between a dummy pad and a device layer. In some embodiments, the interconnection structure includes bonding contacts at the bonding interface.

[0012] In some embodiments, the interconnection structure further includes device contacts between the bonding interface and the device layer that connect the bonding interface and the device layer.

[0013] In some embodiments, the semiconductor device further includes a pad, another second via contact in contact with the pad, another first via contact in contact with the other second via contact, and another interconnection structure in contact with the other first via contact and the device layer.

[0014] In some embodiments, the pad and the dummy pad are on the same plane, and the interconnection structure and other interconnection structures are on the same plane.

[0015] In another embodiment, the semiconductor device includes a device layer containing an electrostatic discharge (ESD) circuit and a functional circuit, a dummy pad isolated from the functional circuit, and an interconnection structure between the device layer and the dummy pad. The dummy pad is connected to the ESD circuit at least via the interconnection structure.

[0016] In some embodiments, the semiconductor device further includes a first via contact located between a dummy pad and an interconnect structure and connected to the interconnect structure.

[0017] In some embodiments, the semiconductor device further includes a semiconductor layer between a dummy pad and a first via contact, a spacer within the semiconductor layer, and a second via contact that contacts the dummy pad and extends through the spacer.

[0018] In some embodiments, the first and second via contacts include tungsten.

[0019] In some embodiments, the dummy pad is connected to the ESD circuit via at least an interconnection structure and first and second via contacts.

[0020] In some embodiments, the semiconductor device further includes a bonding interface between a dummy pad and a device layer. In some embodiments, the interconnection structure includes bonding contacts at the bonding interface.

[0021] In some embodiments, the interconnection structure further includes device contacts between the bonding interface and the device layer that connect the bonding interface and the device layer.

[0022] In yet another embodiment, a method for forming a semiconductor device is provided. A device layer including a functional circuit is formed. An interconnect structure is formed on the device layer and separated from the functional circuit. A first via contact is formed on the interconnect structure and connected to the interconnect structure. A decoupling structure is formed on the first via contact. A dummy pad is formed on the decoupling structure and separated from the first via contact by the decoupling structure.

[0023] In some embodiments, other interconnect structures are formed on the device layer and connected to the functional circuits, other first via contacts are formed on the other interconnect structures and connected to the other interconnect structures, a second via contact is formed in contact with and extending through the isolation structure over the other first via contact, and a pad is formed in contact with the second via contact on the second via contact.

[0024] In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, the first via contact and the other first via contacts are exposed, and a dielectric layer is deposited to fill the trench.

[0025] In some embodiments, to form the second via contact, a portion of the isolation structure is removed to form a hole for exposing the other first via contact rather than the first via contact, and a metal layer is deposited to fill the hole.

[0026] In some embodiments, the metal layer includes tungsten.

[0027] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to further explain the principles of the disclosure and to enable one skilled in the art to make and use the disclosure.

Brief Description of the Drawings

[0028] [Figure 1] A plan view of a semiconductor device with a via contact under a dummy pad according to some embodiments of the present disclosure is shown. [Figure 2] A plan view of a semiconductor device without a via contact under a dummy pad according to some embodiments of the present disclosure is shown. [Figure 3A] A side cross-sectional view of a semiconductor device having a dummy pad according to some embodiments of the present disclosure is shown. [Figure 3B] A side cross-sectional view of a three-dimensional (3D) memory device having a dummy pad and a pad according to some embodiments of the present disclosure is shown. [Figure 4] The following are side cross-sectional views of other semiconductor devices having dummy pads according to some aspects of this disclosure. [Figure 5] The following are side cross-sectional views of yet another semiconductor device having a dummy pad according to some aspects of this disclosure. [Figure 6A] Circuit diagrams of ESD circuits relating to several aspects of this disclosure are shown. [Figure 6B] Circuit diagrams of ESD circuits relating to several aspects of this disclosure are shown. [Figure 7A] This invention illustrates a manufacturing process for forming a semiconductor device having a dummy pad, according to several aspects of this disclosure. [Figure 7B] This invention illustrates a manufacturing process for forming a semiconductor device having a dummy pad, according to several aspects of this disclosure. [Figure 7C] This invention illustrates a manufacturing process for forming a semiconductor device having a dummy pad, according to several aspects of this disclosure. [Figure 7D] This invention illustrates a manufacturing process for forming a semiconductor device having a dummy pad, according to several aspects of this disclosure. [Figure 7E] This invention illustrates a manufacturing process for forming a semiconductor device having a dummy pad, according to several aspects of this disclosure. [Figure 8A] This invention illustrates a manufacturing process for forming other semiconductor devices having dummy pads, according to several aspects of this disclosure. [Figure 8B] This invention illustrates a manufacturing process for forming other semiconductor devices having dummy pads, according to several aspects of this disclosure. [Figure 8C] This invention illustrates a manufacturing process for forming other semiconductor devices having dummy pads, according to several aspects of this disclosure. [Figure 8D] This invention illustrates a manufacturing process for forming other semiconductor devices having dummy pads, according to several aspects of this disclosure. [Figure 8E]This invention illustrates a manufacturing process for forming other semiconductor devices having dummy pads, according to several aspects of this disclosure. [Figure 9] This is a flowchart of a method for forming a semiconductor device having a dummy pad, according to some aspects of the present disclosure. [Modes for carrying out the invention]

[0029] This disclosure will be explained with reference to the attached drawings.

[0030] While specific configurations and arrangements are described, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be applied to a variety of other uses. The functional and structural features described in this disclosure may be combined, adjusted, and modified with respect to each other and in ways not specifically shown in the drawings, so that these combinations, adjustments, and modifications remain within the scope of this disclosure.

[0031] In general, terms can be understood at least partially from their use in context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may, at least partially depending on the context, be understood to convey either a singular or plural usage. Furthermore, the term “based on” may be understood not necessarily to convey an exclusive set of factors, but instead, at least partially depending on the context, may allow for the presence of additional factors that are not necessarily explicitly described.

[0032] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted most broadly, so that “on” not only means “directly on” something, but also “on” something with an intermediate feature or layer in between, and “above” or “over” means “above” or “over” something, but also “above” or “over” something without an intermediate feature or layer in between (i.e., directly on something).

[0033] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate descriptions of the relationship between one element or feature and other elements or features, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or to other directions), and the spatially relative descriptors used herein may be interpreted accordingly.

[0034] As used herein, the term “substrate” refers to the material upon which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate may be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0035] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend over the entirety of a structure below or above it, or may have a smaller extent than the extent of the structure below or above it. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the upper and lower end faces of a continuous structure, or between any pair of horizontal planes between the upper and lower end faces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may contain one or more layers, and / or have one or more layers above, above, and / or below it. A layer may contain multiple layers. For example, an interconnection layer may include one or more conductor and contact layers (on which interconnection lines and / or vertical contacts are formed) and one or more dielectric layers.

[0036] In semiconductor devices, dummy pads can be used for wire bonding during semiconductor device packaging, just like ordinary pads (referred to herein as "pads"). However, unlike ordinary pads, dummy pads are electrically isolated from the functional circuits of the semiconductor device (e.g., those having transistors or memory cells) and therefore do not facilitate the operation of the functional circuits.

[0037] While dummy pads are designed to be electrically isolated from the corresponding functional circuits beneath them, ESD from dummy pads can still cause damage to functional circuits if, for example, during semiconductor device packaging, the distance between the functional circuit and interconnect structure located beneath the dummy pad and in contact with the dummy pad is not sufficiently large, and / or if the functional circuit is not ESD protected.

[0038] To address one or more of the aforementioned problems, this disclosure introduces various solutions for preventing ESD damage to semiconductor devices from dummy pads. According to one aspect of this disclosure, at least one of the via contacts in the interconnect structure located beneath and covering the dummy pad is replaced and removed, for example, by a dielectric structure, so that ESD from the dummy pad cannot propagate to the functional circuit. In some embodiments, the lateral dimension of the isolation structure within the dielectric structure (e.g., embedded shallow trench isolation (BSTI)) is greater than the lateral dimension of the dummy pad, thereby further reducing the risk of burnout due to defects between the dummy pad and the semiconductor layer beneath it. According to other aspects of this disclosure, the dummy pad is electrically connected to an ESD circuit, at least via an interconnect structure, so that ESD from the dummy pad can be mitigated by the ESD circuit.

[0039] Figure 1 shows a plan view of a semiconductor device 100 with via contacts below a dummy pad 104 according to several aspects of the present disclosure. The semiconductor device 100 may include logic devices such as microcontrollers, microprocessors, and application processors; memory devices such as dynamic random access memory (DRAM), NAND or NOR flash memory, and static random access memory (SRAM); or analog devices such as operational amplifiers, timers, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). The semiconductor device 100 may include wire bonding pads used to electrically connect the semiconductor device 100 to external devices. For example, the wire bonding pads may be connected to a circuit board or packaging substrate (e.g., a redistribution layer) or an interposer by soldering and attaching gold or aluminum wires. Thus, the wire bonding pads can function as bond sites on the semiconductor device 100. The semiconductor device 100 may also include functional circuits (e.g., as part of its device layer) configured to perform functions of the semiconductor device, such as transistors for logic devices, memory cells for memory devices, or resistors, capacitors, and inductors for analog devices.

[0040] In some embodiments, depending on whether the wire bonding pad is electrically connected to any functional circuit, i.e., whether the wire bonding pad also facilitates the operation of the corresponding functional circuit (e.g., transmitting / receiving electrical signals to and from a functional device), the wire bonding pad includes a normal pad (also known as a pad) 102 and a dummy pad 104. For example, each pad 102 may be electrically connected to a corresponding functional circuit to facilitate the operation of the functional circuit, while each dummy pad 104 may not be electrically connected to any functional circuit and therefore does not facilitate the operation of any functional circuit. As shown in Figure 1, in some embodiments, either the pad 102 or the dummy pad 104 is in contact with one or more via contacts underneath, forming part of an interconnect structure that overlaps the pad 102 / dummy pad 104. It is understood that an interconnect structure covering pad 102 can connect pad 102 to a corresponding functional circuit, but an interconnect structure covering dummy pad 104 cannot connect dummy pad 104 to any functional circuit. In some embodiments described in detail below, the interconnect structure covering the dummy pad 104 can connect the dummy pad 104 to an ESD circuit to reduce the risk of ESD damage from the dummy pad 104 to a functional circuit close to the interconnect structure covering the dummy pad 104.

[0041] Figure 2 shows a plan view of a semiconductor device 200 without via contacts below the dummy pad 104, according to some embodiments of the present disclosure. The semiconductor device 200 is similar to the semiconductor device 100, except that at least one of the via contacts below the dummy pad 104 is removed and replaced, for example, with a dielectric structure. As a result, according to some embodiments described in detail below, ESD from the dummy pad 104 can be isolated by the dielectric structure before reaching any functional circuit through the interconnect structure covering the dummy pad 104.

[0042] Figure 3A shows a side cross-sectional view of a semiconductor device 300 having a dummy pad 330 according to some embodiments of the present disclosure. The semiconductor device 300 may be an example of the semiconductor device 200. As shown in Figure 3A, the semiconductor device 300 is a bonded chip that, according to some embodiments, includes a first structure 302 and a second structure 304 stacked on top of each other in different planes in the vertical direction (e.g., the z direction). According to some embodiments, the first and second structures 302 and 304 are bonded at a bonding interface 306 between them.

[0043] As shown in Figure 3A, the first structure 302 may include a substrate 308 which may contain silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate 308 contains single-crystal silicon, which is part of the wafer on which the first structure 302 is manufactured, either at its original thickness or thinned. In some embodiments, the first substrate 302 contains, for example, polysilicon, which is a semiconductor layer replacing part of the wafer on which the first structure 302 is manufactured. Note that the x, y, and z axes are included in Figures 1, 2, and 3A to further illustrate the spatial relationships of the components within the semiconductor devices 100, 200, and 300. The substrate 308 of the semiconductor device 300 includes two sides extending laterally in the xy plane: an upper end face on the front of the wafer where the device layer 310 can be formed, and a lower end face on the back of the wafer opposite to the front. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or device) of the semiconductor device 300 is "above," "above," "below," or "below" another component (e.g., a layer or device) is determined relative to the substrate 308 of the semiconductor device 300 in the z-direction (a vertical direction perpendicular to the xy plane) when the substrate 308 is positioned in the z-direction at the lowest plane of the semiconductor device 300. The same concepts for describing spatial relationships apply throughout this disclosure.

[0044] As shown in Figure 3A, the first structure may include a device layer 310 on the substrate 308. In some embodiments, the device layer 310 includes a functional circuit 312. In some embodiments, the semiconductor device 300 is a NAND flash memory device in which memory cells are formed within an array of NAND memory strings, and the functional circuit 312 is a peripheral circuit (also known as a control / sensor circuit) that facilitates the operation of the NAND memory strings and includes any suitable digital, analog, and / or mixed-signal circuits. For example, the peripheral circuit may include one or more of the following: a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output circuit, a charge pump, a voltage source or voltage generator, a current or voltage reference, any part of the aforementioned functional circuit (e.g., a subcircuit), or any active or passive component of the circuit (e.g., a transistor, diode, resistor, or capacitor). The functional circuit 312 may use complementary metal-oxide-semiconductor (CMOS) technology, for example, which can be implemented in a logic process at any suitable technology node.

[0045] In some embodiments, the first structure 302 further includes an interconnection layer 311 above the device layer 310 for transferring electrical signals to and from the device layer 310. As shown in Figure 3A, the interconnection layer 311 may be perpendicular between the junction interface 306 and the device layer 310 (including the functional circuit 312). The interconnection layer 311 may include a plurality of interconnections (also referred to herein as “contacts”), including transverse lines and via contacts. The term “interconnection” as used herein can broadly include any suitable type of interconnection, such as middle-end-of-line (MEOL) interconnections and back-end-of-line (BEOL) interconnections. The interconnection layer 311 may further include one or more interlayer dielectric (ILD) layers (also known as “intermetallic dielectric (IMD) layers”), from which transverse lines and via contacts can be formed. That is, the interconnection layer 311 may include transverse lines and via contacts in a plurality of ILD layers. Although not shown in Figure 3A, it is understood that the functional circuit 312 within the device layer 310 may be electrically connected to any other suitable functional circuit via an interconnect within the interconnect layer 311. The interconnect within the interconnect layer 311 may include, but are not limited to, conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layer within the interconnect layer 311 may include, but are not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnect within the interconnect layer 311 may include, for example, a device contact 316 within a metal 3-5 (M3-M5) layer. The device contact 316 may include Cu, which has relatively low resistivity (better electrical performance) among conductive metallic materials.

[0046] As shown in Figure 3A, the first structure 302 may further include a bonding layer 313 that is in contact with the interconnection layer 311 and at the bonding interface 306, and above the interconnection layer 311. The bonding layer 313 may include a plurality of bonding contacts 318 and a dielectric that electrically insulates the bonding contacts 318. The bonding contacts 318 may include, but are not limited to, conductive materials such as W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 318 of the bonding layer 313 include Cu. The remaining region of the bonding layer 313 may be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 318 and the surrounding dielectric within the bonding layer 313 can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bonding between surfaces without using an intermediate layer such as solder or adhesive), and metal-metal (e.g., Cu-Cu) bonding and dielectric-dielectric (e.g., SiO2 to SiO2) bonding can be obtained simultaneously.

[0047] As shown in Figure 3A, the second structure 304 may include a bonding layer 315 at the bonding interface 306, for example, on the opposite side of the bonding interface 306 from the bonding layer 313 of the first structure 302. The bonding layer 315 may include a plurality of bonding contacts 320 and a dielectric that electrically insulates the bonding contacts 320. The bonding contacts 320 may include a conductive material such as Cu. The remaining area of ​​the bonding layer 315 can be formed of a dielectric material such as silicon oxide. The bonding contacts 320 and the surrounding dielectric within the bonding layer 315 can be used for hybrid bonding. In some embodiments, the bonding interface 306 is the location where the bonding layers 313 and 315 face each other and are bonded. In practice, the bonding interface 306 can be a layer with a specific thickness that includes the upper end face of the bonding layer 313 of the first structure 302 and the lower end face of the bonding layer 315 of the second structure 304.

[0048] As shown in Figure 3A, the second structure 304 may further include an interconnection layer 323 above the junction layer 315 for transferring electrical signals. The interconnection layer 323 may include multiple interconnections, such as MEOL interconnections and BEOL interconnections. Although not shown in Figure 3A, in some examples, the interconnections within the interconnection layer 323 may also include local interconnections, such as bit line contacts and word line contacts. The interconnection layer 323 may further include one or more ILD layers on which transverse lines and via contacts may be formed. The interconnections within the interconnection layer 323 may include, but are not limited to, conductive materials such as W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers within the interconnection layer 323 may include, but are not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnections within the interconnection layer 323 include W, which has a relatively high thermal history (suitable for high-temperature processes) and good quality (reduced defects, e.g., voids) among conductive metallic materials.

[0049] As shown in Figure 3A, the second structure 304 may further include a semiconductor layer 326 above the interconnection layer 323. The semiconductor layer 326 may include a semiconductor material. In some embodiments, the semiconductor layer 326 is a thinned silicon substrate having single-crystal silicon. In some embodiments, the semiconductor layer 326 is a deposited polysilicon layer replacing at least a portion of the silicon substrate having single-crystal silicon. In some examples, it is understood that trench isolation and doped regions (not shown) may also be formed within the semiconductor layer 326. In some examples, it is understood that the semiconductor layer 326 may include a plurality of vertical semiconductor layers with dielectric layers formed between them.

[0050] As shown in Figure 3A, the second structure 304 may further include a pad-out layer 327 above the semiconductor layer 326. The pad-out layer 327 may include a dummy pad 330, one or more ILD layers 332 (e.g., a silicon oxide layer and a silicon nitride layer), and a protective layer 334 (e.g., a polyimide layer) on the upper end face of the semiconductor device 300. The pad-out layer 327 and interconnection layer 323 may be formed on both sides of the semiconductor layer 326. In some embodiments, an opening 336 is formed through the protective layer 334 and ILD layer 332 in the pad-out layer 327 to expose the dummy pad 330, thereby allowing wire bonding to be performed on the upper end face of the dummy pad 330.

[0051] In accordance with the scope of this disclosure, the semiconductor device 300 may include a dielectric structure between the device layer 310 and the dummy pad 330 in the vertical direction (e.g., the z direction in Figure 3A). The dielectric structure may extend in the transverse direction (e.g., the y direction in Figure 3A) and the vertical direction (e.g., the z direction in Figure 3A). In some embodiments shown in Figure 3A, the dielectric structure includes an isolation structure 328, such as a BSTI, within the semiconductor layer 326. For example, the isolation structure 328 may include silicon oxide. The semiconductor device 300 may also include an interconnection structure 314 between the device layer 310 and the dielectric structure (e.g., the isolation structure 328 in Figure 3A) in the vertical direction (e.g., the z direction in Figure 3A). The interconnection structure 314 may extend in the vertical direction (e.g., the z direction in Figure 3A). The semiconductor layer 326 may be positioned between the dummy pad 330 and the interconnection structure 314 in the vertical direction. As shown in Figure 3A, according to several embodiments, the isolation structure 328, the interconnection structure 314, and the dummy pad 330 are superimposed and are considered to be corresponding structures in this disclosure. In other words, for each dummy pad 330, the semiconductor device 300 may include the corresponding overlay isolation structure 328 and interconnection structure 314.

[0052] As shown in Figure 3A, the interconnection structure 314 may include bonding contacts 320 and 318 in bonding layers 315 and 313, and device contacts 316 in the interconnection layer 311 of the first structure 302. According to some embodiments, the device contacts 316 are located between the bonding interface 306 and the device layer 310, and the bonding interface 306 is located vertically between the dummy pad 330 and the device layer 310. In some embodiments, it is understood that the interconnection structure 314 may further include an interconnection 322 in the interconnection layer 323 of the second structure 304.

[0053] As shown in Figure 3A, the second structure 304 of the semiconductor device 300 may further include via contacts 324 extending vertically within the interconnection layer 323. The via contacts 324 may include W. In some embodiments, the via contacts 324 are in contact with the interconnection structure 314 but are isolated from the dummy pad 330 by an isolation structure 328. Thus, even if the device contacts 316 of the interconnection structure 314 are not far enough from the functional circuit 312 in the device layer 310 to prevent ESD damage to the functional circuit 312 via the interconnection structure 314 and the via contacts 324, the isolation structure 328 between the dummy pad 330 and the via contacts 324 can still prevent ESD from propagating from the dummy pad 330 to the via contacts 324. In some embodiments, the thickness of the separation structure 328 (e.g., thickness in the vertical direction) is between 500 nm and 1000 nm (e.g., 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, any range bounded by the lower end by any of these values, or any range defined by any two of these values).

[0054] In some embodiments, the lateral dimension of the isolation structure 328 (e.g., in the y-direction in Figure 3A) is larger than the lateral dimension of the dummy pad 330 (e.g., in the y-direction in Figure 3A). As a result, even if defects may form in the semiconductor layer 326, the increased size of the isolation structure 328 (e.g., BSTI) reduces the risk of burn-in between the dummy pad 330 and the semiconductor layer 326. In some embodiments, the distance d between the edge of the dummy pad 330 and the isolation structure 328 in the lateral direction (e.g., the y-direction in Figure 3A) is greater than 1 μm, for example, between 1 μm and 5 μm (e.g., 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, any range bounded by the lower edge by any of these values, or any range defined by any two of these values).

[0055] Figure 3B shows a side cross-sectional view of a three-dimensional memory device 301 having dummy pads 330 and pads 346 according to several embodiments of the present disclosure. The three-dimensional memory device 301 may be an example of the semiconductor device 300 in Figure 3A, such as a NAND flash memory device. For the sake of clarity, the same components described above with respect to Figure 3A will not be repeated.

[0056] As shown in Figure 3B, the three-dimensional memory device 301 may further include a pad 346, a via contact 344 located below and in contact with the pad 346, a via contact 342 located below and in contact with the via contact 344, and an interconnection structure 340 located below and in contact with the via contact 342. According to some embodiments, the pad 346, via contacts 344 and 342, and the interconnection structure 340 are superimposed. As will be described in detail below with respect to the manufacturing process, the pad 346 and the dummy pad 330 can be formed by the same process and are coplanar. Similarly, the interconnection structure 314 and the interconnection structure 340 can be formed by the same process and are coplanar, and the via contacts 324 and 342 can be formed by the same process and are coplanar. According to some embodiments, the via contact 344 extends through an isolation structure 328 (e.g., BSTI) and connects the pad 346 and the via contact 342. Therefore, unlike the dummy pad 330 and interconnection structure 314 which are electrically isolated by the isolation structure 328, the pad 346 can be electrically connected to the interconnection structure 340 via via contacts 344 and 342. Similar to via contact 324, via contacts 344 and 342 may contain W.

[0057] As shown in Figure 3B, the device layer 310 may further include a functional circuit 312 electrically connected to the interconnect structure 314, distinct from the functional circuit 338 which is electrically isolated from the interconnect structure 340. As a result, the pad 346 can be electrically connected to the functional circuit 338 in the device layer 310 via via contacts 344 and 342 and the interconnect structure 340, thereby facilitating the operation of the functional circuit 338. Although not shown, it is understood that the device layer 310 may further include an ESD circuit electrically connected to the functional circuit 338 and the interconnect structure 340 to avoid ESD damage from the pad 346.

[0058] In some embodiments, the three-dimensional memory device 301 further includes a memory cell array, such as an array of NAND memory strings 350 above a junction interface 306 in a second structure 304. In some embodiments, the NAND memory strings 350 are positioned vertically between a semiconductor layer 326 and the junction interface 306. In some embodiments, the semiconductor layer 326 is positioned above a memory stack 348, in contact with the source of the NAND memory strings 350. In some embodiments, each NAND memory string 350 is a “charge trap” type NAND memory string containing any suitable channel structure. It is understood that the NAND memory strings 350 are not limited to “charge trap” type NAND memory strings, and in other examples may be “floating gate” type NAND memory strings.

[0059] According to several embodiments, each NAND memory string 350 extends vertically through a plurality of pairs, each comprising a conductive layer and a dielectric layer. The stacked and alternating conductive and dielectric layers are also referred herein to as a stack structure, e.g., a memory stack 348. The memory stack 348 and via contacts 324 and 342 may be coplanar. Thus, the via contacts 324 and 342 may also be called "array contacts" because they are coplanar with the memory cell array in the memory stack 348. According to several embodiments, the interleaved conductive and dielectric layers in the memory stack 348 are alternating vertically. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The adhesive layer may include a conductive material such as titanium nitride (TiN) which can improve adhesion between the gate electrode and the gate dielectric layer. The gate electrodes of the conductive layers extend laterally as word lines and may terminate in one or more stepped structures of the memory stack 348.

[0060] In some embodiments, the dummy pad 330 is isolated from the via contacts 324 by an isolation structure 328, compared to the pad 346 which is electrically connected to the corresponding interconnect structure 340 via two via contacts 344 and 342. In other words, in some embodiments, one of the two via contacts covering the dummy pad 330 (i.e., the one coplanar with the via contact 344) is replaced by the isolation structure 328, even if the distance between the interconnect structure 314 and the functional circuit 312 is too close without protection of the functional circuit 312's ESD circuit, in order to ensure electrical insulation between the dummy pad 330 and the interconnect structure 314 and avoid ESD damage to the functional circuit 312.

[0061] To isolate the dummy pad 330 from the interconnect structure 314, one or both of the two via contacts covering the dummy pad 330 can be replaced with a dielectric structure. As shown in Figures 3A and 3B, instead of removing the via contact in contact with the dummy pad 330, in other examples, the same result can be achieved by removing the other via contact (e.g., 324) in contact with the interconnect structure 314. Figure 4 shows a side section view of another semiconductor device 400 having a dummy pad 330 according to some aspects of the present disclosure. The semiconductor device 400 may be another example of the semiconductor device 200. For ease of explanation, the same components described above with respect to Figure 3A will not be repeated.

[0062] In accordance with the scope of this disclosure, the semiconductor device 400 may include a dielectric structure between the device layer 310 and the dummy pad 330 in the vertical direction (e.g., the z direction in Figure 4). The dielectric structure may extend in the transverse direction (e.g., the y direction in Figure 4) and the longitudinal direction (e.g., the z direction in Figure 4). In some embodiments shown in Figure 4, the dielectric structure includes a dielectric layer 401 within an interconnection layer 323. For example, the dielectric layer 401 may contain silicon oxide. The semiconductor device 400 may also include an interconnection structure 314 between the device layer 310 and the dielectric structure (e.g., the dielectric layer 401 in Figure 4) in the vertical direction (e.g., the z direction in Figure 4). The interconnection structure 314 may extend in the vertical direction (e.g., the z direction in Figure 4). As shown in Figure 4, according to some embodiments, the dielectric layer 401, the interconnection structure 314, and the dummy pad 330 are superimposed and are considered to be corresponding structures in this disclosure. In other words, for each dummy pad 330, the semiconductor device 400 may include a corresponding overlay dielectric layer 401 and interconnection structure 314.

[0063] Unlike the semiconductor device 300 in Figure 3A, the semiconductor device 400 may further include a via contact 402 that contacts below the dummy pad 330. In some embodiments, the via contact 402 extends vertically (e.g., in the z direction in Figure 4) through the isolation structure 328. The via contact 402 may include W. Since the via contact 402 also penetrates the semiconductor layer 326, it is sometimes referred to as a "through-silicon via (TSV)" in some examples. However, in contrast to the semiconductor device 300 in Figure 3A, which includes a via contact 324 that is above the interconnect structure 314 and contacts the interconnect structure, according to some embodiments, the semiconductor device 400 does not include a via contact 324, but instead includes a dielectric layer 401 between the via contact 402 and the interconnect structure 314. That is, the via contact 402 can be isolated from the interconnect structure 314 by the dielectric layer 401. Therefore, even if the device contacts 316 of the interconnect structure 314 are not far enough from the functional circuit 312 in the device layer 310 to prevent ESD damage to the functional circuit 312 via the interconnect structure 314, the dielectric layer 401 between the interconnect structure 314 and the via contacts 402 can still prevent ESD from propagating from the dummy pad 330 to the interconnect structure 314. In some embodiments, the thickness of the isolation structure 328 (e.g., thickness in the vertical direction) is between 1000 nm and 2000 nm (e.g., 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, 2000 nm, any range bounded by the lower end by any of these values, or any range defined by any two of these values).

[0064] In some embodiments, the lateral dimension of the isolation structure 328 (e.g., in the y-direction in Figure 4) is larger than the lateral dimension of the dummy pad 330 (e.g., in the y-direction in Figure 4). As a result, even if defects may form in the semiconductor layer 326, the increased size of the isolation structure 328 (e.g., BSTI) reduces the risk of burn-in between the dummy pad 330 and the semiconductor layer 326. In some embodiments, the distance d between the edge of the dummy pad 330 and the isolation structure 328 in the lateral direction (e.g., the y-direction in Figure 4) is greater than 1 μm, for example, between 1 μm and 5 μm (e.g., 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, any range bounded by the lower edge by any of these values, or any range defined by any two of these values).

[0065] Although not shown in the illustration, in some examples, both via contacts 324 and 402 covering the dummy pad 330 can be removed and replaced, for example, with an isolation structure 328 and a dielectric layer 401, thereby isolating the dummy pad 330 from the interconnect structure 314 by the isolation structure 328 and dielectric layer 401, and preventing ESD damage from the dummy pad 330 to the functional circuit 312.

[0066] Figure 5 shows a side cross-sectional view of yet another semiconductor device 500 having a dummy pad 330 according to some aspects of the present disclosure. The semiconductor device 500 may be an example of the semiconductor device 100. As shown in Figure 5, the semiconductor device 500 is a bonded chip including a first structure 302 and a second structure 304 stacked on top of each other in different planes in the vertical direction (e.g., the z direction) according to some embodiments. According to some embodiments, the first and second structures 302 and 304 are bonded at a bonding interface 306 between them.

[0067] As shown in Figure 5, the first structure 302 may include a substrate 308 which may contain silicon (e.g., single-crystal silicon), SiGe, GaAs, Ge, SOI, or any other suitable material. In some embodiments, the substrate 308 contains single-crystal silicon, which is part of the wafer on which the first structure 302 is manufactured, either at its original thickness or thinned. In some embodiments, the first substrate 302 contains, for example, polysilicon, which is a semiconductor layer replacing part of the wafer on which the first structure 302 is manufactured.

[0068] As shown in Figure 5, the first structure may include a device layer 310 on the substrate 308. In some embodiments, the device layer 310 includes a functional circuit 312 and an ESD circuit 502. In some embodiments, the semiconductor device 500 is a NAND flash memory device in which memory cells are formed within an array of NAND memory strings, and the functional circuit 312 is a peripheral circuit (also known as a control / sensor circuit) that facilitates the operation of the NAND memory strings and includes any suitable digital, analog, and / or mixed-signal circuits. For example, the peripheral circuit may include one or more of the following: a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output circuit, a charge pump, a voltage source or voltage generator, a current or voltage reference, any part of the aforementioned functional circuit (e.g., a sub-circuit), or any active or passive component of the circuit (e.g., a transistor, diode, resistor, or capacitor). The functional circuit 312 may use, for example, CMOS technology which can be implemented in a logic process at any suitable technology node.

[0069] The ESD circuit 502 can reduce the ESD voltage to below a certain limit using ESD suppression components. These components can be connected in parallel to the vulnerable line. When an ESD strike occurs, the ESD diode may be destroyed to create a low-impedance path, which may limit the peak voltage and current by diverting the current flow to ground. In one example, as shown in Figure 6A, the ESD circuit 502 may include a resistor R, a capacitor C, and a transistor Q. The resistor R and capacitor C may form a resistor-capacitor circuit (RC circuit), and the transistor Q may be a discharge transistor. When an electrostatic signal is input to electrostatic terminal A, the output terminal of the resistor-capacitor circuit may become logic high level, which can turn on the transistor Q and conduct ESD through the transistor Q. In another example, as shown in Figure 6B, the ESD circuit 502 may include a resistor R, a capacitor C, transistors Qa, Qb, and Qc. The resistor R and capacitor C may form an RC circuit, transistors Qa and Qb may form an inverter, and transistor Qc may be a discharge transistor. When an electrostatic signal is input to electrostatic terminal A, the output terminal of the resistor-capacitor circuit becomes a logic low level, the output terminal of the inverter becomes a logic high level, transistor Qc turns on, and ESD can conduct through transistor Qc.

[0070] As shown in Figure 5, in some embodiments, the first structure 302 further includes an interconnection layer 311 above the device layer 310 for transferring electrical signals to and from the device layer 310. The interconnection layer 311 may be perpendicular to the junction interface 306 and the device layer 310 (including the functional circuit 312 and the ESD circuit 502). The interconnection layer 311 may include a plurality of interconnections and one or more ILD layers. That is, the interconnection layer 311 may include transverse lines and via contacts in the plurality of ILD layers. Although not shown in Figure 5, it is understood that the functional circuit 312 in the device layer 310 may be electrically connected to any other suitable functional circuit via interconnections in the interconnection layer 311. The interconnections in the interconnection layer 311 may include, but are not limited to, conductive materials including W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer within the interconnection layer 311 may include, but not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnection within the interconnection layer 311 includes, for example, device contacts 316 within metal 3-5 (M3-M5) layers. The device contacts 316 may include Cu, which has relatively low resistivity (better electrical performance) among conductive metallic materials.

[0071] As shown in Figure 5, the first structure 302 may further include a bonding interface 306 and a bonding layer 313 located above it and in contact with the interconnection layer 311. The bonding layer 313 may include a plurality of bonding contacts 318 and a dielectric that electrically insulates the bonding contacts 318. The bonding contacts 318 may include, but are not limited to, conductive materials such as W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the bonding contacts 318 of the bonding layer 313 include Cu. The remaining region of the bonding layer 313 may be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 318 and the surrounding dielectric within the bonding layer 313 can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bonding between surfaces without using an intermediate layer such as solder or adhesive), and metal-metal (e.g., Cu-Cu) bonding and dielectric-dielectric (e.g., SiO2 to SiO2) bonding can be obtained simultaneously.

[0072] As shown in Figure 5, the second structure 304 may include a bonding layer 315 at the bonding interface 306, for example, on the opposite side of the bonding interface 306 from the bonding layer 313 of the first structure 302. The bonding layer 315 may include a plurality of bonding contacts 320 and a dielectric that electrically insulates the bonding contacts 320. The bonding contacts 320 may include a conductive material such as Cu. The remaining area of ​​the bonding layer 315 can be formed of a dielectric material such as silicon oxide. The bonding contacts 320 and the surrounding dielectric within the bonding layer 315 can be used for hybrid bonding. In some embodiments, the bonding interface 306 is the location where the bonding layers 313 and 315 face each other and are bonded. In practice, the bonding interface 306 can be a layer with a specific thickness that includes the upper end face of the bonding layer 313 of the first structure 302 and the lower end face of the bonding layer 315 of the second structure 304.

[0073] As shown in Figure 5, the second structure 304 may further include an interconnection layer 323 above the junction layer 315 for transferring electrical signals. The interconnection layer 323 may include multiple interconnections, such as MEOL interconnections and BEOL interconnections. Although not shown in Figure 5, in some examples the interconnections within the interconnection layer 323 also include local interconnections, such as bit line contacts and word line contacts. The interconnection layer 323 may further include one or more ILD layers on which transverse lines and via contacts may be formed. The interconnections within the interconnection layer 323 may include, but are not limited to, conductive materials such as W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers within the interconnection layer 323 may include, but are not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnections within the interconnection layer 323 include W, which has a relatively high thermal history (suitable for high-temperature processes) and good quality (reduced defects, e.g., voids) among conductive metallic materials.

[0074] As shown in Figure 5, the second structure 304 may further include a semiconductor layer 326 above the interconnection layer 323. The semiconductor layer 326 may include a semiconductor material. In some embodiments, the semiconductor layer 326 is a thinned silicon substrate having single-crystal silicon. In some embodiments, the semiconductor layer 326 is a deposited polysilicon layer replacing at least a portion of the silicon substrate having single-crystal silicon. In some examples, it is understood that trench isolation and doped regions (not shown) may also be formed within the semiconductor layer 326. In some examples, it is understood that the semiconductor layer 326 may include a plurality of vertical semiconductor layers with dielectric layers formed between them.

[0075] As shown in Figure 5, the second structure 304 may further include a pad-out layer 327 above the semiconductor layer 326. The pad-out layer 327 may include a dummy pad 330, one or more ILD layers 332 (e.g., a silicon oxide layer and a silicon nitride layer), and a protective layer 334 (e.g., a polyimide layer) on the upper end face of the semiconductor device 500. The pad-out layer 327 and interconnection layer 323 may be formed on both sides of the semiconductor layer 326. In some embodiments, an opening 336 is formed through the protective layer 334 and ILD layer 332 in the pad-out layer 327 to expose the dummy pad 330, thereby allowing wire bonding to be performed on the upper end face of the dummy pad 330.

[0076] In accordance with the scope of this disclosure, the semiconductor device 500 may include an interconnection structure 314 between the device layer 310 and the dummy pad 330 in the vertical direction (e.g., the z-direction in Figure 5), and the dummy pad 330 is connected to the ESD circuit 502 in the device layer 310 at least via the interconnection structure 314. On the other hand, according to some embodiments, the dummy pad 330 is decoupled from the functional circuit 312 in the device layer 310. The interconnection structure 314 may extend in the vertical direction (e.g., the z-direction in Figure 5). The semiconductor layer 326 may be positioned between the dummy pad 330 and the interconnection structure 314 in the vertical direction. As shown in Figure 5, according to some embodiments, the interconnection structure 314 and the dummy pad 330 are superimposed and are considered to be corresponding structures in this disclosure. In other words, for each dummy pad 330, the semiconductor device 500 may include a corresponding overlay interconnection structure 314.

[0077] As shown in Figure 5, the interconnection structure 314 may include bonding contacts 320 and 318 in bonding layers 315 and 313, and device contacts 316 in the interconnection layer 311 of the first structure 302. According to some embodiments, the device contacts 316 are located between the bonding interface 306 and the device layer 310, and the bonding interface 306 is located vertically between the dummy pad 330 and the device layer 310. In some embodiments, it is understood that the interconnection structure 314 may further include an interconnection 322 in the interconnection layer 323 of the second structure 304.

[0078] As shown in Figure 5, the second structure 304 of the semiconductor device 500 may further include a via contact 324 extending vertically within the interconnection layer 323. The via contact 324 may include W. In some embodiments, the via contact 324 is in contact with the interconnection structure 314. That is, the via contact 324 may be positioned between the dummy pad 330 and the interconnection structure 314 and connected to the interconnection structure 314. The second structure 304 of the semiconductor device 500 may further include a spacer 504 in the semiconductor layer 326 and a via contact 402 extending vertically through the spacer 504. The spacer 504 may include a dielectric material such as silicon oxide or silicon nitride. In some embodiments, the via contact 402 is in contact with the dummy pad 330 and the via contact 324 at opposing ends. That is, the via contact 402 can electrically connect the dummy pad 330 and the via contact 324. The via contact 402 may also include W. As a result, the dummy pad 330 can be electrically connected to the ESD circuit 502 in the device layer 310 via at least the interconnection structure 314 and via contacts 324 and 402. Thus, ESD from the dummy pad 330 can be propagated to the ESD circuit 502 and mitigated by the ESD circuit 502, preventing damage to the functional circuit 312.

[0079] Figures 7A to 7E illustrate manufacturing processes for forming semiconductor devices having dummy pads according to some embodiments of the present disclosure. Figures 8A to 8E illustrate manufacturing processes for forming other semiconductor devices having dummy pads according to some embodiments of the present disclosure. Figure 9 shows a flowchart of Method 900 for forming semiconductor devices having dummy pads according to some embodiments of the present disclosure. Examples of semiconductor devices depicted in Figures 7A to 7E, Figures 8A to 8E, and Figure 9 include semiconductor devices 300, 301, and 400 depicted in Figures 3A, 3B, and 4. Hereinafter, Figures 7A to 7E, Figures 8A to 8E, and Figure 9 will be described collectively. The steps shown in Method 900 are not exhaustive, and it should be understood that other steps may be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in an order different from the order shown in Figure 9.

[0080] Referring to Figure 9, Method 900 begins in step 902, where a device layer containing functional circuits is formed. As shown in Figures 7A and 8A, a device layer 710 containing functional circuits 712 and 738 is formed on a silicon substrate 708 having single-crystal silicon. Functional circuits 712 and 738 can be formed by a plurality of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions are formed within the silicon substrate 708 by ion implantation and / or thermal diffusion, serving, for example, as wells and source / drain regions for transistors within the functional circuits 712 and 738. In some embodiments, isolated regions (e.g., STIs) are also formed within the silicon substrate 708 by wet / dry etching and thin film deposition.

[0081] Method 900 proceeds to step 904, as shown in Figure 9, where an interconnect structure is formed on the device layer and disconnected from the functional circuit. In some embodiments, other interconnect structures are formed on the device layer and connected to the functional circuit. The interconnect structure and other interconnect structures can be formed by the same process.

[0082] As shown in Figures 7A and 8A, the interconnection layer 711 is formed above the device layer 710. The interconnection layer 711 may include MEOL and / or BEOL interconnections within multiple ILD layers, such as device contacts 716, so as to make electrical connections to the functional circuit 738 but not to the functional circuit 712. That is, device contacts 716 can connect to the functional circuit 738 but are disconnected from the functional circuit 712. In some embodiments, the interconnection layer 711 includes multiple ILD layers and interconnections formed by multiple processes. For example, interconnections within the interconnection layer 711 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnections may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in Figures 7A and 7B can be collectively referred to as the interconnection layer 711. In some embodiments, interconnects such as device contacts 716 within the interconnection layer 711 include Cu, which has relatively low resistivity among conductive metallic materials.

[0083] As shown in Figures 7A and 8A, a bonding layer 713 is formed above the interconnection layer 711. The bonding layer 713 may include a plurality of bonding contacts 718 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the upper surface of the interconnection layer 711 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts 718 that penetrate the dielectric layer and contact the interconnection in the interconnection layer 711 can then be formed by first patterning contact holes penetrating the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer before depositing the conductor. For example, an adhesive layer can improve the adhesion of conductors to avoid defects, a barrier layer can prevent metal ions (e.g., Cu ions) from diffusing from the conductor to other structures to cause contamination, and a seed layer can facilitate the deposition of conductors (e.g., Cu) in contact holes to improve deposition quality and speed.

[0084] As shown in Figures 7A and 8A, a stack structure such as a memory stack 748, which includes alternately arranged conductive layers and dielectric layers, is formed on a silicon substrate 726. To form the memory stack 748, in some embodiments, a dielectric stack (not shown), which includes alternately arranged sacrificial layers (not shown) and dielectric layers, is formed on the silicon substrate 726. In some embodiments, each sacrificial layer includes a layer of silicon nitride, and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack 748 can then be formed by a gate replacement process, for example, by replacing the sacrificial layers with conductive layers using wet / dry etching of the sacrificial layers with respect to the dielectric layers, and filling the resulting recesses with conductive layers. In some embodiments, each conductive layer includes a metal layer, such as a layer of W. In some examples, it is understood that the memory stack 748 may be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some embodiments, a pad oxide layer containing silicon oxide (e.g., thermally grown local oxidation (LOCOS) of silicon) is formed between the memory stack 748 and the silicon substrate 726.

[0085] As shown in Figures 7A and 8A, NAND memory strings 750 are formed, each extending vertically through the memory stack 748. In some embodiments, the manufacturing process for forming the NAND memory strings 750 includes using wet etching, such as dry etching and / or deep reactive ion etching (DRIE), to form channel holes in the silicon substrate 726 through the memory stack 748 (or dielectric stack), and then filling the channel holes with multiple layers, such as memory films (e.g., tunnel layers, storage layers, and blocking layers) and semiconductor layers, using thin-film deposition processes such as ALD, CVD, PVD, or any combination thereof. Details of the manufacturing of the NAND memory strings 750 may vary depending on the type of channel structure of the NAND memory strings 750, and are therefore not detailed for the sake of clarity.

[0086] As shown in Figures 7A and 8A, a bonding layer 715 is formed above the memory stack 748. The bonding layer 715 may include a plurality of bonding contacts 720 surrounded by a dielectric. In some embodiments, a dielectric layer is deposited on the upper surface of the memory stack 748 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The bonding contacts 720 penetrating the dielectric layer can then be formed by first patterning contact holes penetrating the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some embodiments, filling the contact holes includes depositing an adhesive layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0087] As shown in Figures 7A and 8A, the silicon substrate 726 and the components formed thereon (e.g., the memory stack 748 and the NAND memory string 750 formed through it) are inverted. The downward-facing bonding layer 715 is bonded to the upward-facing bonding layer 713, i.e., bonded in a face-to-face manner, thereby forming a bonding interface 706. That is, the silicon substrate 708 and the components formed thereon can be bonded to the silicon substrate 726 and the components formed thereon, face-to-face, such that the bonding contacts 718 of the bonding layer 713 contact the bonding contacts 720 of the bonding layer 715 at the bonding interface 706. In some embodiments, processing steps, such as plasma treatment, wet treatment and / or heat treatment, are applied to the bonding surface before bonding. In some embodiments, the silicon substrate 726 is thinned after bonding to form a thinned silicon substrate, also referred to herein as a semiconductor layer 726.

[0088] As a result of bonding, for example, hybrid bonding, the bonding contacts 718 and 720 on both sides of the bonding interface 706 can be intermixed. After bonding, the bonding contacts 718 in bonding layer 713 and the bonding contacts 720 in bonding layer 715 can be aligned and in contact with each other to form two interconnection structures 714 and 740. The interconnection structure 714 or 740 may include the bonding contacts 718 and 720 across the bonding interface 706 and the device contact 716. As shown in Figures 7A and 8A, the interconnection structure 714 is formed on the device layer 710 and disconnected from the functional circuit 712, while the interconnection structure 740 is formed on the device layer 710 and connected to the functional circuit 738.

[0089] Method 900 proceeds to step 906, as shown in Figure 9, where a first via contact is formed on an interconnect structure and connected to the interconnect structure. In some embodiments, there are other first via contacts on other interconnect structures and connected to other first via contacts. The first via contact and other first via contacts can be formed by the same process.

[0090] As shown in Figure 7A, prior to bonding, via contacts 724 and 742 are formed by the same process as, for example, forming word line contacts via a memory stack 748. Subsequently, via contacts 724 and 742 can be formed through the dielectric layer by first patterning contact holes that penetrate the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W). In some embodiments, filling the contact holes involves depositing an adhesive layer, a barrier layer, and / or a seed layer before depositing the conductor. After bonding, via contact 724 can be connected to an interconnect structure 714 and formed on the interconnect structure 714, as shown in Figure 7A. Similarly, via contact 742 can be connected to an interconnect structure 740 and formed on the interconnect structure 740.

[0091] Method 900 proceeds to step 908, as shown in Figure 9, where an isolation structure is formed on the first via contact. In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, exposing the first via contact and other first via contacts, and a dielectric layer is deposited to fill the trench.

[0092] As shown in Figure 7A, a portion of the semiconductor layer 726 is removed to expose one end of the via contacts 724 and 742 and form a trench 727. The trench 727 can be formed by etching the semiconductor layer 726, for example, using dry etching and / or wet etching, to remove a portion of the semiconductor layer 726 covering the via contacts 724 and 742 until the via contacts 724 and 742 are exposed.

[0093] As shown in Figure 7B, a dielectric layer is filled into the trench 727 (shown in Figure 7A). For example, the dielectric layer, such as silicon oxide, may be deposited to fill the trench 727 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, as shown in Figure 7B, the isolation structure 728 can be formed on the via contacts 724 and 742 as part of the deposited dielectric layer.

[0094] In some embodiments, a second via contact is formed on and in contact with another first via contact, extending through the separation structure. To form the second via contact, in some embodiments, a portion of the separation structure is removed to create a hole that exposes another first via contact rather than the first via contact, and a metal layer is deposited to fill the hole. The metal layer may contain W.

[0095] As shown in Figure 7C, a hole 746 is formed by removing a portion of the isolation structure 728 to expose one end of the via contact 742, but not the via contact 724. The hole 746 may be formed by etching the isolation structure 728, for example, using dry etching and / or wet etching, to selectively remove a portion of the isolation structure 728 covering the via contact 742, rather than the via contact 724, until the via contact 742 is exposed. First, an etching mask can be patterned using a photolithography process to expose only the portion of the isolation structure 728 that covers the via contact 742 but not the via contact 724. The etching mask can then protect the portion of the isolation structure 728 covering the via contact 724 during the etching process. In some examples, it is understood that other holes 746 may also be formed by the same process that forms the hole 747 to expose, for example, the source end of a slit structure or a component in the memory stack 748, such as a NAND memory string 750.

[0096] As shown in Figure 7D, the hole 746 (shown in Figure 7C) is filled with a metal layer such as W. For example, the hole 746 can be filled by depositing a metal layer such as W by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, the via contact 744 can be formed on the via contact 742, penetrating the isolation structure 728 in contact with it, as shown in Figure 7D. In contrast, as shown in Figure 7D, a via contact cannot be formed on the via contact 724 in contact with it. In some examples, it is understood that other via contacts 749 may also be formed by the same process that forms the via contact 744, for example, on the source end of a slit structure or on a component in the memory stack 748, such as a NAND memory string 750, in contact with it.

[0097] Method 900 proceeds to step 910, as shown in Figure 9, where a dummy pad is formed on a separation structure and separated from the first via contact by the separation structure. In some embodiments, a pad is formed on a second via contact in contact with it. The dummy pad and the pad can be formed by a similar process.

[0098] As shown in Figure 7D, a pad layer 729, such as aluminum, is deposited on the via contact 744. For example, the metal layer, such as aluminum, can be deposited on the via contacts 744 and 749 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0099] As shown in Figure 7E, the pad layer 729 (shown in Figure 7D) is patterned to form dummy pads 730 and 745. Pad 745 can be formed on and in contact with via contact 744, and thus can be electrically connected to the functional circuit 738 in the device layer 710 via via contacts 744 and 742 and the interconnect structure 740. In contrast, dummy pad 730 can be formed on the isolation structure 728 and can be isolated from the via contact 724 by the isolation structure 728. Thus, dummy pad 730 can be electrically isolated from the interconnect structure 714. To form dummy pads 730 and 745, a patterning process (e.g., photolithography and dry / wet etching of the pad layer 729) can be performed on the pad layer 729. Next, a dielectric layer 732 (for example, containing silicon nitride) and a protective layer 734 (for example, containing polyimide) can be formed on the dummy pads 730 and 745. Subsequently, a patterning process can be performed to form openings 736 and 746 that penetrate the dielectric layer 732 and protective layer 734, exposing the dummy pads 730 and 745, respectively.

[0100] In some examples, it is understood that, unlike step 906, a dielectric layer is formed on the interconnect structure, where a first via contact is formed on the interconnect structure and connected to the interconnect structure.

[0101] As shown in Figure 8A, a dielectric layer 801 is formed on the interconnection structure 714. That is, according to some embodiments, via contacts 742 are formed only on the interconnection structure 740 and connected to the interconnection structure 714, but are not formed on the interconnection structure and are not connected to the interconnection structure.

[0102] In some embodiments, the isolation structure is formed on another first via contact. In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, exposing another first via contact, and a dielectric layer is deposited to fill the trench.

[0103] As shown in Figure 8A, a trench 727 is formed by removing a portion of the semiconductor layer 726 to expose one end of the via contact 742. The trench 727 can be formed by etching the semiconductor layer 726, for example, using dry etching and / or wet etching, to remove a portion of the semiconductor layer 726 covering the via contact 742 until the via contact 742 is exposed.

[0104] As shown in Figure 8B, a dielectric layer is filled into the trench 727 (shown in Figure 8A). For example, the dielectric layer, such as silicon oxide, may be deposited to fill the trench 727 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Thus, the isolation structure 728 can be formed on the via contact 742 as part of the deposited dielectric layer, as shown in Figure 8B.

[0105] In some embodiments, a second via contact is formed that extends through the separation structure. In some embodiments, another second via contact is formed on and connected to another first via contact and extends through the separation structure. To form the second via contact and the other second via contact, in some embodiments, a portion of the separation structure is removed to form a hole that penetrates the separation structure, and a metal layer is deposited to fill the hole. The metal layer may contain W.

[0106] As shown in Figure 8C, holes 746 and 802 are formed by removing a portion of the isolation structure 728. Hole 746 can expose one end of a via contact 742, and hole 802 can align with the interconnect structure 714. Holes 746 and 802 can be formed by etching the isolation structure 728 using dry etching and / or wet etching to selectively remove, for example, a portion of the isolation structure 728 that covers the via contact 742 and a portion of the isolation structure 728 that aligns with the interconnect structure 714 until the via contact 742 is exposed. The etching mask can be initially patterned using a photolithography process to expose the portion of the isolation structure 728 that covers the via contact 742 and the portion of the isolation structure 728 that aligns with the interconnect structure 714. In some examples, it is understood that other holes 747 may also be formed by the same process that forms holes 746 and 802 to expose, for example, the source end of a slit structure or components within the memory stack 748, such as a NAND memory string 750.

[0107] As shown in Figure 8D, holes 746 and 802 (shown in Figure 8C) are filled with a metal layer such as W. For example, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, can be used to deposit a metal layer such as W and fill holes 746 and 802. Thus, via contact 744 can be formed on via contact 742 via a separation structure 728 in contact with it, as shown in Figure 8D. Another via contact 804 can be formed penetrating the separation structure 728 and landing on the dielectric layer 801, as shown in Figure 8D, covering the interconnect structure 714. In some examples, it is understood that another via contact 749 can also be formed by the same process that forms via contacts 744 and 804, for example, on the source end of a slit structure or on a component in a memory stack 748 such as a NAND memory string 750, in contact with it.

[0108] In some embodiments, a dummy pad is formed on and in contact with a second via contact. In some embodiments, a pad is formed on and in contact with another second via contact. The dummy pad and the pad can be formed by a similar process.

[0109] As shown in Figure 8D, a pad layer 729, such as aluminum, is deposited on via contacts 744 and 804. For example, a metal layer, such as aluminum, can be deposited on via contacts 744, 804, and 749 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0110] As shown in Figure 8E, the pad layer 729 (shown in Figure 8D) is patterned to form dummy pads 730 and 745. Pad 745 can be formed in contact with via contact 744 and thus electrically connected to the functional circuit 738 in the device layer 710 via via contacts 744 and 742 and the interconnect structure 740. Dummy pad 730 can be formed in contact with via contact 804. However, dummy pad 730 and via contact 804 can be isolated from the interconnect structure 714 by the dielectric layer 801. Thus, dummy pad 730 can be electrically isolated from the interconnect structure 714. To form dummy pads 730 and 745, a patterning process (e.g., photolithography and dry / wet etching of the pad layer 729) can be performed on the pad layer 729. Next, a dielectric layer 732 (for example, containing silicon nitride) and a protective layer 734 (for example, containing polyimide) are formed on the dummy pad 730 and pad 745. Then, a patterning process is performed to form openings 736 and 746 that penetrate the dielectric layer 732 and protective layer 734, thereby exposing the dummy pad 730 and pad 745, respectively.

[0111] The foregoing description of specific embodiments may be readily modified and / or adapted for various uses. Such adaptations and modifications are therefore intended to be within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein.

[0112] The scope of this disclosure should not be limited by any of the typical embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. The device layer, Dummy pad and A dielectric structure extending vertically between the device layer and the dummy pad, An interconnection structure extending vertically between the device layer and the dielectric structure, wherein the dielectric structure, the interconnection structure, and the dummy pad are superimposed on the interconnection structure, The semiconductor layer between the dummy pad and the interconnection structure, Equipped with, The dielectric structure comprises an isolation structure within the semiconductor layer, The aforementioned separation structure is an embedded shallow trench isolation (BSTI). Semiconductor devices.

2. The semiconductor device according to claim 1, wherein the lateral dimension of the separation structure is greater than the lateral dimension of the dummy pad.

3. The semiconductor device according to claim 1, further comprising a first via contact that contacts the interconnection structure and is separated from the dummy pad by the separation structure.

4. The semiconductor device according to claim 3, wherein the first via contact contains tungsten.

5. The system further comprises a second via contact that contacts the dummy pad and extends in the vertical direction, The dielectric structure comprises a dielectric layer between the second via contact and the interconnection structure. The semiconductor device according to claim 1.

6. The semiconductor device according to claim 5, wherein the second via contact is isolated from the interconnection structure by the dielectric layer.

7. The semiconductor device according to claim 5, wherein the second via contact contains tungsten.

8. The semiconductor device according to claim 1, further comprising a bonding interface between the dummy pad and the device layer, and the interconnection structure comprising bonding contacts at the bonding interface.

9. The semiconductor device according to claim 8, wherein the interconnection structure further comprises a device contact between the junction interface and the device layer.

10. pads and, A second via contact that contacts the aforementioned pad, Another first via contact that contacts the other second via contact, The other first via contact and the other interconnection structure that contacts the device layer A semiconductor device according to any one of claims 1 to 9, further comprising the above.

11. The aforementioned pad and the aforementioned dummy pad are on the same plane, The aforementioned interconnection structure and the other interconnection structure are on the same plane. The semiconductor device according to claim 10.

12. A device layer comprising an electrostatic discharge (ESD) circuit and a functional circuit, A dummy pad disconnected from the aforementioned functional circuit, An interconnection structure between the device layer and the dummy pad, wherein the dummy pad is connected to the ESD circuit at least via the interconnection structure, The semiconductor layer between the dummy pad and the interconnection structure, Equipped with, A separation structure is provided within the semiconductor layer, The aforementioned separation structure is an embedded shallow trench isolation (BSTI). Semiconductor devices.

13. The semiconductor device according to claim 12, further comprising a first via contact located between the dummy pad and the interconnection structure and connected to the interconnection structure.

14. The semiconductor layer between the dummy pad and the first via contact, The spacer in the semiconductor layer, A second via contact that contacts the dummy pad and extends through the spacer, The semiconductor device according to claim 13, further comprising the above.

15. A method for forming a semiconductor device, The steps include forming a device layer with a functional circuit, The steps include forming an interconnection structure on the device layer that is disconnected from the functional circuit, The steps include forming a first via contact on the interconnection structure that is connected to the interconnection structure, The steps of forming a separation structure on the first via contact and The steps include forming a dummy pad on the separation structure which is separated from the first via contact by the separation structure, Includes, The aforementioned separation structure is an embedded shallow trench isolation (BSTI). method.

16. The steps include forming other interconnection structures connected to the functional circuit on the device layer, The steps include forming another first via contact on the other interconnection structure that is connected to the other interconnection structure, The steps include forming a second via contact on the other first via contact, which contacts the other first via contact and extends through the separation structure, The steps include forming a pad on the second via contact that contacts the second via contact, The method according to claim 15, further comprising:

17. The step of forming the separation structure is, The steps include removing a portion of the semiconductor layer to form a trench and exposing the first via contact and the other first via contact, The steps include depositing a dielectric layer to fill the trench, The method according to claim 16, including the method described in claim 16.

18. The step of forming the second via contact described above is: A step of removing a portion of the separation structure in order to form a hole to expose the other first via contact instead of the first via contact, The steps include depositing a metal layer to fill the aforementioned hole, The method according to claim 16, including the method described in claim 16.

19. The method according to claim 18, wherein the metal layer contains tungsten.

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