Semiconductor equipment

Abstract

To provide a semiconductor device with a smaller occupied area.SOLUTION: A semiconductor device includes a first transistor including a first oxide semiconductor, a second transistor including a second oxide semiconductor, a capacitor element, a first insulator, and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are disposed so as to be embedded in the first insulator. The second conductor is disposed in contact with an upper surface of the first conductor and an upper surface of a gate of the first transistor. The second insulator is disposed on the second conductor and the first insulator and the third conductor is disposed covering the second conductor through the second insulator.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, method, or method of manufacture. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.

[0003] In this specification, the term "semiconductor device" refers to any device that functions by utilizing semiconductor properties. Therefore, semiconductor elements such as transistors and diodes, and circuits containing semiconductor elements, are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also include semiconductor elements or semiconductor circuits. [Background technology]

[0004] In recent years, transistors using oxide semiconductors or metal oxides in the channel formation region (Oxide Semiconductor transistors, hereinafter referred to as OS transistors) have attracted attention (Patent Document 1).

[0005] OS transistors have a very low off-current. Taking advantage of this, non-volatile memory using OS transistors is disclosed in Patent Documents 2 and 3. Non-volatile memory using OS transistors has no limit on the number of times data can be rewritten, and also consumes little power when rewriting data. Furthermore, Patent Document 3 discloses an example in which the memory cell of non-volatile memory is composed solely of OS transistors.

[0006] In this specification, non-volatile memory using OS transistors may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to RAM having gain cell type (2T type, 3T type) memory cells. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Patent Document 3] Japanese Patent Publication No. 2016-115387 [Overview of the project] [Problems that the invention aims to solve]

[0008] One embodiment of the present invention aims to provide a semiconductor device with a small footprint. Alternatively, one embodiment of the present invention aims to provide a semiconductor device that can be highly integrated. Alternatively, one embodiment of the present invention aims to provide a semiconductor device with a large memory capacity. Alternatively, one embodiment of the present invention aims to provide a semiconductor device with low manufacturing costs. Alternatively, one embodiment of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one embodiment of the present invention aims to provide a novel semiconductor device.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0010] One aspect of the present invention comprises a first transistor, a second transistor, a capacitive element, a first insulator, and a first conductor, wherein the first transistor comprises a first oxide semiconductor, a first gate, and a first gate insulator, the second transistor comprises a second oxide semiconductor, a second gate, and a second gate insulator, and the capacitive element comprises a second conductor, a third conductor, and a second insulator, wherein the first insulator is disposed on the first oxide semiconductor and the second oxide semiconductor, and the first insulator has a first opening formed that reaches the first oxide semiconductor and the second oxide A semiconductor device is formed in which a second opening reaching a semiconductor is formed, a third opening reaching either the source or drain of a second transistor is formed, a first gate insulator and a first gate are placed in the first opening, a second gate insulator and a second gate are placed in the second opening, a first conductor is placed in the third opening, the second conductor is placed in contact with the upper surface of the first conductor and the upper surface of the first gate, the second insulator is placed on the second conductor and the first insulator, and the third conductor is placed covering the second conductor via the second insulator.

[0011] In the above, it is preferable that the second conductor is positioned to cover the first gate.

[0012] Furthermore, in the above configuration, a portion of the first gate may be exposed from the second conductor, and a portion of the first gate may be in contact with the second insulator.

[0013] Furthermore, in the above, it is preferable that the channel length direction of the first transistor and the channel length direction of the second transistor are approximately parallel. Furthermore, in the above, it is preferable that the extension direction of the third conductor is approximately perpendicular to the channel length direction of the first transistor.

[0014] Furthermore, in the above, it is preferable that a fourth conductor is in contact with the upper surface of the second gate, and the extension direction of the fourth conductor is approximately perpendicular to the channel length direction of the second transistor. Furthermore, in the above, it is preferable that the fourth conductor is superimposed on the first oxide semiconductor via the first insulator.

[0015] Another aspect of the present invention comprises first to fourth transistors, a first oxide semiconductor, a second oxide semiconductor, a first capacitive element, a second capacitive element, a first insulator, a second insulator, a first conductor, and a second conductor, wherein the first and third transistors are formed from the first oxide semiconductor, and the second and fourth transistors are formed from the second oxide semiconductor, and the first transistor has a first gate and a first gate insulator, and the second transistor has a second gate and The first capacitor element has a third conductor and a fourth conductor, and the second capacitor element has a fifth conductor and a sixth conductor. The first capacitor is placed on a first oxide semiconductor and a second oxide semiconductor, and the first capacitor has a first opening and a second opening that reach the first oxide semiconductor and the second oxide semiconductor. A third opening and a fourth opening are formed, a fifth opening is formed that reaches either the source or drain of the second transistor, a sixth opening is formed that reaches either the source or drain of the fourth transistor, a first gate insulator and a first gate are placed in the first opening, a third gate insulator and a third gate are placed in the second opening, a second gate insulator and a second gate are placed in the third opening, a fourth gate insulator and a fourth gate are placed in the fourth opening, and A semiconductor device is provided, wherein a first conductor is placed in an opening 5, a second conductor is placed in an opening 6, a third conductor is placed in contact with the upper surface of the first conductor and the upper surface of the first gate, a fifth conductor is placed in contact with the upper surface of the second conductor and the upper surface of the third gate, a second insulator is placed on the third conductor, the fifth conductor and the first insulator, a fourth conductor is placed covering the third conductor via the second insulator, and a sixth conductor is placed covering the fifth conductor via the second insulator.

[0016] In the above, it is preferable that the first oxide semiconductor and the second oxide semiconductor each contain indium, element M (where M is one or more selected from gallium, aluminum, yttrium, and tin), and zinc. [Effects of the Invention]

[0017] One embodiment of the present invention can provide a semiconductor device with a small footprint. Alternatively, one embodiment of the present invention can provide a semiconductor device that can be highly integrated. Alternatively, one embodiment of the present invention can provide a semiconductor device with a large memory capacity. Alternatively, one embodiment of the present invention can provide a semiconductor device with low manufacturing costs. Alternatively, one embodiment of the present invention can provide a highly reliable semiconductor device. Alternatively, one embodiment of the present invention can provide a novel semiconductor device.

[0018] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0019] [Figure 1] Figure 1A is a circuit diagram of a semiconductor device according to one aspect of the present invention. Figure 1B is a top view of a semiconductor device according to one aspect of the present invention. [Figure 2] Figures 2A and 2B are top views of a semiconductor device according to one embodiment of the present invention. [Figure 3] Figures 3A and 3B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 4] Figure 4 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 5]Figure 5A is a diagram illustrating the classification of IGZO crystal structures. Figure 5B is a diagram illustrating the XRD spectrum of a CAAC-IGZO film. Figure 5C is a diagram illustrating the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 6] Figure 6 is a top view of a semiconductor device according to one aspect of the present invention. [Figure 7] Figures 7A and 7B are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 8] Figures 8A and 8B are circuit diagrams of a semiconductor device according to one aspect of the present invention. [Figure 9] Figure 9A is a block diagram illustrating an example configuration of a semiconductor device according to one aspect of the present invention. Figure 9B is a perspective view illustrating an example configuration of a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10 is a circuit diagram of a memory cell array according to one aspect of the present invention. [Figure 11] Figure 11 is a schematic diagram of a memory cell array according to one aspect of the present invention. [Figure 12] Figures 12A and 12B show timing charts of a memory cell array according to one embodiment of the present invention. [Figure 13] Figure 13 is a diagram showing various types of storage devices in a hierarchical structure. [Figure 14] Figures 14A to 14E illustrate an example of an application of a storage device according to one aspect of the present invention. [Figure 15] Figures 15A to 15H show an electronic device according to one aspect of the present invention. [Modes for carrying out the invention]

[0020] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and the repetition of their descriptions is omitted.

[0021] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings. For example, in the actual manufacturing process, resist masks and other materials may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for the sake of ease of understanding.

[0022] Furthermore, in drawings and other diagrams, some components may be omitted from the description to make the explanation easier to understand.

[0023] Furthermore, in this specification, the terms "electrode" and "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0024] Furthermore, in this specification, the term "terminal" in an electrical circuit refers to a part where current is input or output, voltage is input or output, or a signal is received or transmitted. Therefore, a part of the wiring or electrode may function as a terminal.

[0025] In this specification, the terms "above" and "below" do not necessarily mean that the relative positions of the components are directly above or below each other and that they are in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0026] Furthermore, the functions of source and drain can be interchanged depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to definitively determine which is the source and which is the drain. For this reason, in this specification, the terms source and drain may be used interchangeably.

[0027] Furthermore, in this specification, "electrically connected" includes both direct connections and connections made via "something that has some electrical function." Here, "something that has some electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in a real circuit there may be no physical connection point, and only wiring may extend.

[0028] In this specification and other documents, when count values ​​and measured values ​​are referred to as "identical," "same," "equal," or "uniform," unless otherwise explicitly stated, this refers to a margin of error of plus or minus 20%.

[0029] Furthermore, voltage often refers to the potential difference between a given potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential are considered interchangeable.

[0030] Even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it will possess the properties of an "insulator." Therefore, it is possible to replace "semiconductor" with "insulator." In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and a strict distinction between the two is difficult. Consequently, "semiconductor" and "insulator" as used herein may be interchangeable.

[0031] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently high, it will possess the properties of a "conductor." Therefore, it is possible to replace "semiconductor" with "conductor." In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and a strict distinction between the two is difficult. Consequently, "semiconductor" and "conductor" as used herein may be interchangeable.

[0032] Furthermore, ordinal numbers such as "first," "second," etc., in this specification are added to avoid confusion of constituent elements and do not indicate any order or rank, such as process order or layering order. In addition, even if an ordinal number is not used for a term in this specification, an ordinal number may be used in the claims to avoid confusion of constituent elements. In addition, even if an ordinal number is used for a term in this specification, a different ordinal number may be used in the claims. In addition, even if an ordinal number is used for a term in this specification, the ordinal number may be omitted in the claims, etc.

[0033] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited (also called the "conducting state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically disconnected (also called the "non-conducting state").

[0034] Furthermore, in this specification, "on-current" may refer to the current flowing between the source and drain when the transistor is in the "on" state. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is in the "off" state.

[0035] Furthermore, in this specification, the high power supply potential VDD (hereinafter also simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS," "L potential," or "L"). Also, VSS refers to a power supply potential that is lower than VDD. In addition, the ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, if VDD is the ground potential, then VSS is a potential lower than the ground potential, and if VSS is the ground potential, then VDD is a potential higher than the ground potential.

[0036] Furthermore, unless otherwise specified, the transistors described herein are enhancement-type (normally-off type) n-channel field-effect transistors. Therefore, their threshold voltage (also called "Vth") shall be greater than 0V. Also, unless otherwise specified, "supplying a high potential to the gate of the transistor" may be synonymous with "turning the transistor ON." Also, unless otherwise specified, "supplying a low potential to the gate of the transistor" may be synonymous with "turning the transistor OFF."

[0037] Furthermore, in this specification, "gate" refers to the gate electrode and part or all of the gate wiring. Gate wiring refers to wiring that electrically connects the gate electrode of at least one transistor to another electrode or another wire.

[0038] Furthermore, in this specification, "source" refers to a source region, a source electrode, and part or all of the source wiring. The source region refers to a region of the semiconductor layer whose resistivity is below a certain value. The source electrode refers to the conductive layer in the portion connected to the source region. The source wiring refers to wiring used to electrically connect the source electrode of at least one transistor to another electrode or another wiring.

[0039] Furthermore, in this specification, "drain" refers to a drain region, a drain electrode, and part or all of the drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is below a certain value. The drain electrode refers to the conductive layer in the portion connected to the drain region. The drain wiring refers to wiring used to electrically connect the drain electrode of at least one transistor to another electrode or another wiring.

[0040] Furthermore, in drawings and other diagrams, to make the potential of wiring and electrodes easier to understand, a "H" indicating a high potential or a "L" indicating a low potential may be added adjacent to the wiring and electrodes. In addition, a "H" or "L" enclosed in a box may be added to wiring and electrodes where a potential change has occurred. Also, if a transistor is in the off state, an "×" symbol may be added superimposed on the transistor.

[0041] Furthermore, generally speaking, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitive element" includes the case of the aforementioned "capacitance." That is, in this specification, the term "capacitive element" includes cases in which two electrodes face each other with an insulator in between, cases in which two wires face each other with an insulator in between, or cases in which two wires are arranged with an insulator in between.

[0042] Furthermore, in this specification, when the same reference numeral is used for multiple elements, and it is particularly necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring CL may be written as wiring CL[2].

[0043] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0044] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0045] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0046] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0047] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0048] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause problems such as an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0049] In this specification, oxidogenic nitrides are defined as compounds with a higher oxygen content than nitrogen content. Nitride oxides are defined as compounds with a higher nitrogen content than oxygen content.

[0050] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0051] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0052] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0053] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0054] (Embodiment 1) In this embodiment, the configuration of a memory cell 10 will be described with reference to Figures 1 to 8 as an example of a semiconductor device according to one aspect of the present invention. The memory cell 10 functions as part of a storage device and has a transistor 11, a transistor 12, and a capacitive element 13, and is electrically connected to wiring CL, wiring WL, wiring RBL, wiring SL, wiring WBL, wiring BGL1, and wiring BGL2.

[0055] Figure 1A is a circuit diagram of memory cell 10, and Figure 1B is a top view of memory cell 10. Figure 2A is a top view of Figure 1B with wiring CL removed. Figure 2B is a top view of Figure 1B with wiring CL, wiring WL, conductor 207, dashed lines A1-A2-A3, and dashed lines A4-A5-A6 removed. Note that some elements have been omitted from the top views of Figures 1B, 2A, and 2B for clarity.

[0056] Figure 3A is a cross-sectional view of the area indicated by the dashed lines A1-A2-A3 in Figures 1B and 2A. Here, the cross-sectional view shown A1-A2 is a cross-sectional view of transistor 12 in the channel length direction, and the cross-sectional view shown A2-A3 is a cross-sectional view of transistor 11 in the channel width direction. Figure 3B is a cross-sectional view of the area indicated by the dashed lines A4-A5-A6 in Figures 1B and 2A. Here, the cross-sectional view shown A4-A5 is a cross-sectional view of transistor 12 in the channel width direction, and the cross-sectional view shown A5-A6 is a cross-sectional view of transistor 11 in the channel length direction.

[0057] In drawings and other illustrations, arrows indicating the x, y, and z directions may be included. The x, y, and z directions are all orthogonal to each other. In this specification, one of the x, y, or z directions may be referred to as the "first direction" or "first direction." Additionally, one of the other two directions may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0058] <Example of semiconductor device configuration> First, an example of the circuit configuration of the memory cell 10 will be described. As shown in Figure 1A, the memory cell 10 comprises a transistor 11, a transistor 12, and a capacitive element 13. One of the source or drain of transistor 11 is electrically connected to wiring RBL, and the other is electrically connected to wiring SL. The back gate of transistor 11 is electrically connected to wiring BGL1. One of the source or drain of transistor 12 is electrically connected to wiring WBL, and the other is electrically connected to the gate of transistor 11. In this specification, the node or wiring that electrically connects the gate of transistor 11 and the other of the source or drain of transistor 12 may be called node FN. The gate of transistor 12 is electrically connected to wiring WL, and its back gate is electrically connected to wiring BGL2.

[0059] As shown in Figure 1A, it is preferable that transistors 11 and 12 are arranged on the same plane, and that the capacitive element 13 is provided on top of transistors 11 and 12. In other words, it is preferable that the capacitive element 13 is arranged so as to overlap transistors 11 and 12 in the z-axis direction. With this configuration, the capacitive element 13 can be provided without significantly increasing the area of ​​transistors 11 and 12. Therefore, the occupied area of ​​the memory cell 10 can be reduced. This makes it possible to achieve high integration of the semiconductor device and provide a semiconductor device with a large memory capacity. Furthermore, it is possible to provide a semiconductor device with a low manufacturing cost per unit of memory capacity.

[0060] A wiring CL is placed on top of the capacitive element 13. Here, the wiring CL functions as the upper electrode of the capacitive element 13. In contrast, node FN functions as the lower electrode of the capacitive element 13. In other words, the capacitive element 13 constitutes a MIM (Metal-Insulator-Metal) capacitance. Alternatively, the memory cell 10 can be described as having the capacitive element 13 between node FN and wiring CL.

[0061] Memory cell 10 has the function of storing data by holding the potential (charge) written to node FN. Specifically, it supplies a potential to turn on transistor 12 to wiring WL, making wiring WBL and node FN conductive. Then, charge is supplied to node FN via wiring WBL to bring node FN to a predetermined potential. Subsequently, a potential is supplied to the gate of transistor 12 to turn it off. By turning off transistor 12, the charge written to node FN is held.

[0062] Furthermore, to read data stored in the memory cell 10, a constant potential (hereinafter sometimes referred to as the read potential) is applied to the wiring CL. When the read potential is supplied to the wiring CL, the transistor 11 turns on or off according to the potential written to node FN. In other words, the data stored in node FN of the memory cell 10 can be read as the on or off state of transistor 11.

[0063] The semiconductor layers of transistors 12 and 11 can be single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0064] Furthermore, the semiconductor layers used in the transistor may be stacked. When stacking semiconductor layers, semiconductors having different crystalline states may be used for each layer, or different semiconductor materials may be used for each layer.

[0065] In particular, it is preferable that transistor 12 is an OS transistor. Because oxide semiconductors have a band gap of 2 eV or more, the off-current is remarkably low. When an OS transistor is used for transistor 12, the charge written to node FN can be retained for a long period of time. Therefore, the capacitance required for the capacitive element 13 can be reduced. For this reason, by using an OS transistor for transistor 12, the occupied area of ​​the capacitive element 13 can be reduced. This makes it easier to arrange the capacitive element 13 on top of transistors 11 and 12, thus reducing the occupied area of ​​the memory cell 10. When an OS transistor is used for transistor 12, the memory cell 10 can be called an "OS memory".

[0066] OS memory can retain information written to it for more than a year, or even more than 10 years, even when the power supply is cut off. Therefore, OS memory can be considered non-volatile memory.

[0067] Furthermore, because the amount of charge written to OS memory does not change easily over a long period of time, OS memory can store not only binary (1-bit) information but also multi-level (multi-bit) information.

[0068] Furthermore, because OS memory writes charge to nodes via OS transistors, it does not require the high voltage necessary for conventional flash memory, enabling high-speed writing operations. Also, the erase operation performed before data rewriting, which is necessary for flash memory, is unnecessary for OS memory. In addition, since charge injection and extraction to the floating gate or charge trapping layer are not performed, the number of data write and read operations in OS memory can be virtually unlimited. Compared to conventional flash memory, OS memory exhibits less degradation and offers high reliability.

[0069] Furthermore, OS memory does not involve structural changes at the atomic level, unlike phase-change memory (PCM), magnetoresistive random access memory (MRAM), or resistance random access memory (ReRAM). Therefore, OS memory has superior rewrite endurance compared to phase-change memory, magnetoresistive random access memory, and resistance random access memory.

[0070] Furthermore, OS transistors exhibit almost no increase in off-current even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Also, the on-current does not easily decrease even in high-temperature environments. A memory device including OS memory operates stably and has high reliability even in high-temperature environments. For this reason, when configuring OS memory, it is preferable to use OS transistors for transistors 11 and 12. In addition, OS transistors have high dielectric strength between the source and drain. By using OS transistors in the transistors that make up a semiconductor device, a semiconductor device that operates stably and has good reliability even in high-temperature environments can be realized.

[0071] As shown in Figures 3A and 3B, the memory cell 10 includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, an insulator 216 on the insulator 214, an insulator 222 on the insulator 216, an insulator 224 on the insulator 222, an insulator 275 on the insulator 224, an insulator 280 on the insulator 275, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282. The insulators 212, 214, 216, 222, 224, 275, 280, 282, and 283 function as interlayer insulating films. Transistors 11 and 12 are provided in the layer between insulator 214 and insulator 282, and a capacitive element 13 is provided on insulator 280. Insulators 280 and 275 have openings that reach either the source or the drain of the transistor 12, and a conductor 240 is provided so as to be embedded in these openings. It is also preferable that an insulator 241 is provided in contact with the side surface of the conductor 240.

[0072] The transistor 11 includes a conductor 205 (conductors 205a, 205b, and 205c) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 230c, an oxide 243a, and an oxide 243b on the oxide 230b, a conductor 242a on the oxide 243a, a conductor 242b on the oxide 243b, an insulator 250 on the oxide 230c, and a conductor 260 (conductors 260a and 260b) located on the insulator 250 and overlapping with a part of the oxide 230b. In the following, oxides 230a, 230b, and 230c may be collectively referred to as oxide 230. Furthermore, oxides 243a and 243b are sometimes collectively referred to as oxide 243. Similarly, conductors 242a and 242b are sometimes collectively referred to as conductor 242.

[0073] Here, conductor 260 functions as the top gate, and conductor 205 functions as the back gate (wiring BGL1). Insulator 250 functions as the gate insulator of the top gate, and insulators 222 and 224 function as the gate insulators of the back gate. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0074] Furthermore, the insulator 275 covers the insulator 224, oxide 230a, oxide 230b, oxide 243, and conductor 242, and the insulator 280 is provided in contact with the upper surface of the insulator 275. The insulator 280 and the insulator 275 are provided with openings that reach oxide 230b and the insulator 224, and these openings are provided superimposed in the region between conductor 242a and conductor 242b.

[0075] As shown in Figures 2B, 3A, and 3B, oxide 230c, insulator 250, and conductor 260 are arranged within the opening. Thus, oxide 230c is provided in contact with the upper surface of insulator 224, the side surface of oxide 230a, the upper and side surfaces of oxide 230b, the side surfaces of oxide 243a and oxide 243b, the side surfaces of conductor 242a and conductor 242b, the side surface of insulator 275, and the side surface of insulator 280. In addition, insulator 250 is provided in contact with the upper and side surfaces of oxide 230c, and conductor 260 is provided in contact with the upper and side surfaces of insulator 250. Furthermore, the upper surface of conductor 260, the uppermost surface of insulator 250, and the uppermost surface of oxide 230c are arranged to roughly coincide with the upper surface of insulator 280.

[0076] This structure allows the conductor 260, the insulator 250, and the oxide 230c to be formed self-aligningly so as to be embedded in the openings formed in the insulator 280, etc. By forming the conductor 260, etc. in this way, the conductor 260 can be placed in the region between the conductors 242a and 242b without the need for alignment.

[0077] Furthermore, the transistor 12 includes a conductor 206 (conductors 206a, 206b, and 206c) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 206, an insulator 224 on the insulator 222, an oxide 231a on the insulator 224, an oxide 231b on the oxide 231a, an oxide 231c, an oxide 245a, and an oxide 245b on the oxide 231b, a conductor 244a on the oxide 245a, a conductor 244b on the oxide 245b, an insulator 251 on the oxide 231c, and a conductor 261 (conductors 261a and 261b) located on the insulator 251 and overlapping with a portion of the oxide 231b. In the following, oxides 231a, 231b, and 231c may be collectively referred to as oxide 231. Also, oxides 245a and 245b may be collectively referred to as oxide 245. Furthermore, conductors 244a and 244b may be collectively referred to as conductor 244.

[0078] Furthermore, transistor 12 has the same configuration as transistor 11. Therefore, conductor 206 is formed in the same layer as conductor 205, oxide 231 as oxide 230, insulator 251 as insulator 250, and conductor 261 as conductor 260, and they have the same configuration. Therefore, in the following, the descriptions of conductor 206 as conductor 205, oxide 231 as oxide 230, insulator 251 as insulator 250, and conductor 261 as conductor 260 can be taken into consideration.

[0079] Here, conductor 261 functions as the top gate, and conductor 206 functions as the back gate (wiring BGL2). Insulator 251 functions as the gate insulator of the top gate, and insulators 222 and 224 function as the gate insulators of the back gate. Conductor 244a functions as either the source or the drain, and conductor 244b functions as either the source or the drain. At least a portion of the region of oxide 231 that overlaps with conductor 261 functions as a channel-forming region.

[0080] Furthermore, the insulator 275 covers the insulator 224, oxide 231a, oxide 231b, oxide 245, and conductor 244, and the insulator 280 is provided in contact with the upper surface of the insulator 275. The insulator 280 and the insulator 275 are provided with openings that reach the oxide 231b and the insulator 224, and these openings are provided superimposed in the region between the conductor 244a and the conductor 244b.

[0081] As shown in Figures 2B, 3A, and 3B, oxide 231c, insulator 251, and conductor 261 are arranged within the opening. Thus, oxide 231c is provided in contact with the upper surface of insulator 224, the side surface of oxide 231a, the upper and side surfaces of oxide 231b, the side surfaces of oxide 245a and oxide 245b, the side surfaces of conductor 244a and conductor 244b, the side surface of insulator 275, and the side surface of insulator 280. Insulator 251 is provided in contact with the upper and side surfaces of oxide 231c, and conductor 261 is provided in contact with the upper and side surfaces of insulator 251. Furthermore, the upper surface of conductor 261, the uppermost surface of insulator 251, and the uppermost surface of oxide 231c are arranged to roughly coincide with the upper surface of insulator 280.

[0082] By using this structure, the conductor 261, the insulator 251, and the oxide 231c can be formed in a self-aligning manner so as to be embedded in the openings formed in the insulator 280, etc. By forming the conductor 261, etc. in this manner, the conductor 261 can be placed in the region between the conductors 244a and 244b without the need for alignment.

[0083] The capacitive element 13 includes a conductor 207 positioned in contact with the upper surface of the conductor 240 and the upper surface of the conductor 260, an insulator 282 positioned on the insulator 280 and the conductor 207, and a conductor 208 positioned on the insulator 282, with at least a portion overlapping the conductor 207.

[0084] Here, conductor 207 functions as node FN, and conductor 208 functions as wiring CL. In other words, conductor 207 functions as the lower electrode of the capacitive element 13, and conductor 208 functions as the upper electrode of the capacitive element 13. Also, insulator 282 functions as the dielectric of the capacitive element 13.

[0085] As shown in Figure 2A, in a top view, it is preferable that the conductor 207 encompasses the conductor 260. In other words, it is preferable that the conductor 207 is positioned to cover the conductor 260. Also, in a top view, the conductor 207 may also encompass the conductor 240. With this configuration, the capacitive element 13 can be positioned to cover the top gate of the transistor 11 and overlap with the other side of the source or drain of the transistor 12. Therefore, the area of ​​the capacitive element 13 can be increased without substantially increasing the area of ​​the transistors 11 and 12.

[0086] Furthermore, as shown in Figures 1B, 3A, and 3B, it is preferable that the insulator 282 is positioned to cover the conductor 207, and the conductor 208 is positioned to cover the conductor 207 via the insulator 282. This ensures that the conductor 208 is also positioned via the insulator 282 on the side surface of the conductor 207. Thus, the entire region where the conductor 208 and the conductor 207 overlap, as well as the side surface of the conductor 207, can function as a capacitive element 13.

[0087] By adopting the above configuration, the area occupied by the memory cell 10 can be reduced, allowing for the inclusion of the capacitive element 13. This enables high integration of the semiconductor device, providing a semiconductor device with a large memory capacity. Furthermore, it allows for the provision of a semiconductor device with a low manufacturing cost per unit of memory capacity.

[0088] Furthermore, a conductor 209 is positioned in contact with the upper surface of the conductor 261. The conductor 209 can be formed in the same layer as the conductor 207 and is covered by the insulator 282. The conductor 209 functions as a wiring WL.

[0089] Furthermore, a memory cell array can be formed by arranging multiple memory cells 10 in a matrix. In this case, it is preferable that the wiring connecting each memory cell 10 extends in one direction. For example, as shown in Figures 1A and 1B, the wiring CL (conductor 208), wiring WL (conductor 209), wiring BGL1 (conductor 205), and wiring BGL2 (conductor 206) may be provided extending in the y direction. In this case, each memory cell 10 arranged in the y direction will be connected to the common wiring CL (conductor 208), wiring WL (conductor 209), wiring BGL1 (conductor 205), and wiring BGL2 (conductor 206).

[0090] Furthermore, if, for example, the conductor 261 is extended and provided as the wiring WL, parasitic transistors will be formed at the locations where the wiring WL and the oxide 230b overlap. However, in this embodiment, the conductor 209, which is placed on top of the conductor 261, functions as the wiring WL. As a result, as shown in A5 of Figure 3B, the conductor 209 and the oxide 230b overlap via an insulator 280 or the like. Therefore, the formation of parasitic transistors at the locations where the conductor 209 and the oxide 230b overlap can be suppressed.

[0091] Furthermore, when multiple memory cells 10 are arranged in the x-direction, one source or drain of a transistor 11 in a memory cell 10 is connected to the other source or drain of a transistor 11 in an adjacent memory cell 10. Similarly, one source or drain of a transistor 12 in a memory cell 10 is connected to the other source or drain of a transistor 12 in an adjacent memory cell 10. In other words, the sources and drains of multiple transistors 11 are connected in series, and the sources and drains of multiple transistors 12 are also connected in series. To put it another way, in a memory cell 10, one source or drain of a transistor 12 is electrically connected to wiring WBL via another transistor 12, one source or drain of a transistor 11 is electrically connected to wiring RBL via another transistor 11, and the other source or drain of a transistor 11 is electrically connected to wiring SL via another transistor 11.

[0092] In this case, node FN of memory cell 10 is connected to the other of the source or drain of the transistor 12 of memory cell 10 and to one of the source or drain of the transistor 12 of the adjacent memory cell 10. Therefore, the potential (charge) written to node FN can be retained by turning off the transistor 12 of each memory cell 10 and the transistor 12 of the adjacent memory cell 10.

[0093] In the above configuration, as shown in Figure 1B, oxides 230b and 230a, and oxides 231b and 231a can be provided extended in the x-direction. This allows transistor 11 to be formed in the area where oxide 230b and conductor 208 overlap, and transistor 12 to be formed in the area where oxide 231b and conductor 209 overlap. Here, the channel length direction of transistor 11 and the channel length direction of transistor 12 are approximately parallel. Also, the channel length direction of transistor 11 and the extension direction of conductor 208 are approximately perpendicular. Also, the channel length direction of transistor 12 and the extension direction of conductor 209 are approximately perpendicular.

[0094] Furthermore, although the regions that overlap with the conductor 260 and are removed are excluded, the oxide 243 and conductor 242 may also be arranged by extending in the x-direction, similar to the oxide 230b. Similarly, although the regions that overlap with the conductor 261 and are removed are excluded, the oxide 245 and conductor 244 may also be arranged by extending in the x-direction, similar to the oxide 231b.

[0095] The configuration of the memory cell 10 is not limited to the above. For example, in each memory cell 10, wiring RBL and wiring SL may be connected to transistor 11, and wiring WBL may be connected to transistor 12. In this case, oxide 230b, oxide 231b, etc., are not provided in an extended form, but are provided in each memory cell 10 in an island-like pattern. Therefore, the potential (charge) written to node FN can be maintained simply by turning off the transistor 12 of each memory cell 10.

[0096] Furthermore, details of the memory cell array in which multiple memory cells 10 are arranged in a matrix will be described in a later embodiment.

[0097] Next, Figure 4 shows an enlarged view of the vicinity of the channel formation region of transistor 11 in Figure 3B. While the oxide 230 of transistor 11 will be described below, the same description can also be applied to the oxide 231 of transistor 12. As shown in Figure 4, the oxide 230 has a region 232c that functions as the channel formation region of transistor 11, and regions 232a and 232b, which are provided so as to sandwich region 232c and function as the source region or drain region of transistor 11.

[0098] Region 232c overlaps with the conductor 260 in at least part. In other words, region 232c is located in the region between conductors 242a and 242b. Region 232a is located overlapping with conductor 242a, and region 232b is located overlapping with conductor 242b.

[0099] The region 232c that functions as a channel formation region has less oxygen deficiency or a lower impurity concentration than the regions 232a and 232b, so it is a high-resistance region with a low carrier concentration. Therefore, the region 232c can be said to be of i-type (intrinsic) or substantially i-type.

[0100] Also, the regions 232a and 232b that function as a source region or a drain region have a high oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, or a metal element, so the carrier concentration increases and the regions are low-resistance regions. That is, the regions 232a and 232b are n-type regions with a high carrier concentration and low resistance compared to the region 232c.

[0101] Here, the carrier concentration of the region 232c that functions as a channel formation region is preferably 18 cm -3 or less, more preferably 17 cm -3 less than, even more preferably 16 cm -3 less than, even more preferably 13 cm -3 less than, even more preferably 12 cm -3 less than, and even more preferably less than -9 cm -3 For the lower limit value of the carrier concentration of the region 232c that functions as a channel formation region, there is no particular limitation, but for example, it can be

[0102] Furthermore, a region may be formed between region 232c and region 232a, or region 232b, where the carrier concentration is equal to or lower than that of regions 232a and 232b, and equal to or higher than that of region 232c. In other words, this region functions as a junction region between region 232c and region 232a, or region 232b. The hydrogen concentration in this junction region may be equal to or lower than that of regions 232a and 232b, and equal to or higher than that of region 232c. Also, the oxygen deficiency in this junction region may be equal to or less than that of regions 232a and 232b, and equal to or greater than that of region 232c.

[0103] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0104] In transistor 11, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 including the channel formation region. Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and an oxide 230c disposed on the oxide 230b. While the oxide 230 of transistor 11 will be described below, this description can also be applied to the oxide 231 of transistor 12.

[0105] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced. By using a metal oxide with a large band gap, the off-current of transistors 11 and 12 can be reduced. In particular, by reducing the off-current of transistor 12, when transistors 11 and 12 are used as memory cells in a storage device, it is possible to retain the stored contents for a long period of time. In other words, the storage device does not require a refresh operation, or the frequency of refresh operations can be extremely low. This also significantly reduces the power consumption of the storage device.

[0106] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. For example, In-Ga-Zn oxide may be used as oxide 230, or an oxide obtained by adding tin to In-Ga-Zn oxide may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0107] The above metal oxide can be deposited on a substrate using a sputtering method or the like. Therefore, transistors 11 and 12 can be placed on top of peripheral circuits such as drive circuits formed on a silicon substrate. Thus, when transistors 11 and 12 are used as memory cells in a memory device, the occupied area of ​​the memory cell array that can be provided on one chip can be increased, thereby increasing the storage capacity of the memory device. Furthermore, by depositing multiple layers of the above metal oxide film, a stacked memory cell array can be provided. This allows cells to be integrated and arranged without increasing the occupied area of ​​the memory cell array. In other words, a stacked structure of memory cell arrays (hereinafter sometimes referred to as a 3D cell array) can be constructed. As a result, it is possible to achieve high integration of memory cells and provide a semiconductor device with a large storage capacity.

[0108] Furthermore, the above-mentioned method for depositing metal oxide films is not limited to sputtering; chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods may be used as appropriate.

[0109] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. For oxide 230c, any metal oxide that can be used for oxide 230b or oxide 230a may be used.

[0110] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it may be used. For oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, In:M:Zn = 4:2:3 [atomic ratio] or close to it, or In:M:Zn = 5:1:3 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0111] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0112] By placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed. Furthermore, by placing oxide 230c above oxide 230b, the diffusion of impurities and oxygen from structures formed above oxide 230c to oxide 230b can be suppressed.

[0113] However, oxide 230 is not limited to a configuration in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked. For example, it may be configured with a single layer of oxide 230b, two layers of oxide 230a and oxide 230b, or a stacked structure of four or more layers, or each of oxide 230a, oxide 230b, or oxide 230c may have a stacked structure. For example, oxide 230c may have a two-layer stacked structure. In this case, oxide 230c may be provided with a metal oxide that can be used for oxide 230b, and on top of that, a metal oxide that can be used for oxide 230a may be provided.

[0114] Furthermore, because oxides 230a, 230b, and 230c share a common element other than oxygen (as the main component), the defect level density at the interface between oxide 230a and oxide 230b, and between oxide 230b and oxide 230c, can be reduced. Since the defect level density at the interface between oxide 230a and oxide 230b, and between oxide 230b and oxide 230c, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.

[0115] Here, at the junctions of oxide 230a and oxide 230b, and at the junctions of oxide 230b and oxide 230c, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junctions of oxide 230a and oxide 230b, and at the junctions of oxide 230b and oxide 230c, can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c.

[0116] It is preferable that the oxides 230b each have crystalline properties. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b. Alternatively, CAAC-OS may be used for oxide 230a or oxide 230c.

[0117] CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen vacancies (V)). O CAAC-OS is a metal oxide with low oxygen vacancy (also known as oxygen vacancy). In particular, by heat-treating the CAAC-OS after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), a more crystalline and dense structure can be achieved. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0118] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0119] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes referred to as H, it forms a channel and can generate electron carriers even when no voltage is applied to the gate electrode of the transistor. For this reason, if the region in the oxide semiconductor where the channel is formed contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region in the oxide semiconductor where the channel is formed, impurities, oxygen vacancies, and V are important. O It is preferable that H is reduced as much as possible. In other words, the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration when no voltage is applied to the gate electrode of the transistor, and is preferably i-type (intrinsed) or substantially i-type.

[0120] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistors 11 and 12, or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device having the transistors.

[0121] Therefore, in an oxide semiconductor, region 232c, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while regions 232a and 232b, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 232c of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 232a and 232b.

[0122] Therefore, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment was performed in an oxygen-containing atmosphere to remove oxygen vacancies in region 232c, and V O It is preferable to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Simultaneously, microwave processing is also performed on transistor 12 in an oxygen-containing atmosphere with conductors 244a and 244b provided.

[0123] By performing microwave processing in an oxygen-containing atmosphere, the oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 232c. Due to the action of plasma, microwaves, etc., the V of region 232c O By cleaving H, hydrogen H is removed from region 232c, and oxygen is lost. O It can be supplemented with oxygen. In other words, in region 232c, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 232c. Therefore, the oxygen deficiency in region 232c, and V O This can reduce H and lower the carrier concentration.

[0124] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not extend to regions 232a and 232b. In addition, the effect of oxygen plasma can be reduced by insulators 275 and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, in regions 232a and 232b, V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0125] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 232c, and V O By removing H, region 232c can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 232a and 232b, which function as source and drain regions, can be suppressed, maintaining the n-type configuration. This suppresses fluctuations in the electrical characteristics of transistor 11 and prevents variations in the electrical characteristics of transistor 11 within the substrate surface. The same effect can be obtained with transistor 12.

[0126] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good electrical characteristics. Additionally, it is possible to provide a semiconductor device with good reliability.

[0127] In Figures 3A and 3B, the side surface of the opening into which the conductor 260 is embedded, including the groove portion of the oxide 230b, is generally perpendicular to the surface of the oxide 230b being formed. However, this embodiment is not limited to this. For example, the bottom of the opening may have a gently curved surface, resulting in a U-shape. Alternatively, for example, the side surface of the opening may be inclined with respect to the surface of the oxide 230b being formed.

[0128] Furthermore, as shown in Figure 3A, in a cross-sectional view of the transistor 11 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0129] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0130] It is preferable that at least one of insulators 212, 214, 275, 282, and 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above transistors 11 and 12 into transistors 11 and 12. Therefore, it is preferable that at least one of insulators 212, 214, 275, 282, and 283 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0131] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0132] For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used as insulators 212, 214, 275, 282, and 283. For example, it is preferable to use silicon nitride or the like, which has higher hydrogen barrier properties, as insulators 212 and 283. Also, for example, it is preferable to use aluminum oxide or magnesium oxide, which has high hydrogen capture and hydrogen fixation functions, as insulators 214, 275, and 282. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to transistors 11 and 12 through insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located above insulator 283 to transistors 11 and 12. Alternatively, the diffusion of oxygen contained in insulator 224, etc., to the substrate side via insulator 212 and insulator 214 can be suppressed. Alternatively, the diffusion of oxygen contained in insulator 280, etc., upward from transistors 11 and 12 via insulator 282, etc. can be suppressed. Thus, it is preferable to have a structure in which transistors 11 and 12 are surrounded by insulators 212, 214, 275, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0133] Here, when using aluminum oxide or the like as insulators 212, 214, 275, 282, and 283, it is preferable to use an oxide having an amorphous structure. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of transistors 11 and 12, or by providing it around transistors 11 and 12, hydrogen contained in transistors 11 and 12, or hydrogen present around transistors 11 and 12, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of transistors 11 and 12. By using an amorphous metal oxide as a component of transistors 11 and 12, or by providing it around transistors 11 and 12, transistors 11 and 12 and semiconductor devices with good characteristics and high reliability can be manufactured.

[0134] Furthermore, when using aluminum oxide or the like, insulators 212, 214, 275, 282, and 283 are preferably amorphous, but a region of polycrystalline structure may be formed in part. Also, insulators 212, 214, 275, 282, and 283 may be multilayer structures in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer may be used.

[0135] The insulators 212, 214, 275, 282, and 283 can be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen as a deposition gas, the hydrogen concentration of insulators 212, 214, 275, 282, and 283 can be reduced. Note that the deposition method is not limited to sputtering, and CVD, MBE, PLD, ALD, etc. may be used as appropriate.

[0136] Furthermore, it may be preferable to lower the resistivity of insulators 212 and 283. For example, the resistivity of insulators 212 and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212 and 283 may be able to mitigate charge-up of conductors 205, 242, or 260 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 212 and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0137] Furthermore, it is preferable that insulators 216 and 280 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216 and 280.

[0138] In transistor 11, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. The conductor 205 may be provided extending in the y direction, as shown in Figure 1B and other figures. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. The following description will focus on the conductor 205 of transistor 11, but the same description can also be applied to the conductor 206 of transistor 12.

[0139] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of the opening. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately the same as the height of the upper surface of conductor 205a and the upper surface of insulator 216. In other words, conductor 205b is enclosed by conductors 205a and conductor 205c.

[0140] Here, it is preferable to use conductive materials for conductors 205a and 205c that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0141] By using conductive materials that have the function of reducing hydrogen diffusion for conductors 205a and 205c, it is possible to prevent impurities such as hydrogen contained in conductor 205b from diffusing into oxide 230 via insulator 224, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion for conductors 205a and 205c, it is possible to suppress oxidation of conductor 205b and a decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, conductor 205a may be made of the above conductive material in a single layer or laminate. For example, titanium nitride may be used for conductor 205a.

[0142] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0143] Conductor 205 may function as a back gate electrode. In this case, the threshold voltage (Vth) of transistor 11 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 11 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0144] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0145] Furthermore, as shown in Figures 3A and 3B, the conductor 205 should be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, it is preferable that the conductor 205 extends to the region outside the ends that intersect the channel width direction of the oxide 230a and oxide 230b. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the oxide 230, with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the top gate electrode and the electric field of the conductor 205 which functions as the back gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the top gate and the back gate is called a surrounded channel (S-channel) structure.

[0146] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0147] Furthermore, as shown in Figure 1B and other figures, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0148] Although the present invention describes a configuration in which conductor 205 is made up of laminated conductors 205a, 205b, and 205c, the present invention is not limited to this configuration. Conductor 205 may be provided as a single layer, two layers, or a laminated structure of four or more layers. For example, when conductor 205 is made up of two layers, conductor 205c may be omitted, and the upper surface of conductor 205a and the upper surface of conductor 205b may coincide.

[0149] Insulators 222 and 224 function as gate insulators corresponding to the back gates of transistors 11 and 12.

[0150] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0151] The insulator 222 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and oxide 231 to the substrate side, and the diffusion of impurities such as hydrogen from the periphery of transistors 11 and 12 to oxides 230 and oxide 231. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of transistors 11 and 12, and to suppress the generation of oxygen vacancies in oxides 230 and oxide 231. In addition, it is possible to suppress the reaction of conductors 205 and 206 with the oxygen contained in the insulator 224 and oxides 230 and oxide 231.

[0152] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0153] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0154] The insulator 224 in contact with oxides 230 and 231 preferably contains excess oxygen (oxygen is removed by heating). For example, silicon oxide, silicon oxynitride, etc., may be used as appropriate for the insulator 224. By providing an oxygen-containing insulator in contact with oxides 230 and 231, oxygen deficiencies in oxides 230 and 231 can be reduced, and the reliability of transistors 11 and 12 can be improved.

[0155] Specifically, as the insulator 224, it is preferable to use an oxide material from which some oxygen is desorbed upon heating, in other words, an insulating material having an excess oxygen region. An oxide that desorbs oxygen upon heating is defined as one in which the amount of oxygen molecules desorbed is 1.0 × 10⁻⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 molecular / cm² 3 Preferably 1.0 × 10 19 molecular / cm² 3 More preferably 2.0 × 1019 molecular / cm² 3 Above, or 3.0 × 10 20 molecular / cm² 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0156] Furthermore, during the manufacturing process of transistors 11 and 12, it is preferable to perform a heat treatment while the surfaces of oxide 230 and oxide 231 are exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to oxide 230 and oxide 231, thereby preventing oxygen deficiency (V O This can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0157] Furthermore, by performing an oxygenation treatment on oxide 230 and oxide 231, oxygen deficiencies in oxide 230 and oxide 231 are repaired by the supplied oxygen, in other words, "V O This can promote the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 230 and oxide 231, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 and oxide 231 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0158] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island-like manner by being superimposed with oxides 230a and 231a. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0159] Oxide 243a and oxide 243b are provided on oxide 230b. Oxide 243a and oxide 243b are provided separated by the conductor 260. The following description focuses on oxide 243 of transistor 11, but the same description can also be applied to oxide 245 of transistor 12.

[0160] It is preferable that the oxide 243 (oxide 243a and oxide 243b) has the function of suppressing oxygen permeation. Placing the oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or drain electrode, and the oxide 230b is preferable because it reduces the electrical resistance between the conductor 242 and the oxide 230b. With such a configuration, the electrical characteristics and reliability of the transistor 11 can be improved. However, if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, a configuration without oxide 243 may be used.

[0161] As oxide 243, a metal oxide containing element M may be used. In particular, element M may be aluminum, gallium, yttrium, or tin. It is preferable that oxide 243 has a higher concentration of element M than oxide 230b. Gallium oxide may also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide may be used as oxide 243. Specifically, in the metal oxide used for oxide 243, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxide 243 is crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be suitably suppressed. For example, if oxide 243 has a crystalline structure such as hexagonal, the release of oxygen from oxide 230 can be suppressed.

[0162] It is preferable that the conductor 242a is provided in contact with the upper surface of the oxide 243a, and the conductor 242b is provided in contact with the upper surface of the oxide 243b. The conductors 242a and 242b are arranged in the A5-A6 direction and are provided spaced apart with the conductor 260 in between. The following description will focus on the conductor 242 of transistor 11, but this description can also be applied to the conductor 244 of transistor 12.

[0163] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0164] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductors 242a and 242b. In particular, by using tantalum-containing nitrides for conductors 242a and 242b, hydrogen contained in oxide 230b, etc., may diffuse into conductors 242a and 242b, and the diffused hydrogen may combine with nitrogen present in conductors 242a and 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductors 242a and 242b.

[0165] Alternatively, the conductor 242 may be configured so that no curved surface is formed between its side surface and its top surface. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased. This increases the conductivity of the conductor 242 and thus increases the on-current of the transistor 11.

[0166] The insulator 275 is provided covering the insulator 224, oxide 230, oxide 231, oxide 243, oxide 245, conductor 242, and conductor 244, and openings are formed in the regions where conductors 260, conductor 261, conductor 240, etc., are provided. Preferably, the insulator 275 is provided in contact with the upper surface of the insulator 224, the side surface of the oxide 230, the side surface of the oxide 243, the side surface of the conductor 242, the upper surface of the conductor 242, the side surface of the oxide 231, the side surface of the oxide 245, the side surface of the conductor 244, and the upper surface of the conductor 244. Furthermore, it is preferable that the insulator 275 functions as a barrier insulating film that suppresses the permeation of oxygen. Furthermore, it is preferable that the insulator 275 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 224, oxide 230, or oxide 231, and preferably has the function of capturing impurities such as hydrogen. As the insulator 275, for example, an insulator such as aluminum oxide or silicon nitride may be used.

[0167] By providing an insulator 275 in the region sandwiched between insulators 212 and 283, in contact with insulators 280 and 224, and having the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in insulators 280 and 224 can be captured, and the amount of hydrogen in that region can be kept constant. In this case, it is preferable to use aluminum oxide or the like as the insulator 275.

[0168] Furthermore, a barrier insulating film may be provided between the insulator 275 and the conductors 242 and 244, having the same shape as the conductors 242 and 244 when viewed from above. Any insulator suitable for the insulator 275 may be used for this barrier insulating film.

[0169] The insulator 250 functions as a gate insulator for the top gate of transistor 11. In transistor 11, it is preferable that the insulator 250 is placed superimposed on the oxide 230b. The following description focuses on the insulator 250 of transistor 11, but this description can also be applied to the insulator 251 of transistor 12.

[0170] The insulator 250 can be silicon oxide, silicon oxide-nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxide-nitride are particularly preferred because they are stable with respect to heat.

[0171] Similar to the insulator 224, it is preferable that the insulator 250 has a reduced concentration of impurities such as water and hydrogen. The film thickness of the insulator 250 is preferably between 1 nm and 20 nm.

[0172] In Figures 3A and 3B, the insulator 250 is shown as a single layer, but it may also be a laminated structure of two or more layers. When the insulator 250 is a two-layer laminated structure, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260. In other words, it is possible to suppress the reduction in the amount of oxygen supplied to the oxide 230. Furthermore, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 may be made using the material that can be used for the insulator 250 as described above, and the upper layer of the insulator 250 may be made using the same material as the insulator 222.

[0173] Furthermore, when silicon oxide or silicon oxynitride is used as the lower layer of insulator 250, the upper layer of insulator 250 may be made of an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of the lower layer and the upper layer of insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0174] Specifically, as the upper layer of the insulator 250, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides that can be used as oxide 230, can be used. In particular, it is preferable to use an insulator containing oxides of aluminum and hafnium, or both. For example, a laminated structure containing silicon oxide and hafnium oxide on the silicon oxide can be used as the insulator 250.

[0175] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0176] Furthermore, the above-mentioned metal oxide may be configured to function as part of the top gate electrode. For example, a metal oxide that can be used as oxide 230 can be used as the above-mentioned metal oxide. In that case, the electrical resistance of the above-mentioned metal oxide can be reduced by depositing the conductor 260a by sputtering, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0177] By having the above-mentioned metal oxide, the on-current of the transistor 11 can be improved without weakening the influence of the electric field from the conductor 260. Furthermore, by maintaining the distance between the conductor 260 and the oxide 230 through the physical thickness of the insulator 250 and the above-mentioned metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. In addition, by providing a laminated structure of the insulator 250 and the above-mentioned metal oxide, the physical distance between the conductor 260 and the oxide 230, and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.

[0178] The conductor 260 functions as the top gate electrode of the transistor 11. In the transistor 11, it is preferable that the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. The following description will focus on the conductor 260 of the transistor 11, but the same description can also be applied to the conductor 261 of the transistor 12.

[0179] For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 3A and 3B, the top surface of the conductor 260 is roughly aligned with the top surface of the insulator 250 and the top surface of the oxide 230c. In Figures 3A and 3B, the conductor 260 is shown as a two-layer structure consisting of conductor 260a and conductor 260b, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0180] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0181] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0182] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0183] Furthermore, as shown in Figure 3A, in the channel width direction of the transistor 11, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and oxide 230b do not overlap, when the bottom surface of the insulator 222 is used as a reference, is preferably lower than the height of the bottom surface of oxide 230b. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of oxide 230b via an insulator 250 or the like, the electric field of the conductor 260 can be more easily applied to the entire channel formation region of oxide 230b. Therefore, the on-current of the transistor 11 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of oxide 230b in the region where the oxide 230a and oxide 230b and the conductor 260 do not overlap, when the bottom surface of the insulator 222 is used as a reference, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0184] The insulator 280 is provided on the insulator 275, and openings are formed in the region where the conductors 260, 261, 240, etc., are provided. The upper surface of the insulator 280 may also be flattened.

[0185] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216. For example, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0186] The insulator 280, like the insulator 224, preferably has an excess oxygen region or excess oxygen. Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, the insulator 280 may be made of silicon oxide, silicon oxide, silicon oxide nitride, or other silicon-containing oxides. By providing an insulator with excess oxygen in contact with oxides 230 and 231, oxygen deficiencies in oxides 230 and 231 can be reduced, thereby improving the reliability of transistors 11 and 12.

[0187] The conductor 240, provided between the transistor 12 and the capacitive element 13, has its lower surface in contact with the conductor 244b and its upper surface in contact with the conductor 207. Furthermore, it is preferable that an insulator 241 is provided in contact with the side surface of the conductor 240, which functions as a plug.

[0188] Insulator 241 is provided in contact with the inner walls of the openings of insulators 275 and 280, a first conductor of conductor 240 is provided in contact with the side surface of insulator 241, and a second conductor of conductor 240 is provided further inside. Although Figure 3A shows a configuration in which the first conductor and the second conductor of conductor 240 are laminated, the present invention is not limited to this. For example, conductor 240 may be provided as a single layer or as a laminated structure of three or more layers.

[0189] The conductor 240 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 240 may also be in a laminated structure. When the conductor 240 is in a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the insulator 275 and the insulator 280. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated structure. This makes it possible to suppress the mixing of impurities such as water and hydrogen contained in the insulator 280, etc., into the oxide 231 through the conductor 240.

[0190] As the insulator 241, for example, an insulator such as silicon nitride, aluminum oxide, or silicon oxide nitride may be used. Since the insulator 241 is provided in contact with the insulators 275 and 280, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the insulators 280, etc., into the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0191] Furthermore, a conductor 207 is provided in contact with the upper surface of conductor 240 and the upper surface of conductor 260. Here, conductor 207 functions as node FN. In other words, conductor 244b, which functions as either the source or the other drain of transistor 12, is electrically connected to conductor 260, which functions as the gate of transistor 11, via conductor 240 and conductor 207.

[0192] Furthermore, in the same layer as the conductor 207, a conductor 209 is provided in contact with the upper surface of the conductor 261. Here, the conductor 209 functions as a wiring WL.

[0193] Conductors 207 and 209 may be formed by patterning the same conductive film. It is preferable to use conductive materials mainly composed of tungsten, copper, or aluminum for conductors 207 and 209. Conductors 207 and 209 may also be in a laminated structure, for example, a laminate of titanium or titanium nitride with the above conductive material. Conductors 207 and 209 may also be formed so as to be embedded in openings provided in the insulator.

[0194] The insulator 282 covers the conductors 207 and 209 and is positioned in contact with the upper surface of the insulator 280. Since the insulator 282 functions as a dielectric of the capacitive element 13, it is preferable to use an insulator with a thin equivalent oxide thickness (EOT). As the insulator 282, for example, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, or nitrides having silicon and hafnium can be used. In this specification, equivalent oxide thickness refers to the value obtained by converting the physical thickness to an electrical thickness equivalent to that of silicon oxide or silicon oxidized nitride.

[0195] For example, if aluminum oxide with a relative permittivity of 8.5 is used as the insulator 282, and the area of ​​the capacitive element 13 is 61800 nm 2 Therefore, by making the film thickness of the insulator 282 5 nm or less, the capacitance value of the capacitive element 13 can be made 0.9 fF or more. Here, if we express the film thickness of the insulator 282 using EOT with a relative permittivity of 3.9, the film thickness of the insulator 282 will be 2.3 nm.

[0196] If the capacitance value of the capacitive element 13 is 0.9 fF or greater, it is sufficiently larger than the gate capacitance of the transistor 12, so that data can be written to and read from the memory cell 10. In other words, by making the film thickness of the insulator 282 about 5 nm or less, the memory cell 10 can function sufficiently as a memory device.

[0197] Furthermore, it is preferable that the insulator 282 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. It is also preferable that the insulator 282 functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, for example, an insulator such as aluminum oxide may be used. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, it is possible to capture impurities such as hydrogen contained in the insulator 280 and the like, and keep the amount of hydrogen in that region at a constant value.

[0198] Furthermore, it is preferable to form the insulator 282 using a sputtering method. For example, it may be deposited using a sputtering method in an oxygen-containing atmosphere. By depositing the insulator 282 using a sputtering method, oxygen can be added to the insulator 280. This allows the oxygen contained in the insulator 280 to be efficiently supplied to the oxide 230 or oxide 231 via the oxide 230c or oxide 231c, thereby reducing oxygen deficiencies in the oxide 230 and oxide 231 and improving the electrical characteristics and reliability of transistors 11 and 12. However, the method for depositing the insulator 282 is not limited to sputtering, and CVD, MBE, PLD, ALD, etc. may be used as appropriate.

[0199] Furthermore, a conductor 208 is provided on the insulator 282 such that at least a portion of it overlaps with the conductor 207. Here, the conductor 208 functions as wiring CL. The conductor 208 can be any conductor that can be used for conductors 209, etc. Note that the conductor 208 may be formed to be embedded in an opening provided in the insulator.

[0200] The insulator 283 is provided covering the insulator 282 and the conductor 208. The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a silicon nitride film with high density and less susceptibility to porosity can be formed. Alternatively, as the insulator 283, silicon nitride deposited by CVD may be laminated on top of silicon nitride deposited by sputtering.

[0201] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0202] The insulators, conductors, and oxides described below can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD.

[0203] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo-CVD (Photo-CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0204] Furthermore, ALD methods include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants.

[0205] <<Substrate>> As the substrate for forming transistors 11 and 12, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0206] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0207] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0208] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0209] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0210] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0211] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0212] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0213] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0214] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0215] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0216] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 according to the present invention will be described.

[0217] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0218] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, in some cases, multiple elements from the aforementioned list may be combined as element M.

[0219] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0220] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 5A. Figure 5A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0221] As shown in Figure 5A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0222] The structure within the thick frame shown in Figure 5A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0223] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 5B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 5B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 5B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 5B is 500 nm.

[0224] In Figure 5B, the horizontal axis represents 2θ [deg.] and the vertical axis represents intensity [au]. As shown in Figure 5B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ = 31°. As shown in Figure 5B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0225] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 5C. Figure 5C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 5C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0226] As shown in Figure 5C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0227] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 5A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0228] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0229] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0230] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0231] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0232] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0233] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0234] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0235] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0236] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0237] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0238] [a-like OS] The a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0239] [<Composition of Oxide Semiconductor>] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material composition.

[0240] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, and is also referred to as a mosaic state or a patch state.

[0241] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0242] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0243] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0244] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0245] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0246] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0247] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0248] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0249] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0250] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm-3 It is even more preferable that the value be less than [value]. When the carrier concentration of an oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film is reduced to lower the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0251] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0252] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0253] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0254] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0255] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0256] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0257] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0258] In addition, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, thereby forming oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , even more preferably less than 5×10 18 atoms / cm 3 , even more preferably less than 1×10 18 atoms / cm 3 .

[0259] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0260] <<Other semiconductor materials>> The semiconductor materials that can be used for the oxide 230 are not limited to the above-described metal oxides. As the oxide 230, a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layered substance that functions as a semiconductor (also referred to as an atomic layer substance, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layered substance that functions as a semiconductor as the semiconductor material.

[0261] In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0262] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0263] As oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0264] <Modified examples of semiconductor devices> In the following section, an example of a semiconductor device, which is one embodiment of the present invention, will be described using Figures 6, 7A, 7B, 8A, and 8B.

[0265] Figure 6 is a top view of the memory cell 10. Figure 7A is a cross-sectional view of the area indicated by the dashed lines A1-A2-A3 in Figure 6. Here, the cross-sectional view shown A1-A2 is a cross-sectional view of transistor 12 in the channel length direction, and the cross-sectional view shown A2-A3 is a cross-sectional view of transistor 11 in the channel width direction. Figure 7B is a cross-sectional view of the area indicated by the dashed lines A4-A5-A6 in Figure 6. Here, the cross-sectional view shown A4-A5 is a cross-sectional view of transistor 12 in the channel width direction, and the cross-sectional view shown A5-A6 is a cross-sectional view of transistor 11 in the channel length direction. Note that in the top view of Figure 6, some elements (e.g., wiring CL) have been omitted for clarity.

[0266] In the semiconductor devices shown in Figures 6, 7A, and 7B, the same reference numerals are used to denote structures that have the same function as those described in <Example of Semiconductor Device Configuration>. Furthermore, in this section, the components of the semiconductor device can be described in <Example of Semiconductor Device Configuration>.

[0267] The semiconductor device shown in Figures 6, 7A, and 7B is a modified version of the semiconductor device shown in Figures 1B, 2A, 2B, 3A, and 3B. The memory cell 10 shown in Figures 6, 7A, and 7B differs from the memory cell 10 shown in Figures 1B, 2A, 2B, 3A, and 3B in that a portion of the conductor 260 is exposed from the conductor 207.

[0268] Here, a portion of the conductor 260 is in contact with the insulator 282. Therefore, in the memory cell 10 shown in Figures 6, 7A, and 7B, the conductor 207 and the conductor 260 function as the lower electrodes of the capacitive element 13.

[0269] Furthermore, the region of the conductor 260 that is in contact with the insulator 282 includes a region that overlaps with the vicinity of the channel formation region of the transistor 11. In other words, in the memory cell 10 shown in Figures 6, 7A, and 7B, the insulator 282, insulator 280, oxide 230c, insulator 250, and conductor 260 are in contact with each other near the upper part of the channel formation region of the transistor 11.

[0270] This configuration allows for the provision of a barrier insulating film against impurities such as water and hydrogen near the upper part of the channel formation region of the transistor 11, thereby more effectively reducing the diffusion of these impurities into the oxide 230 via the oxide 230c, insulator 250, etc. Furthermore, by depositing the insulator 282 using a sputtering method, oxygen can be added to the region of the insulator 280 closer to the channel formation region of the transistor 11. This allows for more efficient supply of oxygen contained in the insulator 280 to the oxide 230 via the oxide 230c or insulator 250, thereby reducing oxygen deficiencies in the oxide 230 and improving the electrical characteristics and reliability of the transistor 11.

[0271] Furthermore, while Figure 1A and others show examples where wiring BGL1 and wiring BGL2 are extended in the y direction, the semiconductor device according to the present invention is not limited to this. For example, as shown in Figure 8A, transistors 11 and 12 may be configured without back gates. Also, for example, as shown in Figure 8B, wiring BGL1 and wiring BGL2 may be configured to be extended in the x direction.

[0272] Furthermore, while Figure 1A and others show an example in which the wiring CL that provides the read potential when reading from the memory cell 10 is connected to the upper electrode of the capacitive element 13, the semiconductor device according to the present invention is not limited to this. For example, the wiring CL may be connected to the back gate electrode of the transistor 11. In this case, the wiring connected to the upper electrode of the capacitive element 13 should be supplied with a low power supply potential VSS. In other words, the conductor 205 can be used as the wiring CL that provides the read potential when reading from the memory cell 10, and the conductor 208 can be used as the wiring to which the low power supply potential VSS is supplied.

[0273] One embodiment of the present invention can provide a semiconductor device with a small footprint. Alternatively, one embodiment of the present invention can provide a semiconductor device that can be highly integrated. Alternatively, one embodiment of the present invention can provide a semiconductor device with a large memory capacity. Alternatively, one embodiment of the present invention can provide a semiconductor device with low manufacturing costs. Alternatively, one embodiment of the present invention can provide a highly reliable semiconductor device. Alternatively, one embodiment of the present invention can provide a novel semiconductor device.

[0274] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with configurations and methods shown in other embodiments.

[0275] (Embodiment 2) In this embodiment, an example configuration of a semiconductor device 500 including the memory cell 10 shown in the previous embodiment will be described.

[0276] Figure 9A shows a block diagram illustrating an example configuration of a semiconductor device 500 according to one aspect of the present invention. The semiconductor device 500 shown in Figure 9A includes a drive circuit 510 and a memory cell array 520. The memory cell array 520 is a NAND-type memory cell array having a plurality of memory cell strings 20. Each memory cell string 20 has a plurality of memory cells 10. Figure 9A shows an example in which the memory cell array 520 has n (where n is an integer of 2 or more) memory cell strings 20[1] to 20[n]. However, the present invention is not limited to this, and for example, the memory cell array 520 may have a configuration in which n memory cell strings 20 are considered as one block, and a plurality of blocks are included.

[0277] The drive circuit 510 includes a PSW 541 (power switch), a PSW 542, and a peripheral circuit 515. The peripheral circuit 515 includes a peripheral circuit 511, a control circuit 512, and a voltage generation circuit 528.

[0278] In the semiconductor device 500, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0279] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may also be generated by the control circuit 512.

[0280] The control circuit 512 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 500. For example, the control circuit 512 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 500 (e.g., write operation, read operation). Alternatively, the control circuit 512 generates control signals for the peripheral circuit 511 so that this operating mode is executed.

[0281] The voltage generation circuit 528 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 528. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 528, and the voltage generation circuit 528 generates a negative voltage.

[0282] The peripheral circuit 511 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 511 includes a row decoder 521, a column decoder 522, a row driver 523, a column driver 524, an input circuit 525, an output circuit 526, and a sense amplifier 527.

[0283] The row decoder 521 and column decoder 522 have the function of decoding the signal ADDR. The row decoder 521 is a circuit for specifying the row to access, and the column decoder 522 is a circuit for specifying the column to access. The row driver 523 has the function of selecting the wiring WL specified by the row decoder 521. The column driver 524 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data.

[0284] The input circuit 525 has the function of holding the signal WDA. The data held by the input circuit 525 is output to the column driver 524. The output data of the input circuit 525 is the data (Din) to be written to the memory cell 10. The data (Dout) read by the column driver 524 from the memory cell 10 is output to the output circuit 526. The output circuit 526 has the function of holding Dout. In addition, the output circuit 526 has the function of outputting Dout to the outside of the semiconductor device 500. The data output from the output circuit 526 is the signal RDA.

[0285] PSW541 provides V to peripheral circuit 515 DD It has the function of controlling the supply. PSW542 connects to the line driver 523. HM It has a function to control the supply. Here, the high power supply voltage of semiconductor device 500 is V DD Therefore, the low power supply voltage is GND (ground potential). Also, V HM This is a high power supply voltage used to raise the word line to a high level, V DD It is higher than that. Signal PON1 controls the on / off state of PSW541, and signal PON2 controls the on / off state of PSW542. In Figure 9A, in peripheral circuit 515, V DD The number of power domains supplied is set to 1, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0286] The drive circuit 510 and the memory cell array 520 may be provided on the same plane. Alternatively, as shown in Figure 9B, the drive circuit 510 and the memory cell array 520 may be stacked on top of each other. By stacking the drive circuit 510 and the memory cell array 520, the signal propagation distance can be shortened. Furthermore, the semiconductor device 500 can be miniaturized.

[0287] Figure 10 shows a circuit diagram illustrating an example of the arrangement of memory cells 10 in a memory cell array 520. The memory cell array 520 has n memory cell strings 20[1] to 20[n] extending in the x direction. Each memory cell string 20 has m memory cells 10 (where m is an integer of 2 or more) arranged in the x direction, a transistor 14, and a transistor 15. Thus, in the memory cell array 520, m × n memory cells 10 are arranged in an n x m matrix. In addition, n transistors 14[1] to 14[n] and n transistors 15[1] to 15[n] are arranged in the y direction. The circuit configuration of each memory cell 10 is the same as the configuration shown in Figure 1A, and the wiring connections are also the same, so the description of the previous embodiment can be referenced.

[0288] In each memory cell string 20, the sources and drains of multiple transistors 11 are connected in series, and the sources and drains of multiple transistors 12 are also connected in series. At one end of each memory cell string 20, one source or drain of transistor 11 is electrically connected to one source or drain of transistor 14. At the other end of each memory cell string 20, the other source or drain of transistor 11 is electrically connected to one source or drain of transistor 15.

[0289] In Figure 10, the memory cell 10 in the 1st row and 1st column is shown as memory cell 10[1,1], the memory cell 10 in the nth row and mth column is shown as memory cell 10[n,m], and the memory cell 10 in the jth row and ith column (where j is an integer between 1 and n, and i is an integer between 1 and m) is shown as memory cell 10[j,i].

[0290] Note that rows and columns extend in mutually orthogonal directions. In this embodiment, the x-direction is defined as "rows" and the y-direction as "columns," but the x-direction may be defined as "columns" and the y-direction as "rows."

[0291] Furthermore, the memory cell array 520 includes m wirings CL[1] to CL[m] extending in the y direction, m wirings WL[1] to WL[m] extending in the y direction, m wirings BGL1[1] to BGL1[m] extending in the y direction, m wirings BGL2[1] to BGL2[m] extending in the y direction, and two wirings SEL[1] and SEL[2] extending in the y direction. Here, wiring SEL[1] is electrically connected to the gates of transistors 14[1] to 14[n], and wiring SEL[2] is electrically connected to the gates of transistors 15[1] to 15[n].

[0292] Furthermore, the memory cell array 520 has n wirings RBL[1] to RBL[n], n wirings SL[1] to SL[n], and n wirings WBL[1] to WBL[n]. In each memory cell string 20, wiring WBL is electrically connected to transistor 12 at one end, wiring RBL is electrically connected to transistor 14 at the other end, and wiring SL is electrically connected to transistor 15 at the other end.

[0293] For example, in memory cell string 20[1], wiring RBL[1] is electrically connected to either the source or drain of transistor 11 of memory cell 10[1,1] via transistor 14[1]. Also, wiring SL[1] is electrically connected to either the source or drain of transistor 11 of memory cell 10[1,m] via transistor 15[1]. Furthermore, wiring WBL[1] is electrically connected to either the source or drain of transistor 12 of memory cell 10[1,1].

[0294] Figure 11 shows a top view of the memory cell array 520, corresponding to the circuit diagram in Figure 10. Note that some elements have been omitted from the top view in Figure 11 for clarity. Also, for clarity, some elements such as the conductor 207 are shown with solid lines instead of hidden lines. Here, the structure of each memory cell 10 is the same as that shown in Figures 1B, 2A, 2B, 3A, and 3B, and the description of the previous embodiment can be referenced.

[0295] As shown in Figure 11, the memory cell array 520 extends in the y direction and includes m conductors 208[1] to 208[m] that function as wiring CL, m conductors 209[1] to 209[m] that function as wiring WL, m conductors 205[1] to 205[m] that function as wiring BGL1, m conductors 206[1] to 206[m] that function as wiring BGL2, conductor 210[1] that function as wiring SEL[1], and conductor 210[2] that function as wiring SEL[2]. Furthermore, the conductors 210 that function as wiring SEL[1] and wiring SEL[2] may be formed using the same conductive material as conductor 209.

[0296] Furthermore, as shown in Figure 11, the memory cell array 520 extends in the x direction and has n oxides 230b[1] to 230b[n] and n oxides 231b[1] to 231b[n]. One oxide 230b and one oxide 231b are arranged in each memory cell string 20. One end of oxide 230b is provided with a plug electrically connected to wiring RBL, and the other end of oxide 230b is provided with a plug electrically connected to wiring SL. Similarly, one end of oxide 231b is provided with a plug electrically connected to wiring WBL. Although not shown, oxides 230a, 231a, 243, 245, conductor 242, and conductor 244 are also arranged extending as appropriate, similar to oxides 230b and 231b.

[0297] In oxide 230b, transistor 11 is formed in the portion overlapping with conductor 208. In oxide 231b, transistor 12 is formed in the portion overlapping with conductor 209, transistor 14 is formed in the portion overlapping with conductor 210[1], and transistor 15 is formed in the portion overlapping with conductor 210[2]. Here, transistors 14 and 15 can have the same structure as transistor 11. However, the upper surface of the top gate of transistor 14 is in contact with conductor 210[1], and the upper surface of the top gate of transistor 15 is in contact with conductor 210[2].

[0298] Furthermore, the memory cell array 520 has an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, an insulator 216 on the insulator 214, an insulator 222 on the insulator 216, an insulator 224 on the insulator 222, an insulator 275 on the insulator 224, an insulator 280 on the insulator 275, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282, similar to the structure shown in Figures 3A and 3B. In addition, m conductors 205 and m conductors 206 are arranged in the same layer as the insulator 216, n oxides 230b and n oxides 231b are arranged on the insulator 224, m conductors 209 are arranged on the insulator 280, and m conductors 208 are arranged on the insulator 282. Furthermore, in each memory cell 10, transistors 11 and 12 are provided in the layer between the insulator 214 and the insulator 282, a capacitive element 13 is provided on the insulator 280, and a conductor 240 is provided to connect transistors 11 and 12.

[0299] For example, memory cells 10[1,1] and 10[1,2], which constitute the memory cell array 520, also have the structures shown in Figures 3A and 3B, respectively. However, the transistors 11 of memory cell 10[1,2] and the transistors 11 of memory cell 10[1,2] are both formed from oxide 230b[1]. Also, the transistors 12 of memory cell 10[1,2] and the transistors 12 of memory cell 10[1,2] are both formed from oxide 231b[1].

[0300] As shown in Figure 11, in the NAND type memory cell array 520, there is no need to form contact plugs connected to wiring WBL, wiring RBL, etc., in each memory cell 10. Therefore, there is no need to provide space for forming extra contact holes within the memory cell 10. Thus, by designing the shape of the memory cell 10 based on a rectangle enclosed by oxide 230b, oxide 231b, conductor 208 (wiring CL), and conductor 209 (wiring WL), the occupied area of ​​the memory cell 10 can be minimized.

[0301] Here, the layouts of the oxide 230b, the oxide 231b, the conductor 208, and the conductor 209 are preferably designed so that the area of the memory cell 10 is as narrow as possible based on the parasitic capacitance between wirings, the minimum processing dimension, and the like. As a result, the area occupied by the conductor 208 that functions as the upper electrode of the capacitor element 13 in the memory cell 10, that is, the maximum value of the area that the capacitor element 13 can take is also limited. Therefore, it is preferable that the area where the conductor 207 overlaps the designed conductor 208 is as large as possible.

[0302] In the memory cell 10 described in the present embodiment and the like, the conductor 207 that functions as the node FN is disposed so as to overlap the oxides 230b and 231b. Thereby, in the memory cell 10, the area where the conductor 208 and the conductor 207 overlap can be expanded in the y direction.

[0303] With such a configuration, the capacitance of the capacitor element 13 can be increased without substantially increasing the area with respect to the limited area of the memory cell 10. Therefore, the occupied area of the memory cell 10 can be reduced. As a result, high integration of the semiconductor device can be achieved, and a semiconductor device having a large storage capacity can be provided. In addition, a semiconductor device with a low manufacturing cost per storage capacity can be provided.

[0304] Next, an example of the data writing operation and the data reading operation of the memory cell array 520 will be described using FIGS. 12A and 12B. Hereinafter, the operation will be described using the memory cell string 20[1] when m = 4 as a model.

[0305] First, an example of writing data to the memory cell string 20[1] in periods T1 to T4 will be described using the timing chart shown in FIG. 12A. Here, FIG. 12A shows the potential V WBL[1] [V] of the wiring WBL[1], the potential V WL[4] [V] of the wiring WL[4], the potential V WL[3] [V] of the wiring WL[3], the potential V WL[2][V], potential V of wiring WL[1] WL[1] [V] is shown. During period T1 to period T4, the potentials of wiring RBL[1], wiring SL[1], wiring CL[1] to wiring CL[4], wiring BGL1[1] to wiring BGL1[4], and wiring BGL2[1] to wiring BGL2[4] are set to 0V.

[0306] In period T1, data 0 is written into memory cell 10[1,4]. Potential V WBL[1] is set to the potential of data 0 (e.g., 0V), and potential V WL[4] to potential V WL[1] are set to the potentials (e.g., 4V) at which transistors 11 of memory cells 10[1,4] to memory cell 10[1,1] are turned on. As a result, wiring WBL[1] and the node FN of memory cell 10[1,4] are conducting, and the potential of data 0 is applied to node FN. When switching from period T1 to period T2, potential V WL[4] is set to the potential (e.g., -4V) at which transistor 11 is turned off. As a result, the node FN of memory cell 10[1,4] becomes a floating state, and the potential corresponding to data 0 applied to node FN can be retained.

[0307] In period T2, data 1 is written into memory cell 10[1,3]. Potential V WBL[1] is set to the potential of data 1 (e.g., 2V), and potential V WL[3] to potential V WL[1] are set to the potentials (e.g., 4V) at which transistors 11 of memory cells 10[1,3] to memory cell 10[1,1] are turned on. As a result, wiring WBL[1] and the node FN of memory cell 10[1,3] are conducting, and the potential of data 1 is applied to node FN. At this time, since the transistor 11 of memory cell 10[1,4] is in an off state, the data 0 written into memory cell 10[1,4] in period T1 is retained. When switching from period T2 to period T3, potential V WL[3] is set to the potential (e.g., -4V) at which transistor 11 is turned off. As a result, the node FN of memory cell 10[1,3] becomes a floating state, and the potential corresponding to data 1 applied to node FN can be retained.

[0308] In the following steps, during period T3, write data 0 to memory cell 10[1,2] in the same manner as in period T1, and during period T4, write data 1 to memory cell 10[1,1] in the same manner as in period T2.

[0309] Next, using the timing chart shown in Figure 12B, an example of reading data from a memory cell string 20[1] that was written during periods T1 to T4, during periods T5 to T8, will be described. Here, Figure 12B shows the potential V of wiring CL[4]. CL[4] [V], potential V of wiring CL[3] CL[3] [V], potential V of wiring CL[2] CL[2] [V], potential V of wiring CL[1] CL[1] [V], current value I of wiring RBL[1] RBL[1] [μA] is shown. During periods T5 to T8, the potentials of wiring WL[1] to WL[4] are -4V, the potential of wiring RBL[1] is 1.2V, and the potentials of wiring SL[1], wiring WBL[1], wiring BGL1[1] to BGL1[4], and wiring BGL2[1] to BGL2[4] are 0V. Transistors 14[1] and 15[1] are also kept in the ON state.

[0310] During period T5, data 0 is read from memory cell 10[1,4]. Potential V CL[4] Let the read potential be (e.g., 0V), and the potential V CL[3] Potential V CL[1] This sets the potential (e.g., 4V) such that the transistor 11 of memory cell 10[1,3] to memory cell 10[1,1] turns on, regardless of the data it holds. As a result, the conduction state of wiring RBL[1] and wiring SL[1] is determined by the conduction state of transistor 11 of memory cell 10[1,4]. Here, when a read potential is applied to wiring CL, transistor 11 of memory cell 10 turns off if data 0 is held, and turns on if data 1 is held. As shown in Figure 12B, RBL[1]Since the current is 0μA and wiring RBL[1] and wiring SL[1] are non-conductive, it can be read that the memory cell 10[1,4] holds the data 0.

[0311] During period T6, data 1 from memory cell 10[1,3] is read. Potential V CL[3] Let the read potential be (e.g., 0V), and the potential V CL[4]、 Potential V CL[2] , and potential V CL[1] This sets the transistor 11 of memory cells 10[1,4], 10[1,2], and 10[1,1] to a potential (e.g., 4V) that turns them ON, regardless of the data they hold. As a result, the conduction state of wiring RBL[1] and wiring SL[1] is determined by the conduction state of transistor 11 of memory cell 10[1,3]. As shown in Figure 12B, RBL[1] Since the value is positive and wiring RBL[1] and wiring SL[1] are conducting, it can be read that data 1 is held in memory cell 10[1,3].

[0312] In the following steps, during period T7, data 0 from memory cell 10[1,2] should be read using the same method as in period T5, and during period T8, data 1 from memory cell 10[1,1] should be read using the same method as in period T6.

[0313] As described above, data can be written to and read from memory cell string 20[1]. In the above example, writing and reading were performed on one memory cell string 20, but data can be written to and read from multiple memory cell strings 20 simultaneously using the same method. For example, with the memory cell array 520 shown in Figure 10, data can be written to and read from memory cell strings 20[1] to 20[n] simultaneously.

[0314] The data writing and reading operations of the memory cell array 520 described above are merely examples, and the present invention is not limited thereto. For example, as described in the previous embodiment, during a data reading operation, the conductor 205 may function as wiring CL that provides a reading potential, and the conductor 208 may be used as wiring to which a low power supply potential VSS is provided.

[0315] Furthermore, the layout of the memory cell array 520 described above is merely an example, and the present invention is not limited thereto. For example, the wiring WBL may be provided not only at one end of the memory cell string 20 but also at the other end, that is, two wiring WBLs may be connected to one memory cell string 20. With such a configuration, in the data writing operation described above, data can be written simultaneously from two directions of the memory cell string 20, thereby improving the data writing speed.

[0316] Furthermore, for example, the configuration may be one in which wiring BGL1 and wiring BGL2 are not provided, or the configuration may be one in which wiring BGL1 and wiring BGL2 extend in the x direction. Also, the transistors 14 and 15 may be configured to have back gates and wiring BGL1.

[0317] Furthermore, although the memory cell array 520 described above is a NAND type memory cell array, the present invention is not limited to this. For example, oxide 230b and oxide 231b may be patterned in an island-like manner on each memory cell 10 to form a NOR type memory cell array.

[0318] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with configurations and methods shown in other embodiments.

[0319] (Embodiment 3) This embodiment describes an application example of a storage device according to one aspect of the present invention.

[0320] Generally, various types of memory devices are used in semiconductor devices such as computers, depending on the application. Figure 13 shows the different types of memory devices in a hierarchical structure. Higher-level memory devices require faster access speeds, while lower-level memory devices require larger storage capacity and higher recording density. In Figure 13, from the top layer upwards, the memory devices are shown as registers integrated into the processing unit such as the CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0321] Memory integrated as registers into arithmetic processing units such as CPUs is frequently accessed by the arithmetic processing unit because it is used for temporary storage of calculation results. Therefore, faster operating speed is required than storage capacity. Registers also have the function of holding configuration information for the arithmetic processing unit.

[0322] SRAM is used, for example, as a cache. A cache has the function of duplicating and storing some of the information held in main memory. By duplicating frequently used data in the cache, the speed of accessing that data can be increased.

[0323] DRAM is used, for example, in main memory. Main memory has the function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm². 2 That is the case.

[0324] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored long-term, as well as various programs used by the processing unit. Therefore, storage requires a large storage capacity and high recording density rather than just operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm². 2 That is the case.

[0325] A storage device according to one aspect of the present invention has a large storage capacity, high operating speed, and is capable of long-term data retention. The storage device according to one aspect of the present invention can be suitably used as a storage device located in boundary region 901, which includes both the layer where the cache is located and the layer where the main memory is located. Furthermore, the storage device according to one aspect of the present invention can be suitably used as a storage device located in boundary region 902, which includes both the layer where the main memory is located and the layer where the storage is located.

[0326] A storage device according to one aspect of the present invention can be applied to storage devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, etc. Here, "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0327] Furthermore, a storage device according to one aspect of the present invention is applicable to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 14A to 14E schematically show some configuration examples of removable storage devices. For example, a storage device according to one aspect of the present invention is processed into a packaged memory chip and used in various storage devices and removable memory.

[0328] Figure 14A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1105 on the circuit board 1104.

[0329] Figure 14B is a schematic diagram of the external appearance of an SD card, and Figure 14C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. The capacity of the SD card 1110 can be increased by also providing a memory chip 1114 on the back side of the circuit board 1113. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor devices shown in the above embodiment can be incorporated into the memory chip 1114 on the circuit board 1113.

[0330] Figure 14D is a schematic diagram of the external appearance of the SSD, and Figure 14E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. Semiconductor devices as shown in the above embodiment can be incorporated into the memory chips 1154 on the circuit board 1153.

[0331] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with configurations and methods shown in other embodiments.

[0332] (Embodiment 4) Figure 15 shows a specific example of an electronic device equipped with a semiconductor device according to one aspect of the present invention.

[0333] <Electronic Equipment and Systems> A semiconductor device according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, electronic devices with relatively large screens such as television equipment, monitors for desktop or notebook-type information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound playback devices. Furthermore, a semiconductor device according to one aspect of the present invention can be applied as a component of artificial intelligence. Artificial intelligence can be mounted on an electronic device using a semiconductor device according to one aspect of the present invention.

[0334] An electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, the display unit can display images, information, etc. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0335] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0336] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0337] [Information terminal] Figure 15A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. For input interfaces, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0338] The information terminal 5100 can execute applications utilizing artificial intelligence using a semiconductor device according to one aspect of the present invention. Examples of applications utilizing artificial intelligence include applications that recognize conversations and display the content of those conversations on the display unit 5102, applications that recognize characters, figures, etc., entered by the user on a touch panel provided on the display unit 5102 and display them on the display unit 5102, and applications that perform biometric authentication such as fingerprints and voiceprints.

[0339] Figure 15B illustrates a notebook-type information terminal 5200. The notebook-type information terminal 5200 comprises a main unit 5201, a display unit 5202, and a keyboard 5203.

[0340] The notebook-type information terminal 5200, like the information terminal 5100 described above, can execute applications utilizing artificial intelligence using a semiconductor device according to one aspect of the present invention. Examples of applications utilizing artificial intelligence include design support software, document editing software, and automatic menu generation software. Furthermore, the notebook-type information terminal 5200 can be used to develop new artificial intelligence.

[0341] In the above, smartphones and notebook computers were used as examples of electronic devices, as illustrated in Figures 15A and 15B, respectively. However, other types of information terminals can also be used. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0342] [Game console] Figure 15C shows a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Housings 5302 and 5303 can be detached from housing 5301. By attaching the connection unit 5305 provided on housing 5301 to another housing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). At this time, housings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. A semiconductor device according to one aspect of the present invention can be incorporated into chips or the like provided on the circuit boards of housings 5301, 5302, and 5303.

[0343] Figure 15D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection.

[0344] By applying a GPU or chip according to one aspect of the present invention to game consoles such as the handheld game console 5300 and the home game console 5400, a low-power game console can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0345] Furthermore, by using a semiconductor device according to one aspect of the present invention in the portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0346] Normally, the progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the game's program. However, by applying artificial intelligence to the 5300 handheld game console, it becomes possible to create expressions that are not limited to the game's program. For example, it becomes possible to express changes in the content of questions asked by the player, the game's progress, the time of day, and the behavior of characters appearing in the game.

[0347] Furthermore, when playing games that require multiple players on the 5300 handheld game console, artificial intelligence can be used to create anthropomorphic game players. By using AI-generated game players as opponents, it becomes possible to play the game even by a single player.

[0348] Figures 15C and 15D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the semiconductor device according to one aspect of the present invention can be applied are not limited to these. Examples of game consoles to which the semiconductor device according to one aspect of the present invention can be applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0349] [Large computer] A semiconductor device according to one aspect of the present invention can be applied to a large-scale computer.

[0350] Figure 15E shows the supercomputer 5500, an example of a large-scale computer. Figure 15F shows the rack-mount computer 5502, which is part of the supercomputer 5500.

[0351] The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. Furthermore, each computer 5502 is provided with a plurality of circuit boards 5504, on which a semiconductor device according to one aspect of the present invention can be mounted.

[0352] The Supercomputer 5500 is a large computer primarily used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of vast amounts of computation, resulting in high power consumption and significant heat generation from the chips. By applying a semiconductor device according to one aspect of the present invention to the Supercomputer 5500, a low-power supercomputer can be realized. Furthermore, low power consumption reduces heat generation from the circuit, thereby minimizing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0353] Figures 15E and 15F illustrate a supercomputer as an example of a large computer, but the large computers to which the semiconductor device according to one aspect of the present invention is applied are not limited to this. Examples of large computers to which the semiconductor device according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes).

[0354] [Mobile] A semiconductor device according to one aspect of the present invention can be applied to a mobile vehicle and the area around the driver's seat of a vehicle.

[0355] Figure 15G shows the area around the windshield inside the cabin of an automobile 5600, which is an example of a mobile vehicle. In Figure 15G, display panels 5601, 5602, and 5603 mounted on the dashboard are shown, as well as a display panel 5604 mounted on the pillar.

[0356] Display panels 5601 to 5603 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, and more. Furthermore, the display items and layout on the display panels can be changed as needed to suit the user's preferences, enhancing the design. Display panels 5601 to 5603 can also be used as lighting devices.

[0357] The display panel 5604 can display images from an imaging device (not shown) installed in the vehicle, thereby compensating for the blind spots obstructed by the pillars. In other words, by displaying images from an imaging device installed on the outside of the vehicle, blind spots can be compensated for, thereby enhancing safety. Furthermore, by displaying images that compensate for the parts that are not visible, safety checks can be performed more naturally and without discomfort. The display panel 5604 can also be used as a lighting device.

[0358] A semiconductor device according to one aspect of the present invention can be applied as a component of artificial intelligence, and for example, the chip can be used in an autonomous driving system for an automobile. Furthermore, the chip can be used in systems that provide road guidance, predict hazards, and the like. Display panels 5601 to 5604 may be configured to display information such as road guidance and hazard prediction.

[0359] Although automobiles are described above as an example of a mobile device, mobile devices are not limited to automobiles. For example, mobile devices can also include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and a semiconductor device according to one aspect of the present invention can be applied to these mobile devices to provide them with a system utilizing artificial intelligence.

[0360] [electric appliances] Figure 15H shows an example of an electrical appliance, an electric refrigerator-freezer 5700. The electric refrigerator-freezer 5700 includes a casing 5701, a refrigerator door 5702, a freezer door 5703, and the like.

[0361] By using a semiconductor device according to one aspect of the present invention in an electric refrigerator 5700, an electric refrigerator 5700 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5700 can have functions such as automatically generating menus based on the ingredients stored in the electric refrigerator 5700 and their expiration dates, and automatically adjusting the temperature to suit the ingredients stored in the electric refrigerator 5700.

[0362] While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0363] The electronic devices described in this embodiment, their functions, examples of artificial intelligence applications, and their effects can be appropriately combined with descriptions of other electronic devices.

[0364] The configurations and methods described in this embodiment can be used in appropriate combination with other configurations and methods shown in this embodiment, or with configurations and methods shown in other embodiments. [Explanation of symbols]

[0365] BGL1: Wiring, BGL2: Wiring, CL: Wiring, RBL: Wiring, SL: Wiring, SEL: Wiring, T1: Period, T2: Period, T3: Period, T4: Period, T5: Period, T6: Period, T7: Period, T8: Period, WBL: Wiring, WL: Wiring, 10: Memory cell, 11: Transistor, 12: Transistor, 13: Capacitive element, 14: Transistor, 15: Transistor, 20: Memory cell string, 205: Conductor, 205a: Conductor, 205b: Conductor, 205c: Conductor, 206: Conductor, 206a: Conductor, 206b: Conductor, 206c: Conductor, 207: Conductor Electrode, 208: Conductor, 209: Conductor, 210: Conductor, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230b: Oxide, 230c: Oxide, 231: Oxide, 231a: Oxide, 231b: Oxide, 231c: Oxide, 232a: Region, 232b: Region, 232c: Region, 240: Conductor, 241: Insulator, 242: Conductor, 242a: Conductor, 242b: Conductor, 243: Oxide, 243a: Oxide, 243b: Oxide, 244: Conductor, 244a: Conductor, 244 b: Conductor, 245: Oxide, 245a: Oxide, 245b: Oxide, 250: Insulator, 251: Insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 261: Conductor, 261a: Conductor, 261b: Conductor, 275: Insulator, 280: Insulator, 282: Insulator, 283: Insulator, 500: Semiconductor device, 510: Drive circuit, 511: Peripheral circuit, 512: Control circuit, 515: Peripheral circuit, 520: Memory cell array, 521: Row decoder, 522: Column decoder, 523: Row driver, 524: Column driver, 525: Input circuit, 526: Output Power circuit, 527: Sense amplifier, 528: Voltage generation circuit, 541: PSW, 542: PSW, 901: Boundary region, 902: Boundary region, 1100: USB memory, 1101: Enclosure, 1102: Cap, 1103: USB connector, 1104: Circuit board, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: Enclosure, 1112: Connector, 1113: Circuit board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: Enclosure, 1152: Connector, 1153: Circuit board, 1154: Memory chip,1155: Memory chip, 1156: Controller chip, 5100: Information terminal, 5101: Casing, 5102: Display unit, 5200: Notebook-type information terminal, 5201: Main unit, 5202: Display unit, 5203: Keyboard, 5300: Portable game console, 5301: Casing, 5302: Casing, 5303: Casing, 5304: Display unit, 5305: Connection unit, 5306: Operation keys, 5400: Game console, 5402: Controller, 5500: Supercomputer, 5501: Rack, 5502: Calculator, 5504: Circuit board, 5600: Automobile, 5601: Display panel, 5602: Display panel, 5603: Display panel, 5604: Display panel, 5700: Electric refrigerator / freezer, 5701: Enclosure, 5702: Door for refrigerator compartment, 5703: Door for freezer compartment,

Claims

1. A device comprising first to fourth transistors, a first oxide semiconductor, a second oxide semiconductor, a first capacitive element, a second capacitive element, a first insulator, a second insulator, a first conductor, and a second conductor, The first transistor and the third transistor are formed in the first oxide semiconductor, The second transistor and the fourth transistor are formed in the second oxide semiconductor, The first transistor comprises a first gate and a first gate insulator. The second transistor comprises a second gate and a second gate insulator. The third transistor comprises a third gate and a third gate insulator. The fourth transistor comprises a fourth gate and a fourth gate insulator. The first capacitive element comprises a third conductor and a fourth conductor. The second capacitive element comprises a fifth conductor and a sixth conductor. Each of the first oxide semiconductor and the second oxide semiconductor is a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor. The first insulator is placed on the first oxide semiconductor and the second oxide semiconductor. The first insulator has a first opening and a second opening that reach the first oxide semiconductor, a third opening and a fourth opening that reach the second oxide semiconductor, a fifth opening that reaches either the source or the drain of the second transistor, and a sixth opening that reaches either the source or the drain of the fourth transistor. The first gate insulator and the first gate are placed inside the first opening. The third gate insulator and the third gate are positioned within the second opening. The second gate insulator and the second gate are positioned within the third opening. The fourth gate insulator and the fourth gate are placed inside the fourth opening. The first conductor is placed inside the fifth opening. The second conductor is placed inside the sixth opening. The third conductor is positioned in contact with the upper surface of the first conductor and the upper surface of the first gate. The fifth conductor is positioned in contact with the upper surface of the second conductor and the upper surface of the third gate. The second insulator is arranged on the third conductor, the fifth conductor, and the first insulator. The fourth conductor is arranged to cover the third conductor via the second insulator. A semiconductor device in which the sixth conductor is arranged to cover the fifth conductor via the second insulator.

2. In Claim 1, Each of the first oxide semiconductor and the second oxide semiconductor comprises indium, element M (where M is one or more selected from gallium, aluminum, yttrium, and tin), and zinc, respectively, in a semiconductor device.

3. In Claim 1, A semiconductor device in which each of the first oxide semiconductor and the second oxide semiconductor comprises indium oxide.

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