Semiconductor equipment
The semiconductor device optimizes trench and connection region spacing to reduce on-resistance and switching losses, enhancing performance and reliability by minimizing hole accumulation and temperature rise.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2025-07-22
- Publication Date
- 2026-05-19
AI Technical Summary
Existing semiconductor devices face high on-resistance immediately after turning on and increased switching losses due to densely arranged connection regions, which lead to temperature rise and increased electrical resistance during recovery current flow.
The semiconductor device features a semiconductor substrate with a unique arrangement of trenches, gate insulating film, and gate electrodes, including a wider spacing of connection regions at the outer portion of the element region, intersecting bottom regions, and additional connection auxiliary regions to facilitate efficient current flow and reduce accumulation of holes, thereby minimizing on-resistance and switching losses.
The solution effectively reduces on-resistance and switching losses while maintaining high avalanche withstand capability by optimizing the spacing and arrangement of connection regions, ensuring efficient heat dissipation and reduced temperature rise.
Smart Images
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Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to semiconductor devices.
[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a plurality of trenches provided on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of the trenches, and gate electrodes disposed in the trenches. In this semiconductor device, the semiconductor substrate has an n-type source region, a p-type contact region, a p-type body region, an n-type drift region, a p-type bottom region, and a plurality of p-type connection regions. The source region is exposed on the upper surface of the semiconductor substrate and is in contact with the gate insulating film. The contact region is exposed on the upper surface of the semiconductor substrate. The body region is in contact with the gate insulating film below the source region and is in contact with the contact region. The drift region is in contact with the gate insulating film below the body region. The bottom region is disposed below the trench at a distance from the bottom surface of the trench. Each connection region connects the body region and the bottom region, extends parallel to the trench, and is disposed at intervals in a direction orthogonal to the direction in which the trench extends.
[0003] When the semiconductor device of Patent Document 1 is turned off, a depletion layer extends from the bottom region into the drift region. The depletion layer extending from the bottom region into the drift region suppresses the electric field concentration at the lower end of the trench.
[0004] In the semiconductor device of Patent Document 1, a parasitic pn diode (hereinafter referred to as a body diode) is formed by the p-type contact region and body region and the n-type drift region. In the operation of the semiconductor device, when a forward bias voltage is applied to the body diode, the body diode turns on and holes flow from the contact region into the drift region through the body region. Then, when the voltage applied to the body diode switches to a reverse bias, in the process of the body diode turning off, the holes accumulated in the drift region flow through the body region to the contact region. That is, a recovery current flows.
[0005] In the semiconductor device described in Patent Document 1, a bottom region is provided inside the drift region, which is connected to the body region via a connection region. Therefore, when a reverse bias is applied, holes accumulated in the drift region easily flow from the drift region to the bottom region, and most of the holes flow to the body region via the bottom region and the connection region. [Prior art documents] [Patent Documents]
[0006] [Patent Document 1] Japanese Patent Publication No. 2019-46908 [Overview of the project] [Problems that the invention aims to solve]
[0007] In the semiconductor device described in Patent Document 1, when the semiconductor device is turned on, the depletion layer that had spread from the connection region into the drift region contracts. Until the depletion layer has completely contracted, the path through which the main current of the semiconductor device flows is restricted by the depletion layer. In the semiconductor device described in Patent Document 1, the connection regions are densely arranged, so the on-resistance is high immediately after the semiconductor device is turned on.
[0008] When connection regions are loosely spaced to reduce on-resistance, the current density increases in each connection region when the voltage applied to the body diode switches to a reverse bias, causing holes accumulated in the drift region to flow towards the body region. This increases the electrical resistance when recovery current flows, causing the temperature of the semiconductor device to rise. As a result, switching losses increase.
[0009] This specification provides a technique for reducing switching losses while reducing on-resistance. [Means for solving the problem]
[0010] The semiconductor devices (10, 100, 200, 300) disclosed herein include a semiconductor substrate (12) having an element region (62) and a peripheral region (64) arranged around the element region; a plurality of trenches (22) provided on the upper surface (12a) of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction perpendicular to the first direction on the upper surface; a gate insulating film (24) covering the inner surface of each trench; and a gate electrode (26) disposed within each trench and insulated from the semiconductor substrate by the gate insulating film. The element region comprises an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each trench, a p-type contact region (31) exposed on the upper surface of the semiconductor substrate, a p-type body region (32) below the source region in contact with the gate insulating film in each trench and in contact with the contact region, an n-type drift region (34) below the body region in contact with the gate insulating film in each trench and separated from the source region by the body region, a p-type bottom region (36) positioned below the trench at a distance from the bottom surface of the trench and surrounded by the drift region, and a plurality of p-type connection regions (38) each connecting the body region and the bottom region, each extending in the first direction and arranged at intervals in the second direction. The element region has an outer portion (62a) located at both ends of the element region in the second direction and a central portion (62b) positioned between the outer portions. The spacing of the connection regions in the second direction in the outer portion is wider than the spacing of the connection regions in the second direction in the central portion.
[0011] In this semiconductor device, the element region has an outer region located at both ends of the element region in the direction in which the trenches and connection regions are arranged, and a central region located between the outer regions. The spacing of the connection regions in the outer region is wider than the spacing of the connection regions in the central region. Because the spacing of the connection regions is wider in the outer region, the on-resistance is low. Therefore, the on-resistance of the entire element region can be reduced. In addition, the outer region is adjacent to the peripheral region. In the peripheral region, it is difficult to apply voltage to the body diode, so holes do not easily accumulate in the drift region when forward biased. That is, almost no holes flow into the outer region from the peripheral region, so the density of holes accumulated in the drift region when forward biased is low in the outer region. Therefore, the recovery current is small in the outer region, and even if the spacing of the connection regions in the outer region is wide, the temperature of the semiconductor device does not easily rise. Therefore, the switching loss of the entire element region is small. As described above, this semiconductor device can reduce switching loss while reducing on-resistance. [Brief explanation of the drawing]
[0012] [Figure 1] Plan view of a semiconductor device. [Figure 2] An enlarged plan view of the semiconductor device of Example 1, including the boundary between the element region and the surrounding region. [Figure 3] Cross-sectional view along line III-III in Figure 2. [Figure 4] Cross-sectional view along line IV-IV in Figure 2. [Figure 5] An enlarged plan view of the semiconductor device of Example 2, including the boundary between the element region and the surrounding region. [Figure 6] An enlarged plan view of the semiconductor device of Example 3, including the boundary between the element region and the surrounding region. [Figure 7] Cross-sectional view along line VII-VII in Figure 6. [Figure 8] Cross-sectional view along line VIII-VIII in Figure 6. [Figure 9] An enlarged plan view of the device of Example 4, including the boundary between the element region and the surrounding region. [Figure 10]Cross-sectional view taken along the line X-X of FIG. 9. [Figure 11] Cross-sectional view corresponding to FIG. 3 of the semiconductor device of the modified example. [Figure 12] Cross-sectional view corresponding to FIG. 3 of the semiconductor device of another modified example.
Embodiments for Carrying Out the Invention
[0013] In a semiconductor device of an example disclosed in this specification, the interval in the second direction of the connection region in the outer portion may become wider as it approaches the end portion of the element region.
[0014] The amount of holes accumulated in the drift region during forward biasing of the body diode decreases as it approaches the end portion of the element region. In the above configuration, by widening the interval of the connection region as it approaches the end portion of the element region, reduction of on-resistance and reduction of switching loss can be more preferably achieved.
[0015] In a semiconductor device of an example disclosed in this specification, each of the bottom regions may extend in the second direction and be arranged at intervals in the first direction.
[0016] In such a configuration, the direction in which the bottom region extends and the direction in which the connection region extends intersect. Therefore, for example, compared with a configuration in which the bottom region and the connection region extend in parallel, the bottom region and the connection region can be more reliably connected.
[0017] In a semiconductor device of an example disclosed in this specification, the outer portion may further include a plurality of p-type connection auxiliary regions that each connect the body region and the bottom region and are arranged at intervals in the first direction.
[0018] In such a configuration, in the outer portion, when the body diode is reverse-biased, in addition to the connection region, holes flow from the bottom region to the body region through the connection auxiliary region. Since the holes can flow branching into many paths, the switching loss can be further reduced. Also, since the connection auxiliary regions are arranged at intervals in the first direction, the range of the depletion layer spreading from the connection auxiliary regions into the drift region is narrow, and it is difficult to limit the path of the main current when the semiconductor device is turned on. Therefore, an increase in the on-resistance can be suppressed.
[0019] In a semiconductor device of an example disclosed in this specification, the interval in the second direction of the trench in the outer portion may be narrower than the interval in the second direction of the trench in the central portion.
[0020] In such a configuration, since the channel density in the outer portion is high, the channel resistance (i.e., the on-resistance) can be reduced.
[0021] (Example 1) Figs. 1 to 4 show a semiconductor device 10 of Example 1. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). As shown in Fig. 1, the semiconductor device 10 has a semiconductor substrate 12. The semiconductor substrate 12 has an element region 62 and a peripheral region 64. In the semiconductor substrate 12 of the element region 62, the structure of the MOSFET is formed. The peripheral region 64 is arranged around the element region 62. Although not shown, in the semiconductor substrate 12 of the peripheral region 64, a peripheral breakdown voltage structure such as a guard ring is formed. The semiconductor substrate 12 is made of SiC (silicon carbide). However, the material of the semiconductor substrate 12 is not particularly limited, and for example, other semiconductor materials such as Si (silicon) and GaN (gallium nitride) may be used. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, a direction parallel to the semiconductor substrate 12 and perpendicular to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction.
[0022] As shown in Figure 1, a plurality of trenches 22 are provided in the upper surface 12a of the semiconductor substrate 12 within the element region 62. Each trench 22 extends long along the y-direction. Each trench 22 extends parallel to one another. Each trench 22 is arranged with spacing in the x-direction. Figure 2 is an enlarged view including the x-direction boundary between the element region 62 and the peripheral region 64 in Figure 1. Note that the components on the upper surface 12a of the semiconductor substrate 12 (insulating film, electrodes, etc.) are not shown in Figures 1 and 2. As shown in Figures 2 to 4, a gate insulating film 24 and a gate electrode 26 are arranged in each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is located inside each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.
[0023] As shown in Figures 3 and 4, the upper surface of each gate electrode 26 is covered by an interlayer insulating film 28. In the peripheral region 64, almost the entire upper surface 12a of the semiconductor substrate 12 is covered by an insulating film 65. An upper electrode 70 is located on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 in the portion within the element region 62 where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is located on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with almost the entire lower surface 12b of the semiconductor substrate 12.
[0024] The element region 62 is provided with multiple source regions 30, multiple contact regions 31, a body region 32, a drift region 34, a drain region 35, multiple bottom regions 36, and multiple connection regions 38.
[0025] Each source region 30 is an n-type region. Each source region 30 is positioned so as to be exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24 in the trench 22 on the side surface of the trench 22.
[0026] Each contact region 31 is a p-type region. Each contact region 31 is positioned to be exposed on the upper surface 12a of the semiconductor substrate 12. Each contact region 31 is positioned between two source regions 30. Each contact region 31 is in ohmic contact with the upper electrode 70.
[0027] The body region 32 is a p-type region. The body region 32 has a lower p-type impurity concentration than the contact region 31. The body region 32 is in contact with the source region 30 and the contact region 31 from below. The body region 32 is in contact with the gate insulating film 24 in each trench 22 below the source region 30. The body region 32 is positioned to span from the element region 62 into the peripheral region 64.
[0028] The drift region 34 is an n-type region. The drift region 34 is located below the body region 32. The drift region 34 is in contact with the body region 32 from below. The drift region 34 is in contact with the gate insulating film 24 in each trench 22 below the body region 32. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is located spanning from the element region 62 into the peripheral region 64.
[0029] The drain region 35 is an n-type region. The drain region 35 is located below the drift region 34. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is in contact with the drift region 34 from below. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72 on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is located spanning from the element region 62 into the peripheral region 64.
[0030] Each bottom region 36 is a p-type region. Each bottom region 36 extends in a direction perpendicular to the trench 22 (x-direction). As shown in Figure 2, each bottom region 36 is arranged with spacing in the y-direction. Each bottom region 36 is located below the trench 22, spaced apart from the bottom surface of the trench 22. Each bottom region 36 is surrounded by a drift region 34. Each bottom region 36 extends from the element region 62 into the peripheral region 64.
[0031] Each connection region 38 is a p-type region. As shown in Figure 2, each connection region 38 extends parallel to each trench 22 (i.e., in the y-direction). Each connection region 38 is spaced apart in a direction perpendicular to each trench 22. When viewed from above, each connection region 38 is located in the area between the two trenches 22. As shown in Figure 3, each connection region 38 connects the body region 32 and the bottom region 36. Connection regions 38 are also located within the peripheral region 64.
[0032] As described above, each bottom region 36 is connected to the body region 32 via each connection region 38. Therefore, each bottom region 36 is connected to the upper electrode 70 via the connection region 38, the body region 32, and the contact region 31. Consequently, the potential of each bottom region 36 is approximately equal to the potential of the upper electrode 70.
[0033] As shown in Figure 1, the element region 62 has two outer portions 62a and a central portion 62b. The outer portions 62a are located at both ends of the element region 62 in the x-direction. Figures 2-4 only show one end of the element region 62 in the x-direction, but the other end of the element region 62 in the x-direction also has an outer portion 62a. The central portion 62b is located between the two outer portions 62a.
[0034] As shown in Figure 3, in the central section 62b, connection areas 38 are provided in each of the ranges between multiple trenches 22. That is, in the central section 62b, connection areas 38 and trenches 22 are arranged alternately along the x-direction. On the other hand, in the outer section 62a, no connection areas 38 are provided in the ranges between two trenches 22. Within the peripheral section 64, connection areas 38 are provided at the same intervals as in the central section 62b. Therefore, the interval d1 of the connection areas 38 in the outer section 62a is wider than the interval d2 of the connection areas 38 in the central section 62b. Although not shown, the interval of the connection areas 38 is similarly wider in the other outer section 62a. The distance between two adjacent trenches 22 is approximately equal in the outer section 62a and the central section 62b.
[0035] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 72 than to the upper electrode 70. When a voltage above the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in contact with the gate insulating film 24, and the semiconductor device 10 is turned on. When the voltage applied to the gate electrode 26 is reduced to below the gate threshold, the channel disappears, and the semiconductor device 10 is turned off.
[0036] When the semiconductor device 10 is turned off, the potential of the lower electrode 72 is much higher than the potential of the upper electrode 70. In this state, the drift region 34 has a potential close to that of the lower electrode 72. Also, as described above, the bottom region 36 has a potential approximately equal to that of the upper electrode 70. Therefore, a high reverse voltage is applied to the pn junction at the interface between the drift region 34 and the bottom region 36. Consequently, a depletion layer spreads widely from each bottom region 36 into the drift region 34. This suppresses electric field concentration near the lower end of the trench 22, ensuring the breakdown voltage of the semiconductor device 10. Furthermore, a reverse voltage is also applied to the pn junction at the interface between the connection region 38 and the drift region 34. Therefore, a depletion layer also spreads from the connection region 38 into the drift region 34.
[0037] When the semiconductor device 10 is turned on, holes are supplied from the upper electrode 70 to each bottom region 36 via the contact region 31, body region 32, and connection region 38. This causes the depletion layer that had spread from the connection region 38 and bottom region 36 into the drift region 34 to contract. Until holes are supplied to the connection region 38 and bottom region 36, the depletion layer spreads from the connection region 38 and bottom region 36 into the drift region 34. Therefore, immediately after the semiconductor device 10 is turned on, the path of the main current is restricted by this depletion layer. However, in this embodiment, the spacing d1 of the connection region 38 is wide in the outer part 62a of the element region 62. Therefore, in the outer part 62a, there is a relatively wide area in the drift region 34 that is not depleted, and even immediately after the semiconductor device 10 is turned on, a wide area of the drift region 34 (especially the drift region 34 located between the trenches 22) can be used as the path of the main current. Therefore, in the semiconductor device 10 of this embodiment, the on-resistance of the entire element region 62 can be reduced.
[0038] Here, a parasitic pn diode (hereinafter referred to as a body diode) is formed inside the semiconductor substrate 12 by a p-type contact region 31 and body region 32, and an n-type drift region 34 and drain region 35. During the operation of the semiconductor device 10, a higher potential may be applied to the upper electrode 70 than to the lower electrode 72. When the upper electrode 70 is at a higher potential than the lower electrode 72 (forward bias), the body diode turns on. That is, holes flow from the upper electrode 70 into the drift region 34 via the contact region 31 and body region 32.
[0039] Subsequently, when the lower electrode 72 switches to a higher potential than the upper electrode 70 (reverse bias), during the process of the body diode turning off, the holes accumulated in the drift region 34 flow to the upper electrode 70 via the body region 32 and the contact region 31. In other words, a recovery current flows. In the semiconductor device 10, multiple bottom regions 36 connected to the body region 32 via a connection region 38 are provided inside the drift region 34. Therefore, when reverse bias is applied, the holes accumulated in the drift region 34 easily flow from the drift region 34 to the bottom regions 36, and most of the holes flow to the body region 32 via the bottom regions 36 and the connection region 38.
[0040] In this embodiment, the spacing d2 of the connection regions 38 in the central portion 62b of the element region 62 is narrow. That is, the connection regions 38 are densely arranged in the central portion 62b. As a result, there are many paths for holes to flow from the bottom region 36 to the body region 32, and the holes are quickly discharged to the upper electrode 70. Therefore, the switching loss occurring in the central portion 62b is small, and the temperature rise in the central portion 62b is suppressed. On the other hand, the spacing d1 of the connection regions 38 in the outer portion 62a of the element region 62 is wide. As a result, there are fewer paths for holes to flow from the bottom region 36 to the body region 32. However, the outer portion 62a is adjacent to the peripheral region 64. Since there is no contact region 31 in the peripheral region 64, holes are less likely to accumulate in the drift region 34 of the peripheral region 64 when forward biased. As a result, the density of holes accumulated in the drift region 34 when forward biased is lower in the outer portion 62a compared to the central portion 62b. Therefore, the recovery current in the outer portion 62a is small, and even if the spacing d1 of the connection regions 38 in the outer portion 62a is wide, the density of recovery current flowing through each connection region 38 is not very high. As a result, the switching loss generated in the outer portion 62a is small, and the temperature rise of the outer portion 62a is suppressed. In this way, in this embodiment, when recovery current flows, the temperature rise in the entire element region 62 is suppressed, and switching losses are suppressed.
[0041] As described above, when the semiconductor device 10 is turned off, a depletion layer spreads from the body region 32, connection region 38, and bottom region 36 to the drift region 34. As a result, almost the entire area of the drift region 34 is depleted. When a high voltage is applied to the lower electrode 72 while the semiconductor device 10 is turned off, an avalanche current flows from the drift region 34 to the upper electrode 70 via the bottom region 36, connection region 38, body region 32, and contact region 31. In the central portion 62b, the spacing between the connection regions 38 is narrow, so the density of avalanche current flowing through each connection region 38 is low. This suppresses the temperature rise in the central portion 62b. In the outer portion 62a, the spacing between the connection regions 38 is wide, so the density of avalanche current flowing through each connection region 38 is high. However, since the outer portion 62a is adjacent to the outer peripheral portion 64, the outer peripheral portion 62a has high heat dissipation. Therefore, the temperature rise in the outer portion 62a is suppressed. In this way, when an avalanche current flows, the temperature rise in the central portion 62b and the outer portion 62a is suppressed. Thus, in this embodiment, when an avalanche current flows, the temperature rise in the entire element region 62 is suppressed. Therefore, the semiconductor device 10 has high avalanche withstand capability.
[0042] Furthermore, when the semiconductor device 10 is in operation, the semiconductor substrate 12 generates heat, but heat dissipates more easily from the outer portion 62a of the element region 62 compared to the central portion 62b. Also, the outer portion 62a is adjacent to the peripheral region 64 where the main current does not flow. For this reason, the outer portion 62a does not heat up as easily as the central portion 62b, and the temperature of the outer portion 62a is lower than that of the central portion 62b. Therefore, even if the temperature of the outer portion 62a rises, the effect is small. As described above, this semiconductor device 10 can reduce on-resistance while suppressing an increase in switching loss and a decrease in avalanche withstand capability.
[0043] Furthermore, in this embodiment, the direction in which the bottom region 36 extends (x direction) and the direction in which the connecting region 38 extends (y direction) intersect. Therefore, compared to a configuration in which the bottom region 36 and the connecting region 38 extend parallel to each other, for example, the bottom region 36 and the connecting region 38 can be connected more reliably.
[0044] (Example 2) In the semiconductor device 100 of Example 2, the configuration of the connection regions 38 differs from that of Example 1. In Example 2, the spacing of the connection regions 38 in the outer portion 62a widens towards the edge of the element region 62. As shown in Figure 5, in this example, nine trenches 22 are arranged in the outer portion 62a. Also, four connection regions 38 are arranged in the outer portion 62a. In Example 2, the width of the outer portion 62a in the x-direction is wider than in Example 1. For convenience, below, the connection regions will be referred to as 38a, 38b, 38c, and 38d, starting from the outermost connection region 38 (i.e., the one closest to the peripheral region 64) and moving towards the central portion 62b. As shown in Figure 5, the spacing d3 between connection region 38a and connection region 38b is wider than the spacing d4 between connection region 38b and connection region 38c. The spacing d4 is wider than the spacing d5 between connection region 38c and connection region 38d. Furthermore, the intervals d3, d4, and d5 are wider than the interval d6 of the connection region 38 in the central part 62b.
[0045] Four trenches 22 are located between connection area 38a and connection area 38b, three trenches 22 are located between connection area 38b and connection area 38c, and two trenches 22 are located between connection area 38c and connection area 38d. The distance between two adjacent trenches 22 is approximately equal in the outer portion 62a and the central portion 62b.
[0046] When a forward bias voltage is applied to the body diode, the amount of holes accumulated in the drift region 34 decreases towards the edge of the element region 62. In the semiconductor device 100 of Example 2, the spacing of the connection regions 38 is progressively wider in the outer portion 62a, from the central portion 62b towards the peripheral region 64. In Example 2, the connection regions 38 are more sparsely arranged than in Example 1, thus further reducing on-resistance. In addition, since the spacing d3 to d5 of the connection regions 38 is adjusted according to the distribution of the amount of holes accumulated in the drift region 34, switching losses can be efficiently reduced.
[0047] (Example 3) The semiconductor device 200 of Example 3 differs from Example 1 in that it is further provided with a plurality of p-shaped connection auxiliary regions 39 on the outer portion 62a. As shown in Figures 6 and 7, each connection auxiliary region 39 is located in the outer portion 62a within the range between the two trenches 22. As shown in Figure 6, the connection auxiliary regions 39 are spaced apart in the y direction. As shown in Figure 7, each connection auxiliary region 39 connects the body region 32 and the bottom region 36. As shown in Figure 8, the connection auxiliary regions 39 are not located in sections where the bottom region 36 is not provided.
[0048] In Example 3, when a reverse bias voltage is applied to the body diode in the outer portion 62a, holes flow from the bottom region 36 to the body region 32 via the auxiliary connection region 39, in addition to the connection region 38. In Example 3, since holes can branch and flow through more paths than in Example 1, switching losses can be further reduced. The auxiliary connection region 39 is also spaced apart in the y direction. Specifically, as shown in Figures 8 and 9, the auxiliary connection region 39 is located only in the area directly above the bottom region 36. Therefore, when the semiconductor device 200 is off, the depletion layer extending from the auxiliary connection region 39 to the drift region 34 does not spread over a wide area within the drift region 34. Thus, even with the presence of the auxiliary connection region 39, the path of the main current is not easily restricted when the semiconductor device 200 is turned on. Furthermore, the auxiliary connection region 39 is located only in the area directly above the bottom region 36, which does not function as a path for the main current when the semiconductor device 200 is turned on. Therefore, even with the presence of the connection auxiliary region 39, the on-resistance hardly increases. As described above, the semiconductor device 200 of Example 3 can further reduce switching losses while suppressing the increase in on-resistance.
[0049] (Example 4) In the semiconductor device 300 of Example 4, the spacing of the trenches 22 in the outer portion 62a is different from that of Example 1. As shown in Figure 9, in Example 4, three trenches 22 are arranged in the outer portion 62a within the range between two connection regions 38. The spacing D1 of the trenches 22 in the outer portion 62a is narrower than the spacing D2 of the trenches 22 in the central portion 62b. As shown in Figure 10, the semiconductor region between two adjacent trenches 22 in the outer portion 62a is provided with a source region 30, a contact region 31, a body region 32, and a drift region 34, respectively.
[0050] In Example 4, the spacing D1 of the trenches 22 in the outer portion 62a is narrow (i.e., the trenches 22 are densely arranged), so the channel density in the outer portion 62a is higher than in Example 1. Therefore, in Example 4, the channel resistance (i.e., on-resistance) can be reduced further. In this example as well, the spacing of the connection regions 38 in the outer portion 62a is wider than the spacing of the connection regions 38 in the central portion 62b, so the path of the main current is not easily restricted in the outer portion 62a. For this reason, even if the spacing D1 of the trenches 22 in the outer portion 62a is narrowed, the on-resistance due to the presence of the connection regions 38 does not increase much.
[0051] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples illustrated above. Modifications of the embodiments described above are described below.
[0052] (modified version) In the embodiments described above, the connection region 38 was positioned within the range between the trenches 22. That is, the connection region 38 was positioned at a distance from the trenches 22. However, for example, as shown in Figure 11, the connection region 38 may be positioned in contact with the side surface of the trench 22. The connection region 38 may be in contact with the gate insulating film 24 in the trench 22 on the lower side of the body region 32. The connection region 38 may extend in the y-direction along the side surface of the trench 22. In this modified example, the contact region 31 may also be positioned in contact with the side surface of the trench 22. The contact region 31 may be in contact with the gate insulating film 24 in the trench 22 on the side surface of the trench 22.
[0053] Furthermore, in the embodiment described above, the bottom region 36 extended in a direction perpendicular to the trench 22, but as shown in Figure 12, the bottom region 36 may extend parallel to the trench 22 (y-direction). The bottom region 36 may extend along the bottom surface of the trench at a distance from the bottom surface of the trench 22. The bottom region 36 may be arranged at a distance in a direction perpendicular to the trench 22 (x-direction).
[0054] The technical elements described herein or in the drawings demonstrate technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated herein or in the drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness in itself. [Explanation of symbols]
[0055] 10, 100, 200, 300: Semiconductor devices 12: Semiconductor substrates 12a:Top surface 12b: Bottom surface 22: Trench 24: Gate Insulator 26: Grid control point 30: Source area 31: Contact area 32: Body area 34: Drift Region 35: Drain area 36: Bottom area 38: Connection area 39: Connection assistance area 62: Element area 62a:Outer part 62b: Central part 64: Peripheral area
Claims
1. A semiconductor substrate (12) having an element region (62) and a peripheral region (64) arranged around the element region, A plurality of trenches (22) are provided on the upper surface (12a) of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction perpendicular to the first direction on the upper surface, The gate insulating film (24) covering the inner surface of each trench, A gate electrode (26) is disposed within each of the trenches and is insulated from the semiconductor substrate by the gate insulating film. It is equipped with, The element region is An n-type source region (30) is exposed on the upper surface of the semiconductor substrate and is in contact with the gate insulating film in each of the trenches, A p-type contact region (31) exposed on the upper surface of the semiconductor substrate, A p-shaped body region (32) is located below the source region, in contact with the gate insulating film in each trench, and in contact with the contact region, An n-type drift region (34) is located below the body region, in contact with the gate insulating film in each trench, and is separated from the source region by the body region, A p-shaped bottom region (36) located at the bottom of the trench, Each of the p-shaped connection regions (38) connects the body region and the bottom region, each extends in the first direction, and is arranged at intervals in the second direction. It is equipped with, The element region has an outer portion (62a) located at both ends of the element region in the second direction, and a central portion (62b) located between the outer portions. The spacing of the connection regions in the second direction in the outer portion is wider than the spacing of the connection regions in the second direction in the central portion. Semiconductor devices (10, 100, 200, 300).
2. The semiconductor device according to claim 1, wherein the bottom region is arranged at a distance from the bottom surface of the trench.
3. The drift region is A first drift region located above the bottom region, A semiconductor device according to claim 1 or 2, comprising a second drift region located below the bottom region.
4. The semiconductor device according to claim 3, wherein the n-type impurity concentration in the first drift region is higher than the n-type impurity concentration in the second drift region.