Semiconductor equipment

JP7863520B2Active Publication Date: 2026-05-21RENESAS ELECTRONICS CORP
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
RENESAS ELECTRONICS CORP
Filing Date
2023-02-01
Publication Date
2026-05-21

AI Technical Summary

Technical Problem

Existing IGBTs suffer from self-turn-on phenomena due to parasitic capacitances, which are not adequately addressed by existing suppression techniques without compromising the IE effect.

Method used

A semiconductor device design with a specific configuration of trench gates and emitters, including a p+ type floating layer between trench gates and emitters, to enhance parasitic capacitance management and suppress self-turn-on, while maintaining the IE effect.

Benefits of technology

The design effectively suppresses self-turn-on phenomena, improves response speed to gate voltage, reduces switching losses, and enhances carrier storage and discharge capabilities.

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Patent Text Reader

Abstract

To suppress a self-turn-on phenomenon of an IGBT.SOLUTION: A semiconductor device includes first and second active cell regions and an inactive cell region between the first and second active cell regions, on a semiconductor substrate, wherein each of the first and second active cell regions comprises: a trench gate; a first trench emitter; a first hole barrier layer of a first conductivity type formed between the trench gate and the first trench emitter; a base layer of a second conductivity type formed on an upper portion of the first hole barrier layer; an emitter layer of the first conductivity type formed on an upper portion of the base layer; and a latch-up prevention layer of the second conductivity type formed on an upper portion of the first hole barrier layer, wherein the inactive cell region comprises: a second trench emitter formed adjacently to the trench gate in the first active cell region; and a floating layer of the second conductivity type formed between the trench gate and the second trench emitter.SELECTED DRAWING: Figure 2
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