Semiconductor device, method for controlling a semiconductor device, and method for manufacturing a semiconductor device.

Abstract

To expand an acceptable range of a time difference between the transition of a first signal and the transition of a second signal.SOLUTION: A semiconductor device includes a semiconductor substrate, a first semiconductor layer and a second semiconductor layer that are positioned exclusively on a surface layer of the semiconductor substrate, a third semiconductor layer positioned on the opposite side of the semiconductor substrate with respect to the first semiconductor layer and the second semiconductor layer, a fourth semiconductor layer and a fifth semiconductor layer that are positioned exclusively on the opposite side of the semiconductor substrate with respect to the third semiconductor layer, and a first electrode, a second electrode, and a third electrode whose surfaces have an insulating property. The first electrode extends to reach the first semiconductor layer through the first semiconductor layer, the second semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer. The second electrode extends to reach the semiconductor substrate through the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, or through the second semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer. The third electrode extends to reach the semiconductor substrate through the fourth semiconductor layer and the third semiconductor layer, separates the first semiconductor layer from the second semiconductor layer, and has the second semiconductor layer held between the third electrode and the second electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to semiconductor devices. [Background technology]

[0002] As a semiconductor device, the insulated gate bipolar transistor (hereinafter referred to as "IGBT") is well known. In an IGBT, for example, an impurity layer is provided on the upper surface of the semiconductor substrate. For example, trenches are periodically provided that penetrate the impurity layer. Insulating layers are provided on the sides and bottom of the trenches. A conductor is provided in the trenches, surrounded by the insulating layer. For example, the impurity layer functions as a channel layer, and the semiconductor substrate functions as a drift layer.

[0003] IGBTs may employ two types of trenches with different depths (see, for example, Patent Document 1). For example, a deep trench reaches the semiconductor substrate, which acts as a drift layer, while a shallow trench does not reach the drift layer.

[0004] The signals controlling the operation of the semiconductor device are applied separately to the conductors located in the deep trenches and the conductors located in the shallow trenches. These signals control the carrier concentration in the channel layer around each trench. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2016-154218 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] As an example of the operation when an IGBT having the above configuration is turned off, the following sequence is assumed. However, a first signal is applied to the conductor located in the shallow trench, and a second signal is applied to the conductor located in the deep trench: the off transition of the second signal is earlier than the off transition of the first signal. Here, "off transition" is a voltage transition that acts in the direction of reducing the carrier concentration as described above.

[0007] In this sequence, the carrier concentration on the impurity layer side of the semiconductor substrate is reduced in advance by the off-transition of the second signal, and then the semiconductor device is turned off by the off-transition of the first signal. This sequence shortens the time spent on turning off the semiconductor device and reduces the turn-off loss after the off-transition of the first signal. On the other hand, the decrease in the carrier concentration of the semiconductor substrate increases the forward voltage of the semiconductor device, and the forward conduction loss from the off-transition of the second signal to the off-transition of the first signal increases.

[0008] It is conceivable that the increase in forward conduction loss may outweigh the decrease in turn-off loss after the off-transition of the first signal. In this case, the total amount of loss that occurs after the off-transition of the second signal may increase compared to the case where the off-transitions of the first and second signals occur in parallel.

[0009] As a technique to minimize the total amount, one could consider optimizing the time difference between the off-transition of the second signal and the off-transition of the first signal. However, the acceptable range of this time difference is narrow, and problems such as variations in the total amount of loss and difficulty in controlling the off-transitions to obtain the optimal time difference can be anticipated.

[0010] The technology disclosed in this specification has been made in view of these problems and aims to expand the acceptable range of time difference between the transition of the first signal and the transition of the second signal. [Means for solving the problem]

[0011] A semiconductor device according to a first aspect of the technology of this disclosure comprises: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type located on the surface layer of the semiconductor substrate; a second semiconductor layer of the first conductivity type located exclusively with respect to the first semiconductor layer on the surface layer of the semiconductor substrate and having a higher peak impurity concentration than the semiconductor substrate; a third semiconductor layer of the second conductivity type located on the opposite side of the semiconductor substrate from the first and second semiconductor layers; a fourth semiconductor layer of the second conductivity type selectively located on the opposite side of the semiconductor substrate from the third semiconductor layer and having a higher peak impurity concentration than the third semiconductor layer; a fifth semiconductor layer of the first conductivity type located exclusively with respect to the fourth semiconductor layer on the opposite side of the semiconductor substrate from the third semiconductor layer and having a higher peak impurity concentration than the second semiconductor layer; and the first semiconductor layer, second semiconductor layer, third semiconductor layer, fourth semiconductor layer, and the The semiconductor device comprises: a sixth semiconductor layer of second conductivity type located on the opposite side of the fifth semiconductor layer; a first electrode that penetrates the fifth and third semiconductor layers, extends to the first semiconductor layer at a distance from the sixth semiconductor layer beyond the boundary between the second semiconductor layer and the semiconductor substrate, and has an insulating surface; a second electrode that penetrates the second, fourth, and third semiconductor layers, or penetrates the second, fifth, and third semiconductor layers, extends to the semiconductor substrate, is closer to the sixth semiconductor layer than either the first or second semiconductor layer, and has an insulating surface; and a third electrode that penetrates the fourth and third semiconductor layers, extends to the semiconductor substrate, is closer to the sixth semiconductor layer than either the first or second semiconductor layer, separates the first semiconductor layer from the second semiconductor layer, sandwiches the second semiconductor layer together with the second electrode, and has an insulating surface. The second electrode penetrates the fifth semiconductor layer and the third semiconductor layer. ru.

[0012] The control method of a semiconductor device according to the second aspect of the technology related to the present disclosure is a method for controlling the semiconductor device according to the present disclosure. When a first signal is applied to the first electrode and a second signal is applied to the second electrode, and when turning off the semiconductor device by transitioning either the first signal or the second signal, the first signal transitions with a delay relative to the second signal.

Advantages of the Invention

[0013] According to the semiconductor device and its control method related to the present disclosure, the allowable range of the time difference by which the off-transition of the first signal applied to the first electrode is delayed from the off-transition of the second signal applied to the second electrode is expanded.

[0014] The objects, features, aspects, and advantages related to the technology disclosed in the present specification will become even clearer from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0015] [Figure 1] It is a cross-sectional view showing an example of the configuration of a semiconductor device according to Embodiment 1. [Figure 2] It is a cross-sectional view showing another example of the configuration of a semiconductor device according to Embodiment 1. [Figure 3] It is a cross-sectional view showing another example of the configuration of a semiconductor device according to Embodiment 1. [Figure 4] It is a circuit diagram illustrating a circuit for applying two types of gate voltages to an IGBT. [Figure 5] It is a waveform diagram illustrating the sequence of two types of gate voltages. [Figure 6] It is a waveform diagram illustrating the operation in which an IGBT turns off. [Figure 7] It is a cross-sectional view illustrating the configuration of a semiconductor device according to a comparative example. [Figure 8] It is a graph showing the dependence of the total loss on the time difference. [Figure 9] It is a waveform diagram illustrating the operation in which an IGBT turns off in a comparative example. [Figure 10] It is a waveform diagram showing an enlarged view of the region R10 in FIG. 9. [Figure 11] It is a waveform diagram showing an enlarged view of the region R11 in FIG. 9. [Figure 12] It is a waveform diagram illustrating the operation in which the IGBT turns off in the embodiment. [Figure 13] It is a waveform diagram showing an enlarged view of the region R13 in FIG. 12. [Figure 14] It is a waveform diagram showing an enlarged view of the region R14 in FIG. 12. [Figure 15] It is a graph showing the dependence of the total loss on the saturation voltage. [Figure 16] It is a waveform diagram showing another example of the sequence of two gate voltages. [Figure 17] It is a waveform diagram illustrating the on-transition of two gate voltages. [Figure 18] It is a waveform diagram illustrating the on-transition of two gate voltages. [Figure 19] It is a waveform diagram illustrating the operation when the semiconductor device according to Embodiment 1 turns on. [Figure 20] It is a waveform diagram illustrating the operation when the semiconductor device according to Embodiment 1 turns on. [Figure 21] It is a cross-sectional view illustrating the configuration of the semiconductor device according to Embodiment 2. [Figure 22] It is a waveform diagram illustrating the operation when the semiconductor device according to Embodiment 2 turns on. [Figure 23] It is a cross-sectional view illustrating the configuration of the semiconductor device according to Embodiment 3. [[ID=4,2]] [Figure 24] It is a cross-sectional view illustrating the configuration of the semiconductor device according to Embodiment 4. [Figure 25] It is a graph illustrating the relationship between the breakdown voltage of the semiconductor device and the distance between the trench electrodes. [Figure 26] It is a cross-sectional view illustrating part of the first manufacturing method of the semiconductor device according to Embodiment 1 in the order of processes. [Figure 27]This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 28] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 29] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 30] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 31] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 32] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 33] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 34] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 35] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 36] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 37] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 1, in order of the process steps. [Figure 38] This is a cross-sectional view illustrating a part of the second manufacturing method of the semiconductor device according to Embodiment 1, in order of the process steps. [Figure 39] This is a cross-sectional view illustrating a part of the second manufacturing method of the semiconductor device according to Embodiment 1, in order of the process steps. [Figure 40] This is a cross-sectional view illustrating a part of the second manufacturing method of the semiconductor device according to Embodiment 1, in order of the process steps. [Figure 41] This is a cross-sectional view illustrating a part of the second manufacturing method of the semiconductor device according to Embodiment 1, in order of the process steps. [Figure 42] This graph illustrates the relationship between trench depth and mask opening width. [Figure 43] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 4, in order of the process steps. [Figure 44] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 4, in order of the process steps. [Figure 45] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 4, in order of the process steps. [Figure 46] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 4, in order of the process steps. [Figure 47] This is a cross-sectional view illustrating a part of the first manufacturing method of a semiconductor device according to Embodiment 4, in order of the process steps. [Figure 48] This is a cross-sectional view illustrating a part of the second method for manufacturing a semiconductor device according to Embodiment 4. [Figure 49] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to Embodiment 5. [Figure 50] This is a cross-sectional view showing another example of the configuration of a semiconductor device according to Embodiment 5. [Figure 51] This is a cross-sectional view showing another example of the configuration of a semiconductor device according to Embodiment 5. [Figure 52] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to Embodiment 6. [Figure 53] This is a cross-sectional view showing another example of the configuration of a semiconductor device according to Embodiment 6. [Figure 54] This is a cross-sectional view showing another example of the configuration of a semiconductor device according to Embodiment 6. [Modes for carrying out the invention]

[0016] The embodiments will be described below with reference to the attached drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are illustrative, and not all of them are necessarily essential features for the embodiments to be implementable.

[0017] In the descriptions contained herein, even if terms such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back" are used to mean specific locations or directions, these terms are used for convenience to facilitate understanding of the embodiments and are not related to the actual locations or directions in which the embodiments are carried out.

[0018] The presence or absence of the symbols "+" and "-" to the right of the semiconductor conductivity type symbols "N" and "P" indicates the relative levels of impurity concentrations, such as the peak values ​​of impurity concentrations. For example, N+ type semiconductors have a higher N-type impurity concentration than N-type semiconductors, and N-type semiconductors have a higher N-type impurity concentration than N-type semiconductors. P+ type semiconductors have a higher P-type impurity concentration than P-type semiconductors, and P-type semiconductors have a higher P-type impurity concentration than P-type semiconductors. Such relative levels of impurity concentrations are relative; for example, even if two different semiconductors are described as N-type semiconductors, this does not mean that their impurity concentrations are equal.

[0019] <Embodiment 1> Figure 1 is a cross-sectional view illustrating the configuration of semiconductor device 100A according to Embodiment 1. Figure 2 is a cross-sectional view showing an example of the configuration of semiconductor device 100A, and Figure 3 is a cross-sectional view showing another example of the configuration of semiconductor device 100A.

[0020] Both the cross-sections shown in Figure 2 and Figure 3 appear when viewed from the direction of the arrow at position QQ in Figure 1. The cross-section exemplified in Figure 1 is also the cross-section that appears when viewed from the direction of the arrow at position JJ in Figure 2, and the cross-section that appears when viewed from the direction of the arrow at position KK in Figure 3. The configuration exemplified in Figure 2 contributes, for example, to suppressing the multi-layering of wiring using polysilicon, and consequently to improving productivity.

[0021] The semiconductor device 100A comprises a semiconductor substrate 1, semiconductor layers 2, 31, 32, 41, 42, 5, 10, 11, and trench electrodes 81, 82, 9. "Trench electrode" is a provisional name for an electrode that extends in a groove-like manner in the thickness direction of the semiconductor substrate 1, and its specific configuration will be described later.

[0022] The semiconductor substrate 1 is made of, for example, N-type silicon. The semiconductor device 100A is typically an IGBT, and the semiconductor substrate 1 functions, for example, as a drift layer.

[0023] The semiconductor layers 31 and 32 are exclusively located on the surface of the semiconductor substrate 1. The semiconductor layers 31 and 32 are made of, for example, N-type silicon. The semiconductor layers 31 and 32 function as, for example, carrier storage layers. In this embodiment, for example, the semiconductor layers 31 and 32 have the same peak value of impurity concentration.

[0024] In Embodiment 3, described later, the case where the impurity concentration of the semiconductor layer 31 is equal to the impurity concentration of the semiconductor substrate 1 is explained, and the semiconductor layer 31 is considered as part of the semiconductor substrate 1. In Embodiment 4, described later, the case where the peak value of the impurity concentration of the semiconductor layer 31 is lower than the peak value of the impurity concentration of the semiconductor layer 32 is explained.

[0025] Semiconductor layer 2 is located on the opposite side of semiconductor substrate 1 from semiconductor layers 31 and 32. The conductivity type of semiconductor layer 2 is the opposite of that of semiconductor substrate 1 and semiconductor layers 31 and 32; for example, it is realized from P-type silicon. Semiconductor layer 2 functions, for example, as the channel layer of an IGBT.

[0026] Semiconductor layer 5 is selectively located on the opposite side of semiconductor substrate 1 from semiconductor layer 2. Semiconductor layer 5 has the same conductivity type as semiconductor layer 2, but with a higher peak impurity concentration than semiconductor layer 2, and is realized, for example, with P+ type silicon. For example, semiconductor layer 5 functions as the emitter layer of an IGBT.

[0027] Semiconductor layers 41 and 42 are located on the opposite side of semiconductor layer 2 from semiconductor substrate 1 and are exclusively adjacent to semiconductor layer 5. Both semiconductor layers 41 and 42 have the same conductivity type as semiconductor substrate 1 and semiconductor layers 31 and 32, but have a higher peak impurity concentration than semiconductor layer 32, and are realized, for example, with N+ type silicon. For example, semiconductor layers 41 and 42 function as emitter layers of an IGBT.

[0028] The semiconductor layer 11 is located on the opposite side of the semiconductor substrate 1 from all of the semiconductor layers 2, 31, 32, 41, 42, and 5. The semiconductor layer 11 has the same conductivity type as semiconductor layer 2 and is realized, for example, from P-type silicon. For example, the semiconductor layer 11 functions as the collector layer of an IGBT. The semiconductor layer 11 is electrically connected to the collector electrode C of the IGBT by, for example, a structure not shown.

[0029] The semiconductor layer 10 is located between the semiconductor substrate 1 and the semiconductor layer 11, in contact with both. The semiconductor layer 10 has the same conductivity type as the semiconductor substrate 1, but with a higher peak impurity concentration than the semiconductor substrate 1, and is realized, for example, from N-type silicon. For example, the semiconductor layer 10 functions as a buffer layer for an IGBT.

[0030] The trench electrode 81 penetrates the semiconductor layers 41 and 42, and extends to the semiconductor layer 31 at a distance from the semiconductor layer 11 (away from the plane of the paper in Figure 1) beyond the boundary between the semiconductor layer 32 and the semiconductor substrate 1. The surface of the trench electrode 81, specifically the surface facing the semiconductor layers 41, 42, and 41, is insulating. The trench electrode 81 is electrically connected to the gate electrode G1 of the IGBT by, for example, a structure not shown.

[0031] The trench electrode 82 extends through semiconductor layers 2, 42, and 32 to the semiconductor substrate 1. The trench electrode 82 is closer to semiconductor layer 11 than to either semiconductor layer 31 or 32. The surface of the trench electrode 82, specifically the surface facing the semiconductor substrate 1 and semiconductor layers 42, 2, and 32, is insulating. The trench electrode 82 is electrically connected to the gate electrode G2 of the IGBT by, for example, a structure not shown.

[0032] The trench electrode 9 extends through semiconductor layers 5 and 2 to the semiconductor substrate 1. If semiconductor layers 31 and 32 are considered as a single unit, then both trench electrodes 9 and 82 can be said to penetrate semiconductor layers 31 and 32. Trench electrode 9 is closer to semiconductor layer 11 than either semiconductor layer 31 or 32. Trench electrode 9 separates semiconductor layer 31 from semiconductor layer 32. Trench electrode 9, together with trench electrode 82, sandwiches semiconductor layer 32. The surface of trench electrode 9, specifically the surface facing semiconductor substrate 1 and semiconductor layers 2, 31, 32, and 5, is insulating. Trench electrode 9, together with semiconductor layers 41, 42, and 5, is electrically connected to the emitter electrode E of the IGBT. Trench electrode 9 is not connected to either gate electrode G1 or G2 and can be considered a dummy electrode from the perspective that it does not function as a gate.

[0033] Each of the trench electrodes 81, 82, and 9 has an insulating film 6 and a conductor 7. The conductor 7 is made of, for example, polysilicon. The insulating film 6 is responsible for the insulating properties of the trench electrodes 81, 82, and 9 and is made of, for example, silicon oxide. Each of the trench electrodes 81, 82, and 9 can be seen as an electrode that is surrounded by the insulating film 6 inside the groove, but is capable of electrical connection to the outside.

[0034] The trench electrodes 81, 82, and 9 are periodically positioned along the thickness direction of the semiconductor substrate 1. For example, trench electrodes 81 and 82 are positioned alternately along one direction, with trench electrode 9 positioned between them (see Figure 2). For example, trench electrodes 81 and 82 are positioned alternately along two directions, with trench electrode 9 positioned in a grid pattern between them (see Figure 3).

[0035] The semiconductor layer 41 around the trench electrode 81 may be formed continuously as illustrated in Figure 3, or it may be formed intermittently. The semiconductor layer 42 around the trench electrode 82 may be formed continuously as illustrated in Figure 3, or it may be formed intermittently.

[0036] Figure 4 is a circuit diagram illustrating a circuit in which two types of gate voltages are applied to the IGBT100. The semiconductor device 100A can be used as an IGBT100 having gate electrodes G1 and G2, an emitter electrode E, and a collector electrode C.

[0037] The on / off state of the IGBT100 is controlled by two gate voltages. The gate electrode G1 is connected to the signal source 102 via a delay circuit 101 and a resistor. This resistor may be implemented within the signal source 102 or within the delay circuit 101.

[0038] The gate electrode G2 is connected to the signal source 102 via a resistor. This resistor may be implemented within the signal source 102.

[0039] Figure 5 is a waveform diagram illustrating the sequence of the two gate voltages described above. With the potential of the emitter electrode E as the reference, the voltage applied to the gate electrode G1 (hereinafter referred to as the "first gate voltage": corresponding to the first signal described above) transitions between the value Vg1 (>0) and the value (-Vg1), and the voltage applied to the gate electrode G2 (hereinafter referred to as the "second gate voltage": corresponding to the second signal described above) transitions between the value Vg2 (>0) and the value (-Vg2). Both the falling edge of the first gate voltage and the falling edge of the second gate voltage correspond to the off transition.

[0040] The delay circuit 101 has the function of delaying the falling edge of the first gate voltage relative to the falling edge of the second gate voltage by a time difference dt. For example, the second gate voltage can be input to the delay circuit 101 and the first gate voltage can be obtained from the delay circuit 101. Alternatively, the delay circuit 101 can be omitted and the first and second gate voltages can be obtained from the signal source 102.

[0041] Since the first gate voltage is applied to the gate electrode G1, it can be said that the first signal is supplied to the trench electrode 81. Since the second gate voltage is applied to the gate electrode G2, it can be said that the second signal is supplied to the trench electrode 82. As a control method for turning off the semiconductor device 100A, which is used as the IGBT100, both the first and second gate voltages are transitioned, with the transition of the first gate voltage delayed compared to the transition of the second gate voltage. The control of semiconductor devices 100B, 100C, and 100D, which will be described later, is the same.

[0042] Figure 6 is a waveform diagram illustrating the turn-off operation of the IGBT100. In Figure 6, the left vertical axis represents the collector current Ic [A], and the right vertical axis represents the collector voltage Vce [V] relative to the emitter potential. The horizontal axis represents time [s]. Waveform H20 shows the waveform of the collector current Ic, and waveform H21 shows the waveform of the collector voltage Vce.

[0043] The second gate voltage is switched off at time t2, and the first gate voltage is switched off at time t1. The difference between times t1 and t2 is the time difference dt mentioned above. At time t0, the collector current Ic stops flowing. The total amount of loss in the IGBT100 during the period from time t2 to time t0 is treated as the total loss Eoff below.

[0044] Figure 7 is a cross-sectional view illustrating the structure of semiconductor device 100Z as a comparative example to be compared with semiconductor device 100A. The structure of semiconductor device 100Z is broadly different from that of semiconductor device 100A in the order in which the trench electrodes 81, 82, and 9 are arranged. In semiconductor device 100A, trench electrode 9 is interposed between trench electrodes 81 and 82, but in semiconductor device 100Z, trench electrode 9 is not interposed between trench electrodes 81 and 82, and trench electrodes 81 and 82 are sandwiched between trench electrodes 9.

[0045] More specifically, if we consider semiconductor layers 31 and 32 as a single unit in both semiconductor device 100A and 100Z, we can say that the trench electrodes 82 and 89 penetrate the semiconductor layers 31 and 32. In both semiconductor device 100A and 100Z, we can say that the trench electrode 81 penetrates the semiconductor layer 41 and extends to reach the semiconductor layers 31 and 32.

[0046] In semiconductor device 100Z, similar to semiconductor device 100A, the trench electrode 82 faces the semiconductor substrate 1 and semiconductor layers 42, 2, and 32. In semiconductor device 100Z, the trench electrode 82 also faces semiconductor layer 31, and the surface facing semiconductor layer 31 is insulating.

[0047] In semiconductor device 100Z, similar to semiconductor device 100A, the trench electrode 81 faces the semiconductor layers 41 and 42. In semiconductor device 100Z, the trench electrode 81 also faces the semiconductor layer 32, and the surface facing the semiconductor layer 32 is insulating.

[0048] In semiconductor device 100Z, similar to semiconductor device 100A, the trench electrode 9 faces the semiconductor substrate 1 and semiconductor layers 31 and 32. However, in semiconductor device 100A, the trench electrode 9 faces the semiconductor layer 5, whereas in semiconductor device 100Z, the trench electrode 9 does not face the semiconductor layer 5.

[0049] In semiconductor device 100Z, semiconductor layers 41, 42, and 5 are aligned between trench electrodes 81 and 82 without the trench electrode 9 intervening.

[0050] Figure 8 is a graph showing the dependence of the total loss Eoff[%] on the time difference dt. The total loss Eoff is shown as a percentage, with the value when the time difference dt is zero being 100%. The white circles represent comparative examples, specifically the data when semiconductor device 100Z is used in IGBT100, and are connected by dashed lines. The black circles represent this embodiment, specifically the data when semiconductor device 100A is used in IGBT100, and are connected by solid lines.

[0051] In the comparative example, as the time difference dt increases, the total loss Eoff tends to decrease initially before increasing again. Specifically, the total loss Eoff shows a local minimum when the time difference dt is around 20 μs.

[0052] In this embodiment, as the time difference dt increases, the total loss Eoff tends to decrease almost monotonically, and when the time difference dt is longer than around 35 μs, the total loss Eoff tends to stabilize.

[0053] From the graph above, it can be seen that the acceptable range for the time difference dt that reduces loss, in other words, the acceptable range for the time difference dt in which the off-transition of the first gate voltage is delayed from the off-transition of the second gate voltage, is wider in this embodiment than in the comparative example.

[0054] Figure 9 is a waveform diagram illustrating the turn-off operation of IGBT100 in a comparative example. In Figure 9, the left vertical axis represents the collector current Ic [A], and the right vertical axis represents the collector voltage Vce [V] with respect to the emitter potential. The horizontal axis represents time [s]. The dashed waveform represents the waveform of the collector current Ic, and the solid waveform represents the waveform of the collector voltage Vce. For both the collector current Ic and the collector voltage Vce, the cases where the time difference dt takes values ​​of 0 μs, 18 μs, and 60 μs are shown. In all cases of time difference dt, the first gate voltage turns off at time 100 μs (labeled "1.0E-04" in the figure).

[0055] Figure 10 is a waveform diagram showing an enlarged view of region R10 in Figure 9. Figure 11 is a waveform diagram showing an enlarged view of region R11 in Figure 9.

[0056] The solid lines H31, H32, and H33 all represent the collector voltage Vce waveform in the comparative example. The dashed lines H41, H42, and H43 all represent the collector current Ic waveform in the comparative example.

[0057] Waveforms H31 and H41 both show the case where the time difference dt is 0 μs. Waveforms H32 and H42 both show the case where the time difference dt is 18 μs. Waveforms H33 and H43 both show the case where the time difference dt is 60 μs.

[0058] Figure 12 is a waveform diagram illustrating the turn-off operation of the IGBT 100 in this embodiment. In Figure 12, the left vertical axis represents the collector current Ic [A], and the right vertical axis represents the collector voltage Vce [V] with respect to the emitter potential. The horizontal axis represents time [s]. The dashed waveform represents the waveform of the collector current Ic, and the solid waveform represents the waveform of the collector voltage Vce. For both the collector current Ic and the collector voltage Vce, the cases where the time difference dt takes values ​​of 0 μs, 18 μs, and 60 μs are shown. In all cases of time difference dt, the first gate voltage transitions to off at time 100 μs (labeled "1.0E-04" in the figure).

[0059] Figure 13 is a waveform diagram showing an enlarged view of region R13 in Figure 12. Figure 14 is a waveform diagram showing an enlarged view of region R14 in Figure 12.

[0060] The solid lines H51, H52, and H53 all represent the collector voltage Vce waveform in the embodiment. The dashed lines H61, H62, and H63 all represent the collector current Ic waveform in the embodiment.

[0061] Waveforms H51 and H61 both show the case where the time difference dt is 0 μs. Waveforms H52 and H62 both show the case where the time difference dt is 18 μs. Waveforms H53 and H63 both show the case where the time difference dt is 60 μs.

[0062] From Figures 10 and 13, it can be seen that the increase in collector voltage Vce after the second gate voltage turns off is suppressed more effectively in this embodiment than in the comparative example. An increase in collector voltage Vce increases the losses when the IGBT100 conducts. The increase in the total loss Eoff in the comparative example, which is associated with an increase in the time difference dt shown in Figure 8, is thought to originate from the increase in collector voltage Vce.

[0063] From Figures 11 and 14, it can be seen that the rate of rise of the collector voltage Vce is suppressed in this embodiment compared to the comparative example. When the time difference dt is large, distortion occurs in the waveform of the collector voltage Vce in the comparative example.

[0064] In both semiconductor devices 100A and 100Z, semiconductor layers 2, 31, 32, and 5 can be considered as the emitter region of the IGBT. In both semiconductor devices 100A and 100Z, the current flowing inside during their operation passes through the emitter region.

[0065] The electrons accumulated in semiconductor layers 31 and 32 due to the potential of the trench electrode 82 decrease when the second gate voltage is turned off. This decrease leads to a decrease in the electrons injected from semiconductor layers 31 and 32 into the semiconductor substrate 1, and consequently to a decrease in carriers on the semiconductor layer 31 and 32 side of the semiconductor substrate 1. This decrease causes the depletion layer extending from the boundary between the semiconductor substrate 1 and semiconductor layers 31 and 32 to expand.

[0066] In semiconductor device 100Z, trench electrodes 81 and 82 are adjacent to each other, and the emitter region is shared between them. In semiconductor device 100Z, the Hall current flows only through the depletion layer. The resistance component of the depletion layer is high, and expansion of the depletion layer leads to an increase in the voltage required to turn on semiconductor device 100Z. The longer the time difference dt, the longer the depletion layer extends, and the greater the forward conduction loss.

[0067] The longer the time difference dt (the faster the off-transition of the second gate voltage occurs than the off-transition of the first gate voltage), the greater the collector voltage Vce increases (see waveforms H31, H32, and H33 in Figure 10). By the time the first gate voltage turns off, the depletion layer in the emitter region has already expanded, and the rate of increase in the collector voltage Vce is large (see waveforms H32 and H33 in Figure 11).

[0068] In semiconductor device 100A, the emitter region is not shared between trench electrodes 81 and 82. Specifically, the semiconductor layer 31 facing trench electrode 81 and the semiconductor layer 32 facing trench electrode 82 are separated by trench electrode 9.

[0069] Even if the depletion layer extending from semiconductor layer 32 in semiconductor substrate 1 expands due to the off-transition of the second gate voltage, there is almost no depletion layer at the boundary between semiconductor layer 31 and semiconductor substrate 1 where the trench electrode 81 faces until the off-transition of the first gate voltage occurs. The emitter region containing semiconductor layers 2, 31, and 5, where the depletion layer expands, has a smaller resistance component than the emitter region containing semiconductor layers 2, 32, and 5, where the depletion layer expands. In semiconductor device 100A, the Hall current flows through the latter region.

[0070] These two types of emitter regions are arranged in parallel in semiconductor device 100A, and the voltage required to turn on semiconductor device 100A is largely independent of the time difference dt (see waveforms H51, H52, H53 in Figure 13). At the point when the first gate voltage is switched off, there is still almost no depletion layer near the boundary between semiconductor layer 31 and semiconductor substrate 1, and the rate at which the collector voltage Vce rises is suppressed (see waveforms H51, H52, H53 in Figure 14).

[0071] Figure 15 is a graph illustrating the dependence of total loss Eoff on the saturation voltage Vce(sat) with respect to the collector voltage Vce. In Figure 15, the vertical axis represents the total loss Eoff [mJ], and the horizontal axis represents the saturation voltage Vce(sat) [V].

[0072] The white circles represent comparative examples, specifically data when semiconductor device 100Z is used in IGBT100, and are connected by dashed lines. The black circles represent this embodiment, specifically data when semiconductor device 100A is used in IGBT100, and are connected by solid lines. The comparative example data uses the total loss amount Eoff, which is the minimum value with respect to the time difference dt.

[0073] In both the comparative example and this embodiment, a trade-off relationship is observed between the saturation voltage Vce(sat) and the total loss Eoff. A tendency is observed where reducing the total loss Eoff increases the saturation voltage Vce(sat).

[0074] There exists a range of saturation voltage Vce(sat) (hereinafter tentatively referred to as the "low-speed side") in which the comparative example and this embodiment exhibit approximately equal trade-off relationships. There also exists a range of saturation voltage Vce(sat) (hereinafter tentatively referred to as the "high-speed side") in which this embodiment exhibits a smaller total loss Eoff than the comparative example. In the high-speed side, the saturation voltage Vce(sat) is higher than in the low-speed side.

[0075] In both the comparative example and this embodiment, that is, in both semiconductor devices 100A and 100Z, the carrier concentration in the semiconductor substrate 1 is lower on the high-speed side than on the low-speed side. In the comparative example, the larger the time difference dt, the more easily the depletion layer expands on the emitter side of the semiconductor substrate 1, resulting in a larger forward conduction loss between the off-transition of the second gate voltage and the off-transition of the first gate voltage, making it difficult to suppress the total loss Eoff. In this embodiment, the increase in forward conduction loss due to the expansion of the depletion layer is suppressed, and the total loss Eoff is suppressed more effectively than in the comparative example.

[0076] <Example of the range of peak values ​​for impurity concentration> The peak values ​​of impurity concentrations used in semiconductor substrate 1 and semiconductor layers 2, 31, 32, 41, 42, and 5 are exemplified below.

[0077] The peak value of the impurity concentration in semiconductor substrate 1 is, for example, 1 × 10⁻⁶. 12 cm -3with the lower limit of 1×10 14 cm -3 and the upper limit of. The peak value of the impurity concentration in the semiconductor substrate 1 satisfying the upper and lower limits is preferable from the viewpoint that the semiconductor device 100A has a large breakdown voltage as compared with the case where it does not satisfy.

[0078] The peak value of the impurity concentration in the semiconductor layer 2 is, for example, 1×10 16 cm -3 as the lower limit and 1×10 17 cm -3 as the upper limit. The peak value of the impurity concentration in the semiconductor layer 2 satisfying the upper limit is preferable from the viewpoint that the semiconductor device 100A has a large turn-off blocking ability as compared with the case where it does not satisfy. The peak value of the impurity concentration in the semiconductor layer 2 satisfying the lower limit is preferable from the viewpoint that the blocking ability at the time of short circuit is large as compared with the case where it does not satisfy.

[0079] The peak values of the impurity concentrations in the semiconductor layers 31 and 32 are, for example, both 1×10 16 cm -3 as the upper limit. The peak values of the impurity concentrations in the semiconductor layers 31 and 32 satisfying the upper limit are preferable from the viewpoint that the semiconductor device 100A has a large breakdown voltage as compared with the case where it does not satisfy.

[0080] The peak values of the impurity concentrations in the semiconductor layers 41, 42, and 5 are, for example, all 1×10 18 cm -3 as the lower limit. The peak values of the impurity concentrations in the semiconductor layers 41, 42, and 5 satisfying the lower limit are preferable from the viewpoint that the contact resistance in each of them is small as compared with the case where it does not satisfy.

[0081] <Another Example of the Second Gate Voltage> FIG. 16 is a waveform diagram showing another example of the sequence of two kinds of gate voltages. The first gate voltage transitions between the value Vg1 and the value (-Vg1) as in the example of FIG. 5. The second gate voltage transitions between the value 0 and the value (-Vg2), different from the example of FIG. 5. The second gate voltage transitions at a potential below zero.

[0082] In semiconductor device 100A, the conductivity types of semiconductor layers 31, 32 and semiconductor layers 41, 42 are all N-type, and the conductivity type of semiconductor layer 2 is P-type, thus forming two types of N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Specifically, the MOSFET formed by semiconductor layers 41, 2, and 31 (hereinafter tentatively referred to as the "first MOSFET") and the MOSFET formed by semiconductor layers 42, 2, and 32 (hereinafter tentatively referred to as the "second MOSFET") are connected in parallel in semiconductor device 100A.

[0083] The first MOSFET turns on when the first gate voltage exceeds a predetermined positive value. The second MOSFET turns on when the second gate voltage exceeds a predetermined positive value.

[0084] As illustrated in Figure 5, both the first and second gate voltages exceed a predetermined positive value upon rising, causing the semiconductor device 100A to turn on. If the turn-on of the second MOSFET lags behind that of the first MOSFET, the waveform of the current (collector current Ic) that flows when the semiconductor device 100A turns on becomes distorted.

[0085] Figures 17 and 18 are waveform diagrams illustrating the on-transition of two types of gate voltages. In both Figures 17 and 18, the vertical axis represents the gate voltage Vge [V] used for both the first and second gate voltages, and the horizontal axis represents time [s]. Waveform H71 represents the first gate voltage, and waveform H72 represents the second gate voltage. Both Figures 17 and 18 illustrate the case where the rise time of the second gate voltage is 0.15 μs later than the rise time of the first gate voltage.

[0086] Figure 17 illustrates the case where the second gate voltage also transitions from -15V to 15V, similar to the first gate voltage, and corresponds to the sequence of the two gate voltages illustrated in Figure 5, excluding the rise time delay. Figure 18 illustrates the case where the first gate voltage transitions from -15V to 15V and the second gate voltage transitions from 0V to 15V, and corresponds to the sequence of the two gate voltages illustrated in Figure 16, excluding the rise time delay.

[0087] Figure 19 is a waveform diagram illustrating the operation of semiconductor device 100A when it turns on after the transition exemplified in Figure 17. Figure 20 is a waveform diagram illustrating the operation of semiconductor device 100A when it turns on after the transition exemplified in Figure 18. In both Figure 19 and Figure 20, the left vertical axis represents the collector current Ic [A], and the right vertical axis represents the collector voltage Vce [V] with respect to the emitter potential. The horizontal axis represents time [s].

[0088] The collector current Ic waveform shown in Figure 19 is distorted, peaking near its maximum value. Such distortion does not appear in the collector current Ic waveform shown in Figure 20. When the second gate voltage exemplified in Figure 16 is used, the second gate voltage does not reach a predetermined positive value even after transitions, and the second MOSFET does not turn on. In this case, since there is no turn-on of the second MOSFET after the first MOSFET has turned on, the aforementioned distortion does not appear in the collector current Ic waveform.

[0089] When the conductivity type of semiconductor substrate 1 and semiconductor layers 31, 32, 41, and 42 is N-type, as described above, the distortion of the collector current Ic flowing through semiconductor device 100A is suppressed by the transition of the second gate voltage at a voltage of zero or less. When the conductivity type of semiconductor substrate 1 and semiconductor layers 31, 32, 41, and 42 is P-type, the distortion of the collector current Ic flowing through semiconductor device 100A is suppressed by the transition of the second gate voltage at a voltage of zero or more.

[0090] <Embodiment 2> As explained in the previously mentioned "Other Examples of Second Gate Voltage," the failure of the second MOSFET to turn on contributes to suppressing distortion in the collector current Ic. For example, the absence of a second MOSFET contributes to suppressing distortion in the collector current Ic.

[0091] Figure 21 is a cross-sectional view illustrating the configuration of semiconductor device 100B according to Embodiment 2. Compared to semiconductor device 100A, semiconductor device 100B does not have a semiconductor layer 42, and semiconductor layers 2, 5, and 32 are provided between the trench electrodes 82 and 9.

[0092] In semiconductor device 100A, the trench electrode 82 extends through semiconductor layers 2, 42, and 32 to reach the semiconductor substrate 1. In semiconductor device 100B, the trench electrode 82 extends through semiconductor layers 2, 5, and 32 to reach the semiconductor substrate 1. The surface of the trench electrode 82, specifically the surface facing semiconductor layers 5, 2, and 31, is insulating.

[0093] Semiconductor device 100B lacks the semiconductor layer 42 present in semiconductor device 100A, and therefore does not constitute a second MOSFET.

[0094] Figure 22 is a waveform diagram illustrating the operation of semiconductor device 100B when it turns on, following the transitions illustrated in Figure 17. In Figure 22, the left vertical axis represents the collector current Ic [A], and the right vertical axis represents the collector voltage Vce [V] with respect to the emitter potential. The horizontal axis represents time [s].

[0095] Even when the second gate voltage applied to the semiconductor device 100B transitions between positive and negative values, as illustrated in Figure 17, and rises later than the rise of the first gate voltage, no distortion in the collector current Ic appears, just as in the case where it transitions at zero or less, as illustrated in Figure 18.

[0096] In semiconductor device 100B, as in semiconductor device 100A, the trench electrode 9 separates semiconductor layer 31 from semiconductor layer 32, thus expanding the allowable range of the time difference dt, which is the delay between the off-transition of the first gate voltage and the off-transition of the second gate voltage.

[0097] <Embodiment 3> When the impurity concentration of semiconductor layer 31 is equal to the impurity concentration of semiconductor substrate 1, semiconductor layer 31 can be considered as part of semiconductor substrate 1, and a portion of semiconductor layer 2 on semiconductor substrate 1 can also be considered as semiconductor layer 31.

[0098] Figure 23 is a cross-sectional view illustrating the configuration of semiconductor device 100C according to Embodiment 3. The region of the semiconductor substrate 1 in semiconductor device 100C that corresponds to the region where the semiconductor layer 31 existed in semiconductor device 100A is virtually separated and exemplified as the semiconductor layer 31. In semiconductor device 100C, it can be said that the impurity concentration of the semiconductor layer 31 is equal to the impurity concentration of the semiconductor substrate 1.

[0099] Both the cross-section shown in Figure 2 and the cross-section shown in Figure 3 appear when viewed from the direction of the arrow at position LL in Figure 23. Figure 2 can be said to be a cross-sectional view showing one example of the configuration of semiconductor device 100C, and Figure 3 is a cross-sectional view showing another example of the configuration of semiconductor device 100C.

[0100] The semiconductor device 100C can be seen as having a lower peak value of impurity concentration in the semiconductor layer 31 compared to the semiconductor device 100A. The decrease in the peak value of impurity concentration in the semiconductor layer 31 increases the saturation voltage Vce(sat) and contributes to the reduction of the total loss Eoff (see Figure 15). As can be understood from the explanation using the comparative example in Embodiment 1, the total loss Eoff is greatly influenced by the operation of the first MOSFET including the semiconductor layer 31, and the influence of the operation of the second MOSFET is small. Therefore, the trade-off relationship between the saturation voltage Vce(sat) and the total loss Eoff is improved in the semiconductor device 100C compared to the semiconductor device 100A.

[0101] <Embodiment 4> As described in Embodiment 3, the reduction in the peak value of the impurity concentration of the semiconductor layer 31 contributes to improving the trade-off relationship between the saturation voltage Vce(sat) and the total loss Eoff. For example, the peak value of the impurity concentration of the semiconductor layer 31 is higher than the peak value of the impurity concentration of the semiconductor substrate 1 in the semiconductor device 100A, and lower than the peak value of the impurity concentration of the semiconductor layer 32.

[0102] Figure 24 is a cross-sectional view illustrating the configuration of the semiconductor device 100D according to Embodiment 4. Both the cross-section shown in Figure 2 and the cross-section shown in Figure 3 appear when viewed from the direction of the arrow at position MM in Figure 24. Figure 2 can be described as a cross-sectional view showing one example of the configuration of the semiconductor device 100D, and Figure 3 as a cross-sectional view showing another example of the configuration of the semiconductor device 100D.

[0103] In semiconductor device 100A, the peak impurity concentration of semiconductor layer 31 is approximately the same as, for example, the peak impurity concentration of semiconductor layer 32. In semiconductor device 100D, the peak impurity concentration of semiconductor layer 31 is lower than the peak impurity concentration of semiconductor layer 32. Compared to semiconductor device 100A, semiconductor device 100D shows an improved trade-off relationship between saturation voltage Vce(sat) and total loss Eoff.

[0104] <Relationship between the depth of trench electrodes 81, 82, and 9 and the bottom of semiconductor layers 31 and 32> Figure 24 shows the depths d1, d2, d9, d31, and d32 defined in semiconductor device 100D. Similarly, the depths d1, d2, d9, d31, and d32 are shown in semiconductor devices 100A (see Figure 1) and 100B (see Figure 21). Similarly, the depths d1, d2, d9, and d32 are shown in semiconductor device 100C (see Figure 23) (in semiconductor device 100C, the depth d31 is not shown because the semiconductor layer 31 is part of the semiconductor substrate 1).

[0105] The reference positions for depths d1, d2, d9, d31, and d32 (hereinafter referred to as "reference positions") are the surfaces of semiconductor layers 41, 42, and 5 that are furthest from semiconductor layer 11 (hereinafter referred to as "semiconductor surface"). For example, the semiconductor surface of semiconductor layers 41, 42, and 5 are substantially located on the same plane. For example, the position of the semiconductor surface of semiconductor layer 5 is used as the reference position.

[0106] As will be described later, the semiconductor layers 41, 42, and 5 are formed on one main surface of the semiconductor substrate 1, and the semiconductor substrate 1 remains on the side of the semiconductor layers 11 beyond the semiconductor layers 41, 42, and 5. As described above, the trench electrodes 81, 82, and 9 penetrate any of the semiconductor layers 41, 42, and 5, so their openings can be said to be located on the surface of the semiconductor device at the end opposite to the respective semiconductor layer 11 (the end opposite to the "bottom" which will be described later).

[0107] Depth d1 is the depth of the bottom of trench electrode 81 (the part closest to the semiconductor layer 11; the same applies hereafter), depth d2 is the depth of the bottom of trench electrode 82, and depth d9 is the depth of the bottom of trench electrode 9. For example, if depths d2 and d9 are the same, trenches used for trench electrodes 82 and 9 can be formed in parallel during the manufacturing process (described later), which contributes to simplifying the formation process.

[0108] In the direction in which the trench electrode 82 extends (the thickness direction of the semiconductor substrate 1), the trench electrode 82 can be seen as protruding from the semiconductor layer 32 into the semiconductor substrate 1. In the direction in which the trench electrode 9 extends (the thickness direction of the semiconductor substrate 1), the trench electrode 9 can be seen as protruding from the semiconductor layer 32 into the semiconductor substrate 1.

[0109] For example, the length of trench electrode 82 protruding from semiconductor layer 32 in its direction of extension is equal to the length of trench electrode 9 protruding from semiconductor layer 32 in its direction of extension. When the protruding lengths are equal in this way, and the semiconductor device surfaces of semiconductor layers 41, 42, and 5 are substantially on the same plane, the depths d2 and d9 coincide.

[0110] The depth d31 is the depth of the bottom of the semiconductor layer 31, and the depth d32 is the depth of the bottom of the semiconductor layer 32. In the semiconductor devices 100A and 100B, as illustrated in FIGS. 1 and 21 respectively, for example, the depths d31 and d32 are equal.

[0111] As described above, the semiconductor layers 31 and 32 function as carrier accumulation layers. It can be said that the depths d31 and d32 indicate the positions of the boundaries on the collector layer side of the carrier accumulation layers.

[0112] The trench electrode 81 reaches and extends to the semiconductor layer 31 far from the semiconductor layer 11 beyond the boundary between the semiconductor layer 32 and the semiconductor substrate 1. From the viewpoint that the semiconductor layer 31 functions as a carrier accumulation layer in the first MOSFET, for example, the trench electrode 81 does not penetrate the semiconductor layer 31. This positional relationship is expressed as d1 < d32 using the depths d1 and d32. Further, in the semiconductor devices 100A, 100B, and 100D, there is a positional relationship expressed as d1 < d31 using the depth d31.

[0113] In the semiconductor device 100D, for example, further, there is a relationship of d31 < d32, and the semiconductor layer 31 is thinner than the semiconductor layer 32. Such a relationship contributes to the simplification of the process for obtaining the semiconductor layers 31 and 32, specifically, the process of diffusing impurities in the manufacturing process (described later).

[0114] The trench electrodes 9 and 82 extending to the semiconductor substrate 1 on the semiconductor layer 11 side rather than the semiconductor layers 31 and 32 (d31 < d2, d32 < d2, d31 < d9, d32 < d9) relieve the concentration of the electric field in the semiconductor layers 31 and 32 when the semiconductor devices 100A, 100B, and 100D operate, and contribute to the improvement of the breakdown voltage.

[0115] The trench electrodes 9 and 82 extending to the semiconductor substrate 1 on the semiconductor layer 11 side rather than the semiconductor layer 32 (d32 < d2, d32 < d9) relieve the concentration of the electric field in the semiconductor layer 32 when the semiconductor device 100C operates, and contribute to the improvement of the breakdown voltage.

[0116] <Spacing between trench electrodes 81, 82, and 9> Figure 25 is a graph illustrating the relationship between the withstand voltage of semiconductor devices 100A, 100B, 100C, and 100D and the spacing between trench electrodes 81, 82, and 9. In Figure 25, the vertical axis represents the withstand voltage BV [V] at 25°C, and the horizontal axis represents the trench spacing [μm]. The trench spacing here refers to the distance between adjacent trench electrodes 82 and 9 along the direction in which they are aligned. Trench electrode 9 is located on both the one side and the other side of trench electrode 81 in the direction in which trench electrode 9 and trench electrode 81 are aligned (see Figures 1, 21, 23, and 24). The distance between adjacent trench electrodes 9 connected via trench electrode 81 also corresponds to the trench spacing.

[0117] Figure 25 shows that the breakdown voltage decreases as the trench spacing increases. For example, when the peak impurity concentration of semiconductor layers 31 and 32 is the same as that of semiconductor substrate 1, and the trench spacing is 15 μm, the breakdown voltage is approximately 90% of the target breakdown voltage.

[0118] A narrow trench spacing enhances the field-plate effect between trench electrodes 9 and 82, mitigating the concentration of the electric field near the bottom surface of trench electrode 82, and ultimately contributing to improved dielectric strength.

[0119] The fact that the peak impurity concentration of semiconductor layers 31 and 32 is higher than the peak impurity concentration of semiconductor substrate 1 makes the dependence of the withstand voltage on the trench spacing more pronounced. The semiconductor devices 100A, 100B, 100C, and 100D described above all have an N-type semiconductor substrate 1 and an N-type semiconductor layer 32. In this case, narrowing the trench spacing to less than 15 μm contributes to raising the withstand voltage of semiconductor devices 100A, 100B, 100C, and 100D to 90% or more of the target withstand voltage.

[0120] <First manufacturing method of semiconductor device 100A> Figures 26 to 37 are cross-sectional views illustrating, in order, a part of the first manufacturing method of the semiconductor device 100A according to Embodiment 1, particularly the manufacturing process of the trench electrodes 81, 82, and 9.

[0121] Figure 26 illustrates the process of introducing N-type impurities into a structure in which semiconductor layers 25 and 3 have already been formed using semiconductor substrate 1. Semiconductor layer 3 later becomes semiconductor layers 31 and 32. Semiconductor layers 2 and 5 are shown together as semiconductor layer 25.

[0122] The configuration of the semiconductor substrate 1 on the side opposite to the semiconductor layers 25 and 3 is omitted. For example, semiconductor layers 10 and 11 are already provided on the semiconductor substrate 1 on the side opposite to the semiconductor layers 25 and 3. In the description of the manufacturing method described here, and in the manufacturing method described later, the illustration of semiconductor layers 10 and 11 is omitted.

[0123] Before the introduction of the N-type impurity, the semiconductor substrate 1, semiconductor layers 3 and 25, insulating film 400, and mask 501 are stacked in this order, in Figure 26, in a direction from bottom to top of the paper.

[0124] The insulating film 400 is realized, for example, by an oxide film obtained by oxidation of the semiconductor substrate 1 before the semiconductor layers 25 and 3 are provided. When silicon is used as the material for the semiconductor substrate 1, the insulating film 400 is, for example, a silicon oxide film.

[0125] The mask 501 has openings 501a and 501b. The openings 501a and 501b are made in the mask 501 corresponding to the positions where semiconductor layers 41 and 42 (see Figure 1) are formed, respectively. For example, a patterned photoresist film is used for the mask 501. The openings 501a and 501b are made, for example, by photoengraving technology on the photoresist film.

[0126] For example, arsenic (As) is introduced as the N-type impurity. Figure 26 illustrates the case in which ion implantation using arsenic ions (As+; however, the symbol "+" here indicates that it is a positive ion, not the magnitude of the impurity concentration) is employed in the introduction of N-type impurities. The symbol "×" in semiconductor layer 25 schematically indicates the location where N-type impurities have been introduced.

[0127] After the introduction of N-type impurities, the mask 501 is removed by known techniques, exposing the insulating film 400. After the insulating film 400 is exposed, the introduced N-type impurities are diffused by heating at least the vicinity of the semiconductor layer 25, or for example, the entire structure (so-called "drive-in"). Through this diffusion, semiconductor layers 41 and 42 are formed, as illustrated in Figure 27. When the insulating film 400 is a silicon oxide film, for example, the thickness of the insulating film 400 increases through this drive-in process, becoming insulating film 401.

[0128] A mask 502 is provided on the insulating film 401 on the side opposite to the semiconductor substrate 1 (Figure 28). The mask 502 has an opening 502a. The opening 502a is made in the mask 502 corresponding to the position where the trench electrode 81 (see Figure 1) is formed. For example, a patterned photoresist film is used for the mask 502. The opening 502a is made, for example, by photolithography technology for the photoresist film. Etching of the insulating film 401 through the mask 502 creates a hole in the insulating film 401 corresponding to the opening 502a, partially exposing the semiconductor layer 41.

[0129] Selective etching of semiconductor layers 41, 25, and 3 is performed using the mask 502 and the insulating film 401 with openings as described above as masks, and trenches 801 are formed that penetrate the semiconductor layers 41 and 25 and reach the semiconductor layer 3 (Figure 29). The location of the trenches 801 corresponds to the location where the trench electrodes 81 are provided.

[0130] The insulating film 401 is removed by a known technique, such as etching. An insulating film 601 is formed on the semiconductor layers 41, 25, 3 exposed on the inner wall of the trench 801, and on the semiconductor layers 41, 42, 25 exposed by the removal (Figure 30). The insulating film 601 in the trench 801 later becomes the insulating film 6 that provides insulation on the surface of the trench electrode 81. Thermal oxidation, for example, is used to form the insulating film 601.

[0131] A conductor 701 is provided on the insulating film 601 on the side opposite to the semiconductor substrate 1, including within the trench 801 (Figure 31). The trench 801 is filled with the insulating film 601 and the conductor 701. For the conductor 701, for example, polysilicon doped with a high impurity concentration is used.

[0132] The conductor 701 is etched from the side opposite to the semiconductor substrate 1 and remains only in the trench 801 (so-called "etch-back"), becoming exposed as the conductor 7 (Figure 32). Subsequently, for example, by oxidation treatment, the surface of the conductor 7 exposed in the trench 801 is oxidized to obtain the trench electrode 81. This oxidation treatment increases the thickness of the insulating film 601 to obtain the insulating film 602. In view of the above manufacturing process, it can be said that the trench electrode 81 is embedded in the trench 801.

[0133] A mask 503 is provided on the insulating film 602 on the side opposite to the semiconductor substrate 1 (Figure 33). The mask 503 has openings 503a and 503b. The openings 503a and 503b are made in the mask 503 corresponding to the positions where trench electrodes 9 and 82 (see Figure 1) are formed, respectively. For example, a patterned photoresist film is used for the mask 503. The openings 503a and 503b are made, for example, by photolithography technology for the photoresist film. Etching of the insulating film 602 through the mask 503 creates holes in the insulating film 602 corresponding to the openings 503a and 503b, partially exposing the semiconductor layer 42.

[0134] Using the mask 503 and the insulating film 602 with the openings described above as masks, selective etching is performed on the semiconductor layers 25,3 and the semiconductor substrate 1, forming trenches 90 and 802 (Figure 34).

[0135] The location of trench 90 corresponds to the location where trench electrode 9 is provided. Trench 90 penetrates semiconductor layers 25 and 3 and reaches semiconductor substrate 1. The location of trench 802 corresponds to the location where trench electrode 81 is provided. Trench 802 penetrates semiconductor layers 42, 25, and 3 and reaches semiconductor substrate 1. With the formation of trenches 90 and 802, semiconductor layer 3 is divided into semiconductor layers 31 and 32.

[0136] An insulating film 6 is formed on the exposed semiconductor layers 31, 32, 42, 25 and the semiconductor substrate 1 on the inner walls of trenches 90 and 802 (Figure 35). The insulating film 6 in trench 802 later provides insulation on the surface of trench electrode 82. The insulating film 6 in trench 90 later provides insulation on the surface of trench electrode 9. Thermal oxidation, for example, is used to form the insulating film 6.

[0137] A conductor 702 is provided on the side opposite to the semiconductor substrate 1 in the insulating film 6 and insulating film 602 within the trenches 90 and 802 (Figure 36). Both trenches 90 and 802 are filled with insulating film 6 and conductor 702. For the conductor 702, for example, polysilicon doped with a high impurity concentration is used.

[0138] The conductor 702 remains only within the trenches 90 and 802 due to etch-back from the opposite side of the semiconductor substrate 1, and is exposed as conductor 7 (Figure 37). Subsequently, for example, by oxidation treatment, the surface of the conductor 702 exposed in trenches 90 and 802 is oxidized, and the corresponding trench electrodes 9 and 82 are obtained. In view of the above manufacturing process, it can be said that trench electrode 82 is embedded in trench 802 and trench electrode 9 is embedded in trench 90.

[0139] Trenches 90 and 802 are formed by parallel processes (see Figure 34). The fact that the bottom position of trench electrode 82 (e.g., depth d2) and the bottom position of trench electrode 9 (e.g., depth d9) coincide contributes to the adoption of this process. The adoption of such parallel processes contributes to the simplification of the formation of trench electrodes 82 and 9, and consequently to the simplification of the manufacturing process of semiconductor device 100A. This simplification of the manufacturing process contributes to a reduction in the manufacturing cost of semiconductor device 100A.

[0140] The formation of the trenches 802 and 90 described above can be explained as follows: Prior to the formation of either trench electrode 82 or 9, trench 802 for embedding trench electrode 82 and trench 90 for embedding trench electrode 9 are formed in parallel by selective etching using a mask 503 provided with openings 503a and 503b.

[0141] The formation of trenches 90 and 802 may precede the formation of trench 801. The formation of trench 801 may precede the formation of semiconductor layer 41. The formation of trenches 90 and 802 may precede the formation of semiconductor layer 42.

[0142] <Second manufacturing method for semiconductor device 100A> Figures 38 to 41 are cross-sectional views illustrating, in order, a part of the second manufacturing method of the semiconductor device 100A, particularly the manufacturing process of the trench electrodes 81, 82, and 9.

[0143] After obtaining the structure illustrated in Figure 27 in the same manner as the first manufacturing method, a mask 502 is provided on the insulating film 401 on the side opposite to the semiconductor substrate 1 (Figure 38). The mask 502 has openings 502a, 502b, and 502c. The openings 502a, 502b, and 502c are made in the mask 502 corresponding to the positions where trench electrodes 81, 9, and 82 (see Figure 1) are formed, respectively. Etching of the insulating film 401 through the mask 502 creates holes in the insulating film 401 corresponding to the openings 502a, 502b, and 502c, partially exposing the semiconductor layers 41 and 42.

[0144] Using the mask 502 and the insulating film 401 with the openings described above as masks, selective etching is performed on the semiconductor layers 25, 3, 41, 42 and the semiconductor substrate 1, forming trenches 801, 90, and 802 (Figure 39).

[0145] The location of trench 801 corresponds to the location where trench electrode 81 is provided. Trench 801 penetrates semiconductor layers 41 and 25 and reaches semiconductor layer 3. The location of trench 802 corresponds to the location where trench electrode 82 is provided. Trench 802 penetrates semiconductor layers 42, 25 and 3 and reaches semiconductor substrate 1. The location of trench 90 corresponds to the location where trench electrode 9 is provided. Trench 90 penetrates semiconductor layers 25 and 3 and reaches semiconductor substrate 1.

[0146] The formation of trenches 90 and 802 divides semiconductor layer 3 into semiconductor layers 31 and 32.

[0147] Trenches 90 and 802 are used to form trench electrodes 9 and 82, respectively. The insulating film 6 used for surface insulation in trench electrodes 9, 81, and 82 functions as a so-called gate insulating film, so their thicknesses are approximately equal in trenches 90, 801, and 802. Since trench electrodes 9 and 82 are formed deeper than trench electrode 81, trenches 90 and 802 are also formed deeper than trench 801.

[0148] Forming deep trenches 90,802 and shallow trench 801 in parallel in this manner is facilitated by the fact that trenches 90,802 have wider openings than trench 801. For example, the wider the opening in the mask used in selective etching, the wider the resulting trench openings and the faster the etching rate.

[0149] Figure 42 is a graph illustrating the relationship between trench depth and mask aperture width when trenches are formed by selective etching using a mask with an aperture. The horizontal axis represents the minimum width of the aperture provided in the mask, expressed as aperture width [nm]. For example, when the aperture is rectangular, the length of the shorter side of the rectangle is used as the aperture width. The vertical axis represents the trench depth [μm].

[0150] As can be seen from Figure 42, the larger the opening width of the mask, the deeper the trench formed. Since trench electrodes 81, 82, and 9 are embedded in trenches 801, 802, and 90 respectively, the depths of trenches 801, 802, and 90 can effectively be treated as depths d1, d2, and d9, respectively.

[0151] The fact that openings 502b and 502c are wider than opening 502a contributes to the parallel formation of deep trenches 90 and 802 and shallow trench 801, and consequently contributes to the simplification of the process of forming trench electrodes 81, 82, and 9.

[0152] For example, the widths w2 and w3 of trench electrodes 82 and 89, which extend deeper than trench electrode 81, are both larger than the width w1 of trench electrode 81 (see Figure 1). The widths w1, w2, and w3 represent the dimensions of trench electrodes 81, 82, and 9 in directions perpendicular to the direction in which they extend (the vertical direction in Figure 1) (the horizontal direction in Figure 1).

[0153] Generally, the larger the opening width of the mask, the wider the width of the formed trench. Since trench electrodes 81, 82, and 9 are embedded in trenches 801, 802, and 90 respectively, the widths of trenches 801, 802, and 90 can be substantially treated as widths w1, w3, and w3 respectively. The formation of trench electrodes 81, 82, and 9 having the above-described relationship regarding the width (w1 < w2, w1 < w3) contributes to forming deep trench 90, 802 and shallow trench s801 in parallel, and thus contributes to the above-described simplification and, consequently, to suppressing the manufacturing cost. The same also holds for semiconductor devices 100B, 100C, 100D and their manufacturing methods (see FIGS. 21, 23, and 24).

[0154] The formation of trenches 801, 802, and 90 described above can be explained as follows: Prior to forming any of trench electrodes 81, 82, and 9, trenches 801 for embedding trench electrode 81, trenches 802 for embedding trench electrode 82, and trench 90 for embedding trench electrode 9 are formed in parallel by selective etching using mask 502 provided with openings 502a, 502b, and 502c. Opening 502b used for etching to form trench 802 and opening 502c used for etching to form trench 90 are wider than opening 502a used for etching to form trench 801.

[0155] An insulating film 6 is formed on semiconductor layers 41, 25, 31 exposed on the inner wall of trench 801 and on semiconductor substrate 1 and semiconductor layers 42, 25, 31, 32 exposed on the inner walls of trenches 802 and 90 (FIG. 40). For forming such insulating film 6, for example, thermal oxidation is used.

[0156] A conductor 703 is provided on the opposite side of semiconductor substrate 1 to insulating film 6 in trenches 90, 801, and 802 and to insulating film 401 (FIG. 41). All of trenches 90, 801, and 802 are filled with insulating film 6 and conductor 703. For conductor 703, for example, polysilicon doped with a high impurity concentration is employed.

[0157] The conductor 703 remains as a conductor 7 only within trenches 90, 801, and 802 due to etch-back from the opposite side of the semiconductor substrate 1. Subsequently, for example, by oxidation treatment, the surface of the exposed conductor 703 in each of the trenches 90, 801, and 802 is oxidized to obtain trench electrodes 9, 81, and 82. This results in a structure in which the insulating film 602 in Figure 37 is replaced with insulating film 401. In light of this manufacturing process, it can be said that trench electrodes 81, 82, and 9 are embedded in trenches 801, 802, and 90, respectively.

[0158] In the second manufacturing method, the formation of trenches 90, 801, and 802 may precede the formation of semiconductor layers 41 and 42.

[0159] <Manufacturing method for semiconductor device 100B> The semiconductor device 100B according to Embodiment 2 differs from the semiconductor device 100A in that it does not have a semiconductor layer 42. The manufacturing method of the semiconductor device 100B differs from the first manufacturing method of the semiconductor device 100A in that the mask 501 does not have an opening 501b. Because the opening 501b is not present, when an N-type impurity is introduced and drive-in is performed, the semiconductor layer 41 is formed, but the semiconductor layer 42 is not formed.

[0160] <First method for manufacturing semiconductor device 100D> Figures 43 to 47 are cross-sectional views illustrating, in order of process, a part of the first manufacturing method of semiconductor device 100D according to Embodiment 4, particularly the manufacturing process of semiconductor layers 31 and 32. As will be described later, the explanation of this manufacturing method can also be applied to the explanation of the manufacturing methods of semiconductor device 100A according to Embodiment 1, semiconductor device 100B according to Embodiment 2, and semiconductor device 100C according to Embodiment 3.

[0161] Figures 43 to 47 illustrate the case where semiconductor layer 31 is formed to the left of the break line and semiconductor layer 32 is formed to the right of the break line.

[0162] An insulating film 410 is provided on the main surface of the semiconductor substrate 1 (Figure 43). For example, when silicon is used for the semiconductor substrate 1, the insulating film 410 is realized as a silicon oxide film obtained by oxidizing the main surface of the semiconductor substrate 1.

[0163] The mask 511 selectively covers the insulating film 410 (Figure 44). The mask 511 avoids the region where the semiconductor layer 32 will later be formed, and covers the insulating film 410 in the region where the semiconductor layer 31 will later be formed. Alternatively, the insulating film 410 can be covered by the mask 511, which opens in the region where the semiconductor layer 32 will later be formed.

[0164] For example, a patterned photoresist film is used for the mask 511. N-type impurities are introduced into the semiconductor substrate 1 through the insulating film 410 and the mask 511 with the opening described above. For example, phosphorus (P) is introduced as the N-type impurity.

[0165] Figure 44 illustrates an example of ion implantation using phosphate ions (P+; however, the "+" symbol here indicates that it is a positive ion, not the magnitude of the impurity concentration) when introducing N-type impurities.

[0166] The symbol "×" in semiconductor substrate 1 schematically indicates the location where N-type impurities have been introduced. Figure 44 shows region 302 where N-type impurities have been introduced.

[0167] After mask 511 is removed by known techniques, mask 512 selectively covers the insulating film 410 (Figure 45). Mask 512 covers the insulating film 410 in the region where semiconductor layer 32 will be formed, while avoiding the region where semiconductor layer 31 will be formed later. Alternatively, the insulating film 410 can be covered by mask 512, which opens in the region where semiconductor layer 31 will be formed later.

[0168] For example, a patterned photoresist film may be used for the mask 512. N-type impurities are introduced into the semiconductor substrate 1 through the insulating film 410 and the mask 512 with the opening described above. For example, phosphorus (P) is introduced as the N-type impurity.

[0169] Figure 45 illustrates the case where ion implantation using phosphorus ions is employed in the introduction of N-type impurities. In Figure 45, region 301 is shown where N-type impurities have been introduced.

[0170] In semiconductor device 100D, the peak value of the impurity concentration in semiconductor layer 31, for example, its peak concentration, is lower than the peak value of the impurity concentration in semiconductor layer 32, for example, its peak concentration. As one method to obtain semiconductor layers 31 and 32 with such different peak values ​​of impurity concentrations, N-type impurities are introduced into regions 302 and 301, respectively, using masks 511 and 512 as described above.

[0171] In Figure 45, the fact that the amount of introduced peak values ​​of N-type impurity concentrations in region 302 is greater than that in region 301 is schematically shown by the denser arrangement of the symbols "×" in region 302 compared to region 301.

[0172] After the mask 512 is removed, P-type impurities are introduced into the semiconductor substrate 1 via the insulating film 410 (Figure 46). More specifically, P-type impurities are introduced through a mask (not shown) that opens up the region where the semiconductor layer 2 will later be formed.

[0173] For example, boron (B) is introduced as the P-type impurity. Figure 46 illustrates an example in which ion implantation using boron ions (B+; however, the symbol "+" here indicates that it is a positive ion, not the magnitude of the impurity concentration) is employed in the introduction of P-type impurities.

[0174] The symbol "●" in the semiconductor substrate 1 schematically indicates the location where P-type impurities are introduced. In FIG. 46, for both regions 301 and 302, a region 200 where P-type impurities are introduced is shown on the insulating film 410 side.

[0175] After the P-type impurities are introduced into the semiconductor substrate 1, the semiconductor layers 2, 31, and 32 are obtained by drive-in. The P-type impurities are introduced into the region 200 regardless of the positions of the regions 301 and 302. The semiconductor layer 2 is caused by the P-type impurities introduced into the region 200. The semiconductor layer 2 is formed at a depth d2 on the insulating film 410 side with respect to both the semiconductor layers 31 and 32 (FIG. 47).

[0176] The concentration of the N-type impurities introduced into the region 301 is lower than the concentration of the N-type impurities introduced into the region 302. The N-type impurities introduced into the region 301 and the N-type impurities introduced into the region 302 undergo drive-in in parallel to form the semiconductor layers 31 and 32, respectively. Reflecting the above-mentioned high and low peak values of the impurity concentrations, the depth d31 of the semiconductor layer 31 is shallower than the depth d32 of the semiconductor layer 32 (d31 < d32: see also FIG. 24).

[0177] The process of forming the semiconductor layers 31 and 32 can be roughly classified into an introduction process and a diffusion process and described as follows: Prior to the formation of the semiconductor layers 31 and 32, N-type impurities are introduced into the semiconductor substrate 1 into the region 301 at a first introduction amount and into the region 302 at a second introduction amount, respectively. However, the second introduction amount is larger than the first introduction amount (introduction process); The diffusion of the N-type impurities introduced into the region 301 and the diffusion of the N-type impurities introduced into the region 302 are performed in parallel to form the semiconductor layers 31 and 32 (diffusion process).

[0178] After that, the semiconductor layer 5 is formed by a known method, and the semiconductor layers 41, 42, and the trench electrodes 81,

[0179] P-type impurities may be introduced prior to the introduction of N-type impurities.

[0180] When manufacturing semiconductor devices 100A and 100B, semiconductor layer 2, which is shown together with semiconductor layer 5 as semiconductor layer 25, and semiconductor layer 3 are formed by processes exemplified in Figures 43 to 47. For example, if the peak values ​​of impurity concentrations in semiconductor layers 31 and 32 are aligned in semiconductor device 100A, it is not necessary to introduce N-type impurities in two stages (see Figures 44 and 45) using masks 511 and 512. For example, similar to the introduction of P-type impurities (see Figure 46), N-type impurities are introduced in parallel into regions 301 and 302 using a mask that opens in the region where semiconductor layer 3 is to be formed.

[0181] In semiconductor device 100C, the semiconductor layer 31 is considered to be part of the semiconductor substrate 1. When manufacturing semiconductor device 100C, N-type impurities in region 301 are unnecessary. In this case, the introduction of N-type impurities using the mask 512 is unnecessary. Manufacturing semiconductor device 100C is simplified compared to manufacturing semiconductor devices 100A, 100B, and 100D.

[0182] <Second manufacturing method for semiconductor device 100D> Figure 48 is a cross-sectional view illustrating a part of the second manufacturing method of the semiconductor device 100D, particularly a part of the manufacturing process of the semiconductor layers 31 and 32.

[0183] In the second manufacturing method of the semiconductor device 100D, the insulating film 410 is provided on the semiconductor substrate 1 in the same manner as in the first manufacturing method of the semiconductor device 100D (see Figure 43).

[0184] The mask 510 selectively covers the insulating film 410. Similar to the mask 511 (see Figure 44), the mask 510 avoids the region where the semiconductor layer 32 will later be formed, and covers the insulating film 410 in the region where the semiconductor layer 31 will later be formed. It can also be said that the insulating film 410 is covered by the mask 510, which has openings in the region where the semiconductor layer 32 will later be formed.

[0185] However, mask 510 has a lower ability to inhibit the introduction of N-type impurities compared to mask 511. For example, mask 510 has a stripe pattern or dot pattern in the region where the semiconductor layer 31 is later formed.

[0186] For example, a patterned photoresist film is used for the mask 510. N-type impurities are introduced into the semiconductor substrate 1 through the insulating film 410 and the mask 510 with openings as described above. For example, phosphorus (P) is introduced as the N-type impurity.

[0187] N-type impurities are introduced into region 301 in a smaller amount than in region 302 via the stripe or dot pattern of mask 510. N-type impurities are introduced into region 302, which is not covered by mask 510, in a larger amount than in region 301. In Figure 48, as in Figure 45, the density of the symbol "×" schematically indicates the amount of N-type impurities introduced.

[0188] Using mask 510, N-type impurities are introduced into regions 301 and 302 in parallel, with different amounts introduced in each region. The effective injection amount of N-type impurities into region 301 is lower than the effective injection amount of N-type impurities into region 302.

[0189] After introducing N-type impurities into regions 301 and 302, P-type impurities are introduced as illustrated in Figure 46. After the introduction of P-type impurities, a drive-in is performed to obtain the structure illustrated in Figure 47. Subsequent processing is carried out in the same manner as the first manufacturing method of semiconductor device 100D.

[0190] In accordance with the previously described "introduction process," in this introduction process, the introduction of N-type impurities into region 301 and into region 302 is performed in parallel by ion implantation using a mask 510 having a stripe pattern or a dot pattern.

[0191] The second method for manufacturing the semiconductor device 100D involves fewer steps for introducing N-type impurities than the first method for manufacturing the semiconductor device 100D, thereby contributing to the simplification of the manufacturing process for the semiconductor device 100D. This simplification of the manufacturing process contributes to a reduction in the manufacturing cost of the semiconductor device 100D.

[0192] <Embodiment 5> In the above-mentioned explanation of the "spacing between trench electrodes 81, 82, and 9," the trench spacing was exemplified by the spacing between adjacent trench electrodes 82 and 9 along the direction in which they are aligned, and the spacing between adjacent trench electrodes 9 connected via trench electrode 81. The emitter region is not shared between trench electrodes 81 and 82. Even if there are multiple trench electrodes 9 separating the semiconductor layer 31 that trench electrode 81 faces from the semiconductor layer 32 that trench electrode 82 faces, the increase in forward conduction loss due to depletion layer elongation is suppressed, and consequently, the range of acceptable time difference dt for reducing loss is expanded.

[0193] Figure 49 is a cross-sectional view illustrating the configuration of the semiconductor device 100E according to Embodiment 5. Figure 50 is a cross-sectional view showing one example of the configuration of the semiconductor device 100E, and Figure 51 is a cross-sectional view showing another example of the configuration of the semiconductor device 100E.

[0194] Both the cross-section shown in Figure 50 and the cross-section shown in Figure 51 appear when viewed from the direction of the arrow at position AA in Figure 49. The cross-section illustrated in Figure 49 is also the cross-section that appears when viewed from the direction of the arrow at position BB in Figure 50, and the cross-section that appears when viewed from the direction of the arrow at position CC in Figure 51. The configuration illustrated in Figure 50 contributes, for example, to suppressing the multi-layering of wiring using polysilicon, and consequently to improving productivity.

[0195] Compared to semiconductor device 100A (see Figures 1, 2, and 3), semiconductor device 100E is understood to have a configuration in which the trench electrode 9 is divided into two in the direction in which the trench electrodes 81 and 82 are aligned. Between the divided trench electrodes 9, semiconductor layers 31, 2, and 5 are stacked in this order when viewed from the semiconductor substrate 1 side, and neither semiconductor layer 41 nor 42 is present.

[0196] It is considered that the distance between adjacent trench electrodes 9 without passing through the trench electrode 81, as exemplified by the semiconductor device 100E, also corresponds to the trench pitch. In view of FIG. 25 and the description using the same, making the distance between adjacent trench electrodes 9 in the semiconductor device 100E narrower than 15 μm contributes to making the breakdown voltage of the semiconductor device 100E 90% or more of the target breakdown voltage.

[0197] The semiconductor device 100E can also be manufactured in the same manner as the semiconductor device 100A. Specifically, in the first manufacturing method of the semiconductor device 100A, a plurality of openings 503a (see FIG. 33) opened in the mask 503 are provided closer to the trench electrode 81 side than the opening 503b. Alternatively, in the second manufacturing method of the semiconductor device 100A, a plurality of openings 502b (see FIG. 38) opened in the mask 502 are provided between the openings 502a and c.

[0198] Also in the semiconductor device - 100E, similar to the semiconductor device 100D, the peak value of the impurity concentration of the semiconductor layer 31 may be lower than the peak value of the impurity concentration of the semiconductor layer 32. Further, the semiconductor layer 31 may be thinner than the semiconductor layer 32, and the relationship d31 < d32 may hold. The semiconductor device 100E in this case can be manufactured, for example, in the same manner as the semiconductor device 100D. Specifically, for example, the first manufacturing method and the second manufacturing method of the semiconductor device 100D can be applied.

[0199] <Embodiment 6> Even if a pair of trench electrodes 9 sandwich a plurality of trench electrodes 82, the emitter regions are not shared between the trench electrodes 81 and 82. The increase in the forward conduction loss due to the extension of the depletion layer is suppressed, and thus the allowable range of the time difference dt for reducing the loss is expanded.

[0200] [[ID=第十九]] FIG. 52 is a cross - sectional view illustrating the configuration of the semiconductor device 100F according to Embodiment 6. FIG. 53 is a cross - sectional view showing an example of the configuration of the semiconductor device 100F, and FIG. 54 is a cross - sectional view showing another example of the configuration of the semiconductor device 100F.

[0201] Both the cross-section shown in Figure 53 and the cross-section shown in Figure 54 appear when viewed from the direction of the arrow at position DD in Figure 52. The cross-section illustrated in Figure 52 is also the cross-section that appears when viewed from the direction of the arrow at position EE in Figure 53, and the cross-section that appears when viewed from the direction of the arrow at position FF in Figure 54. The configuration illustrated in Figure 53 contributes, for example, to suppressing the multi-layering of wiring using polysilicon, and consequently to improving productivity.

[0202] It is understood that semiconductor device 100F has a configuration in which two trench electrodes 82 are provided in the direction in which trench electrodes 81 and 89 are aligned, compared to semiconductor device 100A (see Figures 1, 2, and 3). For each trench electrode 82, on both sides in the direction in which they are aligned, semiconductor layers 32, 2, and 5 are stacked in this order when viewed from the semiconductor substrate 1 side. For each trench electrode 82, on both sides in the direction in which they are aligned, semiconductor layer 42 is closer than semiconductor layer 5.

[0203] As exemplified in semiconductor device 100F, the distance between adjacent trench electrodes 82 that are not separated by either of the trench electrodes 81 or 89 can also be considered to correspond to the trench distance. And in light of Figure 25 and the explanation using it, making the distance between adjacent trench electrodes 82 in semiconductor device 100F narrower than 15 μm contributes to raising the withstand voltage of semiconductor device 100F to 90% or more of the target withstand voltage.

[0204] The semiconductor device 100F can also be manufactured in the same manner as the semiconductor device 100A. Specifically, referring to Figure 33, in the first manufacturing method of the semiconductor device 100A, a pair of semiconductor layers 42 are provided adjacent to each other, and an opening 503b that opens into the mask 503 is provided in each semiconductor layer 42. Alternatively, referring to Figure 38, in the second manufacturing method of the semiconductor device 100A, a pair of semiconductor layers 42 are provided adjacent to each other, and an opening 502c that opens into the mask 502 is provided in each semiconductor layer 42.

[0205] In the semiconductor device 100F as well, similar to the semiconductor device 100D, the peak value of the impurity concentration of the semiconductor layer 31 may be lower than the peak value of the impurity concentration of the semiconductor layer 32. Further, the semiconductor layer 31 may be thinner than the semiconductor layer 32, and there may be a relationship of d31 < d32. The semiconductor device 100F in this case can be manufactured, for example, in the same manner as the semiconductor device 100D. Specifically, for example, the first manufacturing method and the second manufacturing method of the semiconductor device 100D can be applied.

[0206] Any of the technologies described above can also be adopted for a reverse conducting IGBT (RC - IGBT).

[0207] Note that within the scope of the present invention, the embodiments can be freely combined with each other, or each embodiment can be appropriately modified or omitted.

[0208] Hereinafter, aspects of the present disclosure will be summarized and described as appendices.

[0209] (Appendix 1) A semiconductor substrate of a first conductivity type, A first semiconductor layer of the first conductivity type located on the surface layer of the semiconductor substrate, The aforementioned A second semiconductor layer of the first conductivity type, Exclusively located on the surface layer of the semiconductor substrate with respect to the first semiconductor layer, and having a peak value of impurity concentration higher than that of the semiconductor substrate, The aforementioned A third semiconductor layer of the second conductivity type located on the side opposite to the semiconductor substrate with respect to the first semiconductor layer and the second semiconductor layer, A fourth semiconductor layer of the second conductivity type selectively located on the side opposite to the semiconductor substrate with respect to the third semiconductor layer, and having a peak value of impurity concentration higher than that of the third semiconductor layer, A fifth semiconductor layer of the first conductivity type, The aforementioned Exclusively located on the side opposite to the semiconductor substrate with respect to the third semiconductor layer and the fourth semiconductor layer, and having a peak value of impurity concentration higher than that of the second semiconductor layer, A fifth semiconductor layer of the first conductivity type, The aforementioned A fifth semiconductor layer of the first conductivity type, The semiconductor substrate is located on the opposite side of the first semiconductor layer, second semiconductor layer, third semiconductor layer, fourth semiconductor layer, and fifth semiconductor layer. The aforementioned The sixth semiconductor layer of the second conductivity type, A first electrode that penetrates the fifth semiconductor layer and the third semiconductor layer, extends from the sixth semiconductor layer to the first semiconductor layer at a distance greater than the boundary between the second semiconductor layer and the semiconductor substrate, and has an insulating surface, A second electrode that penetrates the second semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer, or penetrates the second semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer, extends to the semiconductor substrate, is closer to the sixth semiconductor layer than either the first semiconductor layer or the second semiconductor layer, and has an insulating surface, The third electrode extends through the fourth and third semiconductor layers to the semiconductor substrate, is closer to the sixth semiconductor layer than either the first or second semiconductor layer, separates the first semiconductor layer from the second semiconductor layer, sandwiches the second semiconductor layer together with the second electrode, and has an insulating surface. A semiconductor device equipped with a semiconductor device.

[0210] (Note 2) The semiconductor device according to Appendix 1, wherein the peak value of the impurity concentration of the first semiconductor layer is higher than the peak value of the impurity concentration of the semiconductor substrate.

[0211] (Note 3) The semiconductor device described in Appendix 2, wherein the second electrode penetrates the fifth semiconductor layer and the third semiconductor layer.

[0212] (Note 4) The semiconductor device described in Appendix 3, wherein the peak value of the impurity concentration in the first semiconductor layer is lower than the peak value of the impurity concentration in the second semiconductor layer.

[0213] (Note 5) The semiconductor device described in Appendix 4, wherein the first semiconductor layer is thinner than the second semiconductor layer.

[0214] (Note 6) The semiconductor device described in Appendix 2, wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

[0215] (Note 7) The semiconductor device described in Appendix 1, wherein the first semiconductor layer is part of the semiconductor substrate.

[0216] (Note 8) The semiconductor device described in Appendix 1, wherein the second electrode penetrates the fifth semiconductor layer and the third semiconductor layer.

[0217] (Note 9) The semiconductor device described in Appendix 1, wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

[0218] (Note 10) A semiconductor device according to any one of the appendices 1 to 9, wherein the length by which the second electrode protrudes from the second semiconductor layer to the semiconductor substrate in the direction in which the second electrode extends is equal to the length by which the third electrode protrudes from the second semiconductor layer to the semiconductor substrate in the direction in which the third electrode extends.

[0219] (Note 11) A semiconductor device according to any one of the appendices 1 to 10, wherein the size of the first electrode in a direction perpendicular to the direction in which the first electrode extends is smaller than the size of the second electrode in a direction perpendicular to the direction in which the second electrode extends and the size of the third electrode in a direction perpendicular to the direction in which the third electrode extends.

[0220] (Note 12) The semiconductor device according to any one of the appendices 1 to 11, wherein the distance between adjacent second electrodes and third electrodes, the distance between adjacent second electrodes, or the distance between adjacent third electrodes, along the direction in which the second and third electrodes are aligned, is 15 μm or less.

[0221] (Note 13) The third electrode is located on both one side and the other side of the first electrode in the direction in which the first electrode and the third electrode are aligned. The semiconductor device according to any one of the appendices 1 to 11, wherein the distance between the third electrode located on one side of the first electrode and the third electrode located on the other side of the first electrode is 15 μm or less in the direction.

[0222] (Note 14) A method for controlling a semiconductor device described in any one of the appendices 1 to 13, A first signal is applied to the first electrode. A second signal is applied to the second electrode. A method for controlling a semiconductor device, wherein when either the first signal or the second signal is transitioned to turn off the semiconductor device, the first signal transitions with a delay compared to the second signal.

[0223] (Note 15) The control method for a semiconductor device according to Appendix 14, wherein the first conductivity type is N-type, and the second signal transitions at a potential of zero or less relative to the third electrode.

[0224] (Note 16) A method for manufacturing a semiconductor device as described in Appendix 5, Prior to forming the first and second semiconductor layers, the semiconductor substrate is subjected to The aforementioned An introduction process in which a first-type conductive impurity is introduced into the first region in a first introduction amount, and into the second region in a second introduction amount that is greater than the first introduction amount, Introduced in the above first region The aforementioned Diffusion of the first conductivity type impurity and the introduction in the second region The aforementioned A diffusion step is performed in parallel with the diffusion of a first conductivity type impurity to form the first semiconductor layer and the second semiconductor layer. A method for manufacturing a semiconductor device, comprising:

[0225] (Note 17) In the introduction step, ion implantation is performed on the first region using a mask having a stripe pattern or a dot pattern. The aforementioned Introduction of impurities of the first conductivity type and to the aforementioned second region The aforementioned A method for manufacturing a semiconductor device as described in Appendix 16, wherein the introduction of a first-conductivity type impurity is carried out in parallel.

[0226] (Note 18) A method for manufacturing a semiconductor device as described in Appendix 10, A method for manufacturing a semiconductor device, wherein, prior to the formation of either the second electrode or the third electrode, trenches for embedding the second electrode and trenches for embedding the third electrode are formed in parallel by selective etching using a mask having openings.

[0227] (Note 19) A method for manufacturing a semiconductor device as described in Appendix 11, A method for manufacturing a semiconductor device, wherein, prior to the formation of any of the first, second, and third electrodes, a first trench for embedding the first electrode, a second trench for embedding the second electrode, and a third trench for embedding the third electrode are formed in parallel by selective etching using a mask with openings, and the openings used for etching to form the second trench and the third trench are wider than the openings used for etching to form the first trench. [Explanation of Symbols]

[0228] 1 Semiconductor substrate, 2,3,5,10,11,31,32,41,42 Semiconductor layers, 81,82,9 Trench electrodes, 100A~100F Semiconductor equipment, 301,302 Regions, 502,503 Masks, 502a,502b,502c,503a,503b Apertures, 801,802,90 Trenches.

Claims

1. A first-type conductive semiconductor substrate and The first semiconductor layer of the first conductivity type located on the surface layer of the semiconductor substrate, A second semiconductor layer of a first conductivity type, which is exclusively located on the surface layer of the semiconductor substrate and has a higher peak value of impurity concentration than the semiconductor substrate, A third semiconductor layer of a second conductivity type located on the opposite side from the semiconductor substrate to the first and second semiconductor layers, A fourth semiconductor layer of second conductivity type is selectively located on the side opposite to the semiconductor substrate relative to the third semiconductor layer, and has a higher peak value of impurity concentration than the third semiconductor layer. A fifth semiconductor layer of the first conductivity type is located on the opposite side of the semiconductor substrate from the third semiconductor layer and exclusively with the fourth semiconductor layer, and has a higher peak value of impurity concentration than the second semiconductor layer. A sixth semiconductor layer of second conductivity type located on the opposite side of the semiconductor substrate from any of the first, second, third, fourth, and fifth semiconductor layers, A first electrode that penetrates the fifth semiconductor layer and the third semiconductor layer, extends from the sixth semiconductor layer further than the boundary between the second semiconductor layer and the semiconductor substrate, and reaches the first semiconductor layer, and whose surface is insulating, A second electrode that penetrates the second semiconductor layer, the fourth semiconductor layer and the third semiconductor layer, or penetrates the second semiconductor layer, the fifth semiconductor layer and the third semiconductor layer, extends to the semiconductor substrate, is closer to the sixth semiconductor layer than either the first semiconductor layer or the second semiconductor layer, and has an insulating surface, The third electrode extends through the fourth semiconductor layer and the third semiconductor layer to the semiconductor substrate, is closer to the sixth semiconductor layer than either the first semiconductor layer or the second semiconductor layer, separates the first semiconductor layer from the second semiconductor layer, sandwiches the second semiconductor layer together with the second electrode, and has an insulating surface. Equipped with, The second electrode is a semiconductor device that penetrates the fifth semiconductor layer and the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein the peak value of the impurity concentration of the first semiconductor layer is higher than the peak value of the impurity concentration of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein the peak value of the impurity concentration of the first semiconductor layer is lower than the peak value of the impurity concentration of the second semiconductor layer.

4. The semiconductor device according to claim 3, wherein the first semiconductor layer is thinner than the second semiconductor layer.

5. The semiconductor device according to claim 2, wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

6. The semiconductor device according to claim 1, wherein the first semiconductor layer is a part of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein the second electrode penetrates the fourth semiconductor layer and the third semiconductor layer.

8. A semiconductor device according to any one of claims 1 to 7, wherein the length by which the second electrode protrudes from the second semiconductor layer to the semiconductor substrate in the direction in which the second electrode extends is equal to the length by which the third electrode protrudes from the second semiconductor layer to the semiconductor substrate in the direction in which the third electrode extends.

9. The semiconductor device according to any one of claims 1 to 7, wherein the size of the first electrode in a direction perpendicular to the direction in which the first electrode extends is smaller than the size of the second electrode in a direction perpendicular to the direction in which the second electrode extends and the size of the third electrode in a direction perpendicular to the direction in which the third electrode extends.

10. The semiconductor device according to any one of claims 1 to 7, wherein the distance between adjacent second electrodes and third electrodes, the distance between adjacent second electrodes, or the distance between adjacent third electrodes, along the direction in which the second and third electrodes are aligned, is 15 μm or less.

11. The third electrode is located on both one side and the other side of the first electrode in the direction in which the first electrode and the third electrode are aligned. The semiconductor device according to any one of claims 1 to 7, wherein the distance between the third electrode located on one side of the first electrode and the third electrode located on the other side of the first electrode is 15 μm or less in the direction.

12. A method for controlling a semiconductor device according to any one of claims 1 to 7, A first signal is applied to the first electrode. A second signal is applied to the second electrode. A control method for a semiconductor device, wherein when the semiconductor device is turned off by transitioning either the first signal or the second signal, the first signal transitions with a delay compared to the second signal.

13. The control method for a semiconductor device according to claim 12, wherein the first conductivity type is N-type, and the second signal transitions at a potential of zero or less relative to the third electrode.

14. A method for manufacturing a semiconductor device according to claim 4, Prior to the formation of the first semiconductor layer and the second semiconductor layer, an introduction step is performed in which the first conductivity type impurity is introduced into the semiconductor substrate in a first introduction amount into the first region and in a second introduction amount greater than the first introduction amount into the second region. A diffusion step to form the first semiconductor layer and the second semiconductor layer by performing in parallel the diffusion of the first conductivity type impurity introduced in the first region and the diffusion of the first conductivity type impurity introduced in the second region. A method for manufacturing a semiconductor device, comprising:

15. The method for manufacturing a semiconductor device according to claim 14, wherein in the introduction step, the introduction of the first conductivity type impurity into the first region and the introduction of the first conductivity type impurity into the second region are performed in parallel by ion implantation using a mask having a stripe pattern or a dot pattern.

16. A method for manufacturing a semiconductor device according to claim 8, A method for manufacturing a semiconductor device, wherein, prior to the formation of either the second electrode or the third electrode, trenches for embedding the second electrode and trenches for embedding the third electrode are formed in parallel by selective etching using a mask having openings.

17. A method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein, prior to the formation of any of the first, second, and third electrodes, a first trench for embedding the first electrode, a second trench for embedding the second electrode, and a third trench for embedding the third electrode are formed in parallel by selective etching using a mask with openings, and the openings used for etching to form the second trench and the third trench are wider than the openings used for etching to form the first trench.

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