Methods, systems, and computer program products for using high-speed access channels with track status information.

Abstract

A method is provided for determining whether to process a host request on a fast access channel using track status information regarding an active or inactive status of a track. A host request to access a target track is received on a first channel to a host. A determination is made as to whether the target track has an active status or an inactive status. A target track has an active status when at least one process currently maintains a lock on the target track that prevents access, and a target track has an inactive status when no process maintains a lock on the target track that prevents access. In response to the target track having an active status, a failure is returned to the host to cause the host to resend the host request on a second channel. The first channel has less latency than the second channel.

Description

[Technical Field]

[0001] The present invention relates to a computer program product, system, and method for determining whether to process a host request on a high-speed access channel using track status information relating to the active or inactive status of a track. [Background technology]

[0002] In a storage environment, a host system may communicate read / write requests to a storage system connected via a high-speed access channel, such as a bus interface like the Peripheral Component Interconnect Express (PCIe) interface. If the data is in the storage system's cache, i.e., a read hit, the data can be quickly returned to the host system via the faster access channel, where the host thread related to the read / write request is in a spin-loop state waiting for the request to complete. This saves processor time associated with context swapping, which deactivates the thread and reactivates it in response to an interrupt when a response to the read / write request is received. If the data for a read / write request sent over the high-speed channel is not in the cache, the storage system may fail the read / write request, and the host system may communicate the same read / write request over the host adapter via the storage area network, which is slower than processing the I / O request over the bus, for example, the PCIe interface. To communicate read / write requests through a second channel, the host system needs to switch context from the task handling the read / write request to another task while waiting for the read / write request to complete.

[0003] In this field, there is a need for improved techniques for managing host requests over high-speed access channels. [Overview of the Initiative]

[0004] A computer program product, system, and method are provided for determining whether to process a host request on a fast access channel using track status information regarding the active or inactive status of a track. A host request to access a target track is received on a first channel to the host. The determination of whether the target track has an active or inactive status is made from the track status information. A target track has an active status when at least one process currently holds a lock on the target track that is preventing access, and an inactive status when no process holds a lock on the target track that is preventing access by other processes. In response to determining that the target track has an active status, a failure is returned to the host causing it to resend the host request on a second channel, and the first channel has less latency than the second channel. [Brief explanation of the drawing]

[0005] [Figure 1] This is a diagram illustrating one embodiment of a storage environment. [Figure 2] This is a diagram of one embodiment of a cache control block. [Figure 3] This diagram illustrates one embodiment of processing input / output (I / O) requests to a target track on a high-speed access channel. [Figure 4] This diagram illustrates one embodiment of the operation for locking a cache control block in order to access a target track within the cache. [Figure 5] This diagram illustrates one embodiment of the operation for releasing a lock on a cache control block in order to terminate access to the target track. [Figure 6] This is a diagram of one embodiment of the computer architecture used in the described embodiment. [Modes for carrying out the invention]

[0006] In current storage environments using high-speed access channels such as PCIe bus interfaces, a storage system may fail to process an I / O request if the target track is not already in the cache, provided the request must be completed within a certain threshold time. However, even if the track is in the cache, significant latency can be experienced if the target track is currently being accessed by another processor, and a lock must be obtained to access the target track in the cache and process the host I / O request on the high-speed channel. This latency to access a track currently being accessed by another processor can result in unacceptable latency that exceeds the threshold time required to complete processing the host request on the high-speed channel.

[0007] The embodiments described provide an improvement to computer technology for host access requests submitted on a fast access channel by providing track status information, which can be accessed through an active track data structure or through the active bit in the cache control block of the target track, and can be used to determine whether the target track of a host request on the fast access channel has an active status, i.e., is currently being accessed by another process, or has an inactive status and is not being accessed by another process. If the target track has an active status, the host request on the fast access channel is failed to avoid latency resulting from waiting to obtain a lock on the target track in the cache while it is being accessed by another process. If the target track in the cache has an inactive status, the host request can be processed on the fast access channel, as it is possible to immediately access the target track in the cache and complete the processing of the host request.

[0008] Figure 1 shows one embodiment of a storage environment in which a host 100 sends read and write requests to a storage system 102 to access tracks in a volume configured in a storage device 104 within a disk enclosure 106. The host 100 includes a processor complex 108 consisting of one or more processor devices and memory 110 containing an operating system 111 executed by the processor complex 108. The host operating system 111 generates read and write requests to the tracks configured in the storage device 104. The host 100 includes hardware for communicating read and write requests over two different channels. The first channel, also called the high-speed channel or high-speed access channel, is a bus interface such as Peripheral Component Interconnect Express (PCIe) and includes bus 112, a bus switch 114 for connecting one or more devices on bus 112 including a processor complex 108 and a memory system 110, and a bus host adapter 116 for extending the bus interface to the storage system 102 via an external bus interface cable 118. Additional bus interface technologies may be used to extend the bus interface, including components such as PCIe extension cables or distributed PCIe switches, to enable PCIe over Ethernet(R) using technologies such as ExpEther. The second channel for connecting host 100 and storage system 102, also called the low-speed channel, uses a network host adapter 120 connected to bus 112, which connects to another network 122 through which host 100 and storage system 102 communicate additionally. The first channel through the bus interface may have a faster access channel than the network 122 interface through the network host adapter 120.

[0009] The storage system 102 includes a bus interface having buses 124a, 124b, a bus switch 126 connected to termination devices on buses 124a, 124b, and a bus host adapter 128 connected to an external bus interface cable 118 to enable communication through a bus interface with host 100 via a first channel. The storage system 102 includes an input / output bay 130 having a bus host adapter 128, one or more device adapters 132 for connecting to a storage device 104, and one or more network host adapters 134 for connecting to network 122 and a host system.

[0010] The storage system 102 includes a processor complex 136 consisting of one or more processor devices, and a memory 138 having a cache 140 for caching tracks accessed by an attached host 100. The memory 138 includes a cache manager 142 and a storage manager 144. The storage manager 144 manages access requests from processes of host 100 and the storage system 102 for tracks of storage 104. Devices 136, 138, 128, 132, and 134 are connected through a bus interface implemented as bus lanes 124a, 124b and a bus switch 126.

[0011] The cache manager 142 maintains accessed tracks in the cache 140 for future read access to those tracks, allowing accessed tracks to be returned from the high-speed access cache 140 instead of having to be retrieved from storage 104. Furthermore, tracks in the cache 140 can be updated by writes. A track may comprise any data unit configured within storage 110, such as a track, logical block address (LBA), storage cell, group of cells (e.g., column, row, or array of cells), sector, segment, etc., and may be part of a larger grouping of tracks, such as a volume or logical device.

[0012] In certain implementations, such as those using the Z / OS(R) operating system from International Business Machines Corporation ("IBM"), each segment may have an associated descriptor called a Cache Segment Control Block (CSCB), one of which is cast as a cache control block called a Cache Directory Control Block (CDCB). Cache 140 may be divided into 4K segments. Each track within the cache may have up to 17 CSCBs. One of the CSCBs within a track is designated as a cache control block, also known as a CDCB (Cache Directory Control Block), and holds all control information related to the track. There is one cache control block for each track within Cache 140, providing metadata about the track within Cache 140. (Z / OS is a registered trademark of IBM worldwide.)

[0013] The cache manager 142 maintains cache management information 146 in the memory 138 to manage the read (unchanged) and write (changed) tracks in the cache 140. The cache management information 146 includes a least recently used (LRU) cache list 148 indicating the tracks in the cache 140 for determining which track to demote from the cache 140, a cache directory 150 providing a segment descriptor to the index of the cache control block 200 or the location of the segment in the cache 140 having the cache control block 200 or segment specified in the cache 140, and an active track data structure 152 indicating the active tracks in the cache 140.

[0014] In one embodiment, the active track data structure 152 may comprise a bitmap having bits corresponding to each segment of the cache 140. A plurality of segments in the cache 140 may be assigned to one track, and the cache control block 200 i of a track has metadata about that track and may be present in one of the segments assigned to that track. The bit in the bitmap 152 corresponding to the cache control block 200 i of that track may be set to indicate whether that track is active or inactive. Bits in the bitmap of the active track data structure 152 representing segments that do not have track data and are not the cache control block 200 i are left unused. A portion or bits of the bitmap of the active track data structure 152 may be implemented within a cache line that needs to lock the bit to process the bit to determine whether the corresponding cache control block 200 i is active.

[0015] In one embodiment, the cache directory 150 may be implemented as a distributed index table, in which case the track address or cache control block identifier is hashed into an entry in the table. If the cache 140 has data for that cache control block or track, the entry in the cache directory 150 that hashed that value is the cache control block 200 for a certain track. i This will result in a pointer that points to the location within cache 140 where the segment is stored.

[0016] In Figure 1, the cache manager 142 and the storage manager 144 are shown as program code loaded into memory 138 and executed by the processor complex 136. Alternatively, some or all of the functionality may be implemented as microcode or firmware within a hardware device in the storage system 102, such as an application-specific integrated circuit (ASIC).

[0017] In one embodiment, there may be multiple hosts 100 that connect to the storage system 102 through first and second channels to access tracks on the storage device 104. In such a case, the storage system 102 has at least one bus host adapter 128 for connecting to the bus interface 118 of each connected host 100, and one or more network host adapters 134 for connecting to the network host adapter 120 of the host 100.

[0018] In one embodiment, bus interfaces 112, 114, 116, 118, 124a, 124b, 126, and 128 may feature Peripheral Component Interconnect Express (PCIe) bus interface technology. In an alternative embodiment, bus interfaces 112, 114, 116, 118, 124a, 124b, 126, and 128 may utilize suitable bus interface technology other than PCIe. Bus host adapters 116 and 128 may include PCIe host adapters that provide an interface for connecting to PCIe cable 118. Network 122 may consist of a storage area network (SAN), local area network (LAN), wide area network (WAN), internet, intranet, etc., and network host adapters 120, 134 provide network 122 connectivity between host 100 and storage system 102.

[0019] The storage system 102 may comprise a storage system such as the DS8000(R) and DS8880 storage systems from International Business Machines Corporation (IBM(R)), or a storage controller and storage system from another vendor. (IBM and DS8000 are trademarks of International Business Machines Corporation worldwide.) The host operating system 111 may comprise an operating system such as the Z Systems Operating System (Z / OS(R)) from International Business Machines Corporation ("IBM"), or another operating system known in the art. (Z / OS is a registered trademark of IBM worldwide.)

[0020] The storage device 104 within the disk enclosure 106 may consist of various types or classes of storage devices, such as magnetic hard disk drives, solid-state storage devices (SSDs) composed of solid-state electronic elements, EEPROMs (electrically erasable programmable read-only memory), flash memory, flash disks, random-access memory (RAM) drives, storage-class memory (SCM), phase-change memory (PCM), resistive random-access memory (RRAM), spin-transfer torque memory (STT-RAM), conductive bridging RAM (CBRAM), magnetic hard disk drives, optical disks, tapes, etc. The volume within the storage space may further consist of arrays of devices such as Just a Bunch of Disks (JBOD), direct-access storage devices (DASD), redundant arrays of independent disks (RAID), and virtualization devices. Furthermore, the storage device 104 within the disk enclosure 106 may include a heterogeneous mix of storage devices from various vendors and various types of storage devices, such as a first type of storage device, such as a hard disk drive, which has a lower data transfer rate than a second type of storage device, such as an SSD.

[0021] Figure 2 shows a cache control block 200 corresponding to one of the tracks of cache 140. i One embodiment of the example is shown, and is not limited to, the cache control block 200 i Cache control block identifier 202 such as index value; cache control block 200 associated with track iThe cache list 204 shown; the position within the LRU cache list 206 where the track is shown; an active bit 208 indicating whether the track is shown to have an active status or an inactive status within the active track data structure 152; usage information 210 providing usage statistics about the track in the cache, such as the number of active users, the number of active writes, the number of locks, the number of changes, the number of waiting threads (waiters), etc.; the cache control block 200 i including a demote status 212 indicating whether the track identified by i should be demoted from the cache 140. Additional information not described herein used to manage the tracks within the cache 140 may be included in the cache control block 200 i and may be included in the cache control block 200

[0022] The active bit 208 provides an optimization for indicating whether the active track data structure 152 indicates that the track is active. This allows a process to determine whether the track is active without having to obtain a lock on the cache line for the bit within the active track data structure 152 with respect to the cache control block 200 i and without having to lock the cache line having the bit in order to determine whether the bit to be read indicates active or inactive during normal operation, so that the process can determine whether it is necessary to reset the bit within the active track data structure 152

[0023] Figure 3 shows one embodiment of the operation performed by the cache manager 142 or storage manager 144 to process input / output ("I / O") requests, e.g., read or write, to a target track on a low-latency first channel 118. When the storage manager 144 receives an I / O request to a target track on the high-speed access channel 118 (in block 300), if the target track is not in the cache 140 (in block 302), the storage manager 144 returns a failure to the host on the first channel 118 (in block 304), causing the host to resubmit the I / O request on the higher-latency second channel 122 via the network host adapters 120, 134. If the target track is in the cache 140 (in block 302), the cache manager 142 (in block 306) uses the active track data structure 152 or the cache control block 200 for the target track. T The program determines whether the track status information, such as the active bit 208, indicates that the track is active, meaning that another process is currently accessing the track, such as holding a lock on it. If the target track has an active status (in block 306), control proceeds to block 304, which returns failure despite the target track being in cache 140.

[0024] (In block 306) If the target track has an inactive status, that is, if there is no process currently accessing the track and preventing host I / O requests from immediately gaining access, the operation in Figure 4 occurs (in block 308), and the cache control block 200 of the target track TA lock is obtained for the target. (In block 310) If the request includes a read request, the cache manager 142 reads the target track from the cache 140 and returns the read target track to the host 100 on the first channel 118. (In block 310) If the target request includes a write request, the write data in the write request is written to the target track (in block 314). After the requested read or write is performed, completion is returned to the host 100 on the first channel 118 (in block 316). Then the operation in Figure 5 is performed (in block 318) for the cache control block 200 of the target track. T Release the lock on it and terminate access.

[0025] In the operational embodiment shown in Figure 3, during high-speed writing via the bus interface 118 or the first channel, the active track data structure 152 or the cache control block 200 of the target track T If the track status information, such as the active bit 208, indicates that the target track is not currently being accessed, for example, if no lock is held on the target track, the host request can access the target track without latency. In such cases, the read / write request is allowed to proceed when the transaction can be processed very quickly, as it can be accessed immediately without having to wait for another process to relinquish a lock or access to the target track in cache 140. However, if the track status information indicates that the target track has an active status, the host read / write request is failed because the transaction is unlikely to complete within the fast time threshold. This decision is important to avoid host latency when the host processor is processing other tasks while spinning on the thread handling the read / write request and waiting for the read / write request to complete.

[0026] If the target track can be accessed immediately without having to wait for other processes to release access to the target track, there is a high probability that the read / write operation can be completed on the high-speed bus interface channel 118 within the time required to avoid the host processor holding the thread for too long, thereby delaying I / O requests from other hosts 100 by putting them in a queue. If the target track status is active and the host I / O request needs to wait for other processes to relinquish access to the target track, there is a low probability that the read / write request can be completed within the time threshold for the host processor to spin the thread for the read / write request, and a failure is returned. Returning a failure when the target track status is active causes the host thread waiting on the read / write request task to become inactive, and the host processor may switch context to processing other tasks, after which the read / write request may be attempted again on a second network channel 122 during the context switch.

[0027] Figure 4 shows the target track cache control block 200 for accessing the target track in the cache 140. T This shows one embodiment of the operation performed by the cache manager 142 to lock the target track cache (in block 400) of the target track cache control block 200. T When the operation to obtain a lock on begins, the cache manager 142 (in block 402) accesses the target track cache control block 200. T A lock is obtained, which may be obtained through the cache directory 150. (In block 404) Target track cache control block 200 T If the active bit 208 indicates active, this means that the cache control block 200 is being accessed. TSince the settings are correct for it, control ends. If the active bit 208 (in block 404) indicates inactive, the cache manager 142 (in block 408) controls the target track cache control block 200. T A lock is obtained over the cache line containing the bit in the active track data structure 152. The bit in the locked cache line of the active track data structure 152 is then controlled by the cache control block 200. T And because the track is being accessed, it is then set to indicate active (in block 410). Also, the target track cache control block 200 T The active bit 208 within is also set to indicate active (in block 412). And the target track cache control block 200 within the active track data structure 152 T The lock on the cache line containing the bit set for is released.

[0028] In the operational embodiment shown in Figure 4, the target track cache control block 200 accesses the target track in the cache 140. TWhen accessed, a determination is made as to whether the active bit in the active track data structure 152 needs to be updated. In one embodiment, to determine whether an update is needed, an exclusive lock on the cache line having the bit to be updated is obtained by examining the active bit 208 in the cache control block to determine whether the active track data structure 152 actually needs to be updated. This optimization avoids the need to lock and access the bit in the active track data structure 152 by first checking whether the active bit 208 actually needs to be set or reset. Furthermore, the active track data structure 152 is updated with current information about the active status of the target track so as to maintain the active track data structure 152 along with current information about the active track status, enabling better processing of host requests on the high-speed bus channel 118.

[0029] Figure 5 shows the target track cache control block 200 after completing access to the target track in cache 140. T This shows one embodiment of the operation performed by the cache manager 142 to release the lock on the target track cache control block 200 (in block 500). T When the operation to release the lock begins, the cache manager 142 (in block 502) cache control block 200 i Determine whether the active bit 208 is active (in block 502). If the active bit 208 is active, the cache manager 142 processes the cache control block usage information 210 (in block 504), such as the number of active users, the number of writes, and the changed flags, and then determines the target track cache control block 200 based on the usage information 210. T Determine whether it is active.

[0030] (In block 506) Target track cache control block 200 T If it is inactive based on usage information 210 and contradicts the active bit 208, the cache manager 142 (in block 508) the target track cache control block 200 T The cache line containing the bit in the active track data structure 152 is locked, and the cache control block 200 (in block 510) T Resets the bits in the cache line that are locked to indicate inactivity. Cache control block 200 T The active bit 208 within is reset to indicate inactivity (in block 512). The lock on the cache line is released (in block 516), and the target track cache control block 200 T The lock is released. (In block 502) Target track cache control block 200 T If the active bit indicates inactive, control proceeds to block 516 and releases the lock without changing the active bit 208 which already indicates inactive. If the usage information 210 (in block 506) indicates that the track is active, control proceeds to block 516 and releases the lock without changing the active bit 208 which already indicates active.

[0031] In the embodiment of operation shown in Figure 5, the target track / cache control block 200 TWhen access is released, the cache manager 142 checks the active bit 208 in the cache control block to determine whether the active bit in the active track data structure 152 needs to be updated to indicate inactivity. This optimization avoids the need to lock and access the bit in the active track data structure 152 by checking whether the active bit 208 indicates that the bit in the active data structure 152 needs to be reset. Furthermore, if the active bit 208 indicates that the released target track is inactive, the cache manager 142 verifies that other usage information 210 indicates that the target track is still active, even though the active track data structure 152 / active bit 208 indicates that the track is inactive. If the active bit 208 and the active track data structure 152 indicate that the track is inactive, but the released target track is determined to be active, then the information 208 and 152 must be reset to indicate that the target track is active, reflecting the current status of the track based on the usage information 210. This updates the active track data structure 152 with the current information about the active status of the target track, optimizing subsequent host I / O requests on the high-speed access bus interface 118.

[0032] The present invention may be implemented as a system, method, or computer program product, or a combination thereof. The computer program product may include (one or more) computer-readable storage media having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0033] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any preferred combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVDs), memory sticks, floppy(R) disks, mechanically encoded devices such as punch cards and grooved raised structures on which instructions are recorded, and any preferred combination thereof. The computer-readable storage medium used in this invention should not be interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through optical fiber cables), or electrical signals transmitted through electric wires.

[0034] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers those computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0035] The computer-readable program instructions for performing the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code, written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java(R), Smalltalk(R), and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions may be executed as a standalone software package, entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute a computer-readable program instruction by individually configuring the electronic circuit using state information of the computer-readable program instruction in order to carry out an aspect of the present invention.

[0036] Aspects of the present invention are described herein by reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and combinations of blocks in a flowchart or block diagram, or both, are implemented by computer-readable program instructions.

[0037] These computer-readable program instructions may be provided to a general-purpose computer, a special-purpose computer, or a processor of another programmable data processing device to produce a machine such that instructions executed via the processor of a computer or other programmable data processing device produce means for performing functions / operations specified in one or more blocks of a flowchart or block diagram, or both. These computer-readable program instructions may also be stored in a computer-readable storage medium on which the instructions are stored can be instructed to function in a particular manner to a computer, a programmable data processing device, or other device, or a combination thereof, to constitute a product containing instructions that perform modes of functions / operations specified in one or more blocks of a flowchart or block diagram, or both.

[0038] Computer-readable program instructions may be loaded into a computer, another programmable device, or another device such that instructions executed by the computer, another programmable device, or another device perform functions / operations specified in one or more blocks of a flowchart or block diagram, or both, causing a series of operational steps on the computer, another programmable device, or another device to generate a process executed by the computer.

[0039] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or part of an instruction, which contains one or more executable instructions for performing a specified logical function. In some alternative implementations, the functions described in a block may be performed in a different order than shown in the diagram. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or they may sometimes be executed in reverse order depending on the functions involved. It should also be noted that each block in the block diagram or flowchart diagram, or both, and combinations of blocks in the block diagram or flowchart diagram, or both, are implemented by a special-purpose hardware-based system that performs a specified function or operates or implements a combination of special-purpose hardware and computer instructions.

[0040] The computer components of Figure 1, including host 100 and storage system 102, may be implemented in one or more computer systems, such as computer system 602 shown in Figure 6. Computer system / server 602 may be described in the general context of computer system executable instructions, such as program modules, that are executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform a specific task or implement a specific abstract data type. Computer system / server 602 may be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices connected by a communication network. In a distributed cloud computing environment, program modules may reside in both local and remote computer system storage media, including memory storage devices.

[0041] As shown in Figure 6, the computer system / server 602 is represented in the form of a general-purpose computing device. The components of the computer system / server 602 may include, but are not limited to, one or more processors or processing units 604, system memory 606, and a bus 608 that connects various system components, including system memory 606, to the processor 604. The bus 608 represents one or more of several bus structures, including a memory bus or memory controller, peripheral buses, accelerated graphics ports, and a processor bus or local bus, using any of the various bus architectures. Examples of such architectures, but not limited to, include the Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI) bus.

[0042] The computer system / server 602 typically includes various computer system-readable media. Such media may be any available media accessible by the computer system / server 602, and may include both volatile and non-volatile media, and removable and non-removable media.

[0043] System memory 606 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 610 or cache memory 612 or both. Computer system / server 602 may further include other removable / non-removable, volatile / non-volatile computer system storage media. As merely an example, storage system 613 may be provided for reading and writing to a non-removable, non-volatile magnetic medium (not shown; commonly referred to as a “hard drive”). Not shown, magnetic disk drives for reading and writing to removable, non-volatile magnetic disks (e.g., “floppy disks”), and optical disk drives for reading or writing to removable, non-volatile optical disks such as CD-ROMs, DVD-ROMs or other optical media may be provided. In such examples, each may be connected to bus 608 by one or more data medium interfaces. As further illustrated and described below, memory 606 may include at least one program product having a set of program modules (e.g., at least one) configured to perform the functions of embodiments of the present invention.

[0044] A program / utility 614 having a set (at least one) of program modules 616 may be stored in memory 606, not limited to, but as an example, an operating system, one or more application programs, other program modules, and program data may also be stored. Each of the operating system, one or more application programs, other program modules, and program data or any combination thereof may include an implementation of a networking environment. Components of computer 602 may be implemented as program modules 616 that generally perform the functions and / or methodologies of the embodiments of the present invention described herein. The system of Figure 1 may be implemented in one or more computer systems 602, and if they are implemented as multiple computer systems 602, the computer systems may communicate with each other over a network.

[0045] The computer system / server 602 may also communicate with one or more external devices 618, such as a keyboard, pointing device, and display 620; one or more devices that allow a user to interact with the computer system / server 602; and / or any device (e.g., a network card, modem, etc.) that enables the computer system / server 602 to communicate with one or more other computing devices. Such communication can be done via the input / output (I / O) interface 622. Furthermore, the computer system / server 602 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, via the network adapter 624. As depicted, the network adapter 624 communicates with other components of the computer system / server 602 via the bus 608. It should be understood that other hardware components or software components, or both, may be used in conjunction with the computer system / server 602, although these are not shown. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data storage systems.

[0046] The terms “one embodiment,” “embodiment,” “plural embodiments,” “this embodiment,” “this plural embodiment,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments of the present invention,” unless expressly otherwise specified.

[0047] The terms "includes," "equipped with," "have," and their variations mean "includes, but not limited to," unless explicitly specified otherwise.

[0048] The enumerated list of items does not imply that any or all of those items are mutually exclusive unless explicitly specified otherwise.

[0049] The terms "a," "an," and "the" mean "one or more" unless explicitly specified otherwise.

[0050] Devices communicating with each other do not need to communicate continuously unless explicitly specified otherwise. Furthermore, devices communicating with each other may communicate directly or indirectly through one or more intermediaries.

[0051] The description of embodiments having several components that communicate with each other does not imply that all such components are necessary. Rather, various optional components are described in order to illustrate a variety of possible embodiments of the present invention.

[0052] Where a single device or article is described herein, it will be immediately apparent that two or more devices / articles (whether they work together or not) may be used in place of that single device / article. Similarly, where two or more devices or articles are described herein (whether they work together or not), it will be readily apparent that a single device / article may be used in place of those two or more devices or articles, or that a different number of devices / articles may be used in place of the number of devices or programs indicated. The functions or features, or both, of a device may be embodied, as an alternative, by one or more other devices not expressly described as having such functions / features. Thus, other embodiments of the invention do not need to include the device itself.

[0053] The above description of various embodiments of the present invention is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the invention to the exact form disclosed. Many modifications and variations are possible in light of the above teachings. The scope of the present invention is intended to be limited not by this detailed description but by the appended claims. The above specification, examples, and data provide a complete description of the manufacture and use of the configuration of the present invention. Since many embodiments of the present invention can be made without departing from the scope of the present invention, the present invention is contained in the appended claims below.

Claims

1. A computer-readable storage medium recording executable computer-readable program code for managing read and write requests from a host to tracks cached and stored in a cache, wherein the program code is accessible to a computer. The host receives a host request to access the target track via a first channel to the host, Determining from track status information whether the target track has an active status or an inactive status, wherein the target track has an active status when at least one process currently holds a lock on the target track that prevents access, and the target track has an inactive status when no process holds a lock on the target track that prevents access by other processes. In response to determining that the target track has the active status, the first channel returns a failure to the host to cause the host to resend the host request on the second channel, wherein the first channel returns the failure with less latency than the second channel. A computer-readable storage medium that enables execution of [something].

2. The computer-readable storage medium according to claim 1, wherein the track status information includes an active bit in the track's cache control block to indicate the active status or inactive status of the track, and determining whether the target track has the active status or the inactive status includes determining whether the active bit in the target track's cache control block indicates the active status or the inactive status.

3. The aforementioned program code is transmitted to the computer, Maintaining an active track data structure that indicates the track in the cache that has an active status, The active bit is set in the cache control block of the track to indicate that the track indicated as active in the active track data structure is active, A computer-readable storage medium according to claim 2, which further enables the execution of the above.

4. The computer-readable storage medium according to claim 1, wherein the track status information includes a bitmap containing bits for cache control blocks, where a bit for a given cache control block indicates whether the track identified by the cache control block is active or inactive, and determining whether the target track has an active status or an inactive status includes determining whether a bit for the cache control block of the target track in the bitmap indicates the active status or the inactive status.

5. The aforementioned program code is transmitted to the computer, In response to receiving the host request, determine whether the target track is in the cache, and the determination of whether the target track has an active status is performed in response to the determination that the target track is in the cache. In response to determining that the target track is not in the cache, the system returns a failure to the host to cause the host to resend the host request on the second channel, A computer-readable storage medium according to claim 1, which further enables the execution of the above.

6. The host request includes a read request, and the program code is sent to the computer. The computer-readable storage medium according to claim 5, further comprising processing the host request to read the target track from the cache and return the target track on the first channel in response to determining that the target track is in the cache and has the inactive status.

7. The host request includes a read request, and the program code is sent to the computer. In response to determining that the target track has the inactive status, the read request is processed to obtain a lock on the target track in the cache. In response to obtaining the lock, the target track in the cache is read, The read target track is returned to the host via the first channel, A computer-readable storage medium according to claim 1, which further enables the execution of the above.

8. A system for managing read and write requests from a host to tracks that are cached and stored in a cache, Processor and A computer-readable storage medium containing computer-readable program code, wherein the computer-readable program code performs an operation when executed by the processor, and the operation is The host receives a host request to access the target track via a first channel to the host, Determining from track status information whether the target track has an active status or an inactive status, wherein the target track has an active status when at least one process currently holds a lock on the target track that prevents access, and the target track has an inactive status when no process holds a lock on the target track that prevents access by other processes. In response to determining that the target track has the active status, the first channel returns a failure to the host to cause the host to resend the host request on the second channel, wherein the first channel returns the failure with less latency than the second channel. A system that includes this.

9. The system according to claim 8, wherein the track status information includes an active bit in the cache control block of the track to indicate the active status or the inactive status of the track, and determining whether the target track has the active status or the inactive status includes determining whether the active bit in the cache control block of the target track indicates the active status or the inactive status.

10. The aforementioned operation, Maintaining an active track data structure that indicates the track in the cache that has an active status, The active bit is set in the cache control block of the track to indicate that the track indicated as active in the active track data structure is active, The system according to claim 9, further comprising:

11. The system according to claim 8, wherein the track status information includes a bitmap containing bits for cache control blocks, where a bit for a given cache control block indicates whether the track identified by the cache control block is active or inactive, and determining whether the target track has an active status or an inactive status includes determining whether a bit for the cache control block of the target track in the bitmap indicates the active status or the inactive status.

12. The aforementioned operation, In response to receiving the host request, determine whether the target track is in the cache, and the determination of whether the target track has an active status is performed in response to the determination that the target track is in the cache. In response to determining that the target track is not in the cache, the system returns a failure to the host to cause the host to resend the host request on the second channel, The system according to claim 8, further comprising:

13. The host request includes a read request, and the operation is, The system according to claim 12, further comprising processing the host request to read the target track from the cache and returning the target track on the first channel in response to determining that the target track is in the cache and has the inactive status.

14. The host request includes a read request, and the operation is, In response to determining that the target track has the inactive status, the read request is processed to obtain a lock on the target track in the cache. In response to obtaining the lock, the target track in the cache is read, The read target track is returned to the host via the first channel, The system according to claim 8, further comprising:

15. A method for managing read and write requests from a host to tracks that are cached and stored in a cache, The host receives a host request to access the target track via a first channel to the host, Determining from track status information whether the target track has an active status or an inactive status, wherein the target track has an active status when at least one process currently holds a lock on the target track that prevents access, and the target track has an inactive status when no process holds a lock on the target track that prevents access by other processes. A method comprising, in response to determining that the target track has the active status, returning a failure to the host to cause the host to retransmit the host request on a second channel, wherein the first channel returns the failure with less latency than the second channel.

16. The method according to claim 15, wherein the track status information includes an active bit in the cache control block of the track to indicate the active status or the inactive status of the track, and determining whether the target track has the active status or the inactive status includes determining whether the active bit in the cache control block of the target track indicates the active status or the inactive status.

17. Maintaining an active track data structure that indicates the track in the cache that has an active status, The active bit is set in the cache control block of the track to indicate that the track indicated as active in the active track data structure is active, The method according to claim 16, further comprising:

18. In response to receiving the host request, determine whether the target track is in the cache, and the determination of whether the target track has an active status is performed in response to the determination that the target track is in the cache. In response to determining that the target track is not in the cache, the system returns a failure to the host to cause the host to resend the host request on the second channel, The method according to claim 15, further comprising:

19. The host request includes a read request, and the method is The method according to claim 18, further comprising processing the host request to read the target track from the cache and returning the target track on the first channel in response to determining that the target track is in the cache and has the inactive status.

20. The host request includes a read request, and the method is In response to determining that the target track has the inactive status, the read request is processed to obtain a lock on the target track in the cache. In response to obtaining the lock, the target track in the cache is read, The read target track is returned to the host via the first channel, The method according to claim 15, further comprising:

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