Imaging device

Abstract

To provide an imaging element with a global shutter function that enables noise to be reduced in pixels with low incident light intensity.SOLUTION: The imaging element has a pixel including a photoelectric conversion section and a charge-voltage conversion section. The imaging element includes a voltage holding section provided in correspondence with the pixel. The voltage holding sections corresponding to the respective pixels have different capacities in accordance with the amounts of light incident on the respective photoelectric conversion sections.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This invention relates to an imaging device. [Background technology]

[0002] In recent years, a so-called global electronic shutter has been proposed for CMOS image sensors, which synchronizes the signal charge accumulation period (exposure period) between multiple pixels arranged in different pixel rows. To realize a global electronic shutter, each pixel of the CMOS image sensor has a signal holding unit that temporarily holds the signal, and the signals are accumulated simultaneously across all pixels and then transferred to the signal holding unit all at once.

[0003] The imaging device described in Patent Document 1 enables global electronic shutter operation by using multiple pixels that perform photoelectric conversion and charge-voltage conversion to output voltage signals, and multiple voltage holding units that hold the voltage signals output by each pixel. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2017-108066 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, in the prior art disclosed in the aforementioned patent documents, kTC noise is generated when the voltage signal output from a pixel is held in a voltage holding unit and then read out. The magnitude of kTC noise is proportional to temperature and inversely proportional to capacitance. In particular, for pixels with low incident light levels, the ratio of kTC noise to the voltage signal held in the voltage holding unit becomes large, affecting image quality degradation.

[0006] The objective of the present invention is to reduce noise generated in pixels with low incident light levels in an image sensor equipped with a global shutter function. [Means for solving the problem]

[0007] To achieve the above objective, the image sensor of the present invention comprises a plurality of pixels, each equipped with a photoelectric conversion unit and a charge-voltage conversion unit; a plurality of voltage holding units provided corresponding to the plurality of pixels; and a control unit that allocates the plurality of voltage holding units to the plurality of pixels, wherein the control unit, according to the amount of incident light to each of the plurality of pixels, sets the voltage holding capacitance for holding the voltage signal of pixels with a relatively large amount of incident light to be greater than the voltage holding capacitance for holding the voltage signal of pixels with a relatively small amount of incident light to be greater than small The plurality of voltage holding units are distributed to the plurality of pixels in such a manner. [Effects of the Invention]

[0008] According to the present invention, in an image sensor equipped with a global shutter function, noise generated in pixels with low incident light levels can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] A block diagram showing the configuration of the imaging device according to the embodiment. [Figure 2] A block diagram showing the configuration of the image sensor according to the embodiment. [Figure 3] An equivalent circuit diagram including two unit pixels according to the first embodiment, a voltage holding unit corresponding to the two unit pixels, and a column circuit. [Figure 4] A timing chart of the operation of a unit pixel and a voltage holding unit corresponding to the unit pixel in one frame according to the first embodiment. [Figure 5] An equivalent circuit diagram relating to a second embodiment, including two unit pixels, a voltage holding unit corresponding to the two unit pixels, and a column circuit. [Figure 6] This figure shows the relationship between the combination of signals CSEL1, CSEL2, CSEL3, and CSEL4 and the capacitance ratio CR:CG according to the second embodiment. [Figure 7]A timing chart of the operation of a unit pixel and a voltage holding unit corresponding to the unit pixel in one frame according to the second embodiment. [Figure 8] Flowchart relating to the second embodiment. [Figure 9] This figure illustrates a table of capacitance ratios CR:CG with optical signal ratio as a parameter, according to the second embodiment. [Modes for carrying out the invention]

[0010] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0011] (Example 1) The following describes an image sensor equipped with a global shutter function according to the first embodiment of the present invention, and an imaging device using the image sensor, with reference to Figures 1 to 4.

[0012] The imaging device shown in Figure 1 comprises an optical lens barrel 101, an image sensor 102, a video signal processing unit 103, a compression / decompression unit 104, a control unit 105, a light-emitting unit 106, an operation unit 107, an image display unit 108, and an image recording unit 109.

[0013] The optical lens barrel 101 includes a focus mechanism 1011, which consists of a focus lens and a focus control circuit that collect light from the subject onto the image sensor 102 and adjust the focus. It also includes a zoom mechanism 1012, which consists of a zoom lens and a zoom control circuit that vary the magnification of the optical image, an aperture mechanism 1013 that adjusts the amount of light incident on the image sensor 102, and a shutter mechanism 1014. The focus mechanism 1011, zoom mechanism 1012, aperture mechanism 1013, and shutter mechanism 1014 are driven based on control signals from the control unit 105.

[0014] The image sensor 102 performs imaging operations such as exposure, signal readout, and reset in response to control signals from the control unit 105, and outputs an imaging signal. The image sensor 102 will be described in detail in Figure 2, which will be described later.

[0015] The video signal processing unit 103 receives the image signal output from the image sensor 102 and performs signal processing such as AE processing, white balance adjustment processing, and color correction processing.

[0016] The compression / decompression unit 104 operates under the control of the control unit 105. It compresses and encodes the image signal from the video signal processing unit 103 using a predetermined still image data format such as JPEG (Joint Photographic Coding Experts Group). It also decompresses and decodes the encoded data of the still image supplied by the control unit 105. Furthermore, it may be possible to perform compression / encoding / decompression / decoding of moving images using a format such as MPEG (Moving Picture Experts Group).

[0017] The control unit 105 is a microcontroller composed of components such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory). It comprehensively controls each part of the imaging device by executing programs stored in the ROM or other memory.

[0018] The light-emitting unit 106 is a device that illuminates a subject with light when the AE processing in the signal processing unit 104 determines that the exposure value of the subject is low. Examples include strobe devices using xenon tubes and LED light-emitting devices.

[0019] The operation unit 107 consists of various operation keys such as a shutter release button, levers, dials, and a touch panel, and outputs control signals to the control unit 105 in response to user input operations.

[0020] The image display unit 108 consists of a display device such as an LCD (Liquid Crystal Display) and an interface circuit for it. It generates an image signal for display on the display device from the image signal supplied from the control unit 105, and supplies this signal to the display device to display the image.

[0021] The image recording unit 109 is implemented, for example, as a portable semiconductor voltage holder, optical disc, HDD (Hard Disk Drive), magnetic tape, etc., and receives and stores image data files encoded by the compression / decompression unit 104 from the control unit 105. It also reads specified data based on control signals from the control unit 105 and outputs it to the control unit 105.

[0022] Figure 2 is a block diagram showing an example of the image sensor 102 in this embodiment. The image sensor 102 is composed of a pixel section 200, a voltage holding section 201, a vertical control circuit 206, a horizontal control circuit 207, a timing generator (hereinafter referred to as TG) 208, a vertical output line 209, a column circuit 210, and an output section 211.

[0023] Here, the pixel portion 200 and the voltage holding portion 201 are formed on different semiconductor substrates. Furthermore, the first semiconductor substrate on which the pixel portion 200 is formed and the second semiconductor substrate on which the voltage holding portion is formed are electrically connected and have a stacked structure in which they are stacked on top of each other.

[0024] The pixel section 200 has unit pixels 202 to 205 arranged in a matrix. Each of these unit pixels 202 to 205 is equipped with an optical filter 212 to 215 (not shown). Figure 2 shows that the transmittance of the optical filters in unit pixels 202 to 205 differs depending on whether there is a right-angled hatch, a left-angled hatch, or no hatching.

[0025] In this embodiment, the transmittance of these optical filters is assumed to be optical filter 213 = optical filter 214 > optical filter 212 > optical filter 215. For simplicity of explanation, Figure 2 shows 8x8 unit pixels 202-205 in the pixel section 200, but in practical use, many more pixels are arranged.

[0026] The vertical control circuit 206 controls a row selection switch (not shown) of the voltage holding unit 201, thereby transferring the signals stored in the voltage holding capacitors (not shown) of the voltage holding unit 201 corresponding to the unit pixels 202 to 205 to the column circuit 210.

[0027] The pixel signals held in the voltage holding unit 201 are converted into digital signals in the column circuit 207 and output via the output unit 211. The TG208 sends control signals to the vertical control circuit 206 and the horizontal control circuit 207 to output the pixel signals of each pixel.

[0028] Figure 3 shows the configuration of unit pixels 202 and 203, voltage holding unit 300, and column circuit 301. The same configuration applies to unit pixels 204 and 205, so their explanation is omitted here.

[0029] Each unit pixel 202 consists of a photodiode 302 which is a photoelectric conversion unit, a transfer transistor 303, a floating diffusion (FD) 304 which is a charge-voltage conversion unit, a reset transistor 305, an amplification transistor 306, and an output switch 307.

[0030] Similarly, the unit pixel 203 is composed of a photodiode 308, a transfer transistor 309, an FD310, a reset transistor 311, an amplification transistor 312, and an output switch 313.

[0031] The voltage holding unit 300 is a voltage holding circuit corresponding to unit pixels 202 and 203, and corresponds to the voltage holding unit 201 in Figure 2. The column circuit 301 corresponds to the column circuit 210 in Figure 2.

[0032] The voltage holding unit 300 consists of a switch 314, a switch 315, a first voltage holding capacitor 316, a second voltage holding capacitor 317, a reset transistor 318, an amplification transistor 319, and a row selection switch 320, corresponding to the unit pixels 202. The column circuit 301 includes a subtractor 321 and an AD conversion block 322.

[0033] The voltage holding unit 300 consists of a switch 323, a switch 324, a first voltage holding capacitor 325, a second voltage holding capacitor 326, a reset transistor 327, an amplification transistor 328, and a row selection switch 329, corresponding to the unit pixels 203. The column circuit 301 includes a subtractor 330 and an AD conversion block 331.

[0034] The second voltage-holding capacitors 317 and 326 hold the voltage of FD304 and FD310 after the reset is released (hereinafter referred to as the N signal). The first voltage-holding capacitors 316 and 325 hold the voltage of FD304 and FD310 that has decreased in response to the signal charge of photodiodes 302 and 308 (hereinafter referred to as the S signal).

[0035] Thus, in this embodiment, one voltage holding unit for the N signal and one for the S signal are provided for each unit pixel.

[0036] In this embodiment, unit pixel 202 is provided with an R (red) optical color filter, and unit pixel 203 is provided with a G (green) optical color filter. Since the transmittance of the R optical filter is relatively lower than that of the G optical filter, the amount of incident light to the R pixel is less than the amount of incident light to the G pixel.

[0037] Therefore, in order to reduce kTC noise in R pixels where the amount of incident light is relatively low, the capacitances of the first and second voltage-holding capacitors of the R pixels are made larger than those of the G pixels where the amount of incident light is relatively high.

[0038] Capacitance C of the first voltage holding capacitance 316 SR, the capacitance C of the first voltage holding capacitance 325 SG , the capacitance C of the second voltage holding capacitance 317 NR , the capacitance C of the second voltage holding capacitance 326 NG The relationship of is C SR = C NR = C R C SG = C NG = C G It is assumed that

[0039] And, due to the difference in transmittance depending on the type of optical filter for each pixel described above, C R > C G The capacitance is set so that. For example, C R = 100 [fF], C G = 50 [fF] is set. In this way, the capacitances of the first voltage holding capacitance and the second voltage holding capacitance are configured to be different according to the type of optical filter. Note that, similarly, in the voltage holding units corresponding to the unit pixels 204 and 205, the first voltage holding capacitance and the second voltage holding capacitance are configured to have different capacitances according to the type of each optical filter.

[0040] To the gates of each of the above-described switch transistors, signals TX are supplied to the transfer transistors 303 and 309, signals PRS are supplied to the reset transistors 305 and 311, and signals GS are supplied to the output switches 307 and 313. Also, signals PS are supplied to the switches 314 and 323, signals PN are supplied to the switches 315 and 324, signals MRS are supplied to the reset transistors 318 and 327, and signals SEL are supplied to the row selection switches 320 and 329. The signals supplied to the gates of each switch transistor conduct when Hi and insulate when Lo.

[0041] Figure 4 is a timing chart of the operation in one frame of the unit pixels 202 and 203 and the voltage holding unit 300 corresponding to the unit pixels 202 and 203.

[0042] In section T401, signals PRS and TX become high, resetting photodiodes 302, 308, FD304, and 310. Additionally, signals MRS, PS, and PN become high, resetting the first voltage-holding capacitors 316 and 325, and the second voltage-holding capacitors 317 and 326.

[0043] In section T402, signals PRS and TX become low, completing the reset of photodiodes 302, 308, FD304, and 310, and starting the accumulation of charge in photodiodes 302 and 308. Also, signals PS, PN, and MRS become low, completing the reset of the first voltage-holding capacitors 316 and 325 and the second voltage-holding capacitors 317 and 326.

[0044] At this time, kTC noise is generated as a noise signal accumulated in the first voltage-holding capacitors 316 and 325, and the second voltage-holding capacitors 317 and 326. The magnitude σ of the kTC noise is expressed by the following equation 1, and is inversely proportional to the capacitance C. Here, k is Boltzmann's constant and T is the absolute temperature.

[0045]

number

[0046] The magnitude of the kTC noise generated in the first voltage-holding capacitors 316 and 325, and the second voltage-holding capacitors 317 and 326, respectively, is σ SR , σ SG , σ NR , σ NG Let's assume that the capacitance C mentioned above is the case. SR , C NR , C SG , C NG From the relative magnitudes, kTC noise σ SR , σ SG , σ NR , σ NG The relationship between magnitudes is σ SG =σ NG >σ SR =σ NR This is the result.

[0047] In section T403, signals PN and GS become high, and the N signal is stored in the second voltage-holding capacitors 317 and 326. When signal GS becomes high, the pixel amplification transistors 306 and 212, together with a current source (not shown), form a source follower circuit.

[0048] In section T404, the signal TX becomes high, and the signal charge accumulated in photodiode 302 is transferred to FD304, and the signal charge accumulated in photodiode 308 is transferred to FD310.

[0049] In section T405, the signal TX becomes low, and the transfer of the signal charge accumulated in photodiode 302 to FD304 and the transfer of the signal charge accumulated in photodiode 308 to FD310 are completed. The exposure period is from the start of section T402 to the start of section T404.

[0050] In section T406, signals PS and GS become high, and the S signal is stored in the first voltage holding capacitors 316 and 325.

[0051] In section T407, signals SEL, PS, and PN become Hi, and the signal obtained by subtracting the N signal from the S signal at the unit pixel 202 by the subtractor 321 (hereinafter referred to as the SN signal) is AD converted by the AD conversion block 322 of the column circuit 301.

[0052] Furthermore, the subtractor 330 converts the signal-to-noise ratio signal at the unit pixel 203 using the AD conversion block 331 of the column circuit 301.

[0053] At this time, the kTC noise in the SN signal of unit pixel 202 is σ R , the kTC noise in the SN signal of a unit pixel 203 is σ G These can be expressed in equations 2 and 3, and are each √2 times the value before subtraction.

[0054]

number

[0055]

number

[0056] kTC noise σ in the signal output corresponding to unit pixel 202 R This is the kTC noise σ in the signal output corresponding to unit pixel 203. G Smaller than σ R <σ G This is the result.

[0057] As described above, by varying the capacitance of the voltage-holding capacitance according to the type of optical filter provided for each pixel, it is possible to reduce kTC noise in pixels with low incident light levels in an image sensor equipped with a global shutter function.

[0058] When the optical color filter array is an RGB array, white balance gain is applied to the R pixel signal and B pixel signal under typical sunlight conditions, but even in that case, the degradation of image quality caused by the R pixel signal and B pixel signal can be suppressed.

[0059] In this embodiment, the arrangement of optical color filters shown in Figure 2 was used as an example, but the types and arrangement of optical filters with different transmittances can be arbitrarily set. For example, not only color filters, but also optical filters with the same optical properties but different transmittances may be arranged. In other words, optical filters with different optical properties may be arranged.

[0060] Furthermore, a configuration in which polarizing elements are arranged instead of filter arrays with different transmittances is also acceptable. Moreover, it can be applied to image sensors in which unit pixels have different photodiode sizes, microlens focusing rates, and exposure times for each photodiode, instead of filter arrays with different transmittances.

[0061] (Example 2) The following describes an image sensor equipped with a global shutter function and an imaging device using the image sensor, according to a second embodiment of the present invention, with reference to Figures 1, 2, and 5-9. Figures 1 and 2 are the same as in Embodiment 1, and therefore their explanation is omitted here.

[0062] Figure 5 shows the configuration of unit pixels 202 and 203, voltage holding unit 500, column circuit 301, and voltage holding distribution signal circuit 538. Note that unit pixels 202 and 203 and column circuit 301 are the same as in Example 1, so their explanation is omitted here. Furthermore, the explanation of unit pixels 204 and 205 is also omitted.

[0063] The voltage holding unit 500 is a voltage holding circuit corresponding to unit pixels 202 and 203, and corresponds to the voltage holding unit 201 in Figure 2. The column circuit 301 has a configuration corresponding to the column circuit 210 in Figure 2.

[0064] The voltage holding unit 500 can allocate the voltage holding capacitance between adjacent unit pixels. In this embodiment, a configuration in which the voltage holding capacitance of the voltage holding unit 500 is allocated between unit pixels 202 and 203 will be described.

[0065] The voltage holding unit 500 corresponding to unit pixels 202 and 203 includes switches 501 to 504. It also includes first voltage holding capacitors 505 to 508, first voltage holding distribution switches (R) 513 to 516, and first voltage holding distribution switches (G) 517 to 520.

[0066] Furthermore, it is equipped with second voltage holding capacitors 509-512, second voltage holding distribution switches (R) 521-524, and second voltage holding distribution switches (G) 525-528. It also includes a reset transistor 529, amplification transistors 530-533, and row selection switches 534-537.

[0067] The gates of the aforementioned switch transistors are supplied with signals PS to switches 501 and 502, PN to switches 503 and 504, MRS to reset transistor 529, and SEL to row selection switches 532 to 535. The signals supplied to the gates of each switch transistor conduct when high and isolate when low.

[0068] Capacitance C of the first voltage holding capacity 505 S1 , the capacitance C of the first voltage holding capacity 506 S2 , the capacitance C of the first voltage holding capacity 507 S3 , the capacitance C of the first voltage holding capacity 508 S4 The relationship is set as follows. Also, the capacitance C of the second voltage holding capacitance 509 N1 , second voltage holding capacitance 510 capacitance C N2 , the capacitance C of the second voltage holding capacitance 511 N3 , the capacitance C of the second voltage holding capacitance 512 N4 The relationship is set as follows: C S1 =C S2 =C S3 =C S4 =C N1 =C N2 =C N3 =C N4 It will be set to be as follows.

[0069] The voltage holding distribution signal circuit 538 is located outside the voltage holding unit 500 and includes NOT circuits 539 to 542. Signals CSEL1, CSEL2, CSEL3, and CSEL4 are input from the control unit 105, and these signals specify the allocation of voltage holding.

[0070] For example, when the signal CSEL1 is Hi, the first voltage holding distribution switch (R) 513 and the first voltage holding distribution switch (R) 521 are isolated, and the first voltage holding distribution switch (G) 517 and the first voltage holding distribution switch (G) 525 conduct. As a result, the first voltage holding capacitor 505 is connected to switch 502, and the second voltage holding capacitor 509 is connected to switch 504, thereby associating each with the unit pixel 203.

[0071] Conversely, when signal CSEL1 is Lo, the first voltage-holding capacitor 505 and the second voltage-holding capacitor 509 are associated with unit pixel 202. Similarly, for signals CSEL2, CSEL3, and CSEL4, the first voltage-holding capacitors 506-508 and the second voltage-holding capacitors 510-512 are associated with unit pixel 202 or unit pixel 203 depending on these signals.

[0072] In this embodiment, the total capacitance of the first voltage-holding capacitors (hereinafter collectively referred to as the first voltage-holding capacitors R) connected to the switch 501 is C SR The total capacitance of the first voltage-holding capacitors (hereinafter collectively referred to as the first voltage-holding capacitors G) connected to switch 502 is C SG The total capacitance of the second voltage-holding capacitors (hereinafter collectively referred to as the second voltage-holding capacitor R) connected to the N signal switch 503 is C. NR The total capacitance of the second voltage-holding capacitors (hereinafter collectively referred to as the second voltage-holding capacitor G) connected to the N signal switch 504 is C NG Let's assume that C SR =C NR =C R , C SG =C NG =C G It is set up to be that way.

[0073] Figure 6 shows the signals CSEL1, CSEL2, CSEL3, and CSEL4 and the capacitance ratio C. R :C G This diagram shows an example of the correspondence between the two. The first voltage-holding capacitor R stores the S signal of FD304, and the first voltage-holding capacitor G stores the S signal of FD310. The second voltage-holding capacitor R stores the N signal of FD304, and the second voltage-holding capacitor G stores the N signal of FD310.

[0074] Figure 7 is a timing chart of the operation of unit pixels 202 and 203 and the voltage holding unit 500 corresponding to unit pixels 202 and 203 in one frame. Note that the capacitance ratio C is used in this timing chart. R :C G We will now explain the case where the capacitance ratio C is 3:1. R :CG The process for determining this will be described separately later.

[0075] Before the start of section T701, signals CSEL1, CSEL2, and CSEL3 are low, and signal CSEL4 is high, resulting in a capacitance ratio C R :C G The ratio is set to 3:1. As a result, the first voltage holding capacities 505-507 become the first voltage holding capacities R, the first voltage holding capacities 508 become the first voltage holding capacities G, the second voltage holding capacities 509-511 become the second voltage holding capacities R, and the second voltage holding capacities 512 become the second voltage holding capacities G.

[0076] In section T701, signals PRS and TX become high, and photodiodes 302, 308, FD304, and 310 are reset. Additionally, signals MRS, PS, and PN become high, resetting the first voltage-holding capacitor R, the first voltage-holding capacitor G, the second voltage-holding capacitor R, and the second voltage-holding capacitor G.

[0077] In section T702, signals PRS and TX become low, and the reset of photodiodes 302, 308, FD304, and 310 is completed. Also, accumulation begins from the start of section T702.

[0078] Furthermore, in section T702, signals PS, PN, and MRS become low, and the reset of the first voltage-holding capacitor R, the first voltage-holding capacitor G, the second voltage-holding capacitor R, and the second voltage-holding capacitor G is completed.

[0079] At this time, kTC noise is generated as a noise signal accumulated in the first voltage-holding capacitor R, the first voltage-holding capacitor G, the second voltage-holding capacitor R, and the second voltage-holding capacitor G, similar to Example 1.

[0080] The magnitude of the kTC noise generated in the first voltage-holding capacitor R, the first voltage-holding capacitor G, the second voltage-holding capacitor R, and the second voltage-holding capacitor G is σ, respectively. SR , σ SG , σ NR , σ NG Let's assume that the capacitance C mentioned above is the case. SR , CNR , C SG , C NG From the relative magnitudes, kTC noise σ SR , σ SG , σ NR , σ NG The relationship between magnitudes is σ SG =σ NG >σ SR =σ NR This is the result.

[0081] In section T703, signals PN and GS become high, and the N signal is stored in the second voltage-holding capacitors R and G. When signal GS becomes high, the pixel amplification transistors 306 and 312, together with a current source (not shown), form a source follower circuit.

[0082] In section T704, the signal TX becomes high, and the signal charge accumulated in photodiode 302 is transferred to FD304, and the signal charge accumulated in photodiode 308 is transferred to FD310.

[0083] In section T705, the signal TX becomes low, and the transfer of the signal charge accumulated in photodiode 302 to FD304 and the transfer of the signal charge accumulated in photodiode 308 to FD310 are completed. The exposure time is from the start of section T702 to the start of section T704.

[0084] In section T706, signals PS and GS become high, and the S signal is stored in the first voltage-holding capacitors R and G.

[0085] In section T707, the SEL signal becomes Hi, and the SN signal is converted by the subtractor 321 and then by the AD conversion block 322 of the column circuit 301 (hereinafter, the converted signal will be referred to as the R optical signal).

[0086] Furthermore, the subtractor 330 converts the signal-to-noise ratio (S / N) signal at the unit pixel 203 using the AD conversion block 331 of the column circuit 301 (hereinafter, the converted signal will be referred to as the G optical signal).

[0087] At this time, let the kTC noise in the S-N signal of the unit pixel 202 be σ R and the kTC noise in the S-N signal of the unit pixel 203 be σ G Then, similar to Example 1, Equations 2 and 3 are obtained, and each becomes √2 times before subtraction.

[0088] From this, σ R < σ G and the kTC noise in the signal output corresponding to the unit pixel 202 is the capacitance ratio C R : C G is lower than that of the unit pixel 203 according to. That is, the magnitudes of the kTC noise in the unit pixel 202 and the signal output corresponding to the unit pixel 202 can be changed by the signals CSEL1, CSEL2, CSEL3, and CSEL4.

[0089] FIG. 8 shows a flowchart of detecting the amount of light incident on the unit pixel 202 and the unit pixel 203 in the first shooting, and assigning a voltage holding capacitance according to the amount of incident light for each pixel in the first shooting and then shooting in the second shooting.

[0090] When shooting is started, predetermined shooting conditions are set in step S801. <www.

[0091] In step S802, the control unit 105 sets the signals CSEL1 and CSEL2 to Lo and the signals CSEL3 and CSEL4 to Hi, thereby setting the capacitance ratio C R : C G to 2:2.

[0092] In step S803, the imaging device 102 is driven under the control of the control unit 105 under the shooting conditions set in step S801, and shooting is performed with the capacitance ratio C R : C G set to 2:2 in accordance with the timing chart described above.

[0093] In step S804, the R optical signal and the G optical signal, which are the signals output from the unit pixel 202 and the unit pixel 203 in step S803, are compared by the video signal processing unit 103, and the capacitance ratio C R :C G is determined. When the value obtained by dividing the R optical signal by the G optical signal is defined as the RG optical signal ratio P, the video signal processing unit 103 determines the capacitance ratio C R :C G and the signals CSEL1, CSEL2, CSEL3, and CSEL4 according to the magnitude of the RG optical signal ratio P.

[0094] FIG. 9 is a diagram for explaining a table of the capacitance ratio C R :C G with the optical signal ratio as a parameter. A table as shown in FIG. 9 is stored in the video signal processing unit 103 in advance, and the capacitance ratio C R :C G and the signals CSEL1, CSEL2, CSEL3, and CSEL4 may be calculated from the RG optical signal ratio P using the stored table.

[0095] In step S805, the signals CSEL1, CSEL2, CSEL3, and CSEL4 determined in step S804 are set by the control unit 105.

[0096] <000045i>In step S806, the imaging element 102 is driven under the control of the control unit 105 under the imaging conditions set in step S801, and imaging is performed at the capacitance ratio C R :C G set in step S805 in accordance with the above-described timing chart.

[0097] As described above, by allocating the voltage holding capacitance according to the incident light amount to each of a plurality of adjacent pixels, in an imaging element equipped with a global shutter function, kTC noise can be reduced in pixels with a small incident light amount.

[0098] When the optical color filter array is an RGB array, white balance gain is applied to the R pixel signal and B pixel signal under typical sunlight conditions, but even in that case, the degradation of image quality caused by the R pixel signal and B pixel signal can be suppressed.

[0099] In this embodiment, the arrangement of optical color filters shown in Figure 2 was used as an example, but the types and arrangement of optical filters with different transmittances can be arbitrarily set. For example, not only color filters, but also optical filters with the same optical properties but different transmittances may be arranged. In other words, optical filters with different optical properties may be arranged.

[0100] Furthermore, a configuration in which polarizing elements are arranged instead of filter arrays with different transmittances is also acceptable. Moreover, it can be applied to image sensors in which unit pixels exist with different photodiode sizes (light-receiving areas), microlens light-gathering efficiency, and exposure times for each photodiode, instead of filter arrays with different transmittances.

[0101] Furthermore, in this embodiment, the capacitance ratio C R :C G To calculate the capacitance ratio C, we are taking a single frame of footage. R :C G This may be determined according to settings such as white balance and shooting mode set by the user or the control unit 105.

[0102] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of its gist.

Claims

1. Multiple pixels, each equipped with a photoelectric conversion unit and a charge-voltage conversion unit, Multiple voltage holding units provided corresponding to the multiple pixels, A control unit that assigns the plurality of voltage holding units to the plurality of pixels, It has, The control unit is characterized by allocating the plurality of voltage holding units to the plurality of pixels such that, according to the amount of incident light to each of the plurality of pixels, the voltage holding capacitance for holding the voltage signal of a pixel with a relatively large amount of incident light is smaller than the voltage holding capacitance for holding the voltage signal of a pixel with a relatively small amount of incident light.

2. The image sensor according to claim 1, characterized in that each of the plurality of pixels comprises an optical filter with different optical characteristics, a photoelectric conversion unit with different light-receiving areas, or a microlens with different light-gathering efficiency.

3. The image sensor according to claim 1 or 2, characterized in that a first semiconductor substrate on which the plurality of pixels are formed and a second semiconductor substrate on which the plurality of voltage holding portions are formed are stacked on top of each other.

4. An image sensor according to any one of claims 1 to 3, A signal processing unit that performs predetermined signal processing on the image signal output from the image sensor, An imaging device characterized by having the following features.

Images