Sensor device

Abstract

A sensor device (1) according to the present disclosure comprising: a Peltier element (20); a sensor element (10) that is thermally connected to a cooling surface (21a) of the Peltier element (20); and a ceramic package substrate (40) that is thermally connected to a heat dissipation surface (23a) of the Peltier element (20) and accommodates the Peltier element (20) and the sensor element (10).

Description

Technical Field

[0001] The present disclosure relates to a sensor device.

Background Art

[0002] As a means for cooling a sensor element such as a solid-state imaging device, a hermetically sealed package incorporating a Peltier element is known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure proposes a sensor device that can be multi-pixelated.

Means for Solving the Problems

[0005] According to the present disclosure, a sensor device is provided. The sensor device includes a Peltier element, a sensor element thermally connected to the cooling surface of the Peltier element, and a ceramic package substrate thermally connected to the heat dissipation surface of the Peltier element and housing the Peltier element and the sensor element.

Brief Description of the Drawings

[0006] [Figure 1] It is a diagram showing a schematic configuration of a sensor element according to an embodiment of the present disclosure. [Figure 2] It is a diagram showing a pixel circuit of each pixel of a sensor element according to an embodiment of the present disclosure. [Figure 3] It is a cross-sectional view showing the structure of a pixel according to an embodiment of the present disclosure. [Figure 4] It is a plan view of a pixel array region showing the pixel arrangement of charge release pixels. [Figure 5] This figure shows a schematic cross-sectional configuration of a sensor element according to the embodiment of this disclosure. [Figure 6] This is a cross-sectional view showing an example configuration of a sensor device according to the present disclosure. [Figure 7] This is a bottom view showing an example of the configuration of a sensor device according to the present disclosure. [Figure 8] This is a top view showing an example of the configuration of a cooling substrate for a Peltier element according to the present disclosure. [Figure 9] This is a top view showing an example of the configuration of a heat dissipation substrate for a Peltier element according to the present disclosure. [Figure 10] This is a top view showing an example of the configuration of a Peltier element according to the present disclosure. [Figure 11] This figure shows the wavelength dependence of the transmittance of the window members in the examples and reference examples. [Figure 12] This is a cross-sectional view showing an example of the configuration of a sensor device according to Modification 1 of the Embodiment of this Disclosure. [Figure 13] This is a cross-sectional view showing an example of the configuration of a sensor device according to a modified example 2 of the embodiment of this disclosure. [Figure 14] This is a bottom view showing an example of the configuration of a sensor device according to a modified example 3 of the embodiment of this disclosure. [Figure 15A] This figure shows the substrate configuration of a sensor element in another example according to the embodiments of this disclosure. [Figure 15B] This figure shows the substrate configuration of a sensor element in another example according to the embodiments of this disclosure. [Figure 16] This figure shows an example of a circuit configuration of a laminated substrate for a sensor element, which is another example according to the embodiments of this disclosure. [Figure 17] This figure shows an equivalent circuit of a pixel of a sensor element in another example according to the embodiments of this disclosure. [Figure 18] This is a plan view of the pixel array region showing the pixel arrangement of charge-emitting pixels according to Modification 4. [Figure 19] This is a cross-sectional view showing the structure of a pixel according to a modified example 4 of the embodiment of this disclosure. [Figure 20]It is a cross-sectional view showing a configuration example of a sensor device according to Modification 5 of the embodiment of the present disclosure. [Figure 21] It is a cross-sectional view showing a configuration example of a sensor device according to Modification 6 of the embodiment of the present disclosure. [Figure 22] It is a cross-sectional view showing a configuration example of a sensor device according to Modification 7 of the embodiment of the present disclosure. [Figure 23] It is a cross-sectional view showing a configuration example of a sensor device according to Modification 8 of the embodiment of the present disclosure. [Figure 24] It is a cross-sectional view showing a configuration example of a sensor device according to Modification 9 of the embodiment of the present disclosure. [Figure 25] It is a cross-sectional view showing a configuration example of a sensor device according to Modification 10 of the embodiment of the present disclosure.

Mode for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present disclosure will be described in detail based on the drawings. In each of the following embodiments, the same parts are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] As a means for cooling a sensor element such as a solid-state imaging device, a hermetically sealed package incorporating a Peltier element is known. In such a hermetically sealed package, a metal package substrate is used as a package substrate for housing the sensor element and the Peltier element.

[0009] In addition, in order to prevent short-circuiting between external terminals that output signals from the sensor element, an insulating seal member is provided between the external terminals and the package substrate.

[0010] However, in the above technology, since a space for providing a seal member for the external terminals is required, it is difficult to reduce the distance between adjacent external terminals, so it has been difficult to arrange a plurality of external terminals on the package substrate at a high density.

[0011] In other words, with the above technology, even if the sensor element has multiple pixels, it is difficult to provide the necessary number of external terminals to output signals from all pixels, making it difficult to increase the number of pixels in the sensor device.

[0012] Therefore, there is a need for technology that can overcome the aforementioned problems and enable the use of multiple pixels in sensor devices.

[0013] [Sensor element configuration] First, the configuration of the sensor element 10 according to the embodiment will be described with reference to Figures 1 to 5. Figure 1 is a diagram showing the schematic configuration of the sensor element 10 according to the embodiment of this disclosure.

[0014] The sensor element 10 in Figure 1 is constructed on a semiconductor substrate 112 made of, for example, single-crystal silicon (Si) as the semiconductor, and has a pixel array region 103 in which pixels 102 are arranged in a matrix in two dimensions, and a peripheral circuit region 161 (see Figure 4) around it. The peripheral circuit region 161 includes a vertical drive circuit 104, a column signal processing circuit 105, a horizontal drive circuit 106, an output circuit 107, a control circuit 108, and the like.

[0015] Pixel 102 comprises a photoelectric conversion unit made of a semiconductor thin film and a plurality of pixel transistors. The plurality of pixel transistors are composed of, for example, three MOS transistors: a reset transistor, an amplification transistor, and a selection transistor.

[0016] The control circuit 108 receives an input clock and data that commands the operating mode, and outputs data such as internal information of the sensor element 10. In other words, based on the vertical synchronization signal, horizontal synchronization signal, and master clock, the control circuit 108 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 104, column signal processing circuit 105, and horizontal drive circuit 106.

[0017] The control circuit 108 then outputs the generated clock signal and control signal to the vertical drive circuit 104, the column signal processing circuit 105, and the horizontal drive circuit 106, etc.

[0018] The vertical drive circuit 104 is configured, for example, by a shift register, which selects a predetermined pixel drive wiring 110, supplies pulses to the selected pixel drive wiring 110 to drive the pixels 102, and drives the pixels 102 row by row.

[0019] In other words, the vertical drive circuit 104 sequentially selects and scans each pixel 102 of the pixel array region 103 in the vertical direction row by row. The vertical drive circuit 104 then supplies the pixel signal, based on the signal charge generated in the photoelectric conversion section of each pixel 102 according to the amount of light received, to the column signal processing circuit 105 through the vertical signal line 109.

[0020] The column signal processing circuit 105 is located for each column of pixels 102 and performs signal processing such as noise reduction on the signals output from one row of pixels 102 for each column. For example, the column signal processing circuit 105 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion to remove pixel-specific fixed pattern noise.

[0021] The horizontal drive circuit 106 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 105 in order, causing each of the column signal processing circuits 105 to output a pixel signal to the horizontal signal line 111.

[0022] The output circuit 107 processes the signals sequentially supplied from each of the column signal processing circuits 105 through the horizontal signal line 111 and outputs them. The output circuit 107 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 113 exchanges signals with the outside.

[0023] The sensor element 10 configured as described above is a CMOS image sensor called a column AD type, in which column signal processing circuits 105 that perform CDS processing and AD conversion processing are arranged in columns.

[0024] Figure 2 is a diagram showing the pixel circuit of each pixel of the sensor element 10 according to an embodiment of the present disclosure. Each pixel 102 has a photoelectric conversion unit 121, a capacitive element 122, a reset transistor 123, an amplification transistor 124, and a selection transistor 125.

[0025] The photoelectric conversion unit 121 consists of a semiconductor thin film made of a compound semiconductor such as InGaAs, and generates an electric charge (signal charge) corresponding to the amount of light received. A predetermined bias electric charge Va is applied to the photoelectric conversion unit 121.

[0026] The capacitive element 122 stores the charge generated in the photoelectric conversion unit 121. The capacitive element 122 can be configured to include, for example, at least one of the following: a pn junction capacitor, a MOS capacitor, or a wiring capacitor.

[0027] When the reset transistor 123 is turned on by the reset signal RST, the charge stored in the capacitive element 122 is discharged to the source (ground), thereby resetting the potential of the capacitive element 122.

[0028] The amplifying transistor 124 outputs a pixel signal corresponding to the storage potential of the capacitive element 122. In other words, the amplifying transistor 124 forms a source follower circuit with a load MOS (not shown) which is a constant current source connected via the vertical signal line 109.

[0029] As a result, a pixel signal indicating a level corresponding to the charge stored in the capacitive element 122 is output from the amplification transistor 124 to the column signal processing circuit 105 (see Figure 1) via the selection transistor 125.

[0030] The selection transistor 125 is turned on when pixel 102 is selected by the selection signal SEL, and outputs the pixel signal of pixel 102 to the column signal processing circuit 105 via the vertical signal line 109. The signal lines through which the transfer signal TRX, the selection signal SEL, and the reset signal RST are transmitted correspond to the pixel drive wiring 110 in Figure 1.

[0031] Figure 3 is a cross-sectional view showing the structure of a pixel 102 according to an embodiment of this disclosure. As will be described in detail later, in Figure 3, each pixel 102 in the pixel array region 103 is divided into a normal pixel 102A and a charge-emitting pixel 102B depending on the control of the reset transistor 123.

[0032] On the other hand, since the pixel structure of the normal pixel 102A and the charge-emitting pixel 102B are basically the same, they may be simply referred to as pixel 102 below. Note that the charge-emitting pixel 102B is located on the outermost edge of the pixel array region 103 (see Figure 1).

[0033] The readout circuit for each pixel 102, consisting of a capacitive element 122, a reset transistor 123, an amplification transistor 124, and a selection transistor 125, as described in Figure 2, is formed for each pixel 102 on a semiconductor substrate 112 made of a single-crystal material such as single-crystal silicon.

[0034] Note that in Figure 3, the symbols for the capacitive element 122, reset transistor 123, amplification transistor 124, and selection transistor 125 formed on the semiconductor substrate 112 are omitted.

[0035] On the upper side of the semiconductor substrate 112, which is the light incident side, an N-type semiconductor thin film 141, which will serve as the photoelectric conversion section 121, is formed across the entire surface of the pixel array region 103. The N-type semiconductor thin film 141 can be made of InGaP, InAlP, InGaAs, InAlAs, or a compound semiconductor with a chalcopyrite structure.

[0036] Chalcopyrite compound semiconductors are materials that exhibit a high light absorption coefficient and high sensitivity over a wide wavelength range, and are therefore preferably used as N-type semiconductor thin films 141 for photoelectric conversion.

[0037] Compound semiconductors with such chalcopyrite structures are composed of elements surrounding Group IV elements, such as Cu, Al, Ga, In, S, and Se, with examples including CuGaInS mixed crystals, CuAlGaInS mixed crystals, and CuAlGaInSSe mixed crystals.

[0038] Furthermore, in addition to the compound semiconductors mentioned above, amorphous silicon, germanium (Ge), quantum dot photoelectric conversion films, organic photoelectric conversion films, and other materials can also be used as the material for the N-type semiconductor thin film 141. In this disclosure, an InGaAs compound semiconductor is used as the N-type semiconductor thin film 141.

[0039] On the underside of the N-type semiconductor thin film 141, which is on the semiconductor substrate 112 side, a high-density P-type layer 142 constituting the pixel electrode is formed for each pixel 102. Between the high-density P-type layers 142 formed for each pixel 102, an N-type layer 143 is formed, for example, of a compound semiconductor such as InP, to serve as a pixel isolation region that separates each pixel 102. In addition to functioning as a pixel isolation region, this N-type layer 143 also has the role of preventing dark current.

[0040] On the other hand, on the upper side of the N-type semiconductor thin film 141, which is the light incident side, an N-type layer 144 is formed using a compound semiconductor such as InP, which is used as a pixel separation region, resulting in a higher density N-type layer 144 than that of the N-type semiconductor thin film 141.

[0041] This high-concentration N-type layer 144 functions as a barrier layer that prevents the backflow of charge generated in the N-type semiconductor thin film 141. For the material of the high-concentration N-type layer 144, compound semiconductors such as InP, InGaAs, and InAlAs can be used.

[0042] An anti-reflective film 145 is formed on top of a high-concentration N-type layer 144 that acts as a barrier layer. For example, the anti-reflective film 145 can be made from materials such as silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or titanium oxide (TiO2).

[0043] Either the high-concentration N-type layer 144 or the anti-reflective film 145 also functions as the upper electrode of the electrodes that sandwich the N-type semiconductor thin film 141 from above and below, and a predetermined voltage Va is applied to the high-concentration N-type layer 144 or the anti-reflective film 145 as the upper electrode.

[0044] A color filter 146 and an on-chip lens 147 are further formed on the anti-reflective coating 145. The color filter 146 is a filter that transmits light (wavelength light) of either R (red), G (green), or B (blue), and is arranged, for example, in a so-called Bayer array in the pixel array region 103.

[0045] Below the high-density P-type layer 142 that constitutes the pixel electrode and the N-type layer 143 that serves as the pixel isolation region, a passivation layer 151 and an insulating layer 152 are formed. The connecting electrodes 153A and 153B and the bump electrode 154 are formed to penetrate the passivation layer 151 and the insulating layer 152.

[0046] The connecting electrodes 153A and 153B and the bump electrode 154 electrically connect the high-density P-type layer 142 that constitutes the pixel electrode and the capacitive element 122 that stores charge.

[0047] The normal pixel 102A and the charge-emitting pixel 102B are configured as described above and have the same pixel structure. However, the control method of the reset transistor 123 differs between the normal pixel 102A and the charge-emitting pixel 102B.

[0048] In a normal pixel 102A, the reset transistor 123 is switched on and off based on the reset signal RST, depending on the charge generation period (light reception period) by the photoelectric conversion unit 121 and the reset period of the potential of the capacitive element 122 before the start of light reception. On the other hand, in a charge emission pixel 102B, the reset transistor 123 is controlled to be always on.

[0049] As a result, the charge generated in the photoelectric conversion unit 121 is discharged to ground, and a constant voltage Va is always applied to the charge emission pixel 102B.

[0050] Figure 4 is a plan view of the pixel array region 103 showing the pixel arrangement of the charge-emitting pixels 102B. The pixel array region 103 is located inside the peripheral circuit region 161, where the vertical drive circuit 104 and the column signal processing circuit 105 are formed. The outermost row and column of the pixel array region 103 are designated as the charge-emitting region 162, where the charge-emitting pixels 102B are located.

[0051] The charge emission region 162 may consist of multiple rows and columns, including at least the outermost row and column of the rectangular pixel array region 103.

[0052] As shown in Figure 3, pixels 102 located in the outermost columns and rows of each side of the rectangular pixel array region 103 are prone to generating dark current due to the influence of the processed interface (processed end face) of the photoelectric conversion unit 121, which is a compound semiconductor.

[0053] In particular, if the readout circuit formed on the semiconductor substrate 112 is a source follower type circuit, the potential difference of the pixel decreases as charge accumulates, causing the dark current component to bloom and successively affect neighboring pixels.

[0054] Therefore, in this embodiment, the pixels 102 located in the outermost columns and rows of each side of the rectangular pixel array region 103 are defined as charge-emitting pixels 102B, which are controlled so that the reset transistor 123 is always on.

[0055] This concentrates and discharges the charge gushing from the processed end face (processing interface) of the N-type semiconductor thin film 141, which is the photoelectric conversion unit 121, into the charge emission pixel 102B. This prevents the inflow of charge into the normal pixels 102A inside the charge emission region 162.

[0056] As described above, according to the embodiment, it is possible to suppress image quality degradation caused by charge outflow from the processed interface of the N-type semiconductor thin film 141.

[0057] Figure 5 shows a schematic cross-sectional configuration of a sensor element 10 according to an embodiment of this disclosure. The sensor element 10 is applied to infrared sensors and the like using compound semiconductor materials such as III-V semiconductors.

[0058] The sensor element 10 has a photoelectric conversion function for light with wavelengths ranging from the visible region (e.g., 380 nm to less than 780 nm) to the short infrared region (e.g., 780 nm to less than 2500 nm). This sensor element 10 is provided with, for example, a plurality of light-receiving unit regions (pixels 102) arranged in a two-dimensional manner. Figure 5 shows the cross-sectional configuration of a portion corresponding to three pixels 102.

[0059] The sensor element 10 has a laminated structure of an element substrate 180 and a circuit board 190. One side of the element substrate 180 is the light incident surface (light incident surface S1), and the side opposite to the light incident surface S1 (the other side) is the bonding surface with the circuit board 190 (bonding surface S2).

[0060] The element substrate 180 has, in order from the position closest to the circuit board 190, a wiring layer 180W including the first electrode 181, a semiconductor layer 180S, a second electrode 185, and a passivation film 186.

[0061] The surface of the semiconductor layer 180S facing the wiring layer 180W and the end surface (side surface) are covered with an insulating film 187. The circuit board 190 has a wiring layer 192W that is in contact with the bonding surface S2 of the element substrate 180, and a support substrate 191 that faces the element substrate 180 with the wiring layer 192W in between.

[0062] An effective pixel region, R1, is provided in the central part of the element substrate 180, and a semiconductor layer 180S is arranged in this element region R1. In other words, the region on which the semiconductor layer 180S is provided is the element region R1.

[0063] Outside the element region R1, a peripheral region R2 is provided that surrounds the element region R1. In the peripheral region R2 of the element substrate 180, an embedded layer 188 is provided together with an insulating film 187. In the sensor element 10, light is incident on the semiconductor layer 180S from the light incident surface S1 of the element substrate 180 via the passivation film 186, the second electrode 185, and the second contact layer 184.

[0064] The signal charge converted photoelectrically in the semiconductor layer 180S moves through the wiring layer 180W and is read out on the circuit board 190. The configuration of each part is described below.

[0065] The wiring layer 180W is provided across the element region R1 and the peripheral region R2, and has a bonding surface S2 with the circuit board 190. In the sensor element 10, this bonding surface S2 of the element board 180 is provided in the element region R1 and the peripheral region R2, and for example, the bonding surface S2 of the element region R1 and the bonding surface S2 of the peripheral region R2 form the same plane.

[0066] As will be described later, in the sensor element 10, the bonding surface S2 of the surrounding region R2 is formed by providing the embedded layer 188.

[0067] The wiring layer 180W has, for example, a first electrode 181 and contact electrodes 189EA and 189EB in interlayer insulating films 189A and 189B. For example, the interlayer insulating film 189B is placed on the circuit board 190 side and the interlayer insulating film 189A is placed on the first contact layer 182 side, and these interlayer insulating films 189A and 189B are laminated together.

[0068] The interlayer insulating films 189A and 189B are composed of, for example, an inorganic insulating material. Examples of such inorganic insulating materials include silicon nitride, aluminum oxide, silicon dioxide (SiO2), and hafnium oxide. The interlayer insulating films 189A and 189B may be composed of the same inorganic insulating material.

[0069] The first electrode 181 is an electrode (anode) to which a voltage is supplied for reading out the signal charge (hole or electron; for convenience, the signal charge will be described as a hole) generated in the photoelectric conversion layer 183, and is provided in the element region R1 for each pixel 102.

[0070] The first electrode 181 provided in the wiring layer 180W is in contact with the semiconductor layer 180S (more specifically, the first contact layer 182 described later) via connection holes in the interlayer insulating film 189A and the insulating film 187. Adjacent first electrodes 181 are electrically isolated by the interlayer insulating film 189B.

[0071] The first electrode 181 is composed of, for example, one of the following elements: titanium, tungsten, titanium nitride (TiN), platinum, gold, germanium, palladium, zinc, nickel, and aluminum, or an alloy containing at least one of these elements.

[0072] The first electrode 181 may be a single film of such constituent materials, or it may be a multilayer film combining two or more materials. For example, the first electrode 181 is composed of a multilayer film of titanium and tungsten.

[0073] The contact electrodes 189EA are for electrically connecting the first electrode 181 and the circuit board 190, and are provided in the element region R1 for each pixel 102. Adjacent contact electrodes 189EA are electrically isolated by the interlayer insulating film 189B.

[0074] The contact electrode 189EB is for electrically connecting the second electrode 185 to the wiring of the circuit board 190 (wiring 192CB described later) and is located in the peripheral region R2. This contact electrode 189EB is formed, for example, in the same process as the contact electrode 189EA. The contact electrodes 189EA and 189EB are made of, for example, copper (Cu) pads and are exposed on the bonding surface S2.

[0075] The semiconductor layer 180S includes, for example, a first contact layer 182, a photoelectric conversion layer 183, and a second contact layer 184, starting from a position close to the wiring layer 180W. The first contact layer 182, the photoelectric conversion layer 183, and the second contact layer 184 have the same planar shape as each other, and their respective end faces are located in the same position in a plan view.

[0076] The first contact layer 182 is provided, for example, in common to all pixels 102 and is located between the insulating film 187 and the photoelectric conversion layer 183. The first contact layer 182 is for electrically isolating adjacent pixels 102, and the first contact layer 182 is provided with, for example, a plurality of diffusion regions 182A.

[0077] By using a compound semiconductor material with a band gap larger than that of the compound semiconductor material constituting the photoelectric conversion layer 183 for the first contact layer 182, it is possible to suppress dark current. For example, N-type InP can be used for the first contact layer 182.

[0078] The diffusion regions 182A provided in the first contact layer 182 are spaced apart from each other. A diffusion region 182A is provided for each pixel 102, and a first electrode 181 is connected to each diffusion region 182A.

[0079] The diffusion region 182A is for reading out the signal charge generated in the photoelectric conversion layer 183 for each pixel 102, and contains, for example, p-type impurities. Examples of p-type impurities include Zn.

[0080] In this way, a pn junction interface is formed between the diffusion region 182A and the first contact layer 182 other than the diffusion region 182A, so that adjacent pixels 102 are electrically isolated. The diffusion region 182A is provided, for example, in the thickness direction of the first contact layer 182, and also in a part of the thickness direction of the photoelectric conversion layer 183.

[0081] The photoelectric conversion layer 183 between the first electrode 181 and the second electrode 185, more specifically between the first contact layer 182 and the second contact layer 184, is provided in common to all pixels 102, for example.

[0082] This photoelectric conversion layer 183 absorbs light of a predetermined wavelength to generate a signal charge, and is composed of a compound semiconductor material such as a type i III-V semiconductor. Examples of compound semiconductor materials that constitute the photoelectric conversion layer 183 include InGaAs, InAsSb, InAs, InSb, and HgCdTe.

[0083] Alternatively, the photoelectric conversion layer 183 may be constructed using Ge. In the photoelectric conversion layer 183, for example, photoelectric conversion of light with wavelengths from the visible region to the short infrared region is performed.

[0084] The second contact layer 184 is provided, for example, in common to all pixels 102. This second contact layer 184 is provided between the photoelectric conversion layer 183 and the second electrode 185 and is in contact with them.

[0085] The second contact layer 184 is a region where charge discharged from the second electrode 185 moves, and is composed of a compound semiconductor containing, for example, N-type impurities. For example, N-type InP can be used for the second contact layer 184.

[0086] The second electrode 185 is provided, for example, as a common electrode for each pixel 102, on the second contact layer 184 (on the light incident side) and in contact with the second contact layer 184. The second electrode 185 is for discharging charges that are not used as signal charges from the charge generated in the photoelectric conversion layer 183 (cathode).

[0087] For example, if a hole is read out as a signal charge from the first electrode 181, electrons can be discharged through the second electrode 185. The second electrode 185 is made of a conductive film that can transmit incident light, such as infrared light. For the second electrode 185, for example, ITO (Indium Tin Oxide) or ITiO (In2O3-TiO2) can be used.

[0088] The passivation film 186 covers the second electrode 185 from the light incident surface S1 side. The passivation film 186 may have an anti-reflective function. For example, silicon nitride, aluminum oxide, silicon dioxide, and tantalum oxide can be used for the passivation film 186.

[0089] The insulating film 187 is provided between the first contact layer 182 and the wiring layer 180W, and covers the end face of the first contact layer 182, the end face of the photoelectric conversion layer 183, the end face of the second contact layer 184, and the end face of the second electrode 185. In addition, the insulating film 187 is in contact with the passivation film 186 in the peripheral region R2.

[0090] This insulating film 187 is, for example, silicon oxide (SiO2). x ) or an oxide such as aluminum oxide is included. The insulating film 187 may be formed by a laminated structure consisting of multiple films.

[0091] The insulating film 187 may be composed of a silicon (Si)-based insulating material such as silicon oxynitride (SiON), silicon oxide (SiOC), silicon nitride, and silicon carbide (SiC).

[0092] The embedded layer 188 is used in the manufacturing process of the sensor element 10 to fill the step difference between the temporary substrate (not shown) and the semiconductor layer 180S. As will be described in detail later, in this embodiment, since this embedded layer 188 is formed, the occurrence of manufacturing process defects caused by the step difference between the semiconductor layer 180S and the temporary substrate is suppressed.

[0093] The embedded layer 188 in the peripheral region R2 is provided between the wiring layer 180W and the passivation film 186, and has a thickness greater than, for example, the thickness of the semiconductor layer 180S. Here, since this embedded layer 188 is provided surrounding the semiconductor layer 180S, the region around the semiconductor layer 180S (peripheral region R2) is formed.

[0094] This makes it possible to provide a bonding surface S2 with the circuit board 190 in the peripheral region R2. If a bonding surface S2 is formed in the peripheral region R2, the thickness of the embedded layer 188 may be reduced, but it is preferable that the embedded layer 188 covers the semiconductor layer 180S in the thickness direction, and that the entire end face of the semiconductor layer 180S is covered by the embedded layer 188.

[0095] The embedded layer 188 effectively prevents moisture from penetrating the semiconductor layer 180S by covering the entire edge surface of the semiconductor layer 180S via the insulating film 187.

[0096] The surface of the embedded layer 188 on the joint surface S2 side is flattened, and in the peripheral region R2, a wiring layer 180W is provided on this flattened surface of the embedded layer 188. For the embedded layer 188, inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, carbon-containing silicon oxide, and silicon carbide can be used.

[0097] The embedded layer 188 is provided with a through electrode 188V. This through electrode 188V is for connecting the second electrode 185 to the wiring of the circuit board 190 (wiring 192CB described later), and a portion of it is provided on the passivation film 186.

[0098] One end of the through electrode 188V is connected to the second electrode 185 by passing through the passivation film 186 from above. The other end of the through electrode 188V is connected to the contact electrode 189EB by passing through the passivation film 186, insulating film 187, embedding layer 188, and interlayer insulating film 189A from above.

[0099] The support substrate 191 of the circuit board 190 is for supporting the wiring layer 192W and is made of, for example, silicon (Si). The wiring layer 192W has, for example, contact electrodes 192EA, 192EB, pixel circuit 192CA, wiring 192CB, and pad electrode 192P in an interlayer insulating film 192A.

[0100] The interlayer insulating film 192A is composed of, for example, an inorganic insulating material. Examples of this inorganic insulating material include silicon nitride, aluminum oxide, silicon dioxide, and hafnium oxide.

[0101] The contact electrode 192EA is for electrically connecting the first electrode 181 and the pixel circuit 192CA, and is in contact with the contact electrode 189EA at the junction surface S2 of the element substrate 180. Adjacent contact electrodes 192EA are electrically isolated by the interlayer insulating film 192A.

[0102] The contact electrode 192EB is for electrically connecting the second electrode 185 and the wiring 192CB of the circuit board 190, and is in contact with the contact electrode 189EB at the junction surface S2 of the element substrate 180. This contact electrode 192EB is formed, for example, in the same process as the contact electrode 192EA.

[0103] Alternatively, the contact electrodes 189EB and 192EB may be omitted, and the through electrode 188V may be connected to the wiring 192CB. The contact electrodes 192EA and 192EB are, for example, made of copper pads and are exposed on the surface of the circuit board 190 facing the element board 180.

[0104] In other words, for example, a CuCu bond is formed between contact electrode 189EA and contact electrode 192EA, and between contact electrode 189EB and contact electrode 192EB.

[0105] A pixel circuit 192CA is provided for each pixel 102 and is connected to a contact electrode 192EA. This pixel circuit 192CA constitutes the ROIC. The wiring 192CB connected to the contact electrode 192EB is connected to, for example, a predetermined potential.

[0106] In this way, one of the charges generated in the photoelectric conversion layer 183 (for example, a hole) is read out from the first electrode 181 to the pixel circuit 192CA via the contact electrodes 189EA and 192EA.

[0107] Furthermore, the other charge (for example, electrons) generated in the photoelectric conversion layer 183 is discharged from the second electrode 185 to a predetermined potential via the through electrode 188V and contact electrodes 189EB and 192EB.

[0108] The pad electrode 192P is for making an electrical connection to the outside. The sensor element 10 is provided with a hole H that penetrates the element substrate 180 and reaches the pad electrode 192P, and an electrical connection to the outside is made through this hole H. The connection is made by methods such as wire bonding or bumping.

[0109] [Configuration of the sensor device] Next, the configuration of the sensor device 1 according to the embodiment will be described. Figure 6 is a cross-sectional view showing an example of the configuration of the sensor device 1 according to the embodiment of this disclosure, and Figure 7 is a bottom view showing an example of the configuration of the sensor device 1 according to the embodiment of this disclosure.

[0110] The sensor device 1 according to this embodiment has a package structure with an internally hermetically sealed interior, and is a sensor device that receives light transmitted through the window member 60 with an internal sensor element 10. In the following description, for convenience, the side of the sensor device 1 on which the window member 60 is provided will be defined as the upper side, and the directions of up and down will be indicated accordingly.

[0111] As shown in Figure 6, the sensor device 1 according to this embodiment includes a sensor element 10, a Peltier element 20, a relay substrate 30, a package substrate 40, a plurality of pin terminals 50, a window member 60, and a support member 70. The plurality of pin terminals 50 are an example of external terminals.

[0112] The sensor element 10 has an effective pixel region 11 on its main surface (top surface in the figure), which is the light-receiving surface 10a. Multiple pixels 102 (see Figure 1) that convert received light into electrical signals are formed in this effective pixel region 11.

[0113] The sensor element 10 according to the embodiment is, for example, a SWIR (Short Wave InfraRed) image sensor such as an InGaAs image sensor. That is, the sensor element 10 according to the embodiment has a pixel that converts light including the short wave infrared region (for example, light with a wavelength of 400 nm to 2500 nm) into an electrical signal.

[0114] The Peltier element 20 has a cooling substrate 21, a columnar portion 22, and a heat dissipation substrate 23, and these cooling substrate 21, columnar portion 22, and heat dissipation substrate 23 are stacked from top to bottom in this order.

[0115] Figure 8 is a top view showing an example of the configuration of the cooling substrate 21 of the Peltier element 20 according to the present disclosure. As shown in Figure 8, a metal layer ML1, formed of a copper thin film or the like and having a predetermined pattern, is formed on the surface facing the columnar portion 22 (the bottom surface in Figure 6). Note that in Figure 8, for ease of understanding, the arrangement of the metal layer ML1 when viewed from above is shown.

[0116] Figure 9 is a top view showing an example of the configuration of a heat dissipation substrate 23 of a Peltier element 20 according to the present disclosure. As shown in Figure 9, a metal layer ML2 formed of a copper thin film or the like and having a predetermined pattern is formed on the surface (top surface in Figure 6) facing the columnar portion 22 of the heat dissipation substrate 23. In addition, a pair of electrodes 24 are provided at predetermined locations on the metal layer ML2 of the heat dissipation substrate 23.

[0117] Then, by sandwiching the columnar portion 22 between the cooling substrate 21 shown in Figure 8 and the heat dissipation substrate 23 shown in Figure 9, a Peltier element 20 as shown in Figure 10 is constructed. Figure 10 is a top view showing an example of the configuration of a Peltier element 20 according to the present disclosure.

[0118] As shown in Figure 10, the metal layer ML1 of the cooling substrate 21 and the metal layer ML2 of the heat dissipation substrate 23 are aligned, and the columnar portion 22 is placed in the area where both metal layers ML1 and ML2 are positioned.

[0119] As a result, a single-stroke electrical circuit is formed inside the Peltier element 20 between one electrode 24 and the other electrode 24, consisting of the metal layer ML1, the metal layer ML2, and the columnar portion 22.

[0120] Furthermore, the columnar portion 22 has a columnar P-type thermoelectric semiconductor and a columnar N-type thermoelectric semiconductor. One end of each of these P-type and N-type thermoelectric semiconductors is connected to the metal layer ML1, and the other end is connected to the metal layer ML2. The P-type and N-type thermoelectric semiconductors of the columnar portion 22 are alternately connected in series via the metal layers ML1 and ML2.

[0121] As a result, in the Peltier element 20, when a DC current is passed from the N-type thermoelectric semiconductor, the cooling substrate 21 is cooled by absorbing heat from the cooling surface 21a (see Figure 6), and the heat dissipation substrate 23 dissipates the heat absorbed by the cooling substrate 21 from the heat dissipation surface 23a (see Figure 6).

[0122] The cooling surface 21a is the surface of the cooling substrate 21 opposite to the surface to which the columnar portion 22 is joined (i.e., the surface on which the metal layer ML1 is placed). The heat dissipation surface 23a is the surface of the heat dissipation substrate 23 opposite to the surface to which the columnar portion 22 is joined (i.e., the surface on which the metal layer ML2 is placed).

[0123] Returning to the explanation of Figure 6, the relay substrate 30 is placed between the cooling surface 21a of the Peltier element 20 and the sensor element 10. For example, the sensor element 10 is bonded to the front surface 31 of the relay substrate 30 via an adhesive (not shown), and the cooling surface 21a of the Peltier element 20 is bonded to the back surface 32 of the relay substrate 30 via an adhesive (not shown).

[0124] As a result, the sensor element 10 is thermally connected to the cooling surface 21a of the Peltier element 20 via the relay substrate 30.

[0125] Furthermore, the relay substrate 30 has wiring layers (not shown) on its surface and inside, and these wiring layers relay the electrical connection between the sensor element 10 and the package substrate 40.

[0126] For example, the wiring layer of the relay substrate 30 and the sensor element 10 are electrically connected by a bonding wire 33. Also, the wiring layer of the relay substrate 30 and the bonding pad (not shown) provided on the stepped portion 41b of the package substrate 40 are electrically connected by a bonding wire 34. As a result, the relay substrate 30 can relay the electrical connection between the sensor element 10 and the package substrate 40.

[0127] The relay substrate 30 is, for example, an interposer substrate made of ceramic. However, the relay substrate 30 is not limited to a ceramic substrate; it may also be a resin printed circuit board or the like.

[0128] The package substrate 40 is made of a ceramic with high thermal conductivity, such as alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4), and houses the sensor element 10, the Peltier element 20, and the relay substrate 30.

[0129] The package substrate 40 is a multilayer substrate made of ceramic such as alumina, and is, for example, a PGA (Pin Grid Array) substrate. As shown in Figure 6, the package substrate 40 has a first surface (for example, a top surface 42) and a second surface (for example, a bottom surface 43) located on the opposite side of the first surface.

[0130] In the package substrate 40, multiple wirings are arranged in multiple layers inside the area between the top surface 42 and the bottom surface 43. These wirings are connected to multiple terminals (for example, pin terminals 50) provided on the bottom surface 43 of the package substrate 40.

[0131] For example, the package substrate 40 is roughly rectangular in shape, and a recess 41 is formed on its upper surface 42. Then, the Peltier element 20, the relay substrate 30, and the sensor element 10 are stacked on the bottom surface 41a of the recess 41 in this order from bottom to top.

[0132] Furthermore, a stepped portion 41b is provided in the recess 41 at a location higher than the bottom surface 41a. A bonding pad provided in this stepped portion 41b is electrically connected to the wiring layer of the corresponding relay substrate 30 by a bonding wire 34.

[0133] Furthermore, the bonding pad provided on the stepped portion 41b is electrically connected to the pin terminals 50 provided on the bottom surface 43 of the package substrate 40 via a wiring layer (not shown) formed on the surface or inside the package substrate 40. In other words, the package substrate 40 functions as a relay substrate that relays the electrical connection between the relay substrate 30 and the pin terminals 50.

[0134] In this way, by forming a bonding pad on the stepped portion 41b, the distance between the bonding pad and the intermediate substrate 30 can be reduced. As a result, the length of the bonding wire 34 can be shortened, and thus the wiring resistance between the package substrate 40 and the intermediate substrate 30 can be reduced.

[0135] Therefore, according to this embodiment, the electrical characteristics of the sensor device 1 can be improved.

[0136] The bottom surface 43 and multiple sides 44 of the package substrate 40 are each substantially flat. As shown in Figure 7, multiple pin terminals 50 are arranged in a matrix on the bottom surface 43 of the package substrate 40, and a flat bottom heat dissipation area 43a is provided in the area where these multiple pin terminals 50 are not arranged.

[0137] Furthermore, as shown in Figure 6, flat side heat dissipation areas 44a are provided on each of the multiple sides 44 of the package substrate 40.

[0138] The pin terminal 50 is made of a conductive material (for example, metal) and is roughly cylindrical in shape. One end of the pin terminal 50 is electrically and mechanically connected to a wiring layer exposed from the bottom surface 43 of the package substrate 40, and the pin terminal 50 extends downward from the bottom surface 43.

[0139] In this embodiment, a plurality of pin terminals 50 are electrically connected to an external device (not shown), thereby inputting power, control signals, etc., from the external device to the sensor device 1, and outputting electrical signals from the sensor element 10 to the external device.

[0140] Power is supplied from an external device to the electrodes 24 of the Peltier element 20 via a terminal 45 provided on the bottom surface 41a of the recess 41 in the package substrate 40, and a bonding wire 25 connected to the terminal 45.

[0141] The window member 60 is provided facing the light-receiving surface 10a (i.e., the effective pixel area 11) of the sensor element 10 and is made of borosilicate glass, which is a light-transmitting material. In the sensor device 1 according to this embodiment, light transmitted through the window member 60 is received by the effective pixel area 11 of the sensor element 10.

[0142] The support member 70 is positioned between the sensor element 10 and the window member 60 and supports the window member 60. The support member 70 has an opening 71 and a frame portion 72. The opening 71 is formed opposite the light-receiving surface 10a of the sensor element 10 (i.e., the effective pixel area 11) and allows incident light to pass through. The frame portion 72 has a frame shape and is positioned to surround the opening 71 and supports the window member 60.

[0143] The window member 60 is then attached to the support member 70 so as to cover the opening 71, thereby being supported by the support member 70. The window member 60 and the support member 70 are joined together without any gaps using low-melting-point glass or the like.

[0144] Furthermore, the support member 70 is joined to the upper surface 42 of the package substrate 40 so as to cover the recess 41 of the package substrate 40. The support member 70 and the package substrate 40 are joined without gaps using existing methods.

[0145] In this way, by joining the window member 60 and the support member 70 without any gaps, and by joining the support member 70 and the package substrate 40 without any gaps, the sensor device 1 can hermetically seal the inside of the recess 41 of the package substrate 40.

[0146] Furthermore, when hermetically sealing the recess 41 of the package substrate 40, it is preferable to hermetically seal it in such a way that the inside of the recess 41 is in a low-humidity state. In addition, the support member 70 can be made of various materials such as metal or ceramic materials.

[0147] In the sensor device 1 according to the embodiment described above, the detection sensitivity of the sensor device 1 can be improved by making the window member 60 out of borosilicate glass.

[0148] Figure 11 shows the wavelength dependence of the transmittance of the window member 60 in the examples and reference examples. In Figure 11, the transmittance of the window member 60 made of borosilicate glass is shown as an example, and the transmittance of the window member 60 made of sapphire glass is shown as a reference example.

[0149] As shown in Figure 11, in the reference example window member 60, there are regions where the transmittance decreases in the visible region and the short-wave infrared region (for example, wavelengths from 400 nm to 2500 nm). On the other hand, in the embodiment window member 60, the transmittance is consistently high throughout the same visible region and short-wave infrared region.

[0150] Thus, by constructing the window member 60 with borosilicate glass that exhibits a stable and high transmittance across the entire visible and short-wave infrared regions, the amount of light received by the sensor element 10 across the entire visible and short-wave infrared regions can be increased.

[0151] Therefore, according to this embodiment, the detection sensitivity of the sensor device 1 can be improved.

[0152] Furthermore, in this embodiment, by constructing the window member 60 with borosilicate glass having isotropic crystal structure, it is possible to suppress the influence of optical properties (e.g., transmittance) on the axial direction of the crystal. Therefore, according to this embodiment, a sensor device 1 with small variations in optical properties can be realized.

[0153] Furthermore, in this embodiment, the thermal shock characteristics of the sensor device 1 can be improved by constructing the window member 60 from borosilicate glass, which has a low coefficient of thermal expansion and high toughness.

[0154] Furthermore, in this embodiment, the processing cost of the sensor device 1 can be reduced by constructing the window member 60 from borosilicate glass, which is relatively easy to process.

[0155] Furthermore, in this embodiment, a support member 70 having an opening 71 and a frame portion 72, which supports the window member 60, is provided on the sensor device 1. This makes it possible to reduce the area of ​​the window member 60, which is relatively prone to cracking, compared to the case where the window member 60 is directly bonded to the upper surface 42 of the package substrate 40, thereby suppressing malfunctions of the sensor device 1 caused by the window member 60 cracking.

[0156] Therefore, according to this embodiment, the reliability of the sensor device 1 can be improved.

[0157] Furthermore, in the embodiment, the frame portion 72 is preferably positioned outside the effective pixel area 11 in a plan view, and the area of ​​the opening 71 is preferably larger than the area of ​​the effective pixel area 11. For example, in the embodiment, the opening angle of the opening 71 with respect to the effective pixel area 11 is preferably 30° or more.

[0158] This allows light from the object to be detected by the sensor device 1 to be guided to the effective pixel area 11 without being obstructed by the support member 70. Therefore, according to this embodiment, the object to be detected can be detected stably.

[0159] Furthermore, in this embodiment, the window member 60 is preferably positioned to cover the opening 71. That is, in this embodiment, the area of ​​the window member 60 is preferably larger than the area of ​​the opening 71. This allows for a larger overlap between the window member 60 and the support member 70, thereby suppressing the formation of gaps between the window member 60 and the support member 70.

[0160] Therefore, according to this embodiment, the recess 41 of the package substrate 40 can be stably and hermetically sealed. Note that the window member 60 according to this embodiment is not limited to being positioned to cover the opening 71; a window member 60 of approximately the same size as the opening 71 may be positioned to fit into the opening 71.

[0161] Furthermore, in this embodiment, the sensor element 10 is thermally connected to the cooling surface 21a of the Peltier element 20, so that even when using a sensor element 10 that generates a lot of heat during operation, such as a SWIR image sensor, the sensor element 10 can be operated stably.

[0162] Furthermore, in this embodiment, as shown in Figure 6, it is preferable that the cooling surface 21a of the Peltier element 20 is larger than the surface of the sensor element 10 opposite to the light-receiving surface 10a. That is, in a plan view, it is preferable that the cooling surface 21a of the Peltier element 20 is larger than that of the sensor element 10.

[0163] This allows the entire sensor element 10 to be cooled uniformly by the Peltier element 20, thereby enabling the sensor element 10 to operate more stably.

[0164] In the example shown in Figure 6, the case where the cooling surface 21a of the Peltier element 20 is larger than that of the sensor element 10 is shown in a plan view. On the other hand, the cooling surface 21a of the Peltier element 20 may be approximately the same size as that of the sensor element 10, or, as shown in Figure 12, the cooling surface 21a of the Peltier element 20 may be smaller than that of the sensor element 10. Figure 12 is a cross-sectional view showing an example of the configuration of a sensor device 1 according to Modification 1 of the Embodiment of this Disclosure.

[0165] As shown in Figure 12, in a plan view, by making the cooling surface 21a of the Peltier element 20 smaller than that of the sensor element 10, the recess 41 can be reduced in size, thereby enabling miniaturization of the sensor device 1.

[0166] Furthermore, in the embodiment, in the package substrate 40 that houses the sensor element 10 and the Peltier element 20, the bottom surface 41a of the recess 41 in the package substrate 40 is preferably thermally connected to the heat dissipation surface 23a of the Peltier element 20.

[0167] As a result, in the sensor device 1 in which the Peltier element 20 and the sensor element 10 are hermetically sealed, the heat generated in the sensor element 10 can be efficiently dissipated to the outside via the Peltier element 20 and the package substrate 40.

[0168] Furthermore, in this embodiment, since the Peltier element 20 and the sensor element 10 are hermetically sealed in a low humidity state, it is possible to suppress the occurrence of condensation on the cooling surface 21a of the Peltier element 20 when the cooling surface 21a of the Peltier element 20 is cooled.

[0169] Furthermore, in this embodiment, by making the package substrate 40 out of ceramic, the sensor element 10 of the sensor device 1 can be made to have multiple pixels. The reason for this will be explained below.

[0170] Figure 13 is a cross-sectional view showing an example of the configuration of a sensor device 1 according to a modified example 2 of the embodiment of the present disclosure, and shows a sensor device 1 made of a metal package substrate 90. As shown in Figure 13, in the sensor device 1 of modified example 2, the sensor element 10, the Peltier element 20, and the relay substrate 30 are housed in a recess 91 of the metal package substrate 90.

[0171] Furthermore, multiple columnar pin terminals 95 are provided on the bottom surface 91a of the recess 91. In order to ensure insulation between the pin terminals 95, an insulating sealing member 96 is provided between the pin terminals 95 and the package substrate 90.

[0172] Furthermore, one end of the pin terminal 95 protrudes downward from the bottom surface 93 of the package substrate 90, and the other end of the pin terminal 95 is electrically connected to the relay substrate 30 by a bonding wire 34 within the recess 91.

[0173] In the example shown in Figure 13, since the package substrate 90 is made of a conductive metal material, the insulation of each pin terminal 95 must be ensured by the sealing member 96. In other words, in the example shown in Figure 13, space is required to provide the sealing member 96, making it difficult to reduce the distance between adjacent pin terminals 95, and thus making it difficult to arrange multiple pin terminals 95 on the package substrate 90 at a high density.

[0174] On the other hand, in the example shown in Figure 6, since the package substrate 40 is made of insulating ceramic, there is no need to provide a separate component to ensure insulation. Therefore, in the example shown in Figure 6, by making the package substrate 40 out of ceramic, the distance between adjacent pin terminals 50 can be reduced.

[0175] Furthermore, with a ceramic package substrate 40, a three-dimensional wiring layer can be provided inside the package substrate 40, so even if a large number of pin terminals 50 are arranged on the bottom surface 43, all pin terminals 50 can be wired individually.

[0176] In other words, in this embodiment, even when the sensor element 10 has multiple pixels, the signals output from all pixels can be sent to the corresponding pin terminals 50. Therefore, according to this embodiment, the sensor element 10 of the sensor device 1 can have multiple pixels.

[0177] Furthermore, as shown in Figure 13, even if the package substrate 90 of the sensor device 1 is made of metal, the detection sensitivity of the sensor device 1 can be improved by making the window member 60 out of borosilicate glass.

[0178] Furthermore, in this embodiment, as shown in Figure 7, it is preferable that the multiple pin terminals 50 and the Peltier element 20 are provided at different positions in a plan view. This allows a heat dissipation device (not shown) to be directly attached to the position corresponding to the Peltier element 20 on the bottom surface 43 (i.e., directly below the Peltier element 20).

[0179] In other words, in this embodiment, the heat transferred from the heat dissipation surface 23a of the Peltier element 20 to the bottom surface 43 of the package substrate 40 can be dissipated by the heat dissipation device without being obstructed by the pin terminals 50. Therefore, according to this embodiment, the heat dissipation performance of the sensor device 1 can be improved.

[0180] Furthermore, in this embodiment, as shown in Figure 7, it is preferable to provide a bottom heat dissipation area 43a that is wider and flatter than the Peltier element 20 at a position corresponding to the Peltier element 20 on the bottom surface 43 of the package substrate 40.

[0181] This allows a heat dissipation device with a larger area than the Peltier element 20 to be installed in the bottom heat dissipation area 43a, thereby further improving the heat dissipation performance of the sensor device 1.

[0182] Furthermore, in this embodiment, as shown in Figure 7, it is preferable that multiple pin terminals 50 be provided along two opposing sides of the bottom surface 43. This allows the heat dissipation device to be positioned so that it extends beyond the package substrate 40, thereby further improving the heat dissipation performance of the sensor device 1.

[0183] Furthermore, the bottom heat dissipation area 43a is not limited to being wider than the Peltier element 20, but may be approximately the same size as the Peltier element 20, as shown in Figure 14. Figure 14 is a bottom view showing an example of the configuration of the sensor device 1 according to Modification 3 of the Embodiment of this Disclosure.

[0184] As shown in Figure 14, even if the bottom heat dissipation area 43a is approximately the same size as the Peltier element 20, by arranging the bottom heat dissipation area 43a to overlap with the Peltier element 20, the heat from the Peltier element 20 can be dissipated without any problems by the heat dissipation device.

[0185] Furthermore, in this embodiment, as shown in Figure 14, a plurality of pin terminals 50 may be arranged so as to surround the Peltier element 20 in a plan view. This allows a large number of pin terminals 50 to be provided on the package substrate 40, so that the heat dissipation device can be positioned so as to extend beyond the package substrate 40. Therefore, according to the example in Figure 14, the sensor element 10 of the sensor device 1 can be further increased in number of pixels.

[0186] Furthermore, in this embodiment, as shown in Figure 6, a flat side heat dissipation area 44a is provided on the side surface 44 of the package substrate 40. This allows a heat dissipation device (not shown) to be installed in the side heat dissipation area 44a, thereby further improving the heat dissipation performance of the sensor device 1.

[0187] In this embodiment, an example was shown in which a flat bottom heat dissipation area 43a and a side heat dissipation area 44a are provided on the bottom surface 43 and side surface 44 of the package substrate 40. However, the bottom heat dissipation area 43a and the side heat dissipation area 44a are not limited to being flat.

[0188] For example, by providing irregularities in the bottom heat dissipation area 43a and the side heat dissipation area 44a, the surface area of ​​the bottom heat dissipation area 43a and the side heat dissipation area 44a can be increased, thereby improving the heat dissipation performance of the sensor device 1 without the need to provide a separate heat dissipation device.

[0189] Furthermore, in this embodiment, it is preferable to provide a relay board 30 that relays the electrical connection between the package substrate 40 and the sensor element 10. This allows the thickness of the wiring between the package substrate 40 and the sensor element 10 to be thicker than the bonding wires 33 and 34, thereby reducing the wiring resistance between the package substrate 40 and the sensor element 10.

[0190] Therefore, according to this embodiment, the electrical characteristics of the sensor device 1 can be improved. Furthermore, in this embodiment, the sensor device 1 can be made multifunctional by mounting various components (for example, capacitors and resistors) on the relay board 30.

[0191] Furthermore, in this embodiment, the sensor element 10 may be a SWIR image sensor. This allows the sensor device 1 to perform sensing using light with wavelengths longer than visible light.

[0192] Note that the sensor element 10 according to the embodiment is not limited to a SWIR image sensor. For example, the sensor element 10 according to the embodiment may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor having pixels that convert visible light into electrical signals.

[0193] Next, we will explain the case where the sensor element according to the embodiment is a CMOS image sensor having pixels that convert visible light into electrical signals, with reference to Figures 15A to 17.

[0194] Figures 15A and 15B show the substrate configuration of another example of a sensor element 10A according to the present disclosure. The sensor element 10A (see Figure 16) is a semiconductor package in which a laminated substrate 213, which is formed by stacking a lower substrate 211 and an upper substrate 212, is packaged.

[0195] A color filter (not shown) of R (red), G (green), or B (blue) and an on-chip lens (not shown) are formed on the upper surface of the upper substrate 212. The upper substrate 212 is connected to the on-chip lens via a glass protective substrate (not shown) and a glass sealing resin (not shown) in a cavity-less structure.

[0196] For example, as shown in Figure 15A, the upper substrate 212 has a pixel region 221 in which photoelectric conversion pixels are arranged in a two-dimensional array, and a control circuit 222 that controls the pixels. The lower substrate 211 has logic circuits 223, such as a signal processing circuit that processes the pixel signals output from the pixels.

[0197] Alternatively, as shown in Figure 15B, the upper substrate 212 may have only the pixel region 221 formed on it, while the lower substrate 211 may have the control circuit 222 and logic circuit 223 formed on it.

[0198] As described above, in this disclosure, the logic circuit 223 or both the control circuit 222 and the logic circuit 223 are formed on a lower substrate 211 separate from the upper substrate 212 of the pixel region 221 and stacked. This makes it possible to reduce the size of the sensor element 10A compared to the case where the pixel region 221, control circuit 222, and logic circuit 223 are arranged in a planar direction on a single semiconductor substrate.

[0199] In the following explanation, the upper substrate 212 on which at least the pixel region 221 is formed will be referred to as the pixel sensor substrate, and the lower substrate 211 on which at least the logic circuit 223 is formed will be referred to as the logic substrate.

[0200] Figure 16 shows an example of the circuit configuration of a laminated substrate 213 of a sensor element 10A in another example according to the present disclosure. The laminated substrate 213 includes a pixel array section 233 in which pixels 232 are arranged in a two-dimensional array, and a vertical drive circuit 234, a column signal processing circuit 235, a horizontal drive circuit 236, an output circuit 237, a control circuit 238, input / output terminals 239, and the like.

[0201] Pixel 232 consists of a photodiode as a photoelectric conversion element and multiple pixel transistors. An example of the circuit configuration of pixel 232 will be described later with reference to Figure 17.

[0202] Furthermore, pixel 232 can also be a shared pixel structure. This shared pixel structure consists of multiple photodiodes, multiple transfer transistors, one shared floating diffusion region, and one shared other pixel transistor. In other words, in a shared pixel, the photodiodes and transfer transistors that make up multiple unit pixels share one other pixel transistor.

[0203] The control circuit 238 receives an input clock and data that commands the operating mode, and outputs data such as internal information of the laminated substrate 213. In other words, based on the vertical synchronization signal, horizontal synchronization signal, and master clock, the control circuit 238 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 234, column signal processing circuit 235, and horizontal drive circuit 236, etc.

[0204] The control circuit 238 then outputs the generated clock signal and control signal to the vertical drive circuit 234, the column signal processing circuit 235, and the horizontal drive circuit 236, etc.

[0205] The vertical drive circuit 234 is configured, for example, by a shift register, which selects a predetermined pixel drive wiring 240, supplies pulses to the selected pixel drive wiring 240 to drive the pixels 232, and drives the pixels 232 row by row.

[0206] In other words, the vertical drive circuit 234 sequentially selects and scans each pixel 232 of the pixel array section 233 in the vertical direction row by row. The vertical drive circuit 234 then supplies a pixel signal based on the signal charge generated in the photoelectric conversion section of each pixel 232 according to the amount of light received, to the column signal processing circuit 235 through the vertical signal line 241.

[0207] The column signal processing circuit 235 is located for each column of pixels 232 and performs signal processing, such as noise reduction, on the signals output from one row of pixels 232 for each pixel column. For example, the column signal processing circuit 235 performs signal processing such as CDS and AD conversion to remove pixel-specific fixed pattern noise.

[0208] The horizontal drive circuit 236 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 235 in order, causing each of the column signal processing circuits 235 to output a pixel signal to the horizontal signal line 242.

[0209] The output circuit 237 processes the signals sequentially supplied from each of the column signal processing circuits 235 through the horizontal signal line 242 and outputs them. The output circuit 237 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 239 exchanges signals with the outside.

[0210] The stacked substrate 213 configured as described above is a CMOS image sensor called a column AD type, in which column signal processing circuits 235 that perform CDS processing and AD conversion processing are arranged for each pixel row.

[0211] Figure 17 shows an equivalent circuit of a pixel 232 of a sensor element 10A in another example according to the present disclosure. The pixel 232 shown in Figure 17 has a configuration that realizes an electronic global shutter function.

[0212] Pixel 232 includes a photodiode 251, a first transfer transistor 252, a memory section 253, a second transfer transistor 254, an FD255, a reset transistor 256, an amplification transistor 257, a selection transistor 258, and an output transistor 259. The photodiode 251 is an example of a photoelectric conversion element, and the FD255 is a floating diffusion region.

[0213] The photodiode 251 is a photoelectric conversion unit that generates and stores an electric charge (signal charge) corresponding to the amount of light received. The anode terminal of the photodiode 251 is grounded, and the cathode terminal is connected to the memory unit 253 via the first transfer transistor 252. The cathode terminal of the photodiode 251 is also connected to the discharge transistor 259 for discharging unwanted charges.

[0214] When the first transfer transistor 252 is turned on by the transfer signal TRX, it reads the charge generated by the photodiode 251 and transfers it to the memory unit 253. The memory unit 253 is a charge holding unit that temporarily holds the charge until it is transferred to the FD255.

[0215] When the second transfer transistor 254 is turned on by the transfer signal TRG, it reads the charge held in the memory unit 253 and transfers it to the FD255.

[0216] FD255 is a charge holding unit that holds the charge read from the memory unit 253 in order to read it as a signal. When the reset transistor 256 is turned on by the reset signal RST, the charge stored in FD255 is discharged to the constant voltage source VDD, thereby resetting the potential of FD255.

[0217] The amplifying transistor 257 outputs a pixel signal corresponding to the potential of FD255. In other words, the amplifying transistor 257 forms a source follower circuit with the load MOS260, which acts as a constant current source.

[0218] Then, a pixel signal indicating a level corresponding to the charge stored in FD255 is output from the amplification transistor 257 to the column signal processing circuit 235 (see Figure 16) via the selection transistor 258. The load MOS 260 is located, for example, within the column signal processing circuit 235.

[0219] The selection transistor 258 is turned on when pixel 232 is selected by the selection signal SEL, and outputs the pixel signal of pixel 232 to the column signal processing circuit 235 via the vertical signal line 241.

[0220] When the discharge transistor 259 is turned on by the discharge signal OFG, it discharges the unwanted charge accumulated in the photodiode 251 to the constant voltage source VDD. The transfer signals TRX and TRG, the reset signal RST, the discharge signal OFG, and the selection signal SEL are supplied from the vertical drive circuit 234 via the pixel drive wiring 240.

[0221] Next, the operation of pixel 232 will be briefly explained. First, before exposure begins, a high-level emission signal OFG is supplied to the emission transistor 259, which turns on the emission transistor 259. The charge accumulated in the photodiode 251 is then discharged to the constant voltage source VDD, and the photodiodes 251 of all pixels are reset.

[0222] After the photodiode 251 is reset, the emission transistor 259 is turned off by a low-level emission signal OFG, and exposure begins at all pixels in the pixel array 233.

[0223] When a predetermined exposure time has elapsed, the first transfer transistor 252 is turned on by the transfer signal TRX in all pixels of the pixel array 233, and the charge accumulated in the photodiode 251 is transferred to the memory unit 253.

[0224] After the first transfer transistor 252 is turned off, the charge held in the memory section 253 of each pixel 232 is read out row by row to the column signal processing circuit 235. The read operation is performed when the second transfer transistor 254 of the pixel 232 of the read row is turned on by the transfer signal TRG, and the charge held in the memory section 253 is transferred to FD255.

[0225] Then, when the selection transistor 258 is turned on by the selection signal SEL, a signal indicating a level corresponding to the charge stored in FD255 is output from the amplification transistor 257 to the column signal processing circuit 235 via the selection transistor 258.

[0226] As described above, in the example in Figure 17, the exposure time is set to be the same for all pixels in the pixel array 233, and after exposure is complete, the charge is temporarily held in the memory 253, and the charge is read out sequentially from the memory 253 row by row in a global shutter operation (imaging).

[0227] Furthermore, the circuit configuration of pixel 232 is not limited to the configuration shown in Figure 17. For example, a circuit configuration that does not have a memory section 253 and operates using a so-called rolling shutter method can also be adopted.

[0228] [Other variations] Next, other modifications according to the embodiment will be described with reference to Figures 18 to 25. Figure 18 is a plan view of the pixel array region 103 showing the pixel arrangement of charge-emitting pixels according to Modification 4.

[0229] In this modified example 4, an OPB (Optical Black) region for detecting a reference black level is formed as part of the pixel array region 103. The pixel structure of this modified example 4 is the pixel structure when the OPB region is formed as part of the pixel array region 103.

[0230] As shown in Figure 18, when the OPB region 163 is formed as part of the pixel array region 103, the OPB region 163 consists of multiple columns and rows that are the outermost of each side of the rectangular pixel array region 103. The innermost row and column of the OPB region 163 are set as the charge emission region 162.

[0231] The area inside the OPB area 163 of the pixel array area 103 is the effective pixel area where normal pixels 102A (see Figure 19) that output a pixel signal corresponding to the amount of light received are located.

[0232] Figure 19 is a cross-sectional view showing the structure of a pixel 102 according to a modified example 4 of the embodiment of this disclosure. As shown in Figure 19, OPB pixels 102C (102Ca, 102Cb) are arranged in the OPB region 163.

[0233] In the OPB pixel 102C, a light-shielding film 165 is formed above the N-type semiconductor thin film 141, which is the photoelectric conversion unit 121, in place of a color filter 146 and an on-chip lens 147. The light-shielding film 165 is made of a metallic material such as tungsten, aluminum, or gold.

[0234] In the OPB region 163, for example, three OPB pixels 102C are arranged in a row of three or three columns. The innermost OPB pixel 102C (closest to the center of the pixel array region 103) is a charge-discharging OPB pixel 102Cb, controlled so that the reset transistor 123 is always on, similar to the embodiment described above.

[0235] On the other hand, of the OPB region 163 in which three OPB pixels 102C are arranged in a row of three or three columns, the two outer OPB pixels 102C are black level readout OPB pixels 102Ca, which are controlled to read out the black level. The other configurations in Modification 4 are the same as in the embodiment described above.

[0236] For example, when high-intensity light is shone on the pixel array region 103 of the sensor element 10, blooming may occur in the normal pixel 102A that is closest to the OPB region 163. In this case, there is a risk that the adjacent OPB pixel 102C, that is, the innermost OPB pixel 102C of the OPB region 163, will be affected.

[0237] Furthermore, light incident on the normal pixel 102A closest to the OPB region 163 may leak into the adjacent OPB pixel 102C, potentially causing blooming in the adjacent OPB pixel 102C.

[0238] Therefore, in Modification 4, the innermost OPB pixel 102C of the OPB region 163 is made into a charge-discharging OPB pixel 102Cb, which is controlled so that the reset transistor 123 is always on.

[0239] This allows the occurrence of blooming to be blocked by the charge-emitting OPB pixel 102Cb, preventing charge from flowing into the adjacent black-level readout OPB pixel 102Ca. Therefore, according to Modification 4, image quality degradation due to blooming can be suppressed.

[0240] Furthermore, although the above-described embodiment shows an example where the external terminal of the sensor device 1 is a pin terminal 50, the external terminal of the sensor device 1 is not limited to a pin terminal 50. Figure 20 is a cross-sectional view showing an example of the configuration of the sensor device 1 according to modified example 5 of the embodiment of this disclosure.

[0241] As shown in Figure 20, the sensor device 1 of Modified Example 5 differs from the embodiment in that it is provided with a connector 98 instead of a pin terminal 50 as an external terminal. The connector 98 is provided at a position on the bottom surface 43 that is different from the position corresponding to the Peltier element 20 (i.e., directly below the Peltier element 20), and is electrically connected to the wiring layer exposed from the bottom surface 43 of the package substrate 40.

[0242] In modified example 5, the connector 98 is electrically connected to an external device (not shown), so that power and control signals are input from the external device to the sensor device 1, and electrical signals from the sensor element 10 are output to the external device.

[0243] In this modified example 5, the sensor device 1 can be easily attached to an external device (not shown) by configuring the external terminals with a connector 98. In this disclosure, the external terminals of the sensor device 1 are not limited to pin terminals 50 or connectors 98, and various types of external terminals can be used.

[0244] Figure 21 is a cross-sectional view showing an example of the configuration of a sensor device 1 according to Modification 6 of the embodiment of this disclosure. As shown in Figure 21, in the sensor device 1 of Modification 6, a metal heat dissipation member 46 is provided on at least a portion of the surface (bottom surface 41a in this disclosure) of the package substrate 40 that faces the heat dissipation surface 23a of the Peltier element 20.

[0245] In other words, in the sensor device 1 of Modified Example 6, the heat dissipation member 46 is exposed on the bottom surface 41a. In addition, in the sensor device 1 of Modified Example 6, an adhesive or the like may be interposed between the heat dissipation surface 23a of the Peltier element 20 and the bottom surface 41a.

[0246] The heat dissipation member 46 is made of a metal with high thermal conductivity, such as copper, aluminum, or tungsten. In other words, in the package substrate 40 of the modified example 6, at least a portion of the heat transfer path from the heat dissipation surface 23a of the Peltier element 20 to the bottom heat dissipation area 43a is made of a metal with higher thermal conductivity than ceramic.

[0247] This improves the heat transfer efficiency from the heat dissipation surface 23a of the Peltier element 20 to the bottom heat dissipation area 43a. Therefore, according to the modified example 6, the heat dissipation performance of the sensor device 1 can be improved.

[0248] Furthermore, in the modified example 6, the heat dissipation member 46 may penetrate the package substrate 40 between the surface facing the heat dissipation surface 23a of the Peltier element 20 (bottom surface 41a) and the bottom surface 43. This reduces the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a, thereby further improving the heat dissipation performance of the sensor device 1.

[0249] Furthermore, in the modified example 6, as shown in Figure 21, the heat dissipation member 46 may be provided on the entire surface of the package substrate 40 that faces the heat dissipation surface 23a of the Peltier element 20. This further reduces the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a, thereby further improving the heat dissipation performance of the sensor device 1.

[0250] Furthermore, the heat dissipation member 46 is not limited to being provided on the entire surface of the package substrate 40 that faces the heat dissipation surface 23a of the Peltier element 20. Figure 22 is a cross-sectional view showing an example of the configuration of a sensor device 1 according to modified example 7 of the embodiment of this disclosure.

[0251] As shown in Figure 22, a plurality of via-shaped heat dissipation members 46 may be provided on the package substrate 40, penetrating between the surface (bottom surface 41a) facing the heat dissipation surface 23a of the Peltier element 20 and the bottom surface 43. In this example in Figure 22, the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a can be reduced, thereby further improving the heat dissipation performance of the sensor device 1.

[0252] In the above-described modifications 6 and 7, examples were shown in which a metal material was used for the heat dissipation member 46. However, the heat dissipation member 46 is not necessarily limited to a metal material; any material with a higher thermal conductivity than the ceramic material constituting the package substrate 40 is acceptable. For example, a ceramic material with high thermal conductivity may be used as the heat dissipation member 46.

[0253] Furthermore, in the above-described modified examples 6 and 7, the heat dissipation member 46 is shown to be exposed on the surface of the package substrate 40 that faces the heat dissipation surface 23a of the Peltier element 20, but the heat dissipation member 46 does not necessarily have to be exposed on such a surface.

[0254] For example, the heat dissipation member 46 may be positioned on the package substrate 40 so as to be embedded directly beneath the Peltier element 20. That is, the heat dissipation member 46 may be positioned so as to overlap with the Peltier element 20 in a plan view. This reduces the thermal resistance from the bottom surface 41a to the bottom heat dissipation area 43a, thereby further improving the heat dissipation performance of the sensor device 1.

[0255] Furthermore, the heat dissipation member 46 may be placed at a location other than directly beneath the Peltier element 20.

[0256] Figure 23 is a cross-sectional view showing an example of the configuration of the sensor device 1 according to Modification 8 of the embodiment of this disclosure. As shown in Figure 23, the sensor device 1 of Modification 8 differs from the embodiment in the configuration of the Peltier element 20.

[0257] Specifically, in Modification 8, the package substrate 40 is integrally formed with the heat dissipation substrate 23 of the Peltier element 20. That is, in Modification 8, the metal layer ML2 shown in Figure 9 is provided on the bottom surface 41a of the recess 41 in the package substrate 40 instead of the heat dissipation substrate 23, and the columnar portion 22 and the cooling substrate 21 are laminated on the metal layer ML2 on the bottom surface 41a to form the Peltier element 20.

[0258] In this way, by integrating the package substrate 40 with the heat dissipation substrate 23 of the Peltier element 20, the thermal resistance at the interface between the heat dissipation substrate 23 and the package substrate 40 can be reduced. Furthermore, in the modified example 8, the heat dissipation substrate 23 can be omitted, thus shortening the heat transfer path from the sensor element 10 to the bottom heat dissipation area 43a.

[0259] Therefore, according to Modification 8, the heat dissipation of the sensor device 1 can be improved.

[0260] Figure 24 is a cross-sectional view showing an example of the configuration of a sensor device 1 according to modified example 9 of the embodiment of this disclosure. As shown in Figure 24, the sensor device 1 of modified example 9 differs from that of the embodiment and modified example 8 in the configuration of the Peltier element 20.

[0261] Specifically, in Modification 9, the relay substrate 30 is integrated with the cooling substrate 21 of the Peltier element 20. That is, in Modification 9, the metal layer ML1 shown in Figure 8 is provided on the back surface 32 of the relay substrate 30 instead of the cooling substrate 21, and the relay substrate 30 is further laminated on the laminated heat dissipation substrate 23 and columnar portion 22 to form the Peltier element 20.

[0262] In this way, by integrating the relay substrate 30 with the cooling substrate 21 of the Peltier element 20, the thermal resistance at the interface between the relay substrate 30 and the cooling substrate 21 can be reduced. Furthermore, in the modified example 9, the cooling substrate 21 can be omitted, thus shortening the heat transfer path from the sensor element 10 to the bottom heat dissipation area 43a.

[0263] Therefore, according to Modification 9, the heat dissipation of the sensor device 1 can be improved.

[0264] Figure 25 is a cross-sectional view showing an example of the configuration of a sensor device 1 according to a modified example 10 of the embodiment of this disclosure. As shown in Figure 25, the sensor device 1 of modified example 10 differs from the embodiment in that it does not have a relay board 30.

[0265] In other words, in modified example 10, the sensor element 10 is directly bonded to the cooling surface 21a of the Peltier element 20. Also, the sensor element 10 and the package substrate 40 are directly electrically connected by a bonding wire 33.

[0266] In this modified example 10, the relay board 30 can be omitted, thus shortening the heat transfer path from the sensor element 10 to the bottom heat dissipation area 43a. Therefore, according to this modified example 10, the heat dissipation performance of the sensor device 1 can be improved.

[0267] Also, in Modified Example 10, since the recess 41 can be made smaller by omitting the relay substrate 30, the sensor device 1 can be miniaturized.

[0268] [Effect] The sensor device 1 according to the embodiment includes a Peltier element 20, a sensor element 10 (10A), and a package substrate 40. The sensor element 10 (10A) is thermally connected to the cooling surface 21a of the Peltier element 20. The ceramic package substrate 40 is thermally connected to the heat radiating surface 23a of the Peltier element 20 and houses the Peltier element 20 and the sensor element 10 (10A).

[0269] Thereby, the sensor device 1 can be made multi-pixel.

[0270] Also, in the sensor device 1 according to the embodiment, the package substrate 40 has external terminals (pin terminals fifty), and the external terminals (pin terminals fifty) and the Peltier element 20 are provided at different positions in a plan view.

[0271] Thereby, the heat dissipation property of the sensor device 1 can be improved.

[0272] Also, in the sensor device 1 according to the embodiment, a flat bottom heat radiating area 43a is provided at a position corresponding to the Peltier element 20 on the bottom surface 43 of the package substrate 40 where the external terminals (pin terminals fifty) are provided.

[0273] Thereby, the heat dissipation property of the sensor device 1 can be improved.

[0274] Also, in the sensor device 1 according to the embodiment, the bottom heat radiating area 43a is wider than the Peltier element 20.

[0275] Thereby, the heat dissipation property of the sensor device 1 can be further improved.

[0276] Also, in the sensor device 1 according to the embodiment, a plurality of external terminals (pin terminals 50) are provided on the rectangular bottom surface 43 of the package substrate 40. Further, the plurality of external terminals (pin terminals 50) are provided along two opposite sides of the bottom surface 43 of the package substrate 40.

[0277] Thereby, the heat dissipation property of the sensor device 1 can be further improved.

[0278] Also, in the sensor device 1 according to the embodiment, a plurality of external terminals (pin terminals 50) are provided on the bottom surface 43 of the package substrate 40. Further, the plurality of external terminals (pin terminals 50) are provided so as to surround the Peltier element 20 in a plan view.

[0279] Thereby, the sensor element 10 (10A) of the sensor device 1 can be further multi-pixelated.

[0280] Also, in the sensor device 1 according to the embodiment, a flat side heat dissipation area 44a is provided on the side surface 44 of the package substrate 40.

[0281] Thereby, the heat dissipation property of the sensor device 1 can be further improved.

[0282] Also, in the sensor device 1 according to the embodiment, the sensor element 10 is a SWIR image sensor.

[0283] Thereby, the sensor device 1 can perform sensing using light having a wavelength longer than visible light.

[0284] As described above, the embodiments of the present disclosure have been described. However, the technical scope of the present disclosure is not limited to the above-described embodiments as they are, and various modifications are possible without departing from the gist of the present disclosure. Also, components across different embodiments and modifications may be appropriately combined.

[0285] For example, in the above embodiment, an example was shown in which the terminal 45 of the package substrate 40 and the electrode 24 of the Peltier element 20 are electrically connected with a bonding wire 25. However, the connection between the terminal 45 and the electrode 24 is not limited to the bonding wire 25. For example, the terminal 45 and the electrode 24 may be electrically connected with a lead wire or the like.

[0286] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0287] Furthermore, this technology can also be configured as follows. (1) Peltier element and A sensor element thermally connected to the cooling surface of the Peltier element, A ceramic package substrate is thermally connected to the heat dissipation surface of the Peltier element and houses the Peltier element and the sensor element. A sensor device equipped with the following features. (2) The aforementioned package substrate has external terminals, The external terminal and the Peltier element are located at different positions in a plan view. The sensor device described in (1) above. (3) On the bottom surface of the package substrate on which the external terminals are provided, a flat bottom heat dissipation area is provided at a position corresponding to the Peltier element. The sensor device described in (2) above. (4) The bottom heat dissipation area is wider than the Peltier element. The sensor device described in (3) above. (5) Multiple external terminals are provided on the rectangular bottom surface of the package substrate. Multiple external terminals are provided along two opposing sides of the bottom surface of the package substrate. A sensor device as described in any one of (2) to (4) above. (6) A plurality of the external terminals are provided on the bottom surface of the package substrate. The plurality of external terminals are provided so as to surround the Peltier element in a plan view. The sensor device according to any one of (2) to (4) above. (7) A flat side heat dissipation area is provided on the side surface of the package substrate. The sensor device according to any one of (1) to (6) above. (8) The sensor element is a SWIR (Short Wave InfraRed) image sensor. The sensor device according to any one of (1) to (7) above.

Explanation of symbols

[0288] 1 Sensor device 10, 10A Sensor element 10a Light receiving surface 11 Effective pixel area 20 Peltier element 21 Cooling substrate 21a Cooling surface 22 Columnar part 23 Heat dissipation substrate 23a Heat dissipation surface 30 Relay substrate 40 Package substrate 41 Recess 41a Bottom surface 43 Bottom surface 43a Bottom heat dissipation area 44 Side surface 44a Side heat dissipation area 46 Heat dissipation member 50 Pin terminal (an example of an external terminal) 60 Window member 70 Support member 71 Opening 72 Frame part

Claims

1. Peltier element and A sensor element thermally connected to the cooling surface of the Peltier element, A ceramic package substrate is thermally connected to the heat dissipation surface of the Peltier element and houses the Peltier element and the sensor element. Equipped with, The package substrate has two groups of external terminals on its rectangular bottom surface, in which multiple external terminals are arranged in a matrix. The two groups of external terminals and the Peltier element are located in different positions in a plan view. The two groups of external terminals are located along two opposing sides of the bottom surface. Sensor device.

2. On the bottom surface, a flat bottom heat dissipation area is provided at a position corresponding to the Peltier element. The sensor device according to claim 1.

3. The bottom heat dissipation area is wider than the Peltier element. The sensor device according to claim 2.

4. A flat side heat dissipation area is provided on the side surface of the package substrate. A sensor device according to any one of claims 1 to 3.

5. The aforementioned sensor element is a SWIR (Short Wave InfraRed) image sensor. A sensor device according to any one of claims 1 to 4.

Images