Detection device and detection system

Abstract

To provide a technique advantageous for detecting signals generated by pixels with low noise.SOLUTION: A detection device comprises: pixels each including a photodiode, an amplification transistor having its gate connected to an output node of the photodiode, a reset transistor resetting the photodiode, and a selection transistor; signal lines that are connected to the pixels, and a read-out circuit that reads out the signals from the pixels through the signal lines. The read-out circuit includes an AD converter that performs AD conversion for the signals input from the pixels through the signal lines. The AD converter performs an offset cancellation operation of maintaining a signal level according to the signals generated by the photodiode while cancelling the offset of the AD converter, and performs first AD conversion for a changed portion of the signal level after the offset cancellation operation.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a detection device and a detection system.

Background Art

[0002] There is a technique for converting an analog signal output from a pixel into a digital signal by an analog-to-digital converter (hereinafter, an AD converter). Patent Document 1 describes that after reading a signal from a pixel, the pixel is reset and AD conversion is performed. Further, Patent Document l describes canceling the offset of a comparator during the period when the pixel is being reset.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the configuration described in Patent Document 1, AD conversion is performed after resetting the pixel. Therefore, noise of the AD converter, for example, noise in the offset cancellation operation of the comparator, is AD-converted as an overlapping signal. Thus, Patent Document 1 had room for further noise reduction.

[0005] An object of the present invention is to provide a technique advantageous for detecting a signal generated by a pixel with low noise.

Means for Solving the Problems

[0006] One aspect of the present invention relates to a detection device, the detection device comprising a pixel including a photodiode, an amplifying transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, a signal line connected to the pixel, and a readout circuit for reading a signal from the pixel via the signal line, the readout circuit including an AD converter that performs AD conversion on a signal input from the pixel via the signal line, the AD converter performs an offset cancellation operation that holds a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation.

[0007] Another aspect of the present invention relates to a detection device, the detection device comprising a pixel including a photodiode into which radiation is incident, an amplifying transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, a signal line connected to the pixel, and a readout circuit for reading a signal from the pixel via the signal line, the readout circuit including an AD converter that performs AD conversion on a signal input from the pixel via the signal line, the AD converter comprising a differential amplifier circuit having an input node and an output node, a capacitive element with one terminal connected to the input node and the other terminal connected to the signal line, and a switch connected to the one terminal, wherein the switch transitions from an ON state to an OFF state during the period when a first signal, which is a signal level corresponding to the amount of radiation received by the photodiode, is output to the one terminal, and during the period from the OFF state to the next ON state when the switch is output, a second signal, which is a signal level corresponding to the reset level of the gate, is output to the one terminal, and the AD converter performs AD conversion during the period when the second signal is output to the one terminal. [Effects of the Invention]

[0008] The present invention provides a technique advantageous for detecting signals generated by pixels with low noise. [Brief explanation of the drawing]

[0009] [Figure 1] A block diagram showing an example configuration of a detection device set up as a solid-state imaging device. [Figure 2] A diagram showing an example of the configuration of pixels and a readout circuit in the detection device of the first embodiment. [Figure 3A] A timing chart showing a first example of operation of the detection device according to the first embodiment. [Figure 3B] A timing chart showing a second example of operation of the detection device according to the first embodiment. [Figure 4] A timing chart showing an example of clipping circuit operation. [Figure 5] A diagram showing an example of the configuration of pixels and a readout circuit in the detection device of the second embodiment. [Figure 6] A timing chart showing an example of operation of the detection device according to the second embodiment. [Figure 7] A diagram showing the detection system in the third embodiment. [Figure 8] A diagram showing the detection system in the fourth embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0011] Figure 1 shows the configuration of a detection device 1 according to one embodiment. While Figure 1 illustrates a detection device 1 configured as a solid-state imaging device having multiple pixels, the detection device 1 may be configured as a device having at least one pixel (or detection element). The detection device 1 is a direct conversion type detection device equipped with a photodiode that directly converts incident radiation into electric charge. In the following description, "radiation" is a concept that includes non-ionizing radiation (infrared rays, visible light, ultraviolet rays, etc.) and ionizing radiation (electromagnetic radiation and particle radiation). Electromagnetic radiation includes, for example, X-rays and gamma rays, and particle radiation includes, for example, electron beams, proton beams, neutron beams, alpha rays, etc. "Detection system" refers to a general system that uses radiation to acquire images of an imaging target (subject, patient in the case of a medical detection system, etc.) as electronic data. "Image" may be a still image or a moving image.

[0012] The detection device 1 may include, for example, a pixel array 10, a readout circuit 110, a horizontal scanning circuit 40, a vertical scanning circuit 50, a ramp signal generation circuit 60, a counter 70, a timing control unit 80, and a signal processing unit 90. The detection device 1 may further include a plurality of row control line groups 11, a plurality of signal lines 12, a ramp signal line 61, and a count signal line 71.

[0013] The pixel array 10 has a plurality of pixels 100 arranged to form multiple rows and multiple columns. The vertical scanning circuit 50 is electrically connected to the plurality of pixels 100 row by row via a plurality of row control line groups 11. One row control line group 11 is provided in common to correspond to one row of pixels 100. One row control line group 11 may include a selection signal line for transmitting a selection signal and a reset signal line for transmitting a reset signal. The vertical scanning circuit 50 is electrically connected to the timing control unit 80.

[0014] The vertical scanning circuit 50 controls a plurality of pixels 100 in row units based on the timing signal supplied from the timing control unit 80. Each pixel 100 in each column of the row selected by the vertical scanning circuit 50 outputs a signal PIXSIG to the corresponding signal line 12 among the plurality of signal lines 12. Each of the plurality of signal lines 12 is connected to a plurality of rows of pixels 100 located in the corresponding column.

[0015] The ramp signal generation circuit 60 generates a ramp signal RAMP and supplies it to the plurality of AD converters 21 via the ramp signal line 61. The ramp signal generation circuit 60 can start an operation of changing the signal level of the ramp signal RAMP according to the passage of time based on the timing signal supplied from the timing control unit 80.

[0016] The readout circuit 110 includes a plurality of column circuits 20 respectively corresponding to a plurality of columns composed of a plurality of pixels 100. The column circuit 20 may include an AD converter 21, a column memory 30, a clip circuit 140, and a latch signal line 22. The column circuit 20 may include, for example, a sample and hold circuit, an amplifier circuit, etc. in front of the AD converter 21.

[0017] The clip circuit 140 clips the voltage of the signal line 12. The AD converter 21 may be connected to the column memory 30 by the latch signal line 22. Each signal line 12 outputs a signal PIXSIG (first signal) having a signal level corresponding to the signal generated by the photodiode from the pixel 100 connected thereto. The AD converter 21 may output a comparison result signal LATCH indicating the result of comparing the signal level of the signal PIXSIG output from the pixel 100 in the corresponding column to the signal line 12 with the ramp signal RAMP to the corresponding column memory 30.

[0018] The counter 70 counts the clock signal CLK supplied from the timing control unit 80 to generate a count signal COUNT. The counter 70 supplies the count signal COUNT to a plurality of column memories 30 via a count signal line 71. The count signal COUNT is a digital signal of multiple bits. The count signal line 71 typically has a plurality of bit lines for transmitting 1-bit signals and transmits the multiple-bit signals of the count signal COUNT in parallel.

[0019] The horizontal scanning circuit 40 sequentially selects each of the plurality of column memories 30. The column memory 30 selected by the horizontal scanning circuit 40 outputs a digital signal corresponding to the voltage at the signal level of the signal PIXSIG to the signal processing unit 90. The signal processing unit 90 performs various processes such as correction, amplification, and level shift on the digital signal input from the column memory 30 and outputs it to the outside of the detection device 1.

[0020] FIG. 2 shows a configuration example of one pixel 100 and a part (AD converter 21, clip circuit 140) of the readout circuit 110 (more specifically, the column circuit 20 connected to the pixel (100)) as the configuration of the detection device 1 of the first embodiment. The pixel 100 may include a photodiode PD, an amplification transistor M102 whose gate is connected to the output node of the photodiode PD, a reset transistor M101 for resetting the photodiode PD, and a selection transistor M103. The amplification transistor M102, the reset transistor M101, and the selection transistor M103 may be composed of MOS transistors. A row control line group 11 and a signal line 12 may be connected to the pixel 100. The row control line group 11 may include a reset signal line for transmitting a reset signal PRES and a selection signal line for transmitting a selection signal PSEL. The signal line 12 is connected to a current source 130 and supplies a signal PIXSIG having a signal level corresponding to the signal (the amount of radiation received by the photodiode PD) generated by the photodiode PD to the column circuit 20 of the readout circuit 110, more specifically, the AD converter 21.

[0021] The amplifying transistor M102 may have its drain connected to the power supply VDD, its gate connected to the cathode of the photodiode PD, and its source connected to the signal line 12. The selecting transistor M103 may have its source connected to the signal line 12, its drain connected to the source of the amplifying transistor M102, and its gate connected to the selection signal line that transmits the selection signal PSEL. Alternatively, the selecting transistor M103 may be placed in the path connecting the power supply VDD and the amplifying transistor M102.

[0022] The reset transistor M101 has its drain connected to the power supply VDD, its source connected to the cathode of the photodiode PD, and its gate connected to the reset signal line that transmits the reset signal PRES. The anode of the photodiode PD is connected to the reference voltage (GND). The amplification transistor M102 outputs a signal PIXSIG to the signal line 12, which has a signal level corresponding to the signal generated by the photodiode PD, i.e., the signal (potential) appearing at the output node (cathode) of the photodiode PD. The amplification transistor M102 operates as a source follower with the current supplied from the current source 130 connected to the signal line 12 and the voltage VDD connected to its drain.

[0023] The detection device 1 is not limited to a CMOS sensor or solid-state imaging device in which light is irradiated onto the pixel 100, but may be configured as, for example, an electron beam direct detection device in which an electron beam is irradiated onto the pixel 100. It is known that the characteristics of each MOS transistor in the pixel 100 deteriorate in proportion to the electron beam irradiation time, such as threshold fluctuations. Therefore, it is desirable to have a small number of MOS transistors constituting the pixel 100. Thus, in one example, the pixel 100 may be composed of the three MOS transistors described above.

[0024] The AD converter 21 may be composed of, for example, a comparator. The comparator configured as the AD converter 21 may include, for example, a differential amplifier circuit 200, capacitors C201 (capacitive elements), C202, and switches SW201, SW202. The differential amplifier circuit 200 has a non-inverting input node (I+) as the first input node, an inverting input node (I-) as the second input node, a non-inverting output node (O+) as the first output node, and an inverting output node (O-) as the second output node. The first input node and the first output node are in phase, and the second input node and the second output node are in phase. Furthermore, the first input node and the second input node constitute a differential input pair, and the first output node and the second output node constitute a differential output pair. The differential amplifier circuit 200 may be a fully differential amplifier circuit. The differential amplifier circuit 200 further includes an output node (O) that outputs the result of comparing the voltage applied to the first input node with the voltage applied to the second input node.

[0025] The non-inverting input node (I+) of the differential amplifier circuit 200 is connected via the signal line INP to the second terminal (one terminal) of the first capacitor C201 and the first terminal of the switch SW201. The first terminal (the other terminal) of the first capacitor C201 is connected to the signal line 12. The second terminal of the first switch SW201 is connected to the inverting output node (-) of the differential amplifier circuit 200. The first switch SW201 can be understood as a switch that short-circuits the non-inverting input node (I+) as the first input node of the differential amplifier circuit 200 and the inverting output node (O-) as the second output node of the differential amplifier circuit 200. The first switch SW201 is controlled by the control signal FB from the timing control unit 80.

[0026] The inverting input node (-) of the differential amplifier circuit 200 is connected to the second terminal of the second capacitor C202 and the second terminal of the second switch SW202 via the signal line INN. The first terminal of the second capacitor C202 is connected to the ramp signal line 61, to which the ramp signal RAMP is input. The second terminal of the second switch SW202 is connected to the non-inverting output node (+) of the differential amplifier circuit 200. The second switch SW202 can be understood as a switch that shorts the inverting input node (I-+) as the second input node of the differential amplifier circuit 200 and the non-inverting output node (O+) as the first output node of the differential amplifier circuit 200. The second switch SW202 is controlled by the control signal FB from the timing control unit 80.

[0027] Offset cancellation can be performed by controlling switches SW201 and SW202. The offset cancellation operation is an operation in which the signal level of the signal PIXSIG output to the signal line 12 according to the signal generated by the photodiode PD of pixel 100 is maintained while canceling the offset of the AD converter 21. After performing the offset cancellation operation, the AD converter 21 performs AD conversion on the change in the signal level after the offset cancellation operation. The output node (O) of the differential amplifier circuit 200 is connected to the latch signal line 22 and outputs a comparison result signal LATCH. The comparison result signal LATCH indicates the comparison result between the signal level of the signal PIXSIG output to the signal line 12 and the ramp signal RAMP.

[0028] The differential amplifier circuit 200 may have an inverting input node (I-) as the first input node, a non-inverting input node (IO) as the second input node, an inverting output node (O-) as the first output node, and a non-inverting output node (O+) as the second output node.

[0029] Furthermore, the AD converter 21 only needs to be capable of holding the voltage of the signal PIXSIG level (and ramp signal RAMP) (as an initial value) while canceling the offset of the AD converter 21, and is not limited to the above configuration.

[0030] The clipping circuit 140 may consist of, for example, a clipping transistor M141 made of a MOS transistor, switches SW141 and SW142, and a capacitor C141. The clipping circuit 140 only needs to have a configuration that can perform a clipping operation to limit the amplitude of the signal PIXSIG to a predetermined range, and is not limited to the configuration illustrated in Figure 2. Here, we will explain assuming that the voltage drop due to the threshold voltage of the clipping transistor M141 can be ignored. The clipping circuit 140 clips or limits the voltage of the signal line 12 according to the gate voltage of the clipping transistor M141.

[0031] The clip transistor M141 has its source connected to signal line 12 and switch SW141, and its drain connected to power supply VDD. The gate of clip transistor M141 is connected to the first terminal of switch SW141, the second terminal of switch SW142, and the second terminal of capacitor C141. The first terminal of capacitor C141 is supplied with a first voltage VCLIPSH. The first terminal of switch SW142 is supplied with a second voltage VCLIP. The first voltage VCLIPSH and the second voltage VCLI may be supplied from outside the detection device 1 or generated inside the detection device 1. The control terminal of switch SW142 is supplied with a first signal PCLIP from the timing control unit 80. The control terminal of switch SW141 is supplied with a second signal PCLIPSH from the timing control unit 80.

[0032] Switch SW141 conducts when the second signal PCLIPSH is at a high level and samples the signal PIXSIG into capacitor C141. When the second signal PCLIPSH transitions from a high level to a low level, switch SW141 transitions from a conduction state to a non-conduction state and holds the sampled signal PIXSIG into capacitor C141. By changing the first voltage CLISH, which is the first voltage V, while switch SW141 is in a non-conduction state, the gate voltage of clip transistor M141 can be controlled. Switch SW142 conducts when the second voltage PCLIP is at a high level and supplies the second voltage VCLIP to the gate of clip transistor M141. Switch SW142 needs to be made conduction when switch SW141 is in a non-conduction state.

[0033] The operation examples of the detection device 1 of the first embodiment will be described below with reference to Figures 3A and 3B. Figure 3A shows the first operation example of the detection device 1 of the first embodiment, and Figure 3B shows the second operation example of the detection device 1 of the first embodiment. The timing of the signal FB differs between the first and second operation examples. Figures 3A and 3B show operation examples of two rows of pixels 100. Period T1 is the signal readout period for the first row (or n-row plane) of pixels 100, and period T2 is the signal readout period for the second row (or n+1g plane) of pixels 100.

[0034] First, the first example of operation will be explained with reference to Figure 3A. Period T1 represents the operation when there is no accumulated charge in the photodiode PD of the selected pixel 100. Period T2 represents the operation when there is accumulated charge in the photodiode PD of the selected pixel 100. After the operation in periods T1 and T2, the operation in periods T1 and T2 is performed for the selected pixel 10 of the next row, and thereafter the same operation is repeated for subsequent rows.

[0035] First, let's explain period T2. At time t20, the timing control unit 80 sets the signal FB supplied to each column circuit 20 of the readout circuit 110 to a high level. This causes the first switch SW201 and the second switch SW202 of the AD converter 21 to conduct. The signal lines INP and INN of the AD converter 21 are reset to the voltages of the non-inverting output node (O+) and inverting output node (O-) of the differential amplifier circuit 200, respectively. The AD converter 21 is reset to a state where the offset voltage of the differential amplifier circuit 200 is held (as an initial value) so that it is canceled. This enables offset cancellation operation. Figures 3A and 3B show the operation when there is no offset voltage of the differential amplifier circuit 200 for the sake of simplicity.

[0036] At time t21, the vertical scanning circuit 50 raises the selection signal PSEL supplied to the selected row in the pixel array 10. This causes the selection transistor M103 of that row to conduct. The amplification transistor M102 of each pixel 100 in that row outputs a signal PIXSIG to the signal line 12, which has a signal level corresponding to the signal generated by the photodiode PD, in other words, the potential (stored charge) of the photodiode PD. As a result, the signal level of the signal PIXSIG changes.

[0037] At time t22, the timing control unit 80 lowers the signal FB supplied to the column circuit 20 of the readout circuit 110 to a low level. As a result, the first switch SW201 and the second switch SW202 of the AD converter 21 become non-conductive. This signifies the end of the offset cancellation operation. The signal PIXSIG is supplied to the first terminal of the first capacitor C201 of the AD converter 21. The second terminal of the first capacitor C201 of the AD converter 21 completes holding the voltage reset by the voltage at the inverting output node (O-) of the differential amplifier circuit 200. The ramp signal RAMP is supplied to the first terminal of the second capacitor C202 of the AD converter 21. At this time, the ramp signal generation circuit 60 sets the ramp signal RAMP to a predetermined reference voltage. The second terminal of the second capacitor C202 of the AD converter 21 completes holding the voltage reset at the non-inverting output node (O+) of the differential amplifier circuit 200. This series of operations enables the offset cancellation operation of the differential amplifier circuit 200 (AD converter 21). However, the reset voltage of the differential amplifier circuit 200 is superimposed with noise from the AD converter 21, such as noise generated when the first switch SW201 and the second switch SW202 are turned off.

[0038] At time t23, the ramp signal generation circuit 60 starts ramp signal RAMP slope operation. When the voltage (signal level) of signal line INP and the voltage of signal line INN become the same, the differential amplifier circuit 200 outputs a pulse lt21 to the comparison result signal LATCH. Then, the aforementioned AD conversion operation stores the digital signal in the column memory 30. This is the first AD conversion, and a digital signal corresponding to the reset voltage of the differential amplifier circuit 200, which includes noise from the AD converter 21, can be obtained.

[0039] At time t24, the vertical scanning circuit 50 raises the reset signal PRES to a high level. This causes the reset transistor M101 to conduct, resetting the photodiode PD. The signal PIXSIG then changes to a signal level corresponding to the reset voltage of the photodiode PD.

[0040] At time t25, the vertical scanning circuit 50 sets the reset signal PRES to a low level. This causes the reset transistor M101 to become non-conductive, and the reset of the photodiode PD is released. The difference (potential difference) between the signal level of the photodiode PD signal PIXSIG before the reset and the signal level of the photodiode PD signal PIXSIG after the reset, i.e., the change in signal level, becomes the pixel signal voltage Vpix corresponding to the accumulated charge of the photodiode PD.

[0041] At time t26, the ramp signal generation circuit 60 starts the slope operation of the ramp signal RAMP, and the second AD conversion is performed. The second AD conversion is performed on the change in the signal level of the pixel signal PIXSIG due to the reset of the photodiode PD by the reset transistor M101 after the first AD conversion. The differential amplifier circuit 200 outputs a pulse lt22 to the comparison result signal LATCH at a timing corresponding to the value of the pixel signal voltage Vpix, and the digital signal is held in the column memory 30. By subtracting the first AD conversion result from the second AD conversion result, a digital signal corresponding to the pixel signal voltage Vpix with the noise of the AD converter removed can be obtained. The AD converter 21 may be configured to output the value obtained by subtracting the first AD conversion result from the second AD conversion result.

[0042] Next, we will explain the operation during period T1. The operation during period T1 differs from the operation during period T2 only in that there is no accumulated charge in the photodiode PD. Therefore, we will only explain the difference here and omit the explanation of other operations.

[0043] At time t11, the signal level of signal PIXSIG has not changed. This is because there is no accumulated charge in the photodiode PD.

[0044] At time t12, the offset cancellation operation of the differential amplifier circuit 200 is performed, similar to that in period T2. The signal level of the signal PIXSIG at this time depends on the accumulated charge of the photodiode PD. The subsequent operation is the same as the operation in period T2.

[0045] Next, we will explain the second example of operation shown in Figure 3B. The second example of operation in Figure 3B differs from the first example of operation in Figure 3A only in the timing of raising the signal FB to a high level. The other timings and operations are the same, and a detailed explanation will be omitted.

[0046] The operation during period T2 will now be explained. At time t20, the timing control unit 80 does not raise the signal FB supplied to each column circuit 20 of the readout circuit 110 to a high level. Then, at time t200, the timing control unit 80 raises the signal FB to a high level. In this respect, the second operation example differs from the first operation example shown in Figure 3A.

[0047] At time t21, the vertical scanning circuit 50 sets the selection signal PSEL to a high level. In the second operating example, since the signal FB is at a low level at this point, the signal line INP of the AD converter 21 has not been reset. Therefore, the voltage of the signal line INP changes in accordance with the signal level of the signal PIXSIG via the first capacitor C201. If the voltage fluctuation of the signal line INP is large, errors may occur in the offset cancellation operation due to fluctuations in the power supply voltage VDD, etc. In that case, errors will also occur in the result of the first AD conversion. Therefore, as in the first operating example, it is desirable to set the signal FB to a high level before the signal level of the signal PIXSIG changes.

[0048] Next, the operation of the clipping circuit 140 in Figure 2 will be explained with reference to Figure 4. In the period T2 in Figure 4, the same timing as in the period T2 in Figures 3A and 3B is indicated by the same sign.

[0049] The voltage Vg_M141 (dashed line) indicates the gate voltage of the clipping transistor M141 of the clipping circuit 140. As mentioned above, the clipping circuit 140 clips the voltage of the signal line 12 so that it does not fall below the voltage Vg_M141.

[0050] At time t20, the first signal PCLIP is set to a high level. The switch SW142 of the clipping circuit 140 becomes conductive, and the voltage Vg_M141 changes to the second voltage VCLIP. The second voltage VCLIP is higher than the lower limit voltage at which the current source 130 operates.

[0051] At time t24, the first signal PCLIP is set to a low level. This causes switch SW142 of the clipping circuit 140 to become non-conductive. Next, the second signal PCLIPSH is set to a high level. This causes switch SW141 of the clipping circuit 140 to become conductive, and the voltage Vg_M141 changes to the signal level of signal PIXSIG. Next, the first voltage VCLIPSH is changed to the first reference voltage.

[0052] At time t27, the second signal PCLIPSH is set to a low level. This causes switch SW141 to become non-conductive, and the voltage Vg_M141 becomes the sampled and held value of the signal level of signal PIXSIG. At time t25, the first voltage VCLIPSH is changed to the second reference voltage. The difference between the first reference voltage and the second reference voltage is the voltage ΔVCLIPSH. Voltage Vg_M141 changes to a voltage lower by the voltage ΔVCLIPSH via capacitance C141. Voltage ΔVCLIPSH is set so that voltage Vg_M141 is lower than the voltage of signal PIXSIG.

[0053] At time t25, the reset signal PRES becomes low. As a result, the photodiode PD enters an accumulation state. Consider the case where the photodiode PD is irradiated with radiation during the second AD conversion in period T2. Without the clipping circuit 140, the signal level of signal PIXSIG changes during the second AD conversion, and it may not be possible to perform AD conversion according to the pixel signal voltage Vpix. However, by providing the clipping circuit 140, the signal level of signal PIXSIG is clipped according to the voltage Vg_M141 obtained by sampling and holding the signal level of signal PIXSIG at time t27. Therefore, AD conversion according to the voltage Vpix' can be performed. For example, in electron beam detection applications, it is sometimes necessary to determine the presence or absence of an electron beam. In this case, there is no problem if the voltage Vpix' is a voltage value sufficient to determine the presence or absence of an electron beam.

[0054] The signal PIXSIG' (dotted line) indicates a state where a threshold fluctuation occurs at pixel 100 due to the electron beam. Signal PIXSIG' is an example that assumes a voltage value ΔVth lower than signal PIXSIG due to a threshold fluctuation in the amplifying transistor M102.

[0055] The clipping circuit 140 performs clipping operations based on the signal level of signal PIXSIG' at time t24, even when the output of pixel 100 changes, such as with signal PIXSIG'. Therefore, even if a threshold fluctuation occurs at pixel 100, appropriate clipping can be performed on the output after the fluctuation.

[0056] According to the first embodiment, for example, it is possible to reduce the degradation of image quality due to noise in the AD converter and improve image quality.

[0057] In the above example, the readout circuit 110 is located on one side of the pixel array 10, but this is merely illustrative, and the present invention is not limited thereto. For example, multiple readout circuits 110 may be provided, such as by arranging readout circuits 110 on both sides of the pixel array 10. Also, multiple lamp signal generation circuits 60 and lamp signal lines 61 may be provided. When multiple lamp signal generation circuits 60 and lamp signal lines 61 are provided, it is preferable to adjust the gain for each column circuit 20 to which the lamp signal lines 61 are connected. Gain adjustment for each column circuit 20 can be performed by adjusting the gain within the lamp signal generation circuit 60, adjusting the gain in the signal processing unit 90, or adjusting the gain in an external system. Furthermore, the first switch SW201 may be connected to the second terminal of the first capacitor C201 and to a node to which the power supply voltage is supplied, as in Patent Document 1.

[0058] The second embodiment will be described below. Matters not mentioned as part of the second embodiment may follow those of the first embodiment. Figure 5 shows an example configuration of the detection device 1 of the second embodiment, which includes one pixel 100 and a readout circuit 110 (more specifically, a portion of the column circuit 20 connected to the pixel 100). In the second embodiment, the readout circuit 110 includes a sample-and-hold circuit 210 located between the signal line 12 and the AD converter 21. The sample-and-hold circuit 210 may include, for example, a buffer circuit 211, a capacitor C211, and a switch SW211.

[0059] The input node of the buffer circuit 211 is connected to the first terminal of capacitor C211 and the second terminal of switch SW211. The output node of the buffer circuit 211 is connected to the first terminal of the first capacitor C201 of the AD converter 21. The second terminal of capacitor C211 is connected to the reference voltage (GND). The first terminal of switch SW211 is connected to the signal line 12. Switch SW211 is controlled by the signal SH from the timing control unit 80. The other configurations are the same as in the first embodiment and are omitted from the description.

[0060] The operation example of the detection device 1 of the second embodiment will be described below with reference to Figure 6. Figure 6 describes the operation of two rows of pixels 100. Period T3 is the signal readout period for the first row (n-row plane) of pixels 100, and period T4 is the signal readout period for the second row (n+1 row) of pixels 100.

[0061] Period T3 represents the operation when there is no accumulated charge in the photodiode PD of the selected pixel 100. Period T4 represents the operation when there is accumulated charge in the photodiode PD of the selected pixel 100.

[0062] The operation of the sample-and-hold circuit 210 in Figure 5 will be explained with reference to period T4 in Figure 6. Period T3 in Figure 6 is the same operation as period T4, except for the accumulation state of the photodiode PD, so its explanation will be omitted. In addition, the operation described in the description of the first embodiment will be omitted.

[0063] At time t41, the vertical scanning circuit 50 raises the selection signal PSEL, which is supplied to the selected row in the pixel array 10, to a high level. This changes the signal level of signal PIXSIG, as in the first embodiment. However, in the second embodiment, because of the sample-and-hold circuit 210, the change in signal PIXSIG is not transmitted to the signal line INP during the period when signal SH is at a low level.

[0064] At time t410, the timing control unit 80 raises the signal FB supplied to the column circuit 20 to a high level. As described in the first embodiment, it is desirable that the signal FB be raised to a high level before the voltage of the signal line INP changes.

[0065] At time t411, the timing control unit 80 raises the signal SH supplied to the column circuit 20 of the readout circuit 110 to a high level. As a result, the switch SW211 of the sample-and-hold circuit 210 conducts, and the signal level of signal PIXSIG is sampled into capacitor C211.

[0066] At time t42, the timing control unit 80 lowers the signal FB supplied to the column circuit 20 of the readout circuit 110 to a low level. As a result, the offset cancellation operation of the differential amplifier circuit 200 (AD converter 21) is performed, as described in the first embodiment.

[0067] At time t412, the timing control unit 80 lowers the signal SH supplied to the column circuit 20 of the readout circuit 110 to a low level. As a result, the switch SW211 of the sample-and-hold circuit 210 becomes non-conductive, and the voltage of the signal PIXSIG is held across the capacitor C211.

[0068] At time t43, the ramp signal generation circuit 60 starts the slope operation of the ramp signal RAMP, and the first AD conversion is performed. At time t44, the vertical scanning circuit 50 sets the reset signal PRES to a high level. At time t45, the vertical scanning circuit 50 sets the reset signal PRES to a low level. At time t413, the timing control unit 80 sets the signal SH to a high level. As a result, the signal level of signal PIXSIG is sampled into capacitor C211. At time t414, the timing control unit 80 sets the signal SH to a low level. As a result, the signal level of signal PIXSIG is held in capacitor C211. At time t46, the ramp signal generation circuit 60 starts the slope operation of the ramp signal RAMP, and the second AD conversion is performed.

[0069] Similar to the first embodiment, noise from the AD converter 21 can be removed by subtracting the result of the first AD conversion from the result of the second AD conversion. Furthermore, the operation of the clipping circuit 140 is the same as in the first embodiment, so its explanation is omitted.

[0070] As described above, in the second embodiment, the AD converter 21 starts the offset cancellation operation before the signal level of the pixel signal PIXSIG is supplied to the AD converter 21 via the sample-and-hold circuit 210. The AD converter 21 starts the offset cancellation operation after a predetermined time (for example, the predetermined period is a set storage period) has elapsed since the photodiode PD was last reset by the reset transistor M101, and before the signal level of the pixel signal PIXSIG is supplied to the AD converter 21 via the sample-and-hold circuit 210.

[0071] In the second embodiment, the second AD conversion can be superimposed on the read operation of the next row's pixel 100. As explained in Figure 6, the second AD conversion in period T3 is performed in period T4. This allows periods T3 and T4 to be shortened, and a higher frame rate can be achieved.

[0072] This can be used in various systems, such as the detection device 1 described above. Such systems may be, for example, a camera (imaging device) or an electron beam detection system. The system may comprise, for example, the detection device 1 and a processing unit that processes the image detected using multiple pixels of the detection device 1.

[0073] The third embodiment will be described below. Matters not mentioned in the third embodiment may follow those of the first or second embodiment. Figure 7 shows a detection system incorporating the detection device 1.

[0074] The detection system 1100 shown in Figure 7 includes an imaging device 1101, an exposure control unit 1102, a radiation source 1103, and a computer 1104. The detection device 1 described in the first or second embodiment can be used as the imaging device 1101.

[0075] The radiation source 1103 begins irradiating with radiation in accordance with the exposure command from the exposure control unit 1102. The radiation emitted from the radiation source 1103 passes through the imaging target (subject) and enters the image sensor 1001 of the imaging device 1101. The radiation source 1103 stops emitting radiation in accordance with the stop command from the exposure control unit 1102.

[0076] The imaging device 1101 is a flat panel detector used for radiography, for example, in medical imaging diagnosis and non-destructive testing. The imaging device 1101 includes an imaging panel 100P which contains a direct conversion type image sensor 100 as a detection device. The imaging panel 100P can be a plate-shaped object sized to match the size of the object to be imaged. For example, the image sensor 100 has 3300 x 2800 pixels arranged on a substrate measuring 550 mm x 445 mm.

[0077] The imaging device 1101 includes the imaging panel 100P described above, a control unit 1105 for controlling the imaging panel 100P, and a signal processing unit 1106 for processing signals output from the imaging panel 1001P. The signal processing unit 1106 may determine the background component of the pixel signal output from the imaging panel 100P and perform a process of subtracting the background component from the pixel signal. The signal processing unit 1106 may include the functions of the signal processing unit 90 of the first and second embodiments and may output digital image data to the computer 1104. The signal processing unit 1106 may also generate a stop signal to stop the irradiation of radiation from the radiation source 1103 based on the signal output from the imaging panel 100P, for example. The stop signal is supplied to the exposure control unit 1102 via the computer 1104, and the exposure control unit 1102 sends a stop command to the radiation source 1103 in response to the stop signal.

[0078] The control unit 1105 may consist of, for example, a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), a general-purpose computer with a program installed, or a combination of all or part of these.

[0079] In this embodiment, the signal processing unit 1106 is shown as being located within the control unit 1105 or as a function of the control unit 1105, but is not limited to this. The control unit 1105 and the signal processing unit 1106 may each have a separate configuration. Furthermore, the signal processing unit 1106 may be located separately from the imaging device 1101. For example, the computer 1104 may have the functions of the signal processing unit 1106. For this reason, the signal processing unit 1106 can be included in the detection system 1100 as a signal processing device that processes signals output from the imaging device 1101.

[0080] Computer 1104 can control the imaging device 1101 and the exposure control unit 1102, and can receive radiation image data from the imaging device 1101 and process it for display as a radiation image. Computer 1104 can also function as an input unit for the user to input conditions for capturing radiation images.

[0081] For example, the exposure control unit 1102 has an exposure switch, and when the exposure switch is turned on by the user, it sends an exposure command to the radiation source 1103 and also sends a start notification to the computer 1104 indicating the start of radiation emission. Upon receiving the start notification, the computer 1104 responds by notifying the control unit 1105 of the imaging device 1101 of the start of radiation irradiation. In response, the control unit 1105 causes the imaging panel 100P to generate a signal corresponding to the incident radiation.

[0082] A fourth embodiment is described below. Figure 8 shows another example of a detection system incorporating a detection device.

[0083] Figure 8(a) shows the EQP as a detection system equipped with the detection device 1. The detection device 1 includes an image sensor 100, which is a semiconductor device, as well as a package PKG for mounting the image sensor 100.

[0084] The package PKG may include a substrate on which the image sensor 1001 is fixed, a cover made of glass or the like facing the image sensor 1001, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the image sensor 1001. The image sensor 1001 has a pixel region 100 in which pixels are arranged in a matrix and a peripheral region PR around it.

[0085] The EQP device may further comprise at least one of the following: an optical system OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical system OPT images radiation onto the detection device 1 and is, for example, a lens, shutter, or mirror. Depending on the type of radiation being handled, the optical system OPT may also image particle beams such as electron beams or proton beams onto the detection device 1. The control unit CTRL controls the detection device 1 and is, for example, an ASIC. The processing unit PRCS processes the signals output from the detection device 1 and is a device such as a CPU or ASIC for configuring an AFE (analog front end) or DFE (digital front end). The display device DSPL is an EL display device or liquid crystal display device that displays the information obtained by the detection device 1 in the form of a visible image or the like. The memory device MMRY is a magnetic device or semiconductor device that stores the information obtained by the detection device 1. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has a movable part or propulsion part such as a motor or engine.

[0086] The EQP device displays the signals output from the detection device 1 on the display device DSPL, or transmits them externally using a communication device (not shown) provided by the EQP device. For this purpose, it is preferable that the EQP device further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the detection device 1. The mechanical device MCHN may be controlled based on the signals output from the detection device 1.

[0087] The EQP device shown in Figure 8(a) may be a medical device such as an endoscope or radiological diagnostic equipment, a measuring instrument such as a distance sensor, or an analytical instrument such as an electron microscope.

[0088] Figure 8(b) is a schematic diagram showing the configuration of a transmission electron microscope (TEM) as an example of an EQP instrument. The EQP instrument as an electron microscope includes an electron source 1202 (electron gun), an illumination lens 1204, a vacuum chamber 1201 (microscope tube), an objective lens 1206, a magnification lens system 1207, and a camera 1209 as a detection device 1.

[0089] The electron beam 1203, an energy beam emitted from the electron source 1202, is focused by the irradiation lens 1204 and irradiated onto the sample S, which is held in the sample holder and is the target of analysis. The space through which the electron beam 1203 passes is formed by the vacuum chamber 1201 (lens tube), and this space is maintained under vacuum. The detection device 1 is positioned to face the vacuum space through which the electron beam 1203 passes. The electron beam 1203 that has passed through the sample S is magnified by the objective lens 1206 and the magnifying lens system 1207 and projected onto the detection device 1. The electron optical system for irradiating the sample S with the electron beam is called the irradiation optical system, and the electron optical system for imaging the electron beam that has passed through the sample S onto the detection device 1 is called the imaging optical system.

[0090] The electron source 1202 is controlled by the electron source control device 1211. The irradiation lens 1204 is controlled by the irradiation lens control device 1212. The objective lens 1206 is controlled by the objective lens control device 1213. The magnification lens system 1207 is controlled by the magnification lens system control device 1214. The sample holder control mechanism 1205 is controlled by the holder control device 1215, which controls the drive mechanism of the sample holder.

[0091] The electron beam 1203 that passes through the sample S is detected by the direct detector 1200 of the camera 1209. The output signal from the direct detector 1200 is processed by the signal processing device 1216 and the image processing device 1218, which function as the processing device PRCS, to generate an image signal. The generated image signal (transmitted electron image) is displayed on the image display monitor 1220 and the analysis monitor 1221, which correspond to the display device DSPL.

[0092] Camera 1209 is located at the bottom of the EQP instrument. Camera 1209 has a direct electron detector 1200, which corresponds to the image sensor 100. At least a portion of camera 1209 is located inside the camera 1209 so that it is exposed to the vacuum space formed by the vacuum chamber 1201.

[0093] The electron source control device 1211, the irradiation lens control device 1212, the objective lens control device 1213, the magnification lens system control device 1214, and the holder control device 1215 are each connected to the image processing device 1218. This allows for the exchange of data between them to set the imaging conditions of the electron microscope. For example, the electron beam irradiation rate can be set to 0.5 electrons / pix / frm or less. In this case, the electron source control device 1211 and the image processing device 1218 function as control means for controlling the radiation irradiation rate. Signals from the image processing device 1218 allow for the driving control of the sample holder and the setting of observation conditions for each lens.

[0094] The operator prepares the sample S to be photographed and sets the imaging conditions using the input device 1219 connected to the image processing device 1218. Predetermined data is input to the electron source control device 1211, the irradiation lens control device 1212, the objective lens control device 1213, and the magnification lens system control device 1214, respectively, to obtain the desired acceleration voltage, magnification, and observation mode. The operator also inputs conditions such as the number of continuous field images, the starting position for imaging, and the movement speed of the sample holder into the image processing device 1218 using the input device 1219, such as a mouse, keyboard, or touch panel. Alternatively, the image processing device 1218 may be configured to automatically set the conditions without operator input.

[0095] The detection systems described in the third and fourth embodiments above are merely illustrative, and the detection devices described in the first and second embodiments may be applied to other systems.

[0096] This specification and accompanying drawings include the following disclosures: (Item 1) A pixel including a photodiode, an amplification transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on the signal input from the pixel via the signal line, The AD converter performs an offset cancellation operation to maintain a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation. A detection device characterized by the following features. (Item 2) The AD converter performs a second AD conversion on the change in the signal level caused by the reset of the photodiode by the reset transistor after the first AD conversion. The detection device described in item 1, characterized by the features described herein. (Item 3) The AD converter starts the offset cancellation operation before the signal level is supplied to the AD converter. A detection device according to item 1 or 2, characterized by the above. (Item 4) The AD converter starts the offset cancellation operation after a predetermined time has elapsed since the photodiode was last reset by the reset transistor, and before the signal level is supplied to the AD converter. A detection device according to item 1 or 2, characterized by the above. (Item 5) The readout circuit further includes a sample-and-hold circuit positioned between the signal line and the AD converter. A detection device according to item 1 or 2, characterized by the above. (Item 6) The AD converter initiates the offset cancellation operation before the signal level is supplied to the AD converter via the sample-and-hold circuit. The detection device described in item 5, characterized by the features described herein. (Item 7) The AD converter starts the offset cancellation operation after a predetermined time has elapsed since the photodiode was last reset by the reset transistor, and before the signal level is supplied to the AD converter via the sample-and-hold circuit. The detection device described in item 5, characterized by the features described herein. (Item 8) The aforementioned AD converter A differential amplifier circuit having a first input node to which the signal level is applied, a second input node to which a ramp signal is applied, a first output node in phase with the first input node, and a second output node in phase with the second input node, A first capacitor is placed between the signal line and the first input node, A second capacitor is placed between the signal line and the second input node, A first switch that short-circuits the first input node and the second output node, A second switch that short-circuits the second input node and the first output node, A detection device according to any one of items 3 to 7, characterized by including the following: (Item 9) The offset cancellation operation is an operation that turns the first switch and the second switch into a conductive state and then into a non-conductive state. The detection device described in item 8, characterized by the features described above. (Item 10) The offset cancellation operation is initiated by making the first switch and the second switch conductive. The detection device according to item 9, characterized in that it is a detection device. (Item 11) The termination of the offset cancellation operation is to change the first switch and the second switch from a conductive state to a non-conductive state. The detection device described in item 10, characterized by the features described herein. (Item 12) The aforementioned first input node is a non-inverting input node, The aforementioned second input node is an inverting input node, The aforementioned first output node is a non-inverting output node, The previous second output node is an inverted output node. A detection device according to any one of items 8 to 11, characterized in that it is a detection device. (Item 13) The aforementioned photodiode detects an electron beam. A detection device according to any one of items 1 to 12, characterized by the features described herein. (Item 14) The readout circuit further includes a clipping circuit for clipping the voltage of the signal line. The detection device described in item 13, characterized by the features described herein. (Item 15) The clipping circuit clips the voltage of the signal line according to the voltage obtained by sampling and holding the voltage of the signal line. The detection device described in item 14, characterized by the features described herein. (Item 16) A pixel comprising a photodiode into which radiation is incident, an amplification transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on the signal input from the pixel via the signal line, The AD converter comprises a differential amplifier circuit having an input node and an output node, a capacitive element with one terminal connected to the input node and the other terminal connected to the signal line, and a switch connected to the one terminal. During the period in which a first signal, which is a signal level corresponding to the amount of radiation received by the photodiode, is output to one of the terminals, the switch transitions from the ON state to the OFF state. During the period between the switch going from the off state to the on state, a second signal, whose signal level corresponds to the reset level of the gate, is output to one of the terminals. The AD converter performs AD conversion during the period when the second signal is output to one of the terminals. A detection device characterized by the following features. (Item 17) The detection device according to item 16, characterized in that the switch is a switch that connects one of the terminals and the output node. (Item 18) The detection device according to item 16, characterized in that the switch is a switch that connects one of the terminals to a node to which a power supply voltage is supplied. (Item 19) The system comprises multiple pixels arranged in multiple rows, After the selection transistor of the pixel arranged in the first row transitions from the off state to the on state, the switch transitions from the on state to the off state. The detection device according to any one of items 16 to 18, characterized in that, during the period before the selection transistor transitions from the ON state to the OFF state, the reset transistor transitions from the OFF state to the ON state, and then transitions from the ON state to the OFF state to perform the AD conversion. (Item 20) A radiation source that irradiates the object to be imaged, A detection device as described in any one of items 1 to 19, A processing unit that processes an image detected using multiple pixels of the detection device, A detection system characterized by comprising the following features.

[0097] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0098] PD: Photodiode, M101: Reset transistor, M102: Amplifier transistor, M103: Selection transistor, 1: Detection device, 10: Pixel array, 100: Pixel, 12: Signal line, 21: AD converter, 110: Readout circuit

Claims

1. A pixel comprising a photodiode, an amplifying transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on the signal input from the pixel via the signal line, The AD converter performs an offset cancellation operation to maintain a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation. The AD converter performs a second AD conversion on the change in the signal level caused by the reset of the photodiode by the reset transistor after the first AD conversion. A detection device characterized by the following features.

2. The readout circuit further includes a sample-and-hold circuit positioned between the signal line and the AD converter. The detection device according to claim 1, characterized in that it is a detection device.

3. A pixel comprising a photodiode, an amplifying transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on the signal input from the pixel via the signal line, The AD converter performs an offset cancellation operation to maintain a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation. The AD converter starts the offset cancellation operation before the signal level is supplied to the AD converter. A detection device characterized by the following features.

4. A pixel comprising a photodiode, an amplifying transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on the signal input from the pixel via the signal line, The AD converter performs an offset cancellation operation to maintain a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation. The AD converter starts the offset cancellation operation after a predetermined time has elapsed since the photodiode was last reset by the reset transistor, and before the signal level is supplied to the AD converter. A detection device characterized by the following features.

5. A pixel comprising a photodiode, an amplifying transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on a signal input from the pixel via the signal line, and a sample-and-hold circuit disposed between the signal line and the AD converter. The AD converter performs an offset cancellation operation to maintain a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation. The AD converter initiates the offset cancellation operation before the signal level is supplied to the AD converter via the sample-and-hold circuit. A detection device characterized by the following features.

6. A pixel comprising a photodiode, an amplifying transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on a signal input from the pixel via the signal line, and a sample-and-hold circuit disposed between the signal line and the AD converter. The AD converter performs an offset cancellation operation to maintain a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation. The AD converter starts the offset cancellation operation after a predetermined time has elapsed since the photodiode was last reset by the reset transistor, and before the signal level is supplied to the AD converter via the sample-and-hold circuit. A detection device characterized by the following features.

7. The aforementioned AD converter is A differential amplifier circuit having a first input node to which the aforementioned signal level is applied, a second input node to which a ramp signal is applied, a first output node in phase with the first input node, and a second output node in phase with the second input node, A first capacitor is placed between the signal line and the first input node, A second capacitor is placed between the signal line and the second input node, A first switch that short-circuits the first input node and the second output node, A second switch that short-circuits the second input node and the first output node, The detection device according to claim 3, characterized by including the following:

8. The offset cancellation operation is an operation that turns the first switch and the second switch into a conductive state and then into a non-conductive state. The detection device according to claim 7.

9. The offset cancellation operation is initiated by making the first switch and the second switch conductive. The detection device according to claim 8.

10. The termination of the offset cancellation operation is to change the first switch and the second switch from a conductive state to a non-conductive state. The detection device according to claim 9.

11. The first input node is a non-inverting input node, The aforementioned second input node is an inverting input node, The aforementioned first output node is a non-inverting output node, The aforementioned second output node is an inverted output node. The detection device according to claim 7.

12. The aforementioned photodiode detects ionizing radiation. The detection device according to claim 1, characterized in that it is a detection device.

13. A pixel comprising a photodiode for detecting ionizing radiation, an amplification transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on the signal input from the pixel via the signal line, The AD converter performs an offset cancellation operation to maintain a signal level corresponding to the signal generated by the photodiode while canceling the offset of the AD converter, and performs a first AD conversion on the change in the signal level after the offset cancellation operation. The readout circuit further includes a clipping circuit for clipping the voltage of the signal line. A detection device characterized by the following features.

14. The clipping circuit clips the voltage of the signal line according to the voltage obtained by sampling and holding the voltage of the signal line. The detection device according to claim 13, characterized in that it is a detection device.

15. A pixel comprising a photodiode into which radiation is incident, an amplification transistor with a gate connected to the output node of the photodiode, a reset transistor for resetting the photodiode, and a selection transistor, The signal line connected to the aforementioned pixel, The system includes a readout circuit that reads a signal from the pixel via the signal line, The readout circuit includes an AD converter that performs AD conversion on the signal input from the pixel via the signal line, The AD converter comprises a differential amplifier circuit having an input node and an output node, a capacitive element with one terminal connected to the input node and the other terminal connected to the signal line, and a switch connected to the one terminal. During the period in which a first signal, which is a signal level corresponding to the amount of radiation received by the photodiode, is output to one of the terminals, the switch transitions from the ON state to the OFF state. During the period between the switch going from the off state to the on state, a second signal, whose signal level corresponds to the reset level of the gate, is output to one of the terminals. The AD converter performs AD conversion during the period when the second signal is output to one of the terminals. The system comprises multiple pixels arranged in multiple rows, After the selection transistor of the pixel arranged in the first row transitions from the off state to the on state, the switch transitions from the on state to the off state. During the period before the selection transistor transitions from the ON state to the OFF state, the reset transistor transitions from the OFF state to the ON state, then transitions from the ON state to the OFF state, and performs the AD conversion. A detection device characterized by the following features.

16. The detection device according to claim 15, characterized in that the switch is a switch that connects one of the terminals to the output node of the differential amplifier circuit.

17. The detection device according to claim 15, characterized in that the switch is a switch that connects one of the terminals to a node to which a power supply voltage is supplied.

18. A radiation source that irradiates the object to be imaged, A detection device according to any one of claims 1 to 17, A processing unit that processes an image detected using multiple pixels of the detection device, A detection system characterized by comprising the following features.

Images