Semiconductor equipment

Abstract

To provide a semiconductor device having a large storage capacity.SOLUTION: A semiconductor device includes first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. An opening is provided collectively for a structure in which the first insulator, the first conductor, the second insulator, the second conductor and the third insulator are stacked in the order. Further, the second conductor is selectively removed by etching in the opening. Then, the fourth insulator is formed on a side face of the opening, and the third conductor is formed in a region where the second conductor is removed. The first semiconductor, the fifth insulator and the second semiconductor are formed in order in the remaining opening to form a semiconductor device having a three-dimensional structure. A material containing a metal oxide may be applied for the first semiconductor, and a material containing a metal oxide or silicon may be applied for the second semiconductor.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention is: Process, machine, manufacture, or composition of matter This relates to the technology of one aspect of the present invention disclosed more specifically herein. The fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, Storage devices, processors, electronic devices, methods for driving them, methods for manufacturing them, and inspections thereof. A method, or a system having at least one of them, can be given as an example. [Background technology]

[0003] In recent years, various electronic devices such as personal computers, smartphones, and digital cameras have been used. The equipment includes a central processing unit (CPU) and a graphics processing unit. Electronic components such as memory devices and sensors are used, and these electronic components are miniaturized, Improvements have been made in various aspects, including lower power consumption.

[0004] In particular, the amount of data handled by the aforementioned electronic devices has been increasing in recent years. There is a need for storage devices with large capacities. Patent documents 1 and 2 describe multi-level data This document discloses a semiconductor device that enables writing and reading of data. To realize memory devices with hundreds of millions of units of capacity, technologies are needed to miniaturize the circuits contained within the memory device. It is being done.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present invention aims to provide a novel semiconductor device. Or, one aspect of the present invention aims to provide a storage device having a novel semiconductor device. Or, one aspect of the present invention aims to provide an electronic device using a storage device having a novel semiconductor device. Or, one aspect of the present invention aims to provide a storage device with a large data capacity. Or, one aspect of the present invention aims to provide a highly reliable storage device. It should be noted that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are those not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not necessarily solve all of the problems listed above and other problems.

Means for Solving the Problems

[0007] [[ID=4l]] ​​​​​​

[0008] (1) One aspect of the present invention is a semiconductor device having first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. The first conductor is provided on the upper surface of the first insulator, and the second insulator is provided on the upper surface of the first conductor. The second conductor is provided on the first upper surface of the second insulator, and the second conductor is provided on the first lower surface of the third insulator. The fourth insulator is provided so as to be continuous with a region including the side surface of the first insulator, the side surface of the first conductor, the side surface of the second insulator, the second upper surface of the second insulator, the side surface of the second conductor, the second lower surface of the third insulator, and the side surface of the third insulator. The third conductor is provided in a region overlapping the side surface of the second conductor among the region where the fourth insulator is formed. The first semiconductor is provided on the formation surface of the third conductor and in regions overlapping the side surface of the first insulator, the side surface of the second conductor, the side surface of the second insulator, and the side surface of the third insulator among the region where the fourth insulator is formed. The fifth insulator is provided on the formation surface of the first semiconductor, and the second semiconductor is provided on the formation surface of the fifth insulator. This is a semiconductor device characterized by this. [[ID=2l]] <00C0105>device.

[0009] (2) Alternatively, one aspect of the present invention is a semiconductor device having first to fifth insulators, first to third conductors, and first to third semiconductors. The first conductor is provided on the first upper surface of the first insulator, and the first conductor is provided on the first lower surface of the second insulator. The second conductor is provided on the first upper surface of the second insulator, and the second conductor is provided on the first lower surface of the third insulator. The third semiconductor is provided in a region including the second upper surface of the first insulator, the side surface of the first conductor, and the second lower surface of the second insulator. The fourth insulator is provided on the side surface of the first insulator, the formation surface of the first semiconductor, the side surface of the second insulator, and the second upper surface of the second insulator. A region including the surface, the side surface of the second conductor, the second lower surface of the third insulator, and the side surface of the third insulator. The third conductor is connected to the second conductive region in the region where the fourth insulator is formed. The first semiconductor is located in a region overlapping with the side of the body, and the third conductor is formed on the surface where the fourth insulator is formed. Of the formed regions, the region overlapping with the side surface of the first insulator and the region overlapping with the formation surface of the third semiconductor In the area where it is laid, the area where it overlaps with the side surface of the second insulator, and the area where it overlaps with the third insulator, The fifth insulator is located on the formation surface of the first semiconductor, and the second semiconductor is located on the formation surface of the fifth insulator. This semiconductor device is characterized by the following:

[0010] (3) Alternatively, one aspect of the present invention comprises a first to fourth insulator, a first to fourth conductor, and a first semiconductor. A semiconductor device having a first semiconductor and a second semiconductor, wherein the first insulator is on the first upper surface of the first conductor The second conductor is located on the first upper surface of the first insulator, and the second insulator is located on the first lower surface of the third conductor. The second conductor is located on the first lower surface of the second insulator, and the third insulator is located on the side of the first conductor. The surface, the second upper surface of the first conductor, the side surface of the first insulator, the second upper surface of the first insulator, and the second conductor The side surface of the electric body, the second lower surface of the second insulator, the side surface of the second insulator, and the second lower surface of the third conductor. The third conductor has a side surface and is connected to the fourth conductor, and the third insulator is formed on the fourth conductor. Of the regions, the region that overlaps with the side surface of the first insulator and the region that overlaps with the side surface of the second conductor The first semiconductor has a region that overlaps with the side surface of the second insulator, and the first semiconductor has a formation surface for the fourth conductor. Of the regions where the third insulator is formed, the region that overlaps with the first conductor and the region that overlaps with the third conductor The region to be laid and the fourth insulator are located on the formation surface of the first semiconductor, and the second semiconductor is the fourth This semiconductor device is characterized by having an insulating material on its forming surface.

[0011] (4) Alternatively, in one aspect of the present invention, in (1) to (3) above, the sixth insulator and the fifth conductor The sixth insulator is located on the formation surface of the second semiconductor, and the fourth conductor is in the shape of the sixth insulator. This semiconductor device is characterized by having a surface-forming feature.

[0012] (5) Alternatively, in one aspect of the present invention, in (1) to (4) above, the first semiconductor is a metal oxide This is a semiconductor device characterized by having [a certain feature].

[0013] (6) Alternatively, in one aspect of the present invention, in (1) to (5) above, the second semiconductor is a metal oxide This is a semiconductor device characterized by having [a certain feature].

[0014] (7) Alternatively, in one aspect of the present invention, in (1) to (5) above, the second semiconductor is silico This semiconductor device is characterized by having a n.

[0015] (8) Alternatively, one aspect of the present invention is a semiconductor device described in (1) to (7) above, and a peripheral circuit It is a memory device having the following features.

[0016] (9) Alternatively, one aspect of the present invention is an electronic device having the storage device described in (8) above and a housing. That is the case. [Effects of the Invention]

[0017] According to one aspect of the present invention, a novel semiconductor device can be provided. Or, according to the present invention In one embodiment, a storage device having a novel semiconductor device can be provided. According to one aspect of the invention, an electronic device using a memory device having a novel semiconductor device is provided. This is possible. Alternatively, according to one aspect of the present invention, a storage device with a large data capacity is provided. This is possible. Or, according to one aspect of the present invention, a highly reliable storage device can be provided. It is possible.

[0018] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the effect of, in some cases, the effects listed above. They may not always be present. [Brief explanation of the drawing]

[0019] [Figure 1] A circuit diagram showing an example configuration of a semiconductor device. [Figure 2] A circuit diagram showing an example configuration of a semiconductor device. [Figure 3] A circuit diagram showing an example configuration of a semiconductor device. [Figure 4] A flowchart illustrating an example of the operation of a semiconductor device. [Figure 5] A top view and a cross-sectional view illustrating an example configuration of a semiconductor device. [Figure 6] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 7] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 8] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 9]A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 10] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 11] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 12] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 13] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 14] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 15] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 16] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 17] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 18] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 19] A cross-sectional diagram illustrating a semiconductor device. [Figure 20] A cross-sectional diagram illustrating a semiconductor device. [Figure 21] A cross-sectional diagram illustrating a semiconductor device. [Figure 22] A block diagram showing an example of a storage device. [Figure 23] A diagram illustrating the range of atomic ratios for metal oxides. [Figure 24] A block diagram explaining the CPU. [Figure 25] A perspective view showing an example of an electronic device. [Figure 26] A perspective view showing an example of an electronic device. [Modes for carrying out the invention]

[0020] In this specification and elsewhere, "metal oxide" refers to a metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called Oxide Semiconductor or simply OS) They are classified into categories such as the following. For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes referred to as oxide semiconductors. In other words, metal oxides have amplification and rectification effects. and a channel formation region of a transistor having at least one switching action. If possible, the metal oxide is used as a metal oxide semiconductor (metal oxide semiconductor). It can be abbreviated as OS (iconductor). It can also be written as OS FET. In such cases, it can be rephrased as a transistor having a metal oxide or oxide semiconductor. It is possible.

[0021] Furthermore, in this specification, a transistor having silicon in the channel formation region is referred to as Si It is sometimes written as "transistor".

[0022] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0023] (Embodiment 1) In this embodiment, the circuit configuration, operating method, and of a semiconductor device according to one aspect of the disclosed invention are described. The manufacturing method will be explained. Note that in the following description, for example, "[x,y]" is This refers to the element in the xth or yth column, while "[z]" refers to the element in the zth row or zth column. These notations are omitted when there is no need to specify rows or columns.

[0024] <Example Circuit Configuration> First, the circuit configuration of the semiconductor device will be explained with reference to Figure 1(A). Figure 1(A The diagram shows a circuit diagram of n memory cells (where n is an integer greater than or equal to 1). This refers to memory cells MC[1] to MC[n] and the control system for them. Wiring WWL[1] to WWL[n] for the purpose of wiring, wiring RWL[1] to RWL[n] It has wiring WBL and wiring RBL. Note that wiring WBL functions as a write word line. The RWL wiring functions as the read word line, and the WBL wiring functions as the write bit line. It functions, and the RBL wiring acts as a read bit line.

[0025] Each memory cell MC consists of a transistor WTr, a transistor RTr, and a capacitive element C. It has S. The transistor RTr shown in Figure 1(A) has a back gate. It is a transistor, and by applying a potential to the back gate, the transistor RTr The key voltage can be varied. Note that the wiring BGL shown in Figure 1(A) is Each of the memory cells MC[1] to MC[n] has a transistor RTr It is electrically connected to the gate. Also, in the semiconductor device shown in Figure 1, the wiring BGL is The backgain of transistor RTr in a Morissel MC[1] or memory cell MC[n] It is not a configuration in which each of the back gates is electrically connected, but rather each of the back gates Alternatively, the devices may be electrically connected independently, each supplying a different potential to the others.

[0026] The channel formation region of the transistor WTr has a metal oxide as described in Embodiment 3. It is preferable to use indium, element M (for example, aluminum) In the case of metal oxides selected from one or more of the following (gallium, yttrium, tin, etc.) and zinc. Because the metal oxide functions as a wide-bandgap semiconductor, the metal oxide is cha Transistors included in the filament formation region have a very low off-current characteristic. By applying a transistor with these characteristics as the transistor WTr that holds the element, This allows data to be retained in the memory cell MC for a long time. This reduces the number of data refresh cycles, thereby reducing the power consumption of semiconductor devices. It is possible.

[0027] Furthermore, the channel formation region of transistor RTr is the field-effect transfer of the transistor. It is preferable to use a material that has a high degree of intensity. By using such a transistor, Semiconductor devices can operate faster. For example, the channel shape of the transistor RTr Materials included in the compounding region include metal oxides and silicon, as described in Embodiment 3. It may have a conductive material.

[0028] The transistor WTr functions as a write transistor, and the transistor RTr is a read transistor. It functions as a diverter transistor. It switches the on and off states of transistor WTr. This is done by the potential applied to the wiring WWL. It is controlled by the wiring RWL. The other electrode of the capacitive element CS is the gateway of the transistor RTr. It is electrically connected to the node. The other electrode of the capacitive element CS can be referred to as the memory node. This is possible. Each memory cell MC's memory node has the transients that the memory cell MC possesses. It is electrically connected to the first terminal of the staWTr.

[0029] Furthermore, the second terminal of transistor WTr is, in terms of circuit configuration, connected to the adjacent memory cell MC. It is electrically connected in series with the first terminal of transistor WTr. Similarly, The first terminal of transistor RTr is in series with the second terminal of the adjacent memory cell transistor RTr. Electrically connected. And the second transistor WTr of the memory cell MC[n] The terminal is electrically connected to the wiring WBL and the transistor R of the memory cell MC[n] The second terminal of Tr is electrically connected to wiring RBL. In this embodiment, The connection point between the second terminal of transistor RTr in the Morissel MC[n] and the wiring RBL is It is referred to as N1, and the first terminal of the transistor RTr of the memory cell MC[1] is N1. It will be referred to as node N2. Furthermore, in order to control the conductivity between node N1 and wiring RBL, A selection transistor may be connected in series with transistor RTr. Similarly, node N To control the conduction state between the wiring connected to 2 and node N2, transistor R A selection transistor may be connected in series with Tr.

[0030] Furthermore, one aspect of the present invention is not limited to the semiconductor device shown in Figure 1(A). Depending on the circumstances, situation, or as needed, the semiconductor device shown in Figure 1(A) may be used. The circuit configuration can be modified as appropriate. For example, one aspect of the present invention is shown in Figure 1(B). As shown, if necessary, a semiconductor device with a back gate also provided for the transistor WTr. This is also acceptable. Note that the semiconductor device shown in Figure 1(B) is the same as the one shown in Figure 1(A). In addition to the configuration of the semiconductor device, the challenges that the memory cell MC[1] to memory cell MC[n] have A back gate is provided on the inverter WTr, and wiring BGL and electrical wiring are connected to each of the back gates. The configuration is electrically connected. Furthermore, for example, one aspect of the present invention is shown in Figure 1(C). As described above, semiconductors without back gates for transistors RTr and WTr. It can also be used as a device.

[0031] By the way, if you want to further increase the memory capacity of the semiconductor device shown in Figures 1(A), 1(B), and 1(C) If the semiconductor devices shown in Figures 1(A), 1(B), and 1(C) are arranged in a matrix, For example, the semiconductor devices shown in Figure 1(B) are arranged in a matrix. In that case, the circuit configuration will be as shown in Figure 2.

[0032] The semiconductor device shown in Figure 2 is arranged in m rows, with the semiconductor device shown in Figure 2(B) forming one row (where m is 1 or less). The integers above are arranged side by side, with the RWL and WWL wirings noted on the same line. It is electrically connected to share the same configuration as the Recell MC. The conductive device is a semiconductor device in the shape of an n x m matrix, and the memory cell MC[1,1] It has memory cells MC[n,m]. Therefore, the semiconductor device shown in Figure 2 has wiring RWL. [1] or wiring RWL[n], wiring WWL[1] or wiring WWL[n], wiring RBL [1] or wiring RBL[m], wiring WBL[1] or WBL[m], wiring BGL[1 ] or wiring BGL[m] and are electrically connected by. Specifically, memory cells MC[j,i] (where j is an integer between 1 and n, and i is an integer between 1 and m, inclusive.) One electrode of the capacitive element CS is electrically connected to the wiring RWL[j], and the memory cell MC The gate of transistor WTr at [j,i] is electrically connected to wiring WWL[j]. The wiring WBL[i] is connected to the second terminal of transistor WTr of memory cell MC[n,i]. Electrically connected, wiring RBL[i] connects to transistor RT of memory cell MC[n,i]. It is electrically connected to the second terminal of r.

[0033] Figure 2 shows memory cell MC[1,1], memory cell MC[1,i], and memory cell M C[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC [j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[ n,m], wiring RWL[1], wiring RWL[j], wiring RWL[n], wiring WWL[1] Wiring WWL[j], Wiring WWL[n], Wiring RBL[1], Wiring RBL[i], Wiring R BL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[1] ], wiring BGL[i], wiring BGL[m], capacitive element CS, transistor WTr, transistor Only the stator RTr, node N1, and node N2 are shown in the diagram; other wiring, components, and symbols are not included. The symbols and signs have been omitted.

[0034] Furthermore, the semiconductor devices shown in Figure 2(C) are arranged in m columns (where m is an integer greater than or equal to 1). The arrangement is shown in Figure 3. Note that the semiconductor device shown in Figure 3 contains all the memory cells. The MC has a configuration in which each transistor does not have a back gate. Therefore, the semiconductor device shown in Figure 3 does not have wiring BGL. For placement, please refer to the description of the semiconductor device shown in Figure 2.

[0035] <Example of operation method> Next, an example of the operation method of the semiconductor device shown in Figures 1(A) to 1(C) will be explained. In the following explanation, "low-level potential" and "high-level potential" refer to specific potentials. It's not that the potential is the same; if the wiring is different, the specific potential may also be different. For example, wiring WW The low-level potential and high-level potential applied to L are, respectively, the same as the low-level potential applied to the wiring RWL. The Bell potential and high-level potential may be different potentials.

[0036] Furthermore, in this example of operation method, the wiring BGL shown in Figures 1(A) and (B), and Figure 1(B) The BGW[1] to BGW[n] shown contain transistors RTr and WTr. It is assumed that a potential within the normal operating range is applied beforehand. Therefore, Figure 1 ( The operation of the semiconductor devices shown in A) through (C) can be considered in a similar manner to one another.

[0037] Figure 4(A) is a timing chart showing an example of the operation of writing data to a semiconductor device. Figure 4(B) is a timing chart showing an example of data reading operation from a semiconductor device. The timing charts in Figures 4(A) and (B) are shown for wiring WWL[1] and distribution. Wire WWL[2], Wiring WWL[n], Wiring RWL[1], Wiring RWL[2], Wiring RWL [n], the change in potential magnitude at node N1 and node N2 is shown. Also, wiring W BL indicates the data supplied to the wiring WBL.

[0038] Figure 4(A) shows that each of the data D[1] to data D[n] is stored in memory cell MC[1]. This shows an example of writing to memory cell MC[n]. Note that data D[1] to data D[n] can be binary or multi-valued. Then, data D[1] to data D [n] is to be supplied from the wiring WBL. That is, as shown in Figures 1(A) to (C). In the circuit configuration of a semiconductor device, data is written from the memory cell MC[1] to the memory This process is carried out sequentially in cell MC[n].

[0039] Conversely, after writing data to memory cell MC[2], When attempting to write data, the system first reads the data already written to memory cell MC[2]. If you don't take it out and save it elsewhere, the data held in the memory cell MC[2] will be lost. The data is lost during the process of writing it to the Ricell MC[1].

[0040] In the circuit configuration of the semiconductor device shown in Figures 1(A) to (C), the memory cell MC[i]( i is an integer between 2 and n. When writing data to the memory cell MC[1] or To prevent overwriting of data held in memory cell MC[i-1], wiring WWL [1] or wiring WWL[i-1] is supplied with a low-level potential to the memory cell MC[1] or This turns off each transistor WTr in the memory cell MC[i-1]. Therefore, each of the memory cells MC[1] to MC[i-1] that are held This data can be protected.

[0041] Furthermore, when writing data to memory cell MC[i], the data is supplied from the wiring WBL. Therefore, a high-level potential is supplied to the wiring WWL[i] to the wiring WWL[n], and the memory Each transistor WTr in memory cell MC[i] to memory cell MC[n] is sufficient Turn it on. This will hold the data in the memory node of memory cell MC[i]. It is possible.

[0042] Furthermore, when writing data to the circuit configuration of the semiconductor device shown in Figures 1(A) to (C), Since the RBL line can be controlled independently, it is not necessary to set it to a specific potential, but for example, low-level electric current It can be set to this position. Also, the potential of the wiring RWL, i.e., node N1, is low level electric It can be set to a low level potential. In addition, the potential of node N2 can also be set to a low level potential. .

[0043] Based on the above, the example operation shown in the timing chart of Figure 4(A) will be explained. At time T10, wiring WWL[1] to wiring WWL[n], wiring RWL[1] to The potentials of wiring RWL[n], wiring WBL, node N1, and node N2 are low. It is at a Bell potential.

[0044] At time T11, a high-level potential is supplied to wiring WWL[1] through wiring WWL[n]. This is supplied. As a result, each of the memory cells MC[1] to MC[n] possesses The transistor WTr is then sufficiently turned ON. And the wiring WBL has data D[ 1] is supplied. Each of the memory cells MC[1] to MC[n] possesses Since transistor WTr is sufficiently ON, data D[1] is the memory cell. The data reaches the memory node of MC[1] and is written to.

[0045] At time T12, a low-level potential is supplied to wiring WWL[1], and wiring WWL[ 2) or wiring WWL[n] continues to be supplied with a high-level potential. This allows The transistor WTr in the Morissel MC[1] is turned off, and the memory cell MC[2 ] or each transistor WTr in memory cell MC[n] is in a sufficiently ON state And the data D[2] is supplied to the wiring WBL. Memory cell MC[2] Each transistor WTr in the memory cell MC[n] is in a sufficiently ON state. Therefore, data D[2] reaches the memory node of memory cell MC[2] and writes It is loaded. Also, the transistor WTr of the memory cell MC[1] is in the off state. Therefore, the data D[1] held in memory cell MC[1] is from this time T12 to time The data will not be lost during the write operation up to time T13.

[0046] Between time T13 and time T14, the memory between time T11 and time T12 The operation of writing data D[1] to cell MC[1] and the time from T12 to T13 The operation of writing data D[2] to the memory cell MC[2] in between, and similarly to each of the following, Data D[3] is sequentially stored in each of the memory cells MC[3] through MC[n-1]. Data D[n-1] is written to it. Specifically, data has already been written to the memory space. Memory cell MC[1] or memory cell MC[j-1] (where j is an integer between 3 and n-1) The transistor WTr is turned off, and the memory cell MC has no data written to it. [j] or the transistor WTr of the memory cell MC[n] is turned on sufficiently, Data D[j] is supplied from the wiring WBL and written to the memory node of the memory cell MC[j]. Then, when the writing of data D[j] to memory cell MC[j] is complete... With the transistor WTr of the memory cell MC[j] turned off, the wiring WBL The data D[j+1] is supplied and written to the memory node of the memory cell MC[j+1]. The operation should be performed. Note that the write operation when j is n-1 is described below, at time T14 This refers to the operation from [time] to T15.

[0047] At time T14, the wiring WWL[1] to wiring WWL[n-1] have a low-level potential. This is supplied, and the wiring WWL[n] continues to be supplied with a high-level potential. The transistor WTr in memory cell MC[1] to memory cell MC[n-1] is In this state, each transistor WTr in the memory cell MC[n] has sufficient power. The state becomes [undefined]. Then, data D[n] is supplied to the wiring WBL. Memory cell MC Each transistor WTr in [n] is sufficiently ON, so the data Data D[n] is written to the memory node of memory cell MC[n]. The transistor WTr of memory cell MC[1] to memory cell MC[n-1] is in the off state. Therefore, each of the memory cells MC[1] to MC[n-1] is stored The data D[1] to D[n-1] held are from time T14 to time T15 This data is not lost during the write operation.

[0048] As a result of the above operation, in any one of the semiconductor devices shown in Figures 1(A) to (C), Data can be written to the memory cell MC of the semiconductor device.

[0049] Figure 4(B) shows that each of the data D[1] to data D[n] is stored in the memory cell MC[1]. The example shows reading from memory cell MC[n]. Note that in this case, each memory cell To maintain the data held in the MC, the transistor WTr must be in the off state. Therefore, data is required from memory cell MC[1] to memory cell MC[n]. During the read operation, the potential of wiring WWL[1] to wiring WWL[n] is at a low level potential. Let's assume that.

[0050] In the semiconductor device circuit configuration shown in Figure 1, the data of a specific memory cell MC is read out. In this case, after ensuring that the transistor RTr of the other memory cell MC is sufficiently turned ON, The transistor RTr of the specific memory cell MC is operated in the saturation region. Furthermore, flow occurs between the source and drain of the transistor RTr in the specific memory cell MC. The current is determined by the source-drain voltage and the data held in that particular memory cell MC. It is determined according to Ta and.

[0051] For example, the memory cell MC[k] (where k is an integer between 1 and n) holds Let's consider the case where data is read. In this case, the memory cell M is excluded from the memory cell MC[k]. Each transistor RTr in C[1] or memory cell MC[n] is turned on sufficiently. To achieve this state, high Level potential is supplied.

[0052] On the other hand, the transistor RTr in the memory cell MC[k] is used to store the data. To enable the corresponding ON state, the wiring RWL[k] is connected to the memory cell MC[k] with the relevant data. The wiring RWL[k] needs to be at the same potential as when the code was written. The potential of the wiring RWL[k] during write and read operations is set to a low-level potential. think.

[0053] For example, apply a potential of +3V to node N1 and 0V to node N2. Floating the current, the potential of node N2 is measured. Excluding the wiring RWL[k] When the potential of the wiring RWL[1] to wiring RWL[n] is set to a high-level potential, memory The transients of memory cells MC[1] to MC[n], excluding MC[k] The transistor RTr is in a sufficiently ON state. Meanwhile, the transistor of the memory cell MC[k] The voltage between the first and second terminals of the RTr is equal to the potential of the gate of the transistor RTr. Since it is determined by the potential of node N1, the potential of node N2 is determined by the memory node of memory cell MC[k] It is determined by the data stored in the code.

[0054] In this way, the data held in the memory cell MC[k] can be read. ru.

[0055] Based on the above, the example operation shown in the timing chart in Figure 4(B) will be explained. At time T20, wiring WWL[1] to wiring WWL[n], wiring RWL[1] to The potentials of wiring RWL[n], wiring WBL, node N1, and node N2 are low. It is at a bell potential. In particular, node N2 is in a floating state. Each memory node of memory cell MC[1] to memory cell MC[n] contains data Assume that data D[1] through D[n] are stored.

[0056] At time T21, a low-level potential is supplied to wiring RWL[1], and wiring RWL[ 2) or wiring WWL[n] is supplied with a high-level potential. This allows the memory cell M Each transistor RTr in C[2] or memory cell MC[n] is sufficiently ON This is the state. Then, the transistor RTr of the memory cell MC[1] is the memory cell MC[ The ON state is determined according to the data D[1] held in the memory node of [1]. Potential V across line RBL RThis supplies V. As a result, the potential at node N1 is V R And so, node N The potential at point 2 is the potential at node N1, V R The potential of node N2 is the memory of memory cell MC[1] It is determined by the data held in the node. Here, the potential of node N2 is V D[1 ] Let's assume that the potential V of node N2 is... D[1] By measuring the memory cell M The data D[1] held in the memory node C[1] can be read.

[0057] At time T22, a low-level potential is supplied to wiring RWL[1] through wiring WWL[n]. It is supplied. Also, a low-level potential is supplied to node N2, and then node N2 is flooded. The wiring state is activated. In other words, between time T22 and time T23, the wiring RW The potentials of L[1] or wiring WWL[n] and node N2 are as follows: The situation will be the same as up to day 21. Note that the RBL wiring will continue to have a potential of V. R to supply Alternatively, a low-level potential may be supplied. In this example of operation, wiring RBL is at time T After 21, the potential V R It is assumed that the supply will continue.

[0058] At time T23, a low-level potential is supplied to wiring RWL[2], and wiring RWL[ 1], a high-level potential is supplied to the wiring RWL[3] to the wiring WWL[n]. Therefore, memory cell MC[1], memory cell MC[3], and memory cell MC[n] have Each transistor RTr is sufficiently turned ON. Then, the memory cell MC[2] The transistor RTr holds the data held in the memory node of the memory cell MC[2] It becomes an on state according to D[2]. Also, the potential V R is continuously supplied to the wiring RBL. As a result, the potential of node N2 is the potential V of node N1 R and the potential of node N2 is me determined according to the data held in the memory node of the memory cell MC[2]. Here, no the potential of node N2 is set to V D[2] . Then, the potential V of node N2 D[2] is measured to read out the data D[2] held in the memory node of the memory cell MC[2].

[0059] ​​​​​​​​​​​​​​​​​​​​​​​​​​​​Then, data D[j] can be read. Note that the memory cell MC[j] holds After reading data D[j] is complete, the wiring RWL prepares for the next reading operation. [1] or wiring WWL[n] is supplied with a low-level potential, and node N2 is supplied with a low-level potential. After supplying, node N2 is put into a floating state. Note that when j is n-1, this Preparation refers to the actions performed between time T25 and time T26.

[0060] At time T25, a low-level potential is supplied to wiring RWL[1] through wiring WWL[n]. It is supplied. Also, a low-level potential is supplied to node N2, and then node N2 is flooded. The wiring state is activated. In other words, between time T25 and time T26, the wiring RW The potentials of L[1] or wiring WWL[n] and node N2 are as follows: The situation will be the same as up to day 21. Note that the RBL wiring will continue to have a potential of V. R to supply Alternatively, a low-level potential may be supplied. In this example of operation, wiring RBL is at time T After 21, the potential V R It is assumed that the supply will continue.

[0061] At time T26, a low-level potential is supplied to wiring RWL[n], and wiring RWL[ A high-level potential is supplied to wiring WWL[n-1]. This allows memory cells to Each transistor RTr in memory cell MC[1] or memory cell MC[n-1] is It turns ON for a while. Then, the transistor RTr of the memory cell MC[n] is memory The ON state is determined according to the data D[n] held in the memory node of MC[n]. Furthermore, the wiring RBL has a potential V R The supply continues. This means that the power to node N2 The position is the potential V of node N1. R The potential of node N2 is the memory node of memory cell MC[n] It is determined according to the data held in. Here, the potential of node N2 is V D[n] tosu And the potential V of node N2. D[n] By measuring, the memory cell MC[n The data D[n] held in the memory node of ] can be read.

[0062] Through the operations described above, each memory cell of the semiconductor device shown in Figures 1(A) to (C) Data can be read from the MC.

[0063] <Examples of structures and manufacturing methods> The following describes the manufacturing method to help understand the structure of the semiconductor device of this embodiment. I will reveal it.

[0064] Figures 5(A) and (B) are schematic diagrams showing the semiconductor devices shown in Figures 1(A) to (C). Figure 5(A) shows a top view of the semiconductor device, and Figure 5(B) is a single point view of Figure 5(A). The cross-sectional view corresponding to the dashed line A1-A2 is shown.

[0065] The semiconductor device consists of a wiring RWL, a wiring WWL, and an insulator (hatched in Figure 5). The structure has a layered structure (a region that is not included) and an opening in the structure, A conductive PG is formed to fill the space. Wiring ER is formed on the conductive PG. As a result, wiring ER and wiring RWL or wiring WWL are electrically connected. Yes, they are.

[0066] In addition, the wiring RWL and wiring WWL pass through the structure in a single manner. An opening is formed. And in the area AR through which wiring RWL and wiring WWL pass, In order to provide the Morisel MC, an insulator, a conductor, and a semiconductor are formed in the opening. Furthermore, the conductor functions as wiring WBL and wiring RBL, and the semiconductor is It functions as the channel formation region of the transistor WTr and transistor RTr. In Figure 5, In the diagram, the region where an insulator, a conductor, and a semiconductor are formed in the opening is referred to as region HL. This indicates that the transistors in the memory cell MC are equipped with back gates. In this case, the conductor in region HL is used to electrically connect with the back gate. It can also function as a line BGL.

[0067] In other words, in Figure 5, the semiconductor device shown in any one of Figures 1(A), (B), or (C) is in region S. The semiconductor device configured in D1, as shown in Figure 2 or Figure 3, is configured in region SD2. This indicates that.

[0068] In the following fabrication method examples 1 and 2, memory cells MC are formed in region AR. I will explain the method.

[0069] <<Example of manufacturing method 1>> Figures 6 to 10 are cross-sectional views illustrating an example of the fabrication of the semiconductor device shown in Figure 1(A). In particular, the cross-sectional views of transistors WTr and RTr in the channel length direction are shown. In addition, in the cross-sectional views of Figures 6 to 10, some elements have been omitted from the illustration for clarity. They are doing it.

[0070] As shown in Figure 6(A), the semiconductor device in Figure 1(A) is located above the substrate (not shown). An insulator 101A is placed, a conductor 131A is placed on the insulator 101A, and a conductor An insulator 101B placed on 131A, and a conductor 132 placed on the insulator 101B A, an insulator 101C placed on the conductor 132A, and a placed on the insulator 101C A conductor 131B, an insulator 101D placed on the conductor 131B, and on the insulator 101D A conductor 132B is arranged on the conductor 132B, and an insulator 101E is arranged on the conductor 132B. Hereafter, the laminate having these multiple conductors and multiple insulators will be referred to as laminate 1. Write 00.

[0071] For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as the substrate. For example, an insulating substrate can be a glass substrate, a quartz substrate, a sapphire substrate, or a stabilized substrate. These include zirconia substrates (such as yttria-stabilized zirconia substrates) and resin substrates. Examples of semiconductor substrates include single-component semiconductor substrates such as silicon and germanium, or carbon Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, oxide Examples include compound semiconductor substrates made of gallium. Furthermore, insulation is provided inside the aforementioned semiconductor substrate. Semiconductor substrates having a body region, for example, SOI (Silicon On Insulator) Examples include substrates. Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. There are plates, etc. Or, there are substrates having metallic nitrides, substrates having metallic oxides, etc. Furthermore, a substrate in which a conductor or semiconductor is provided on an insulating substrate, and a semiconductor substrate with a conductor or a substrate with an insulator, a substrate with a semiconductor or insulator on a conductive substrate, etc. There are. Alternatively, you may use substrates on which elements are provided. Examples of such elements include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0072] Furthermore, a flexible substrate may be used as the substrate. One method for creating the transistor is to fabricate the transistor on a non-flexible substrate, and then the transistor Another method involves peeling off the material and transferring it to a flexible substrate. In that case, the non-flexible material... It is preferable to provide a release layer between the substrate and the transistor. Furthermore, the substrate may be made of woven fibers. A sheet, film, or foil may be used. The substrate may also be stretchable. Furthermore, the substrate may have the property of returning to its original shape when bending or pulling is stopped. Alternatively, it may have the property of not returning to its original shape. The substrate may be, for example, 5 μm to 700 μm thick. m or less, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm It has a region with a thickness of less than μm. When the substrate is thinned, semiconductor equipment with transistors is available. The weight can be reduced. Also, by making the substrate thinner, when using glass, etc. It may also have elasticity, or it may have the property of returning to its original shape when it is no longer bent or stretched. This can happen. Therefore, it is necessary to mitigate the impact on semiconductor devices on the substrate caused by drops, etc. This is possible. In other words, it is possible to provide a robust semiconductor device.

[0073] Examples of flexible substrates include metal, alloy, resin, or glass, These fibers can be used. A flexible substrate has a low coefficient of thermal expansion. Deformation due to the environment is suppressed, which is desirable. Examples of flexible substrates include wire Expansion rate is 1 × 10⁻⁶ -3 / K or less, 5×10 -5 / K or less, or 1 × 10 -5 / K or less Any material can be used. Examples of resins include polyester, polyolefin, and poly Examples include amides (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. In particular, aramid is suitable as a substrate for flexible substrates because of its low coefficient of thermal expansion. .

[0074] In the manufacturing example described in this embodiment, a heat treatment is included in the process, so the substrate Therefore, it is preferable to use a material that has high heat resistance and a low coefficient of thermal expansion.

[0075] Conductor 131A (Conductor 131B) functions as the wiring WWL shown in Figure 1(A), and The electrical element 132A (conductor 132B) functions as the RWL wiring shown in Figure 1(A).

[0076] Examples of conductors 131A, 131B, 132A, and 132B include, for example, Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium A material containing one or more metallic elements selected from um, beryllium, indium, ruthenium, etc. Materials can be used. Also, polycrystalline silicon containing impurity elements such as phosphorus is a representative example. High-electrical-conductivity semiconductors, such as nickel silicide, may also be used. .

[0077] Furthermore, the above-mentioned conductors, in particular conductor 131A and conductor 131B, are semiconductors 1 described later. 51, included in metal oxides applicable to semiconductors 152, 153a, and 153b. Conductive materials containing the aforementioned metal elements and oxygen may also be used. Conductive materials containing nitrogen may be used. For example, titanium nitride, tantalum nitride, and other nitrogen-containing materials. Conductive materials may be used. In addition, indium tin oxide and indium oxide containing tungsten oxide may be used. Indium oxide, indium zinc oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium tin oxide containing titanium oxide, indium zinc oxide, and silicon are added. Indium tin oxide with added nitrogen may also be used. In addition, nitrogen-containing indium gallium zinc acid may be used. Chemicals may also be used. By using such materials, water that may be mixed in from surrounding insulators, etc. It is sometimes possible to capture the raw material.

[0078] Furthermore, the above-mentioned conductor, in particular conductor 132A and conductor 132B, may be water or hydrogen, etc. It is preferable to use a conductive material that has the function of suppressing the permeation of impurities. For example, Tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are used. It is preferable that it be present, and it can be in the form of a single layer or multiple layers.

[0079] Furthermore, multiple conductive materials formed from the above materials may be stacked and used. For example, as described above. A laminated structure may be formed by combining a material containing a metallic element with a conductive material containing oxygen. Furthermore, a laminate combining the aforementioned metal element-containing material and a nitrogen-containing conductive material is also used. It may also be used as a structure. Furthermore, a material containing the aforementioned metal element, a conductive material containing oxygen, and nitrogen A laminated structure may be formed by combining conductive materials containing elements with other materials. In addition, a contact is made around the conductor. By applying an insulator having an excess oxygen region as the insulator, the conductive material in contact with the insulator... In the region where oxygen diffuses, this can occur. As a result, materials containing metal elements and oxygen A laminated structure can be formed by combining a conductive material containing with . Similarly, By applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, the conductivity In the region of the body that is in contact with the insulator, nitrogen may diffuse. This can cause metal elements to... A laminated structure can be formed by combining a material containing nitrogen with a conductive material containing nitrogen. .

[0080] Note that each of the conductors 131A, 131B, 132A, and 132B These may be made of the same material or different materials. Conductors 131A, 131B, and 132A constituting a semiconductor device according to one aspect of the invention The materials to be applied to the conductor 132B can be appropriately selected and used.

[0081] As insulators 101A to 101E, the concentration of impurities such as water or hydrogen is reduced. It is preferable that the material contains hydrogen in insulators 101A to 101E. The amount of desorption is determined by thermal desorption gas analysis (TDS (Thermal Desorption Sp)). In ectroscopy, in the range of 50°C to 500°C, hydrogen molecules are converted The calculated amount of desorption is converted to an amount per unit area of ​​any one of the insulators 101A to 101E. , 2 x 10 15 molecular / cm² 2 The following is preferably 1 × 10 15 molc ules / cm 2 The following is more preferable: 5 x 10 14 molecular / cm² 2 Below It is desirable to have it. Also, insulators 101A to 101E release oxygen when heated. It may also be formed using an insulator. As a result, as described above, conductor 131A, conductor 1 31B, conductor 132A, and conductor 132B are materials containing metal elements and a conductive material containing oxygen. A laminated structure can be created by combining materials.

[0082] Examples of insulators 101A to 101E include boron, carbon, nitrogen, oxygen, and f Electrolyte, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, gel Manium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum Insulators containing silicon dioxide can be used in single-layer or multi-layer configurations. Also, for example, silicon dioxide Materials containing silicon oxide or silicon nitride can be used.

[0083] In this specification, silicon oxidnitride refers to a material whose composition contains more oxygen than nitrogen. It refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, contains more nitrogen than oxygen. This indicates a material with a high concentration of [amount]. Furthermore, in this specification, aluminum oxide nitride is defined as [component]. It refers to a material in which the oxygen content is higher than the nitrogen content, and aluminum nitride oxide is a combination of these materials. This refers to materials with a higher nitrogen content than oxygen content.

[0084] In the next step, as shown in Figure 6(B), resist mask formation and etching processes are performed. Therefore, an opening 191 can be formed in the laminate 100 shown in Figure 6(A). .

[0085] The resist mask is formed using appropriate methods such as lithography, printing, and inkjet printing. It is possible to use a photomask when a resist mask is formed using an inkjet method. Therefore, manufacturing costs can be reduced. Also, regarding the etching process, dry etching is used. Either the etching method or the wet etching method may be used, or both may be used.

[0086] Then, as shown in Figure 7(A), etching is used to remove the side surface of the opening 191. The conductors 132A and 132B present in the surface are removed, and the recess 192A (recess) is removed from the side surface. Part 192B) is formed. Here, the conductor 132A (conductor 132B) is, A material in which the conductor 132A (conductor 132B) is selectively removed from the layer 100. (More than insulators 101A to 101E, and conductor 131A (conductor 131B) It is assumed that a material with a high tread rate is being used.

[0087] Furthermore, recess 192A (recess 192B) is a step in the semiconductor device manufacturing process shown in Figure 6(A). On each floor, a sacrificial layer is provided in the region where the opening 191 and recess 192A (recess 192B) are formed. Alternatively, the aperture 191 may be formed at the same time as the semiconductor device fabrication process shown in Figure 6(B). Furthermore, when the opening 191 is formed without providing a sacrificial layer, the recess 192A (recess 19 In some cases, 2B) can be formed.

[0088] In the next step, as shown in Figure 7(B), the side of the opening 191 shown in Figure 7(A), and The insulator 102 is formed in the aforementioned recess.

[0089] As the insulator 102, an insulating material having the function of suppressing oxygen permeation is used. Preferred. For example, as the insulator 102, silicon nitride, silicon oxide nitride, silicon nitride It is preferable to use aluminum nitride, aluminum nitride oxide, etc. By forming the insulator 102, oxygen enters through the insulator 102, as will be described later. This prevents a decrease in the conductivity of the conductor 133 due to oxidation of the conductor 133. .

[0090] In the next step, as shown in Figure 8(A), the side of the opening 191 shown in Figure 7(B), and A conductive film 133 is formed in the recessed area. In other words, a conductive film is formed on the surface where the insulator 102 is formed. The electric body 133 is formed.

[0091] As the conductor 133, the aforementioned conductors 131A, 131B, 132A, Materials applicable to the electrical body 132B can be used. In particular, among these materials, conductive It is preferable to apply a high-quality material to the conductor 133.

[0092] In the next step, as shown in Figure 8(B), resist mask formation and etching processes are performed. Therefore, the conductor 133 contained in the opening 191 remains only in the aforementioned recess. 33 is removed. This forms conductors 133a and 133b. At this time, the insulators 101A to 101E, the conductor 131A, and the conductor 131B A portion of the insulator 102 may be removed, as long as it is not exposed to the opening 191. .

[0093] For details on the formation of the resist mask and the etching process, please refer to the explanation in Figure 6(B). To pour a drink.

[0094] By the way, conductor 133a (conductor 133b) is, in addition to the capacitive element CS shown in Figure 1(A), It functions as an electrode. In other words, in region 181A (region 181B) shown in Figure 8(B) And there, a capacitive element CS is formed.

[0095] In the next step, as shown in FIG. 9(A), an insulator 10 located on the side surface of the opening 191 2, a semiconductor 151 is formed on the formation surfaces of the conductor 133a and the conductor 133b.

[0096] As the semiconductor 151, a material containing a metal oxide described in Embodiment 3 is preferably applied. Preferably.

[0097] By the way, when the semiconductor 151 contains a metal oxide, the insulator 102 in contact with the semiconductor 151<00​​​​​​​​​​​​​​​​​​​​​​​​​​​ The region on the formation surface of the conductor 133a (conductor 133b) is shown as region 151c. . In particular, region 151a is a region that overlaps with the side surface of the conductor 131A (conductor 131B). , region 151b overlaps with the side surface of the insulator 101A (insulator 101B to insulator 101E). Region 151c is in contact with the conductor 133a (conductor 133b). Therefore, there is a case where impurities such as hydrogen or water contained in the conductor 133a diffuse into the region 151c. As described above, when impurities such as water or hydrogen diffuse into the semiconductor 151, electrons that become carriers may be generated. Therefore, the region 151c may have a lower resistance. For this reason, the region 151c becomes a region with higher conductivity than the regions 151a and 151b.

[0099] Region 151a is a region that becomes the channel formation region of the transistor. Therefore, when the transistor is in the on state, the region 151a has a lower resistance, so the conductivity becomes higher than that of the region 151b.

[0100] In the next step, as shown in Fig. 9(B), the insulator 103 and the semiconductor 152 are sequentially formed on the formation surface of the semiconductor 151 located on the side surface of the opening 191.

[0101] As the insulator 103, a material applicable to the above-described insulator 102 can be used. [[ID=3�]]. In particular, when the semiconductor 151 contains a metal oxide, the insulator 102 is preferably an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen in addition to oxygen.

[0102] By the way, in the region 182A (region 182B) shown in Fig. 9(B), as shown in Fig. 1(A). A transistor WTr is configured. Specifically, in region 182A (region 182B) In this configuration, region 151a of semiconductor 151 serves as the channel formation region of transistor WTr. Each of the two regions 151b of semiconductor 151 is the source electrode of transistor WTr. It functions as the drain electrode, and conductor 132A acts as the gate electrode of transistor WTr. It works. In particular, when applying materials containing metal oxides as semiconductor 151, The zistar WTr will thus constitute an OS transistor.

[0103] As semiconductor 152, similar to semiconductor 151, it contains a metal oxide as described in Embodiment 3. Materials that can be used can be used. Also, as an alternative to semiconductor 152, silicon and other semiconductors can be used. Conductive materials can be used.

[0104] In the next step, as shown in Figure 10(A), an insulator 104 is formed on the formation surface of the semiconductor 152. A film is formed, and a conductor 134 is deposited so that the remaining openings 191 are filled.

[0105] As the insulator 104, a material applicable to the insulators 102 and 103 described above is used. It is possible.

[0106] The conductor 134 is the aforementioned conductor 131A, conductor 131B, conductor 132A, Materials applicable to conductors 132B, 133a, and 133b can be used. ru.

[0107] By the way, in region 183A (region 183B) shown in Figure 10(A), The transistor RTr shown is configured. Specifically, region 183A (region 183B) In this case, the region 151c of the semiconductor 151, the two regions 151b, and the conductor 133a (conductor 133b) function as the gate electrode of the transistor RTr, the semiconductor 152 functions as the channel formation region of the transistor RTr, and the conductor 134 functions as the back gate electrode of the transistor RTr. In particular, when a material containing a metal oxide is applied as the semiconductor 152, the transistor RTr constitutes an OS transistor.

[0108] By performing the steps from FIG. 6(A) to FIG. 10(A), the semiconductor device shown in FIG. 1(A) can be manufactured.

[0109] One aspect of the present invention is not limited to the configuration example of the semiconductor device shown in FIG. 10(A). One aspect of the present invention can be a configuration in which the semiconductor device shown in FIG. 10(A) is appropriately modified depending on the case, the situation, or the necessity

[0110] For example, as described above, one aspect of the present invention can be a semiconductor device in which the transistor WTr and the transistor RTr are not provided with a back gate as shown in FIG. 1(C). When manufacturing the semiconductor device shown in FIG. 1(C), in the process of manufacturing FIG. 1(A), <{ the steps shown in FIG. 10(B) may be performed instead of the steps shown in FIG. 10(A). In FIG. 10(B ), a step of forming an insulator 105 so that the opening 191 is filled is shown instead of the conductor 134 in FIG. 10(A). Note that the insulator 105 can be made of a material that can be applied as the insulator 104, for example.

[0111] Also, for example, one aspect of the present invention is to improve the switching characteristics of the Therefore, the gate electrode configuration of the transistor WTr is changed from the configuration shown in Figure 10(A). It may be modified. Figures 11(A), (B), and 12(A)(B) show the method for manufacturing the semiconductor device. This shows an example. In Figure 11(A), in Figure 6(B), there is on the side of the opening 191 The conductor 131A (conductor 131B) is removed, and the recess 193A (recess 193B) This shows the formation process. Here, the conductor 131A (conductor 131B) is: A material such that the conductor 131A (conductor 131B) is selectively removed from the laminate 100. Materials (conductor 132A (conductor 132B), insulator 101A to insulator 101E are more effective) Assume that high-quality materials (such as Chingrate) are being used.

[0112] Furthermore, recess 193A (recess 193B) is a step in the semiconductor device manufacturing process shown in Figure 6(A). On each floor, a sacrificial layer is provided in the region where the opening 191 and the recess 193A (recess 193B) are formed. Alternatively, the opening 191 may be formed simultaneously with the semiconductor device during the manufacturing process shown in Figure 6(B). Furthermore, when the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess 1) is automatically formed. 93B) can also be formed in some cases.

[0113] In the next step, as shown in Figure 11(B), the side of the opening 191 shown in Figure 11(A) A semiconductor 153 is formed in the recess 193A (recess 193B).

[0114] As the semiconductor 153, a material containing a metal oxide as described in Embodiment 3 is applied. It shall be done.

[0115] In the next step, as shown in Figure 12(A), resist mask formation and etching processes are performed. As a result, the semiconductor 153 remains only in the aforementioned recess 193A (recess 193B), The semiconductor 153 contained in part 191 is removed. Also, simultaneously with this process, or this process After the process, etching is performed to remove the conductor 132A (conductor 132B) and the recesses. Forms 192A (recess 192B).

[0116] Next, similar to the process in Figure 8(B), the semiconductor 153a (semiconductor) is applied to the side surface of the opening 191. An insulator 102 is formed to cover the conductor 153b). Semiconductor 153 (semiconductor 153b) For example, when a material containing a metal oxide is applied, semiconductor 153a (semiconductor 153b ) comes into contact with the insulator 102, causing impurities such as hydrogen and water contained in the insulator 102 to become semiconductors. It diffuses into body 153a (semiconductor 153b). Also, semiconductor 153a (semiconductor 153b) By contacting the conductor 133a (conductor 133b), the conductor 133a (conductor 133b) Impurities such as hydrogen and water contained in the semiconductor diffuse into semiconductor 153a (semiconductor 153b). Furthermore, semiconductor 153a (semiconductor 153b) has the role of collecting impurities such as hydrogen and water. This reduces the resistance of semiconductor 153a (semiconductor 153b), and the transistor WT It can function as the gate electrode of r. From here on, see Figures 9(A) to 10(A). By performing the same process as shown above, the semiconductor device shown in Figure 12(B) can be constructed. Cut.

[0117] Furthermore, for example, in one aspect of the present invention, the first terminal of the transistor WTr shown in Figure 1(A) Alternatively, to reduce the electrical resistance between the second terminal and the gate of transistor RTr. Therefore, the configuration of the gate electrode of transistor RTr is changed from the configuration shown in Figure 10(A). This is also acceptable. Figures 13(A) and (B) show an example of a method for fabricating the semiconductor device. Figure 1 In 3(A), the conductor 132A (conductor) is located on the side surface of the opening 191 in Figure 7(A). Not only is 132B removed, but insulators 101A to 101E are also removed. This shows the process in which recess 194B (recess 194A, recess 194C) is formed. So, as conductor 132A (conductor 132B) and insulators 101A to insulators 101E In the laminate 100, the conductive material 132A (conductive material 132B) and the insulator 101A to insulating material are included. A material from which the edge 101E is selectively removed (from conductor 131A (conductor 131B)) It is assumed that a material with a high etching rate is being used.

[0118] Furthermore, recess 194B (recess 194A, recess 194C) is the semiconductor device shown in Figure 6(A). During the manufacturing process, the opening 191 and the recess 194B (recess 194A, recess 194C) A sacrificial layer is provided in the region to be formed, and in the semiconductor device fabrication process shown in Figure 6(B), the opening 1 It may be formed together with 91. Also, when the opening 191 is formed without providing a sacrificial layer, In some cases, recesses 194B (recesses 194A and 194C) can be formed dynamically.

[0119] Furthermore, in Figure 13(A), in recess 194B (recess 194A, recess 194C), Edge body 101B, insulator 101C (insulator 101A, insulator 101D, insulator 101E) However, conductor 132A (conductor 132B) is removed more significantly, but conductor 13 Insulator 101B and insulator 101C (insulator 101A, insulator 132B) are better than 2A (conductor 132B). The edge material 101D and the insulator 101E) may be removed in larger quantities. Also, the insulator 101B , insulator 101C (insulator 101A, insulator 101D, insulator 101E), and conductor 13 2A (conductor 132B) may be formed to the same depth.

[0120] Figure 13(B) shows an example of the configuration of a semiconductor device when the process shown in Figure 13(A) is followed. After the process in Figure 13(A), the recess 194B (recess 194A, recess 194C) is filled. A conductive film 133 is formed in this manner, and the gate electrode of the transistor RTr is formed. Figure 1 In 3(A), the conductor 133a functions as the gate electrode of the transistor RTr, and the conductor Figures 133b and conductor 133c are shown. The following are shown in Figures 9(A) through 10(A). By performing a similar process, the semiconductor device shown in Figure 13(B) can be constructed. This semiconductor device has more semiconductor 151 and conductor 13 than the semiconductor device shown in Figure 10(A). The configuration has a larger contact area with 3a (conductor 133b). When a material containing a specific oxide is applied, the semiconductor device shown in Figure 13(B) is different from the one shown in Figure 10(A). Since region 151b shown is not present, the first terminal or the second terminal of transistor WTr This allows for a reduction in the electrical resistance between the gate of transistor RTr and the other element.

[0121] <<Example of manufacturing method 2>> Here, we will describe an example of a semiconductor device in this embodiment with a structure different from that of manufacturing method example 1. This will be explained using Figures 14 to 16.

[0122] Figures 14 to 16 show examples of the fabrication of the semiconductor device shown in Figure 1(A), similar to Figures 6 to 10. This is a cross-sectional diagram to explain the chain of transistors WTr and RTr. The images show cross-sectional views in the direction of the nellum's length. Furthermore, the cross-sectional views in Figures 14 to 16 are shown in relation to Figures 6 to 1. Similar to example 0, some elements have been omitted from the diagram for clarity.

[0123] The initial steps are explained in Figures 6(A) to 7(B) as described in Manufacturing Method Example 1. Please take the information into consideration.

[0124] The process shown in Figure 14(A) is a continuation of the process shown in Figure 7(B). Figure 14 In (A), semiconductors are applied to the side surface of the opening 191 shown in Figure 7(B) and to the recesses that are formed. The body 151 is formed. In other words, the semiconductor 151 is formed on the surface where the insulator 102 is formed.

[0125] It is preferable to use the semiconductor described in Embodiment 3 as the semiconductor 151.

[0126] In the next step, as shown in Figure 14(B), the side of the opening 191 shown in Figure 14(A) A conductive material 133 is formed in the recesses that are created.

[0127] For the conductor 133, refer to the description of the conductor 133 explained in Manufacturing Method Example 1.

[0128] In the next step, as shown in Figure 15(A), resist mask formation and etching processes are performed. As a result, the conductor included in the opening 191 remains in the aforementioned recess only, so that the conductor 133 remains in the recess. 133 is removed. This forms conductors 133a and 133b. Oh, at this time, if the insulator 102 is not exposed to the opening 191, then the semiconductor 151 It's okay if some parts are removed.

[0129] For details on the formation of the resist mask and the etching process, please refer to the explanation in Figure 6(B). To pour a drink.

[0130] By the way, conductor 133a (conductor 133b) is, in addition to the capacitive element CS shown in Figure 1(A), It functions as an electrode. In other words, in region 181A (region 181B) shown in Figure 15(A) A capacitive element CS is formed there.

[0131] For semiconductor 151, refer to the description of semiconductor 151 explained in manufacturing method example 1. Furthermore, if semiconductor 151 contains a metal oxide, semiconductor 151 is in region 151a, region It can be divided into region 151b and region 151c. Region 151a, region 151b, region 1 For 51c, refer to regions 151a, 151b, and 151c as explained in Fabrication Method Example 1. We will take the above information into consideration.

[0132] In the next step, as shown in Figure 15(B), the conductor 1 located on the side of the opening 191 An insulator 103 is formed on the formation surfaces of 33a, the conductor 133b, and the semiconductor 151, and then Then, a semiconductor 152 is formed on the surface where the insulator 103 is formed.

[0133] For the insulator 103, refer to the description of the insulator 103 explained in Manufacturing Method Example 1.

[0134] For semiconductor 152, refer to the description of semiconductor 152 explained in example 1 of the manufacturing method.

[0135] By the way, in region 182A (region 182B) shown in Figure 15(B), The transistor WTr shown is configured. Specifically, region 182A (region 182B) In this, region 151a of semiconductor 151 is the channel formation region of transistor WTr Functioning, each of the two regions 151b of semiconductor 151 is the source power of transistor WTr The electrode functions as a drain electrode, and the conductor 132A acts as the gate electrode of the transistor WTr. It functions in particular when using a material containing a metal oxide as semiconductor 151. The WTr transistor will constitute an OS transistor.

[0136] In the next step, as shown in Figure 16(A), an insulator 104 is formed on the formation surface of the semiconductor 152. A film is formed, and a conductor 134 is deposited so that the remaining openings 191 are filled.

[0137] For the insulator 104, refer to the description of the insulator 104 explained in Manufacturing Method Example 1.

[0138] For the conductor 134, refer to the description of the conductor 134 explained in Manufacturing Method Example 1.

[0139] By the way, in region 183A (region 183B) shown in Figure 16(A), The transistor RTr shown is configured. Specifically, region 183A (region 183B) In this, the semiconductor 151 has region 151c, two regions 151b, and the conductor 133a (conductor The electrode 133b) acts as the gate electrode of the transistor RTr, and the semiconductor 152 is the transistor It functions as a channel-forming region of transistor RTr, and the conductor 134 is the channel of transistor RTr. It functions as a gate electrode. In particular, materials containing metal oxides are applied as semiconductor 152. If this is the case, then transistor RTr constitutes an OS transistor.

[0140] By performing the steps from Figure 6(A) to Figure 7(B) and from Figure 14(A) to Figure 16(A), Therefore, the semiconductor device shown in Figure 1(A) can be fabricated.

[0141] One aspect of the present invention is not limited to the semiconductor device configuration example shown in Figure 16(A). One aspect of this may vary depending on the circumstances, or as needed, as shown in Figure 16(A). The conductor device can be modified as appropriate.

[0142] For example, one aspect of the present invention, as described above, is the transistor W shown in Figure 1(C) It is also possible to create a semiconductor device in which transistors RTr do not have back gates. To do so. When manufacturing the semiconductor device shown in Figure 1(C), in the process of manufacturing Figure 1(A) Instead of following the steps shown in Figure 16(A), you should follow the steps shown in Figure 16(B). Figure 16(B) So, instead of the conductor 134 in Figure 16(A), an insulator is used so that the opening 191 is filled. This shows the process of forming film 105. Note that insulator 105 may be, for example, insulator 104. Applicable materials can be used.

[0143] Furthermore, for example, one aspect of the present invention improves the switching characteristics of a transistor WTr. Therefore, the configuration of the gate electrode of the transistor WTr is changed from the configuration shown in Figure 16(A). It may be modified. Figure 17 shows an example of the configuration of the semiconductor device. The semiconductor device shown in Figure 17 When manufacturing, the recess 19 is as shown in the example configuration in Figure 12(B) described in Manufacturing Method Example 1. Semiconductor 153a (semiconductor 153b) is formed so that 3A (recess 193B) is filled. Furthermore, an insulating layer covers the semiconductor 153a (semiconductor 153b) with respect to the side surface of the opening 191. Body 102 is formed. After that, the same process as in Figures 14(A) to 16(A) is carried out. By doing so, the semiconductor device shown in Figure 17 can be constructed. The effects of doing so are explained in the example of manufacturing method 1, as shown in Figures 11(A), (B), and 12(A). Refer to the description in B).

[0144] Furthermore, for example, in one aspect of the present invention, the first terminal of the transistor WTr shown in Figure 1(A) Alternatively, to reduce the electrical resistance between the second terminal and the gate of transistor RTr. Therefore, the configuration of the gate electrode of transistor RTr is changed from the configuration shown in Figure 16(A). It is also possible. Figure 18 shows an example of the configuration of such a semiconductor device. The semiconductor device shown in Figure 18 can be constructed. When manufacturing, the example configuration shown in Figure 13(A), as explained in Manufacturing Method Example 1, is manufactured. After that, By performing the same process as shown in Figures 14(A) to 16(A), the semiconductor shown in Figure 18 is produced. A body device can be constructed. Note that the effects of constructing Figure 18 are shown in the example of the manufacturing method. Refer to the description of Figure 13(B) explained in section 1.

[0145] A semiconductor capable of holding a large amount of data can be produced by the above-described manufacturing method example 1 or manufacturing method example 2. The device can be manufactured.

[0146] Here, in region SD2 of the semiconductor device shown in Figure 5(B), the semiconductor device shown in Figure 10(A) is placed. Figure 19 shows the structure to which the cross-sectional view of the circuit configuration in Figure 1(A) is applied. Note that region SD1 is This corresponds to the memory cell MC. As shown in Figure 19, the conductors are wiring RWL and wiring WWL. The above-mentioned manufacturing method example 1 involves providing an opening in both the insulator and the laminated structure at once. Alternatively, by manufacturing as described in Manufacturing Method Example 2, the circuit configuration shown in Figure 1(A) can be realized. It is possible.

[0147] <Example of connection with peripheral circuits> The semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2 has a readout circuit in its lower layer, Peripheral circuits of the memory cell array, such as a recharge circuit, may be formed. In this case, silico A Si transistor is formed on a substrate or the like to constitute the peripheral circuit, and then the manufacturing method If, in Example 1 or Manufacturing Method Example 2, a semiconductor device according to one aspect of the present invention is formed on the peripheral circuit, Good. Figure 20(A) shows the peripheral circuit composed of planar Si transistors, and the upper layer Figure 21(A) shows a cross-sectional view in which a semiconductor device according to one aspect of the present invention is formed. The circuit is constructed with FIN-type Si transistors, and a semiconductor device according to one aspect of the present invention is placed on top of it. This is a formed cross-sectional view. Note that the semiconductor device shown in Figures 20(A) and 20(B) is just one example. Therefore, the configuration shown in Figure 10(A) is applied.

[0148] In Figures 20(A) and 21(A), the Si transistors constituting the peripheral circuit are located on the substrate. It is formed on 1700. The element isolation layer 1701 is formed between multiple Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed extending in the channel width direction, and is connected to other Si transistors, or It is connected to the conductor 1712 (not shown).

[0149] The substrate 1700 can be a single-crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. Conductor substrates, compound semiconductor substrates made of silicon germanium, and SOI substrates are used. It is possible.

[0150] Furthermore, the substrate 1700 can be, for example, a glass substrate, a quartz substrate, a plastic substrate, or a metal substrate. Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film, etc. Any of these may be used. Alternatively, a semiconductor element can be formed using one substrate, and then a semiconductor can be formed on another substrate. The conductive elements may be transposed. In Figures 20(A) and 21(A), as an example, substrate 170 An example using a single-crystal silicon wafer is shown in section 0.

[0151] Here, we will explain the details of Si transistors. The planar type is shown in Figure 20(A). The Si transistor shown here is a cross-sectional view in the channel length direction and is a planar type as shown in Figure 20(B). The Si transistor shown is a cross-sectional view in the channel width direction. Channel formation region 1793 provided in cellulose 1792, low-concentration impurity region 1794 and The high-concentration impurity region 1795 (these are collectively also simply called the impurity region), and the impurity region A conductive region 1796 provided in contact with the region, and a channel forming region 1793 provided A gate insulating film 1797 and a gate electrode 1790 provided on the gate insulating film 1797, The gate electrode 1790 has side wall insulating layers 1798 and 1799 provided on its side. In addition, metal silicide or the like may be used in the conductive region 1796.

[0152] Furthermore, the FIN-type Si transistor shown in Figure 21(A) has a cross-sectional view in the channel length direction. As shown, the FIN-type Si transistor shown in Figure 21(B) has a cross-sectional view in the channel width direction. The Si transistors shown in Figures 21(A) and (B) have a channel formation region 1793. The gate insulating film 1797 and gate electrode 179 have a convex shape, and along their side and top surfaces are the gate insulating film 1797 and gate electrode 179 A 0 is provided. In this embodiment, a part of the semiconductor substrate is processed to form a protrusion. Although this is shown, a semiconductor layer with a convex shape may be formed by processing the SOI substrate. The symbols shown in Figures 21(A) and (B) are the same as the symbols shown in Figures 20(A) and (B).

[0153] Furthermore, the insulators, conductors, semiconductors, etc. disclosed in this specification are subject to PVD (Phistory Vegetable Damping). cal vapor deposition) method, CVD (Chemical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, It can be formed by the Deposition method. For example, the PVD method is... Sputtering method, resistance heating deposition method, electron beam deposition method, PLD (Pulsed Laminate) Examples include the plasma deposition method. Furthermore, CVD methods include plasma deposition. Examples include formation using CVD methods and thermal CVD methods. In particular, thermal CVD methods include, for example... For example, MOCVD (Metal Organic Chemical Vapor Dep. Methods such as the (Issay) method and the ALD (Atomic Layer Deposition) method. Some examples include:

[0154] Thermal CVD is a film deposition method that does not use plasma, so defects can occur due to plasma damage. It has the advantage of never being accomplished.

[0155] In the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the chamber is subjected to atmospheric pressure. Alternatively, by applying reduced pressure and reacting the film near or on the substrate, the film can be deposited on the substrate. You may go.

[0156] Furthermore, the ALD method maintains atmospheric pressure or reduced pressure inside the chamber, and the raw material gas for the reaction is The gases are introduced into the chamber sequentially, and film deposition can be performed by repeating this gas introduction sequence. For example, by switching between each switching valve (also called a high-speed valve), two types or less The above raw material gases are supplied to the chamber in order, and the first is supplied in order to prevent the mixing of multiple types of raw material gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the raw material gas. A second raw material gas is introduced. If an inert gas is introduced at the same time, the inert gas is... It acts as a carrier gas, and also when introducing a second raw material gas, an inert gas is introduced at the same time. Good. Also, instead of introducing an inert gas, the first source gas was removed by vacuum evacuation. Later, a second raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate and the first thin A thin layer is formed, and it reacts with a second raw material gas that is introduced later, so that a second thin layer is formed against the first thin layer. Thin films are formed by stacking layers. The order of gas introduction is controlled until the desired thickness is achieved. By repeating this process multiple times, a thin film with excellent step coverage can be formed. (Thickness of the thin film) This can be adjusted by the number of times the gas introduction sequence is repeated, allowing for precise film thickness control. It is possible and suitable for fabricating miniature FETs.

[0157] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-G When forming an α-Zn-O film, trimethylindium (In(CH3)3), tri Methyl gallium (Ga(CH3)3) and dimethyl zinc (Zn(CH3)2) are used. Furthermore, the combinations are not limited to these, and triethylgallium can be substituted for trimethylgallium. It is also possible to use um(Ga(C2H5)3), and diethylzinc can be used instead of dimethylzinc. Zn(C2H5)2) can also be used.

[0158] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing hafnium precursor compounds (such as hafnium alkoxide or tetrakisdimethyl Hafnium amides such as TDMAH and Hf[N(CH3)2]4) Two types of gases are used: a raw material gas that is vaporized, and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamide)hafnium.

[0159] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, A liquid containing a medium and an aluminum precursor compound (trimethylaluminum (TMA, Al(C)) Two types of gases are used: a raw material gas obtained by vaporizing H3, etc., and H2O as an oxidizing agent. Other materials include tris(dimethylamide)aluminum and triisobutylaluminum. Luminium, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedi Examples include Honor.

[0160] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Chlorodisilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are removed. It is supplied and reacted with the adsorbed material.

[0161] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 The initial tungsten film is formed by sequentially introducing gas and B2H6 gas, and then WF A tungsten film is formed by sequentially introducing 6 gas and H2 gas. SiH4 gas may be used instead of S.

[0162] For example, oxide semiconductor films, such as In-Ga-Zn-, can be deposited using an ALD-based film deposition system. When forming an O film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. - An O layer is formed, and then Ga(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form a Ga An O layer is formed, and then Zn(CH3)2 gas and O3 gas are repeatedly introduced in sequence to form a Zn layer. An O layer is formed. Note that the order of these layers is not limited to this example. Also, these gases are used This forms mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers. It is permissible to do so. Furthermore, the water obtained by bubbling it with an inert gas such as Ar instead of O3 gas. While H2O gas can be used, it is preferable to use O3 gas, which does not contain H. In(C2H5)3 gas may be used instead of (CH3)3 gas. Also, Ga(CH 3) Ga(C2H5)3 gas may be used instead of 3 gas. Also, Zn(CH3)2 You may use gas.

[0163] Note that the configuration examples of the semiconductor device described in this embodiment can be combined with each other as appropriate. It can be done.

[0164] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0165] (Embodiment 2) This embodiment describes a storage device having the semiconductor device described in the above embodiment. I will reveal it.

[0166] Figure 22 shows an example of the configuration of a storage device. The storage device 2600 is connected to peripheral circuit 2601, and It has a memory cell array 2610. Peripheral circuit 2601 includes a low decoder 2621, and a power D-line driver circuit 2622, bit-line driver circuit 2630, output circuit 2640, control It has a roll logic circuit 2660.

[0167] The semiconductor device shown in Figure 1(A), (B), or (C) described in Embodiment 1 is a It can be applied to the Morisel array 2610.

[0168] The bit line driver circuit 2630 includes a column decoder 2631 and a pre-charge circuit 263 2. It has a sense amplifier 2633 and a programming circuit 2634. Pre-charge circuit 26 32 is node N1 (not shown in Figure 22) of the wiring RBL described in Embodiment 1. It has a function to precharge to a predetermined potential. The sense amplifier 2633 reads out the noise It has the function of acquiring the potential of N2 as a data signal and amplifying the said data signal. The amplified data signal is output via output circuit 2640 to the digital data signal RDATA. It is output to the outside of the storage device 2600.

[0169] Furthermore, the storage device 2600 receives a low power supply voltage (VSS) from an external source as the power supply voltage, and peripheral circuits. High power supply voltage (VDD) for path 2601, high power supply voltage (VI) for memory cell array 2610 L) is supplied.

[0170] Furthermore, the storage device 2600 contains control signals (CE, WE, RE) and address signals ADDR. The data signal WDATA is input from an external source. The address signal ADDR is used by the raw decoder. The data signal WDATA is input to 2621 and column decoder 2631 and is written to the writing circuit It will be entered into 2634.

[0171] The control logic circuit 2660 processes external input signals (CE, WE, RE). Then, control signals are generated for the low decoder 2621 and the column decoder 2631. , is the chip enable signal, WE is the write enable signal, and RE is the read This is the enable signal. The signal processed by the control logic circuit 2660 is this It is not limited to this; other control signals can be input as needed.

[0172] Furthermore, the aforementioned circuits and signals can be selected or omitted as needed.

[0173] Furthermore, a p-channel Si transistor and an oxide semiconductor (preferably) according to the embodiment described later. A transistor is used that includes an oxide containing In, Ga, and Zn in the channel formation region. By applying this to the storage device 2600, a compact storage device 2600 can be provided. We can provide a storage device 2600 that can reduce power consumption. Furthermore, we can improve the operating speed. A memory device 2600 capable of doing so can be provided. In particular, the Si transistor is p-channel type. By doing so, manufacturing costs can be kept low.

[0174] Note that the configuration example of this embodiment is not limited to the configuration shown in Figure 22. For example, peripheral circuit 26 A portion of 01, for example, the pre-charge circuit 2632 and / or the sense amplifier 2633, is stored in memory. The configuration may be modified as appropriate, such as by placing it in a lower layer of the cell array 2610.

[0175] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0176] (Embodiment 3) In this embodiment, the channel formation region of the OS transistor used in the above embodiment is included This section will primarily explain metal oxides.

[0177] The metal oxide preferably contains at least indium or zinc. In particular, indium It is preferable to include aluminum and zinc. In addition to these, aluminum, gallium, It is preferable that it contains yttrium or tin, etc. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Selected from neodymium, hafnium, tantalum, tungsten, or magnesium, etc. It may contain one or more types.

[0178] Here, the metal oxide is In-M-Zn oxide, which has indium, element M, and zinc. Let's consider the case where it is a substance. Note that element M is aluminum, gallium, yttrium or Examples include tin. Other elements that can be used for element M include boron, silicon, and titanium. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Examples include odymium, hafnium, tantalum, tungsten, and magnesium. However, these are elements. In some cases, M may be a combination of multiple elements as mentioned above.

[0179] Next, using Figures 23(A), 23(B), and 23(C), the metal according to the present invention This section describes the preferred range of atomic ratios of indium, element M, and zinc in oxides. Figures 23(A), 23(B), and 23(C) show the atomic ratio of oxygen. It will not be listed. Also, the number of atoms of indium, element M, and zinc in the metal oxide. Let the terms of the ratio be [In], [M], and [Zn].

[0180] In Figures 23(A), 23(B), and 23(C), the dashed line represents [In]:[M The line where the atomic ratio of ]:[Zn]=(1+α):(1-α):1 (-1≦α≦1), [In]:[M]:[Zn]=(1+α):(1-α):2 is the line where the atomic ratio is, The line [I]:[M]:[Zn]=(1+α):(1-α):3 represents the atomic ratio. The line where the atomic ratio of n]:[M]:[Zn]=(1+α):(1-α):4, and The line represents the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):5. vinegar.

[0181] Furthermore, the dashed line represents the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0) The line where the atomic ratio is [In]:[M]:[Zn]=2:1:β, [In [In]:[M]:[Zn] = 1:1:β is the atomic ratio line, [In]:[M]:[Zn The line where the atomic ratio of [In]:[M]:[Zn]=1:3:β The line represents the ratio of the number of atoms, and the atomic ratio is [In]:[M]:[Zn]=1:4:β. It represents a line.

[0182] Also, as shown in Figures 23(A), 23(B), and 23(C), [In]:[M]: Metal oxides with an atomic ratio of [Zn]=0:2:1, and values ​​near that, exhibit spinel-type crystal formation. It's easy to create a structure.

[0183] Furthermore, multiple phases may coexist within a metal oxide (e.g., two-phase coexistence, three-phase coexistence). Example For example, if the atomic ratio is in the vicinity of [In]:[M]:[Zn]=0:2:1, then spin Two phases, one with a crystalline structure and the other with a layered structure, tend to coexist. Also, the atomic ratio is [In]: When [M]:[Zn]=1:0:0, the crystal structure is of the Bixbyte type and layered. Two phases with the crystal structure tend to coexist. When multiple phases coexist in a metal oxide, different formations occur. Grain boundaries may form between crystal structures.

[0184] Region A shown in Figure 23(A) represents the indium, element M, and zinc present in the metal oxide. An example of a preferred range for the atomic ratio is shown.

[0185] By increasing the indium content of metal oxides, the carrier mobility of the metal oxides can be improved. The electron mobility can be increased. Therefore, metal oxides with a high indium content Compared to metal oxides with a low indium content, it exhibits higher carrier mobility.

[0186] On the other hand, when the content of indium and zinc in the metal oxide decreases, the carrier mobility decreases. It becomes lower. Therefore, the atomic ratio is [In]:[M]:[Zn]=0:1:0, and close to that. When the value is an adjacent value (for example, region C shown in Figure 23(C)), the insulating properties are high.

[0187] Therefore, a metal oxide according to one aspect of the present invention has high carrier mobility and few grain boundaries. It is preferable to have the atomic ratio shown in region A of Figure 23(A), which tends to result in a layered structure. It seems so.

[0188] In particular, in region B shown in Figure 23(B), within region A, CAAC(c-axis a (ligned crystalline)-OS is likely to form, and has high carrier mobility. A metal oxide is obtained.

[0189] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It is a crystal structure that is linked and distorted. The distortion refers to the region where multiple nanocrystals are linked. In this context, the orientation of the grid arrangement between a region with aligned grid arrangements and another region with aligned grid arrangements This refers to the parts that have changed.

[0190] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. There are also cases where the distortion has a grid arrangement such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bows) are present. It is not possible to confirm (also called 'ndary') crystal grains. In other words, due to the distortion of the lattice arrangement, It can be seen that the formation of the boundary is suppressed. This is because CAAC-OS is in the ab-plane direction. The oxygen atoms are not densely arranged, and the substitution of metal elements reduces the bond distance between atoms. This is thought to be because the distortion can be tolerated through changes and other processes.

[0191] CAAC-OS is a highly crystalline metal oxide. On the other hand, CAAC-OS has a clear bond. Since grain boundaries cannot be identified, a decrease in electron mobility caused by grain boundaries does not occur. It can be said that this is a problem. Also, the crystallinity of metal oxides decreases due to the inclusion of impurities and the formation of defects. Because this can occur, CAAC-OS is a metal oxide with few impurities or defects (such as oxygen deficiencies). It can be described as a substance. Therefore, metal oxides containing CAAC-OS have stable physical properties. Therefore, metal oxides containing CAAC-OS are heat-resistant and highly reliable.

[0192] Furthermore, region B is 4.1 from [In]:[M]:[Zn]=4:2:3, and its vicinity Includes adjacent values. Neighboring values ​​include, for example, [In]:[M]:[Zn]=5:3:4. Furthermore, region B is defined as [In]:[M]:[Zn]=5:1:6, and its neighboring values, and The values ​​include [In]:[M]:[Zn] = 5:1:7 and its neighbors.

[0193] Furthermore, the properties of metal oxides are not uniquely determined by the atomic ratio. Even with ratios, the properties of metal oxides can differ depending on the formation conditions. For example, metal acids When depositing a phosphate using a sputtering device, the atomic ratio deviates from the target atomic ratio. A film is formed. Also, depending on the substrate temperature during film formation, the amount of [Zn] may be greater than that of the target [Zn]. The [Zn] content of the film may decrease. Therefore, the region shown in the illustration is where the metal oxide exhibits specific characteristics. This region exhibits an atomic ratio that tends to have a certain property, and the boundary between region A and region C is not strictly defined. stomach.

[0194] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0195] (Embodiment 4) In this embodiment, the CPU that can be equipped with the semiconductor device of the above embodiment is described below. explain.

[0196] Figure 24 shows an example configuration of a CPU that partially uses the semiconductor device described in Embodiment 1. This is a block diagram.

[0197] The CPU shown in Figure 24 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (1189). The substrate 1190 is a semiconductor substrate, SOI base A plate, glass substrate, etc., is used. ROM1199 and ROM interface1189 are, It may also be provided on a separate chip. Of course, the CPU shown in Figure 24 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. A configuration including the CPU or arithmetic circuit shown in Figure 24 is considered one core, and a configuration including multiple such cores is considered... Alternatively, a configuration where each core operates in parallel, such as a GPU, is also possible. Furthermore, the number of bits that a CPU can handle in its internal arithmetic circuits and data bus is, for example, 8 bits, 16 bits. It can be 1 bit, 32 bits, 64 bits, etc.

[0198] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0199] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. It generates a dress and reads or writes to register 1196 depending on the CPU state. .

[0200] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0201] In the CPU shown in Figure 24, a memory cell is located in register 1196. The transistor shown in the previous embodiment can be used as the memory cell of TA1196. Cut.

[0202] In the CPU shown in Figure 24, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, the data will not be rewritten to the capacitive element. This process can be performed to stop the supply of power voltage to the memory cell in register 1196. ru.

[0203] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0204] (Embodiment 5) A memory card (for example, an SD card) that can be equipped with the storage device of the above embodiment. USB (Universal Serial Bus) memory, SSD (Solid) This can be applied to various removable storage devices such as State Drives. In this embodiment, several configuration examples of removable storage devices are explained using Figure 25. I will reveal it.

[0205] Figure 25(A) is a schematic diagram of a USB memory device. USB memory 5100 is housed in enclosure 5101 It has a cap 5102, a USB connector 5103, and a circuit board 5104. Circuit board 5104 It is housed in the enclosure 5101. The circuit board 5104 contains a memory device and a drive for the memory device. A circuit is provided for this purpose. For example, the circuit board 5104 has a memory chip 5105, a controller A roller chip 5106 is attached. The memory chip 5105 is in Embodiment 3. The memory cell array 2610, word line driver circuit 2622, and raw decoder 26 described above 21. Sense amplifier 2633, pre-charge circuit 2632, column decoder 2631, etc. It is incorporated. The controller chip 5106 specifically includes the processor, work machine It incorporates a memory chip, ECC circuit, etc. Note that the memory chip 5105 and controller are also included. The circuit configurations for each of the 5106 components are not limited to those described above, and may vary depending on the situation. Depending on the circumstances, the circuit configuration may be changed as appropriate. For example, word line driver circuit 2622, Low decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder The -der 2631 was incorporated into the controller chip 5106 instead of the memory chip 5105. This configuration is also acceptable. The USB connector 5103 is an interface for connecting to external devices. It functions as a system.

[0206] Figure 25(B) is a schematic diagram of the external appearance of an SD card, and Figure 25(C) shows the internal structure of an SD card. This is a schematic diagram of the structure. The SD card 5110 consists of a housing 5111, a connector 5112, and a circuit board. It has 5113. Connector 5112 serves as an interface for connecting to an external device. It functions. The circuit board 5113 is housed in the casing 5111. The circuit board 5113 has memory Circuits for driving memory chips and storage devices are provided. For example, the substrate 5113 has memory chips The chip 5114 and controller chip 5115 are installed. Memory chip 511 4 includes the memory cell array 2610 and the word line driver circuit 26 described in Embodiment 3. 22. Low decoder 2621, sense amplifier 2633, precharge circuit 2632, color It incorporates a 2631 decoder and other components. The controller chip 5115 contains a processor It incorporates a sasser, work memory, ECC circuit, etc. Note that the memory chip 5114 and The circuit configurations for each controller chip 5115 are not limited to those described above, and may vary depending on the situation. Depending on the circumstances, the circuit configuration may be modified as appropriate. For example, the word line driver. Circuit 2622, Low Decoder 2621, Sense Amplifier 2633, Precharge Circuit 263 2. The column decoder 2631 is connected to the controller chip 5114, not the memory chip 5114. It could also be incorporated into configuration 5.

[0207] By also providing a memory chip 5114 on the back side of the circuit board 5113, the SD card 5110 The capacity can be increased. Also, a wireless chip with wireless communication functionality can be placed on board 5113. It may be provided. This will enable wireless communication between the external device and the SD card 5110. This enables reading and writing data to the memory chip 5114.

[0208] Figure 25(D) is a schematic diagram of the external appearance of an SSD, and Figure 25(E) is a schematic diagram of the internal structure of an SSD. This is a diagram. The SSD5150 has a housing 5151, a connector 5152, and a circuit board 5153. Connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the casing 5151. The circuit board 5153 contains a storage device and a memory device. A circuit is provided to drive the device. For example, the circuit board 5153 has a memory chip 5154 Memory chip 5155 and controller chip 5156 are installed. The top 5154 includes the memory cell array 2610 described in Embodiment 3, and the word line dryer. Circuit 2622, Low Decoder 2621, Sense Amplifier 2633, Precharge Circuit 26 32. It incorporates a column decoder 2631, etc. There is also a memo on the back of circuit board 5153. By adding the Rechip 5154, the capacity of the SSD5150 can be increased. Chip 5155 has work memory built into it. For example, memory chip 5155 A DRAM chip can be used. The controller chip 5156 has a processor, E CC circuits and other components are incorporated. Note that memory chip 5154 and memory chip 515 The circuit configurations of 5 and the controller chip 5115 are not limited to those described above. Depending on the situation or circumstances, the circuit configuration may be changed as appropriate. For example, control The chip 5156 may also be provided with memory that functions as work memory.

[0209] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0210] (Embodiment 6) This embodiment provides an example of an electronic device to which the storage device of the above embodiment can be applied. I will explain this.

[0211] <Notebook personal computer> Figure 26(A) shows a notebook personal computer, consisting of a casing 5401 and a display unit 540 2. It has a keyboard 5403, a pointing device 5404, etc. One aspect of the present invention This storage device can be included in a notebook personal computer.

[0212] <Smartwatch> Figure 26(B) shows a smartwatch, a type of wearable device, with a housing 5901 It includes a display unit 5902, operation buttons 5903, a control element 5904, a band 5905, etc. A storage device according to one aspect of the present invention can be provided in a smartwatch. 5902 may use a display device that has the added function of a position input device. Furthermore, the function as a position input device is added by providing a touch panel on the display device. It is possible. Alternatively, the function as a position input device is a photoelectric sensor, also known as a photosensor. It can also be added by providing a conversion element in the pixel section of the display device. The 5903 has a power switch to activate the smartwatch, and the smartwatch app case... The buttons for operating the controls, volume control buttons, or the display unit 5902 can be turned on or off. It can be equipped with one of the following: a switch or the like. Also, as shown in Figure 26(B) The Towatch indicates that there are 2 operation buttons (5903), but the smartwatch has... The number of operation buttons is not limited to this. Also, the control element 5904 is a smartwatch It functions as a crown for setting the time. In addition, the control 5904 is used for functions other than time setting. It is used as an input interface for operating smartwatch applications. It may be done in this way. Note that in the smartwatch shown in Figure 26(B), the operator 590 The configuration has 4, but is not limited to this, and may also have a configuration without the operator 5904. That's fine.

[0213] <Video camera> Figure 26(C) shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 5 It has 803, an operation key 5804, a lens 5805, a connecting part 5806, etc. One embodiment of the present invention The video camera can be equipped with a memory device. Operation key 5804 and lens 58 05 is provided in the first housing 5801, and the display unit 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connecting part 5806. The connection is maintained, and the angle between the first housing 5801 and the second housing 5802 is determined by the connecting part 5806. It can be changed. The video on the display unit 5803 is connected to the first housing on the connection unit 5806. The configuration may also be such that the switching occurs according to the angle between 5801 and the second housing 5802.

[0214] <Mobile phone> Figure 26(D) shows a mobile phone with information terminal functionality, consisting of a housing 5501 and a display unit 55 It has 02, a microphone 5503, a speaker 5504, and an operation button 5505. One embodiment of the present invention The storage device can be installed in a mobile phone. Also, the display unit 5502 has a position input device. A display device with added positioning functionality may be used. This functionality can be added by providing a touch panel on the display device. The function as a position input device involves a photoelectric conversion element, also called a photosensor, which is used in the display device's image. It can also be added by providing it in the base part. Furthermore, a mobile phone can be connected to the operation button 5505. Power switch for turning on the device, buttons for operating mobile phone applications, volume control buttons. The device must also include a switch to turn the display unit 5502 on or off. It is possible.

[0215] Furthermore, the mobile phone shown in Figure 26(D) has two operation buttons 5505. However, the number of control buttons on a mobile phone is not limited to this. Also, although not shown in the diagram... The mobile phone shown in Figure 26(D) has a light-emitting device for use as a flashlight or illumination. It may also be a configuration that includes a placement.

[0216] <Television equipment> Figure 26(E) is a perspective view showing a television system. The television system consists of a housing 9 000, display unit 9001, speaker 9003, operation key 9005 (power switch, or (including operating switch), connection terminal 9006, sensor 9007 (force, displacement, position, velocity, acceleration) Speed, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field It measures electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation. A storage device according to one aspect of the present invention is provided for use in a television device. Television equipment can have a large screen, for example, 50 inches or more, or 100 inches. It is possible to incorporate a display unit 9001 with a size of 1 inch or larger.

[0217] <Mobile> The display device described above can also be applied to the area around the driver's seat of a moving vehicle.

[0218] For example, Figure 26(F) is a diagram showing the area around the windshield inside a car. Figure 26(F) shows the display panel 5701 and display panel 5 mounted on the dashboard. In addition to display panel 5703 (702), a display panel 5704 mounted on the pillar is also shown. It is.

[0219] Display panels 5701 to 5703 display navigation information, speedometer - Various information such as tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It can provide information. Also, the display items and layout displayed on the display panel are It can be modified as needed to suit the user's preferences, and the design can be enhanced. Display panels 5701 to 5703 can also be used as lighting devices. be.

[0220] The display panel 5704 displays images from an imaging device installed on the vehicle body. This allows for the correction of the blind spot (view obstructed by the pillars). In other words, on the outside of the car... By displaying images from the provided imaging means, blind spots are compensated for, and safety is enhanced. This is possible. Furthermore, by displaying images that fill in the gaps in the unseen areas, it becomes more natural and less jarring. Safety checks can be performed without any problems. The display panel 5704 can also be used as a lighting device. can.

[0221] A storage device according to one aspect of the present invention can be installed in a mobile device. For example, when displaying an image on display panel 5701 to display panel 5704, Frame memory for temporarily storing image data, and the system that drives the moving object. It can be used as a storage device to save programs, etc.

[0222] Additionally, although not shown in the illustrations, the electronic devices are shown in Figures 26(A) to (C), (E), and (F). This configuration may include a microphone and a speaker. With this configuration, for example, as described above This allows electronic devices to be equipped with voice input functionality.

[0223] Additionally, although not shown in the illustrations, the electronic devices are shown in Figures 26(A), (B), (D) through (F). This configuration may include a camera.

[0224] Also, although not shown in the illustrations, the electronic devices shown in Figures 26(A) to (F) are located inside the enclosure. Sensors (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration It may also be a configuration that includes a function for measuring motion, odor, or infrared radiation. In addition, the mobile phone shown in Figure 26(D) has a tilt detection sensor such as a gyroscope and an accelerometer. By providing a detection device that has a s, the orientation of the mobile phone (the mobile phone is in the vertical direction) can be determined. The device determines the orientation of the mobile phone and displays the screen of the display unit 5502 accordingly. It can be configured to switch automatically depending on the situation.

[0225] Also, although not shown in the illustrations, the electronic devices shown in Figures 26(A) to (F) are fingerprint, vein, The configuration may include a device that acquires biological information such as iris scans or voiceprints. By using this technology, it is possible to realize electronic devices with biometric authentication capabilities.

[0226] Furthermore, as the display unit of the electronic device shown in Figures 26(A) to (F), a flexible substrate is used. It may also be used. Specifically, the display unit has a transistor and a capacitor on a flexible substrate. The configuration may include elements and display elements. By applying this configuration, This includes not only housings with flat surfaces, such as the electronic devices shown in Figures 26(A) to (F), but also curved housings. This makes it possible to realize electronic devices with enclosures that have surfaces.

[0227] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0228] (Notes regarding the descriptions in this specification, etc.) A description of each component in the above embodiment is provided below.

[0229] <Notes relating to one aspect of the present invention described in the embodiments> The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to represent the present invention. This can be one embodiment. Furthermore, multiple configuration examples may be shown within a single embodiment. The combination allows for appropriate combinations of the configuration examples.

[0230] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one other content. It is possible to replace or otherwise perform actions such as [doing something else].

[0231] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0232] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even if only a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, even more diagrams can be constructed.

[0233] <Notes regarding ordinal numbers> In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. This was added to avoid that. Therefore, it does not limit the number of components. This does not limit the order of the components. Also, for example, in one of the embodiments described herein In the first embodiment, the component referred to in the first embodiment may be used in other embodiments or claims. It may also be considered a component referred to in "Section 2". Furthermore, for example, in this specification, etc. In one embodiment of the application, the component referred to as "first" is used in other embodiments or patents. Some details may be omitted within the scope of the claim.

[0234] <Notes regarding descriptions of drawings> The embodiments are described with reference to the drawings. However, the embodiments are many different. It is possible to implement it in any manner, without deviating from its purpose and scope, in any form It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, the present invention The invention of the embodiment is not to be interpreted as being limited to the description of the embodiment. In the configuration, the same reference numeral is used for identical parts or parts with similar functions across different drawings. We will use it throughout, and omit the explanation of its repetition.

[0235] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. The positional relationships are used for convenience in explaining them by referring to the diagram. The positional relationships between the components are The arrangement changes appropriately depending on the direction in which each component is described. Therefore, the words indicating the arrangement are specified in the specification. The explanation provided is not the only way to express the idea; it can be appropriately rephrased depending on the situation.

[0236] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly connected. It does not limit what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B are not in direct contact. This does not exclude those that include other components in between.

[0237] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are made with clarity in mind. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings. For example... , variations in signals, voltages, or currents due to noise, or signals due to timing discrepancies This can include variations in voltage, current, and other parameters.

[0238] Furthermore, in drawings, in perspective views and other similar views, some structural elements are used to ensure clarity of the drawings. In some cases, the original description may be omitted.

[0239] Furthermore, in the drawings, identical elements or elements with similar functions, elements of the same material, and In some cases, elements formed simultaneously may be given the same symbol, and the explanation for this repetition is as follows: It may be omitted in some cases.

[0240] <Notes regarding paraphrasable descriptions> In this specification and other documents, when describing the connection relationships of transistors, the source and drain are referred to as one The side is referred to as "either the source or the drain" (or the first electrode, or the first terminal), and the source The other side of the source and drain is referred to as "the other side of the source or drain" (or the second electrode, or the second terminal). It is indicated that the source and drain of a transistor are related to the structure or movement of the transistor. This is because it varies depending on the operating conditions, etc. Regarding the terminology for the source and drain of a transistor... Depending on the situation, you can use appropriate terms such as source (drain) terminal or source (drain) electrode. They can be replaced. Also, in this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. These may be referred to as terminals, or as the third terminal, fourth terminal, etc. The channel formation region refers to the region where a channel is formed by applying an electric potential to the gate. This region is formed, allowing current to flow between the source and drain.

[0241] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when the circuit The direction of the current may change during operation, which can cause the current to switch positions. In detailed documents, the terms "source" and "drain" may be used interchangeably. ru.

[0242] Furthermore, when the transistor described herein has two or more gates (this configuration (This is sometimes called a dual-gate structure), and these gates are called the first gate, the second gate and It can be called by name, or it can be called the front gate or back gate. In particular, "front gate" The phrases " " can be replaced with the phrase "gate". Also, The term "backgate" can be interchanged with the term "gate." The bottom gate is a region in the transistor fabrication process that is larger than the channel formation region. It refers to the terminal that is formed first, and the term "top gate" is used when manufacturing a transistor. This refers to terminals that are formed after the channel formation region.

[0243] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and This includes cases where the wiring is formed as an integrated unit.

[0244] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is a base This refers to the potential difference from the reference potential; for example, the reference potential is the ground potential (earth potential). If we consider it as electric potential, then voltage can be rephrased as electric potential. Ground potential is not necessarily 0V. This does not necessarily mean that. Furthermore, electric potential is relative, and depending on the reference potential, This may change the potential supplied to wiring, etc.

[0245] In this specification, the terms "membrane," "layer," etc. may be used in some cases or in some situations. Depending on the context, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive layer". In some cases, the term can be changed to "electromagnetic film." Alternatively, for example, "insulating film" could be used. In some cases, the term may be changed to "insulating layer." Or, depending on the circumstances... Alternatively, depending on the situation, you can replace terms such as "membrane" or "layer" with other terms. It is possible to use the term "conductor" instead of "conductive layer" or "conductive film". In some cases, the terminology can be changed. For example, terms such as "insulating layer" or "insulating film" can be used. In some cases, it may be possible to change the term to "insulator."

[0246] In this specification, terms such as "wiring," "signal line," and "power line" may be used as appropriate. Depending on the situation, they can be interchanged. For example, "wiring" and In some cases, it may be possible to change the term "signal line" to "signal line". Also, for example, In some cases, the term "wiring" can be changed to terms such as "power lines." Conversely, terms such as "signal line" and "power line" should be changed to the term "wiring." In some cases, this may be possible. Terms such as "power lines" may be changed to terms such as "signal lines." This is sometimes possible. Conversely, terms like "signal line" can also be used for "power line," etc. In some cases, it may be possible to change the terminology. Also, the "potential" applied to the wiring Change the terminology to a term like "signal," depending on the circumstances or situation. This is sometimes possible. Conversely, terms like "signal" can also be used in the context of "electric potential." It may be possible to change it to a different word.

[0247] <Notes regarding the definition of terms> The following explains the definitions of terms used in the above embodiment.

[0248] <<Regarding impurities in semiconductors>> Impurities in semiconductors refer to components other than the main components that make up the semiconductor layer, for example. Elements present in less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, affect semiconductors. The formation of Density of States (DOS) and carrier mobility In some cases, the quality may decrease, or the crystallinity may decrease. In the case of semiconductors, impurities that alter the properties of semiconductors include, for example, Group 1 elements and Group 2 elements. These include elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, for example, hydrogen (also found in water), lithium, sodium, silicon, boron, ri These include hydrogen, carbon, and nitrogen. In the case of oxide semiconductors, for example, the inclusion of impurities such as hydrogen can cause problems. This can lead to the formation of oxygen vacancies. Furthermore, if the semiconductor is a silicon layer, the semiconductor properties... Impurities that alter the composition include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and Group 1 elements. These include Group 3 elements and Group 15 elements.

[0249] <<About the switch>> In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow when it enters a certain state. Alternatively, it can refer to a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows.

[0250] For example, an electrical switch or a mechanical switch can be used. Furthermore, any switch that can control the current will suffice, and is not limited to any particular type.

[0251] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is.

[0252] Furthermore, when using a transistor as a switch, the "conductive state" of the transistor refers to: A state in which the source and drain electrodes of a transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of a transistor refers to the state where the source electrode and drain electrode of the transistor are connected. This refers to a state in which the poles can be considered electrically blocked. Note that a transistor is not simply a switch. When operating in this manner, the polarity (conductivity type) of the transistor is not particularly limited.

[0253] One example of a mechanical switch is a digital micromirror device (DMD). Switches using MEMS (Micro-Electro-Mechanical Systems) technology are Yes, it exists. The switch has electrodes that can be moved mechanically, and when those electrodes move... Therefore, it operates by controlling the states of conduction and non-conductivity.

[0254] <<About Connection>> In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. When they are directly connected, when X and Y are functionally connected, and when X and Y are directly connected This includes cases where a connection is made. Therefore, a predetermined connection relationship, for example, in the diagram or This includes not only connections shown in text, but also connections other than those shown in diagrams or text. It shall be considered as such.

[0255] Here, X, Y, etc., refer to the object (e.g., device, element, circuit, wiring, electrode, terminal). (Conductive film, layer, etc.)

[0256] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not it is released.

[0257] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc. ), voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0258] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are functionally connected) (When functionally connected with another circuit in between) and when X and Y are directly connected (That is, the case where X and Y are connected without another element or circuit in between) It shall be assumed that it is electrically connected. In other words, when explicitly stating that it is electrically connected, simply, This is equivalent to the case where it is explicitly stated only that it is "continued".

[0259] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (or Without an intermediary, X is electrically connected, and the drain (or second terminal, etc.) of the transistor is connected to X. If Y is electrically connected via (or without) Z2, or if the transistor's saw A part of Z1 (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are indirectly connected, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When they are connected and another part of Z2 is directly connected to Y, the following table It can be expressed.

[0260] For example, "X and Y and the source (or first terminal, etc.) and drain (or the first terminal) of the transistor" Terminals 2, etc., are electrically connected to each other, and X is the source of the transistor (or The electrical components are connected in the following order: the first terminal (or the second terminal), the transistor's drain (or the second terminal), and Y. It can be expressed as "connected to the source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as, "X is the source (or first terminal, etc.) of the transistor." Alternatively, "X is the source (or first terminal, etc.) of the transistor." Y is electrically connected to X, and the transient is electrically connected to X via the drain (or second terminal, etc.) and the drain. The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) It can be expressed as, "Y is provided in this connection order." Similar to these examples... By using a method of representation to specify the order of connections in a circuit configuration, the transition Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the starter. This allows us to determine the technical scope. Note that these expressions are just examples, and this... The method of expression is not limited to these. Here, X, Y, Z1, Z2 are objects (e.g., devices, (Examples include elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0261] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0262] <<Regarding parallel and perpendicular lines>> In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" refers to a state where two straight lines are positioned at an angle between -30° and 30°. Furthermore, "perpendicular" refers to a state where two straight lines are positioned at an angle between 80° and 100°. This refers to the case where the angle is between 85° and 95°. Furthermore, "approximately perpendicular" means This refers to a state where two straight lines are positioned at an angle between 60° and 120°. [Explanation of Symbols]

[0263] MC[1] Memory cell MC[2] Memory cell MC[n] Memory Cell MC[1,1] memory cell MC[j,1] Memory cell MC[n,1] Memory cell MC[1,i] Memory cell MC[j,i] Memory cell MC[n,i] Memory cell MC[1,m] Memory Cell MC[j,m] Memory Cell MC[n,m] memory cell WWL[1] Wiring WWL[2] Wiring WWL[j] Wiring WWL[n] wiring RWL[1] Wiring RWL[2] Wiring RWL[j] Wiring RWL[n] Wiring WBL Wiring WBL[1] Wiring WBL[i] Wiring WBL[m] Wiring RBL wiring RBL[1] Wiring RBL[i] Wiring RBL[m] Wiring BGL Wiring BGL[1] Wiring BGL[i] Wiring BGL[m] Wiring WTr transistor RTr transistor CS capacitive element N1 node N2 node PG conductor WWL wiring RWL wiring ER wiring HL area AR area SD1 area SD2 area 100-layer structure 101A Insulator 101B Insulator 101C insulator 101D Insulator 101E Insulator 102 Insulator 103 Insulator 104 Insulator 105 Insulator 131A Conductor 131B Conductor 132A Conductor 132B Conductor 133 Conductors 133a Conductor 133b Conductor 133c conductor 134 Conductors 151 Semiconductors 151a area 151b area 151c area 152 Semiconductors 153 Semiconductors 153a Semiconductor 153b Semiconductor 181A area 181B area 182A area 182B area 183A area 183B area 191 Opening 192A Recess 192B Recess 193A Recess 193B Recess 194A Recess 194B Recess 194C recess 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1189 ROM Interface 1190 circuit board 1700 circuit boards 1701 Element Isolation Layer 1712 Conductors 1730 Conductor 1790 🙏 1792 Well 1793 Channel formation region 1794 Low concentration impurity region 1795 High concentration impurity region 1796 Conductive region 1797 Gate insulating film 1798 Sidewall insulation layer 1799 Sidewall insulation layer 2600 storage device 2601 Peripheral Circuits 2610 memory cell array 2621 Low Decoder 2622 Word Line Driver Circuit 2630 bit line driver circuit 2631 Column Decoder 2632 Precharge Circuit 2633 SenseAmp 2634 Programming Circuit 2640 Output Circuit 2660 Control Logic Circuit 5100 USB flash drive 5101 enclosure 5102 Cap 5103 USB connector 5104 circuit board 5105 memory chip 5106 Controller Chip 5110 SD card 5111 enclosure 5112 connector 5113 circuit board 5114 memory chip 5115 Controller Chip 5150 SSD 5151 enclosure 5152 Connector 5153 circuit board 5154 memory chip 5155 memory chip 5156 Controller Chip 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5501 enclosure 5502 Display section 5503 Microphone 5504 Speaker 5505 Operation Buttons 5701 Display Panel 5702 Display Panel 5703 Display Panel 5704 Display Panel 5801 First cabinet 5802 Second cabinet 5803 Display section 5804 Operation Keys 5805 Lens 5806 Connection part 5901 enclosure 5902 Display section 5903 Operation Buttons 5904 Operator 5905 Band 9000 cabinets 9001 Display section 9003 Speaker 9005 Operation Keys 9006 Connection terminal 9007 Sensor

Claims

[Claim 1] A semiconductor device having a memory cell, The aforementioned memory cell is A first conductor and A first oxide semiconductor having a region surrounding the first conductor via a first insulator, A second oxide semiconductor having a region surrounding the first oxide semiconductor via a second insulator, A second conductor having a region in contact with the second oxide semiconductor and a region surrounding the second oxide semiconductor, A third conductor having a region surrounding the second conductor via a third insulator, In the region where the second oxide semiconductor and the second conductor are in contact, a fourth insulator is provided that surrounds the second conductor via the third insulator, The present invention comprises a fourth conductor having a region surrounding the second oxide semiconductor via the third insulator, The first conductor has the function of being the first gate electrode of the first transistor and the function of being the first gate electrode of the second transistor. The first oxide semiconductor functions as a channel formation region for the first transistor. The second oxide semiconductor functions as a channel formation region for the second transistor. The second conductor has the function of being the second gate electrode of the first transistor and the function of being one electrode of a capacitive element. The third conductor functions as the other electrode of the capacitive element. The fourth conductor functions as the second gate electrode of the second transistor. The second conductor is a semiconductor device having a region located above or below the fourth conductor.

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