Image sensor and imaging device

Abstract

To increase an aperture ratio even though imaging and focus detection signal acquisition can be realized by a global electronic shutter.SOLUTION: A solid-state imaging device 4 includes a plurality of pixels PX each including a plurality of photoelectric conversion units PDa and PDb that generates and accumulate charges according to incident light, a first charge holding unit CH in which a charge is transferred and held, a plurality of first switches TXa1 and TXb1 that electrically connects and disconnects the plurality of photoelectric conversion units PDa and PDb and the first charge holding unit CH, respectively, a second charge holding unit FD to which the charge is transferred from the first charge holding unit CH and held, a second switch TX2 that electrically connects and disconnects between the first charge holding unit CH and the second charge holding unit FD, and an amplification unit AMP that outputs a signal corresponding to the charge held in the second charge holding unit FD.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

Background Art

[0002] In a CMOS image sensor, global electronic shutter technology is known. When a configuration is adopted to obtain a focus detection signal by the pupil division phase difference method using the global electronic shutter technology, the aperture ratio is reduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Means for Solving the Problems

[0004] A solid-state imaging device according to a first aspect includes a plurality of photoelectric conversion units that generate and accumulate charges in response to incident light, a first charge holding unit in which the charges are transferred and held, a plurality of first switches that electrically connect and disconnect between each of the plurality of photoelectric conversion units and the first charge holding unit, a second charge holding unit in which the charges are transferred and held from the first charge holding unit, a second switch that electrically connects and disconnects between the first charge holding unit and the second charge holding unit, and an amplification unit that outputs a signal corresponding to the charges held in the second charge holding unit, and includes a plurality of pixels provided with these components.

[0005] A solid-state image sensor according to the second embodiment includes a control unit that controls the plurality of first switches and the second switches such that, when reading an image signal from the pixels, the second switch is turned off, the plurality of first switches are turned on, and after the charge accumulated in the plurality of photoelectric conversion units is transferred to and held in the first charge holding unit, the plurality of first switches are turned off, the second switches are turned on, and the charge held in the first charge holding unit is transferred to and held in the second charge holding unit.

[0006] A solid-state image sensor according to a third embodiment includes a control unit that controls the plurality of first switches and the second switches such that, when reading a focus detection signal from the pixel in the first or second embodiment, the second switch is turned off, some of the plurality of first switches are turned on, the remaining first switches are turned off, the charge stored in the photoelectric conversion unit corresponding to the some of the first switches is transferred to and held in the first charge holding unit, and then the plurality of first switches are turned off, the second switches are turned on, and the charge held in the first charge holding unit is transferred to and held in the second charge holding unit.

[0007] The solid-state image sensor according to the fourth embodiment is such that, in any of the first to third embodiments, two or more pixels among the plurality of pixels share the second charge holding unit and the amplification unit.

[0008] A solid-state image sensor according to the fifth embodiment comprises a plurality of pixels, each containing: first and second photoelectric conversion units that generate and store charge in response to incident light; a first charge holding unit to which the charge generated and stored by the first photoelectric conversion unit is transferred and held; a first switch that electrically connects and disconnects the first photoelectric conversion unit and the first charge holding unit; a second charge holding unit to which the charge is transferred and held from the first charge holding unit and / or the second photoelectric conversion unit; second and third switches that electrically connect and disconnect the first charge holding unit and the second charge holding unit; a fourth switch that, together with the third switch, electrically connects and disconnects the second photoelectric conversion unit and the second charge holding unit; and an amplification unit that outputs a signal corresponding to the charge held in the second charge holding unit.

[0009] The solid-state image sensor according to the sixth embodiment includes a control unit that controls the first to fourth switches such that, when reading an image signal from the pixels, the third switch is turned off, the first, second, and fourth switches are turned on, and after the charge accumulated in the first and second photoelectric conversion units is transferred to and held in the first charge holding unit, the first and fourth switches are turned off, the second and third switches are turned on, and the charge held in the first charge holding unit is transferred to and held in the second charge holding unit.

[0010] The solid-state image sensor according to the seventh embodiment includes a control unit that controls the first to fourth switches such that, when reading a focus detection signal from the pixels in the fifth or sixth embodiment, the second switch is turned off, the first, third and fourth switches are turned on, the charge stored in the first photoelectric conversion unit is transferred to and held in the first charge holding unit, and the charge stored in the second photoelectric conversion unit is transferred to and held in the second charge holding unit, and then the first and fourth switches are turned off, the second and third switches are turned on, and the charge held in the first charge holding unit is transferred to and held in the second charge holding unit.

[0011] The imaging device according to the eighth aspect includes a solid-state imaging device according to any one of the first to seventh aspects, a detection processing unit that outputs a detection signal indicating a focus adjustment state based on a focus detection signal obtained from the pixel, and an adjustment unit that performs focus adjustment based on the detection signal from the detection processing unit. As means to solve the above problem, the following embodiments are also presented. The first surface image sensor includes a first microlens into which light emitted from an optical system is incident, a first photoelectric conversion unit that converts light transmitted through the first microlens into electric charge, a second photoelectric conversion unit that converts light transmitted through the first microlens into electric charge, a first transfer unit that transfers the charge converted by the first photoelectric conversion unit, a second transfer unit that transfers the charge converted by the second photoelectric conversion unit, and a first charge holding unit that holds the charge transferred from the first photoelectric conversion unit by the first transfer unit and the charge transferred from the second photoelectric conversion unit by the second transfer unit. The device comprises a third transfer unit that transfers the charge held in the first charge holding unit, a second charge holding unit that holds the charge transferred from the first charge holding unit by the third transfer unit, and an output unit that has a transistor including a gate electrically connected to the second charge holding unit and outputs a signal for detecting the focus of the optical system, which outputs a first signal based on the charge held in the second charge holding unit and converted by the first photoelectric conversion unit, and a second signal based on the charge held in the second charge holding unit and converted by the second photoelectric conversion unit. The second surface image sensor includes a control unit that controls the first transfer unit and the second transfer unit so that, when the first surface image sensor outputs a signal for detecting the focus of the optical system, the timing at which the charge converted in the first photoelectric conversion unit is transferred to the first charge holding unit by the first transfer unit and the timing at which the charge converted in the second photoelectric conversion unit is transferred to the first charge holding unit by the second transfer unit are different. In the third image sensor, when the output unit outputs a signal for generating an image of the captured subject in the first or second image sensor, it outputs a third signal based on the charge held in the second charge holding unit, which is converted by the first photoelectric conversion unit and the charge converted by the second photoelectric conversion unit. In the image sensor with a fourth surface, the second photoelectric conversion unit is arranged next to the first photoelectric conversion unit in the row direction, in the image sensor with any of the first to third surfaces. The fifth image sensor is an image sensor with any of the first to third surfaces, wherein the second photoelectric conversion unit is arranged next to the first photoelectric conversion unit in the column direction. The sixth image sensor comprises, in the first image sensor, a third photoelectric conversion unit that converts light transmitted through the first microlens into electric charge, and a fourth transfer unit that transfers the charge converted by the third photoelectric conversion unit to the first charge holding unit. When the output unit outputs a signal for detecting the focus of the optical system, it outputs a fourth signal based on the charge held in the second charge holding unit and converted by the third photoelectric conversion unit. The seventh image sensor includes a control unit that controls the first transfer unit, the second transfer unit, and the third transfer unit so that when the sixth image sensor outputs a signal for detecting the focus of the optical system, the timing at which the charge converted in the first photoelectric conversion unit is transferred to the first charge holding unit by the first transfer unit, the timing at which the charge converted in the second photoelectric conversion unit is transferred to the first charge holding unit by the second transfer unit, and the timing at which the charge converted in the third photoelectric conversion unit is transferred to the first charge holding unit by the third transfer unit are all different. The image sensor with the eighth surface outputs a fifth signal based on the charge held in the second charge holding unit, which is converted by the first photoelectric conversion unit, and the charge converted by the second photoelectric conversion unit, and the charge converted by the third photoelectric conversion unit, in the case of the image sensor with the sixth or seventh surface, when the output unit outputs a signal for generating an image of the captured subject. The image sensor with a ninth plane is an image sensor with any of the sixth to eighth planes, wherein the second photoelectric conversion unit is located next to the first photoelectric conversion unit in the row direction, and the third photoelectric conversion unit is located next to the first photoelectric conversion unit in the column direction. The tenth image sensor, in any of the first to third image sensors, includes a second microlens, which is positioned next to the first microlens in the column direction, into which light emitted from the optical system is incident, a third photoelectric conversion unit that converts light transmitted through the second microlens into electric charge, a fourth photoelectric conversion unit that converts light transmitted through the second microlens into electric charge, a fourth transfer unit that transfers the charge converted by the third photoelectric conversion unit, a fifth transfer unit that transfers the charge converted by the fourth photoelectric conversion unit, and the charge transferred from the third photoelectric conversion unit by the fourth transfer unit and the charge transferred from the fourth photoelectric conversion unit by the fifth transfer unit. The optical system includes a third charge holding unit for holding charges, and a sixth transfer unit for transferring the charges held in the third charge holding unit to the second charge holding unit. When the output unit outputs a signal for detecting the focus of the optical system, it outputs a first signal based on the charges held in the second charge holding unit and converted by the first photoelectric conversion unit, a second signal based on the charges held in the second charge holding unit and converted by the second photoelectric conversion unit, a fourth signal based on the charges held in the second charge holding unit and converted by the third photoelectric conversion unit, and a fifth signal based on the charges held in the second charge holding unit and converted by the fourth photoelectric conversion unit. In the image sensor with the 11th plane, when the control unit outputs a signal for detecting the focus of the optical system, it controls the 4th transfer unit and the 5th transfer unit so that the timing at which the charge converted in the 3rd photoelectric conversion unit is transferred to the 3rd charge holding unit by the 4th transfer unit and the timing at which the charge converted in the 4th photoelectric conversion unit is transferred to the 3rd charge holding unit by the 5th transfer unit are different. In the image sensor with the twelfth plane, when the output unit outputs a signal for generating an image of the captured subject, it outputs a sixth signal based on the charge held in the second charge holding unit, which is converted by the third photoelectric conversion unit and the charge converted by the fourth photoelectric conversion unit. The 13th image sensor is an image sensor with any of the 10th to 12th surfaces, wherein the second photoelectric conversion unit is located next to the first photoelectric conversion unit in the row direction, and the fourth photoelectric conversion unit is located next to the third photoelectric conversion unit in the row direction. The 14th image sensor is an image sensor with any of the 10th to 12th surfaces, wherein the second photoelectric conversion unit is located next to the first photoelectric conversion unit in the row direction, and the fourth photoelectric conversion unit is located next to the third photoelectric conversion unit in the row direction. The image sensor with a 15th plane is equipped with a signal line that is electrically connected to the output unit of the image sensor with any of the 1st to 14th planes, and from which the first signal and the second signal are output. The 16th image sensor comprises a conversion unit that converts the first signal output to the signal line and the second signal output to the signal line into digital signals, as in the 15th image sensor. The imaging device with the 17th plane comprises an image sensor with any of the first to 16 planes. The imaging device with the 18th plane is equipped with a focus calculation unit that calculates the amount of defocus of the optical system using the first signal and the second signal, as in the imaging device with the 17th plane. The imaging device using the 19th plane is an imaging device using the 17th or 18th plane, and includes an adjustment unit that adjusts the focus of the optical system based on the defocus amount calculated by the focus calculation unit.

Advantages of the Invention

[0012] According to the present invention, it is possible to realize imaging by a global electronic shutter, obtain a focus detection signal, and provide a solid-state imaging device capable of increasing the aperture ratio and an imaging device using the same.

Brief Description of the Drawings

[0013] [Figure 1] It is a schematic block diagram showing an electronic camera according to the first embodiment of the present invention. [Figure 2] It is a circuit diagram showing a schematic configuration of the solid-state imaging device in FIG. 1. [[ID=5}} [Figure 3] This is a circuit diagram showing one pixel of the solid-state image sensor in Figure 1. [Figure 4] Figure 3 is a schematic plan view illustrating the essential parts of the pixel shown. [Figure 5] This is a timing chart showing an example of the readout operation of the solid-state image sensor in Figure 1. [Figure 6] This is a circuit diagram showing one pixel of a solid-state image sensor in a comparative example. [Figure 7] Figure 6 shows a timing chart illustrating an example of the readout operation of a solid-state image sensor. [Figure 8] This is a circuit diagram showing one pixel of a solid-state image sensor used in an electronic camera according to a second embodiment of the present invention. [Figure 9] Figure 8 is a schematic plan view illustrating the essential parts of the pixel. [Figure 10] This is a timing chart showing an example of the readout operation of a solid-state image sensor used in an electronic camera according to a second embodiment of the present invention. [Figure 11] This is a circuit diagram showing one pixel of a solid-state image sensor used in an electronic camera according to a third embodiment of the present invention. [Figure 12] This is a timing chart showing an example of the readout operation of a solid-state image sensor used in an electronic camera according to a third embodiment of the present invention. [Figure 13] This is a circuit diagram showing one pixel of a solid-state image sensor used in an electronic camera according to a fourth embodiment of the present invention. [Figure 14] This is a timing chart showing an example of the readout operation of a solid-state image sensor used in an electronic camera according to the fourth embodiment of the present invention. [Modes for carrying out the invention]

[0014] The solid-state image sensor and imaging device according to the present invention will be described below with reference to the drawings.

[0015] [First Embodiment]

[0016] Figure 1 is a schematic block diagram showing an electronic camera 1 as an imaging device according to a first embodiment of the present invention.

[0017] The electronic camera 1 according to this embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this and can be applied to various imaging devices such as other electronic cameras such as compact cameras, electronic cameras mounted on mobile phones, and video cameras that capture video.

[0018] An imaging lens 2 is attached to the electronic camera 1. The focus and aperture of this imaging lens 2 are driven by the lens control unit 3. The imaging surface of the solid-state image sensor 4 is positioned in the image space of this imaging lens 2.

[0019] The solid-state image sensor 4 is driven by commands from the imaging control unit 5 and outputs a digital signal. The signal output from the solid-state image sensor 4 is either an image signal or a focus detection signal. Both signals are processed by the digital signal processing unit 6 and then temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The lens control unit 3, imaging control unit 5, CPU 9, recording unit 10, focus calculation unit 11, image processing unit 12, image compression unit 13, and display unit 14 such as a liquid crystal display panel are also connected to the bus 8. An operating unit 15 such as a shutter release button is connected to the CPU 9. A recording medium 10a is detachably mounted on the recording unit 10.

[0020] The CPU 9 in the electronic camera 1 drives the image capture control unit 5 in synchronization with the half-press operation of the release button on the operation unit 15. The image capture control unit 5 reads focus detection signals from the pixels PX arranged on the solid-state image sensor 4 and stores them in the memory 7. Here, as will be described later, all pixels PX generate focus detection signals. Also, all pixels PX generate image signals at a different timing than the focus detection signals. However, this is not limited to this, and it is sufficient that at least some of the pixels arranged on the solid-state image sensor 4 generate focus detection signals. In this case, the other pixels output image signals. This point is the same for each embodiment described later.

[0021] When the solid-state image sensor 4 outputs a focus detection signal in response to a command from the imaging control unit 5 and stores it in the memory 7, the focus calculation unit 11 uses this signal to perform focus detection calculation processing and calculate the amount of defocus. Incidentally, as will be described later, in the solid-state image sensor 4 of this embodiment, the pixels that output the focus detection signal have two photoelectric conversion units. A common microlens is arranged on these two photoelectric conversion units. The focus detection signals output from these two photoelectric conversion units form a pair (a set), and the amount of defocus is calculated based on the focus detection signals of each pair of pixels at the desired position by calculation according to the pupil division phase difference method (detection processing of the focus adjustment state).

[0022] The amount of defocus detected by the focus calculation unit 11 is transmitted to the lens control unit 3. The lens control unit 3 functions as an adjustment unit that drives the focus of the photographic lens 2 based on this amount of defocus, and focuses the photographic lens 2 on the subject. Subsequently, the CPU 9 in the electronic camera 1 starts reading out the image signal using the imaging control unit 5 in synchronization with the full pressing of the release button.

[0023] The imaging control unit 5 reads image signals from pixels and stores them in the memory 7. Then, based on commands from the operation unit 15, the CPU 9 performs the necessary processing in the image processing unit 12 and image compression unit 13, and outputs the processed signal to the recording unit 10 for recording on the recording medium 10a.

[0024] Figure 2 is a circuit diagram showing the schematic configuration of the solid-state image sensor 4 in Figure 1. In this embodiment, the solid-state image sensor 4 is configured as a CMOS type solid-state image sensor, but it is not limited to this.

[0025] The solid-state image sensor 4 includes a pixel section 21 having a plurality of pixels PX arranged in a two-dimensional matrix, a vertical scanning circuit 22 as a control unit, control lines 23 provided for each row of pixels PX, a plurality of vertical signal lines 24 provided for each column of pixels PX to receive signals from the corresponding column's pixels PX, a constant current source 25 provided for each vertical signal line 24, a column amplifier 26, a CDS circuit (correlated double sampling circuit) 27, and an A / D converter 28 provided in conjunction with each vertical signal line 24, and a horizontal readout circuit 29.

[0026] Furthermore, an analog amplifier or a so-called switched-capacitor amplifier may be used as the column amplifier 26. Also, the column amplifier 26 is not necessarily required.

[0027] The vertical scanning circuit 22 and the horizontal readout circuit 29 output control signals based on commands from the imaging control unit 5 of the electronic camera 1. Each pixel PX is driven by receiving a control signal output from the vertical scanning circuit 22 via a predetermined control line 23, and outputs an image signal or a focus detection signal to the vertical signal line 24. There are multiple control signals output from the vertical scanning circuit 22, and consequently, there are multiple control lines 23. These will be described later.

[0028] The signal read from the pixel PX to the vertical signal line 24 is processed by a column amplifier 26 and then subjected to a predetermined noise reduction process in a CDS circuit 27 for each column, before being converted into a digital signal by an A / D converter 28, which holds the digital signal. The digital image signal held in each A / D converter 28 is horizontally scanned by a horizontal readout circuit 29, converted to a predetermined signal format as needed, and output to the outside (digital signal processing unit 6 in Figure 1). Note that the solid-state image sensor does not necessarily need to include an A / D converter 28; it may be configured so that the analog image signal is output from the horizontal readout circuit 29.

[0029] The CDS circuit 27 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in Figure 1. It samples the output signal of the column amplifier 26 as a dark signal at the timing when φDARKC switches from a high level (H) to a low level (L). Simultaneously, under the control of the imaging control unit 5 in Figure 1, it receives an optical signal sampling signal φSIGC from the timing generation circuit. It samples the output signal of the column amplifier 26 as an optical signal at the timing when φSIGC switches from a high level to a low level. The CDS circuit 27 then outputs a signal corresponding to the difference between the sampled dark signal and the optical signal, based on the clock or pulse from the timing generation circuit. A known configuration can be adopted for such a CDS circuit 27.

[0030] Figure 3 is a circuit diagram showing one pixel PX of the solid-state image sensor 4 in Figure 1. Figure 4 is a schematic plan view showing the main parts of the pixel PX shown in Figure 3 (photodiodes PDa, PDb and microlens 30).

[0031] As shown in Figure 3, pixel PX includes two photodiodes PDa and PDb as two photoelectric conversion units that generate and store charge corresponding to incident light guided to the same microlens 30, two transistors TXa1 and TXb1 as two first switches that electrically connect and disconnect each of the two photodiodes PDa and PDb to the first node N1, a capacitor CH provided at the first node N1 as a first charge holding unit to which the charge is transferred and held, a transistor TX2 as a second switch that electrically connects and disconnects the first node N1 and the second node N2, a floating capacitor FD provided at the second node N2 as a second charge holding unit to which the charge is transferred and held from capacitor CH, an amplification transistor AMP as an amplification unit that outputs a signal corresponding to the charge held in the floating capacitor FD, a reset transistor FDRST as a reset unit that resets the potential of the second node N2, and a selection transistor SEL as a selection unit that selects the pixel PX, and is connected as shown in Figure 3. In Figure 3, VDD is the power supply voltage. Capacitor CH may have a structure with metal electrodes on both sides, or it may have other structures. The first charge holding part is not limited to capacitor CH, but may also be a storage diode or a MOS capacitor, for example.

[0032] As shown in Figure 4, a single microlens 30 is positioned on the light-incident side of the two photodiodes PDa and PDb. The two photodiodes PDa and PDb are positioned symmetrically with respect to the center line X-X' (a line including the diameter) of the microlens 30 that extends in the row direction of the pixel PX when viewed from the light-incident side. As a result, the incident light guided by the microlens 30 is pupil-split and incident on each photodiode PDa and PDb. Therefore, each photodiode PDa and PDb can generate a focus detection signal. On the other hand, by summing the photocharges of the two photodiodes PDa and PDb and outputting a signal, the solid-state image sensor 4 can obtain an image signal. Note that the two photodiodes PDa and PDb may also be positioned symmetrically with respect to the center line (a line including the diameter) of the microlens 30 that extends in the column direction of the pixel PX when viewed from the light-incident side.

[0033] In this embodiment, each pixel PX has the same structure and can output focus detection signals and image signals at different timings. However, the solid-state image sensor 4 is not limited to this, and may be configured such that a focus detection area is provided in a predetermined part, and pixels having the circuit shown in Figure 3 are arranged in this area to generate focus detection signals, while pixels having only one photoelectric conversion unit are arranged in the other areas to generate only image signals.

[0034] Furthermore, in Figure 3, one terminal of the photodiodes PDa and PDb, one terminal of the capacitor CH, and one terminal of the floating capacitance FD are connected to ground. However, this is not the only option; a predetermined reference potential may be applied instead of ground.

[0035] The gate of transistor TXa1 is connected in common to each pixel row, and a control signal φTXa1 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of transistor TXb1 is connected in common to each pixel row, and a control signal φTXb1 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of transistor TX2 is connected in common to each pixel row, and a control signal φTX2 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of reset transistor FDRST is connected in common to each pixel row, and a control signal φFDRST is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of selection transistor SEL is connected in common to each pixel row, and a control signal φSEL is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23.

[0036] In this embodiment, transistors TXa1, TXb1, TX2, AMP, FDRST, and SEL are all nMOS transistors. Therefore, they are turned on by a high-level control signal and turned off by a low-level control signal.

[0037] Figure 5(a) is a timing chart showing an example of the readout operation of the solid-state image sensor 4 in Figure 1 when reading out an image signal. Period T1 is the period during which all pixels PX in all rows are driven simultaneously. That is, during period T1, the same control signal is output from the vertical scanning circuit 22 for all rows. Period T2 is the period during which the first row is read out, and period T3 is the period during which the second row is read out, and the control signal shown in this figure is output only for the selected row. In this example, in order to acquire a still image, the series of periods from period T1 to the readout period of the last row is repeated twice. The first series of periods is a reset period to remove unwanted charges from the photodiodes PDa and PDb and reset them, and the second series of periods is the actual readout period for each row. The series of periods may be repeated three or more times to acquire a moving image.

[0038] First, during period T11 of period T1, the control signals φTXa1 and φTXb1 of all rows are set to high level, and the transistors TXa1 and TXb1 of all rows are turned on. This operation transfers the charge accumulated in the photodiodes PDa and PDb of all pixels PX to the capacitor CH of each pixel PX, where the charges are added together and held. The charge transferred to the capacitor CH during period T11 of the first series of periods is the unwanted charge accumulated in the photodiodes PDa and PDb. On the other hand, the charge transferred to the capacitor CH during period T11 of the second series of periods is the signal charge that forms the captured image. The period from the end of period T11 of the first series of periods to the start of period T11 of the second series of periods becomes the exposure period, and this exposure period is the same for all rows and at the same timing. Therefore, all pixels PX can acquire image information without timing misalignment, and imaging using a global electronic shutter is realized.

[0039] The following explanation describes the second series of periods following the exposure period, but the same applies to the first series of periods.

[0040] During period T12 within period T2, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T12, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0041] During period T13 within period T12, the control signal φFDRST on the first line is set to a high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0042] At a predetermined timing between the end of period T13 and the start of period T14, in response to the dark signal sampling signal φDARKC (not shown), the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0043] During the period T14 following period T12, the control signal φTX2 of the first row is set to a high level, turning on transistor TX2. This operation causes the signal charge held in capacitor CH of the first row pixel PX (the charge transferred from photodiodes PDa and PDb of the pixel PX to capacitor CH and then added together) to be transferred to and held in the floating capacitance FD. The potential of node N2 of the first row pixel PX (the potential of the floating capacitance FD, the potential of the gate of the amplification transistor AMP) is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the floating capacitance FD of the pixel PX, excluding noise components.

[0044] At a predetermined timing between the end of period T14 and the end of period T12, in response to the optical signal sampling signal φSIGC (not shown), the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0045] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0046] Similarly, the second row is read during period T3. The control signal for the second row in period T3 is the same as the control signal for the first row in period T2. In the same manner, once image signals are output from all rows, the series of periods ends, and the acquisition of one frame of image is completed.

[0047] As can be understood from the above explanation, although each pixel PX has two photodiodes PDa and PDb, it can output an image signal as usual. Moreover, a global electronic shutter is possible with the exposure timing of all pixel PX being the same.

[0048] Figure 5(b) is a timing chart showing an example of the readout operation of the solid-state image sensor 4 in Figure 1 when reading out the focus detection signal. Period T21 is the period during which the first row is read out, and period T22 is the period during which the second row is read out. The control signal shown in this figure is output only for the selected row. In this example, in order to acquire the focus detection signal, the series of periods from period T21 to the readout period of the last row is repeated twice. The first series of periods is a reset period to remove unwanted charges from the photodiodes PDa and PDb and reset them, and the second series of periods is the actual readout period for each row.

[0049] The following explanation will primarily describe the second series of periods, but the same principles apply to the first series of periods.

[0050] During period T31 within period T21, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T31, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0051] During period T32 within period T31, the control signal φFDRST on the first line is set to a high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0052] During the period T33 following period T31, the control signal φTXa1 for the first row is set to a high level, and transistor TXa1 is turned on. This operation transfers the charge accumulated in the photodiode PDa of the first row pixel PX to the capacitor CH of that pixel PX and holds it there. The charge transferred to capacitor CH during period T33 of the first series of periods is the unwanted charge accumulated in the photodiode PDa. On the other hand, the charge transferred to capacitor CH during period T33 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T33 of the first series of periods to the start of period T33 of the second series of periods is the exposure period for the photodiode PDa of the first row pixel PX.

[0053] At a predetermined timing between the end of period T32 and the start of period T34, in response to the dark signal sampling signal φDARKC (not shown), the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0054] During the period T34 following period T31, the control signal φTX2 of the first row is set to a high level, and transistor TX2 is turned on. This operation causes the signal charge held in capacitor CH of the first row pixel PX (the charge transferred from the photodiode PDa of the pixel PX to capacitor CH) to be transferred to and held in the floating capacitance FD. The potential of node N2 of the first row pixel PX (the potential of the floating capacitance FD, the potential of the gate of the amplification transistor AMP) is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the floating capacitance FD of the pixel PX, excluding noise components.

[0055] At a predetermined timing between the end of period T34 and the start of period T35, in response to the optical signal sampling signal φSIGC (not shown), the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0056] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0057] During the period T35 following period T31, the control signal φFDRST on the first line is set to a high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0058] During the period T36 following period T31, the control signal φTXb1 for the first row is set to a high level, and the transistor TXb1 is turned on. This operation transfers the charge accumulated in the photodiode PDb of the first row pixel PX to the capacitor CH of that pixel PX and holds it there. The charge transferred to the capacitor CH during period T36 of the first series of periods is the unwanted charge accumulated in the photodiode PDb. On the other hand, the charge transferred to the capacitor CH during period T36 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T36 of the first series of periods to the start of period T36 of the second series of periods is the exposure period for the photodiode PDb of the first row pixel PX.

[0059] At a predetermined timing between the end of period T35 and the start of period T37, in response to the dark signal sampling signal φDARKC (not shown), the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0060] During the period T37 following period T31, the control signal φTX2 of the first row is set to a high level, turning on transistor TX2. This operation causes the signal charge held in capacitor CH of the first row pixel PX (the charge transferred from the photodiode PDb of the pixel PX to capacitor CH) to be transferred to and held in the floating capacitance FD. The potential of node N2 of the first row pixel PX (the potential of the floating capacitance FD, the potential of the gate of the amplification transistor AMP) is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the floating capacitance FD of the pixel PX, excluding noise components.

[0061] At a predetermined timing between the end of period T37 and the end of period T31, in response to the optical signal sampling signal φSIGC (not shown), the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0062] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0063] Similarly, the second row is read during period T22. The control signal for the second row in period T22 is the same as the control signal for the first row in period T21. In the same manner, when focus detection signals are output from all rows, the series of periods ends.

[0064] As can be understood from the above explanation, this solid-state image sensor 4 can obtain a focus detection signal. When obtaining a focus detection signal, the exposure periods of photodiodes PDa and PDb are shifted for each row of pixels PX, and even for pixels PX in the same row, the exposure periods of photodiode PDa and photodiode PDb are shifted.

[0065] Figure 6 is a circuit diagram showing one pixel of a solid-state image sensor according to a comparative example, and corresponds to Figure 3. In Figure 6, elements that are the same as or corresponding to the elements in Figure 3 are denoted by the same reference numerals, and redundant explanations are omitted.

[0066] The difference between the solid-state image sensor in this comparative example and the solid-state image sensor 4 in this embodiment is that in this embodiment, a set of capacitor CH and transistor TX2 is provided in common for transistors TXa1 and TXb1 in each pixel PX, whereas in this comparative example, a set of capacitor CHa and transistor TXa2 is provided individually for transistor TXa1 in each pixel PX, and a set of capacitor CHb and transistor TXb2 is provided individually for transistor TXb1.

[0067] In this comparative example, the gate of transistor TXa2 is connected in common to each pixel row, and the control signal φTXa2 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. Similarly, the gate of transistor TXb2 is connected in common to each pixel row, and the control signal φTXb2 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. Transistors TXa2 and TXb2 are nMOS transistors, just like the other transistors TXa1, TXb1, AMP, FDRST, and SEL.

[0068] Figure 7(a) is a timing chart showing an example of the readout operation of a solid-state image sensor according to the comparative example shown in Figure 6 when reading out an image signal. Period T41 is the period during which all pixels PX in all rows are driven simultaneously. That is, during period T41, the same control signal is output from the vertical scanning circuit 22 for all rows. Period T42 is the period during which the first row is read out, and period T43 is the period during which the second row is read out, and the control signal shown in this figure is output only for the selected row. In this example, in order to acquire a still image, the series of periods from period T41 to the readout period of the last row is repeated twice. The first series of periods is a reset period to eliminate unwanted charges from the photodiodes PDa and PDb and reset them, and the second series of periods is the actual readout period for each row.

[0069] First, during period T51 within period T41, the control signals φTXa1 and φTXb1 for all rows are set to high level, turning on the transistors TXa1 and TXb1 for all rows. This operation transfers the charge accumulated in the photodiodes PDa and PDb of each pixel PX to the capacitors CHa and CHb of that pixel PX, respectively, and holds it there. The charge transferred to capacitors CHa and CHb during period T51 of the first series of periods is the unwanted charge accumulated in the photodiodes PDa and PDb. On the other hand, the charge transferred to capacitors CHa and CHb during period T51 of the second series of periods is the signal charge that forms the captured image. The period from the end of period T51 of the first series of periods to the start of period T51 of the second series of periods becomes the exposure period, and this exposure period is the same for all rows and at the same timing. Therefore, all pixels PX can acquire image information without timing misalignment, and imaging using a global electronic shutter is realized.

[0070] The following explanation describes the second series of periods following the exposure period, but the same applies to the first series of periods.

[0071] During period T52 within period T42, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T52, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0072] During period T53 within period T52, the control signal φFDRST on the first line is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 to the power supply voltage VDD.

[0073] At a predetermined timing between the end of period T53 and the start of period T54, in response to the dark signal sampling signal φDARKC (not shown), the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0074] During the period T54 following period T52, the control signals φTXa2 and φTXb2 of the first row are set to high level, turning on transistors TXa2 and TXb2. This operation causes the signal charge held in capacitor CHa of the first row pixel PX (the charge transferred from the photodiode PDa of the pixel PX to capacitor CHa) and the signal charge held in capacitor CHb of the first row pixel PX (the charge transferred from the photodiode PDb of the pixel PX to capacitor CHb) to be transferred to the floating capacitance section FD, where they are added together and held.

[0075] At a predetermined timing between the end of period T54 and the end of period T52, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0076] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0077] Similarly, the second row is read during period T43. The control signal for the second row in period T43 is the same as the control signal for the first row in period T42. In the same manner, once image signals are output from all rows, the series of periods ends, and the acquisition of one frame of image is completed.

[0078] As can be understood from the above explanation, imaging using a global electron shutter can also be achieved in this comparative example.

[0079] Figure 7(b) is a timing chart showing an example of the readout operation of a solid-state image sensor according to the comparative example shown in Figure 6 when reading out a focus detection signal. Period T61 is the period during which all pixels PX in all rows are driven simultaneously. That is, during period T61, the same control signal is output from the vertical scanning circuit 22 for all rows. Period T62 is the period during which the first row is read out, and period T63 is the period during which the second row is read out, and the control signal shown in this figure is output only for the selected row. In this example, in order to acquire a focus detection signal, the series of periods from period T61 to the readout period of the last row is repeated twice. The first series of periods is a reset period to eliminate unwanted charges from the photodiodes PDa and PDb and reset them, and the second series of periods is the actual readout period for each row.

[0080] First, during period T71 within period T61, the control signals φTXa1 and φTXb1 for all rows are set to high level, turning on the transistors TXa1 and TXb1 for all rows. This operation transfers the charge accumulated in the photodiodes PDa and PDb of each pixel PX to the capacitors CHa and CHb of that pixel PX, respectively, and holds them there. The charge transferred to capacitors CHa and CHb during period T71 of the first series of periods is the unwanted charge accumulated in the photodiodes PDa and PDb. On the other hand, the charge transferred to capacitors CHa and CHb during period T71 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T71 of the first series of periods to the start of period T71 of the second series of periods becomes the exposure period, and this exposure period is the same for all rows and at the same timing. Therefore, all pixels PX can acquire focus detection information without timing misalignment, and acquisition of the focus detection signal by the global electronic shutter is realized.

[0081] The following explanation describes the second series of periods following the exposure period, but the same applies to the first series of periods.

[0082] During period T72 within period T62, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T72, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0083] During period T73 within period T72, the control signal φFDRST on the first line is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0084] At a predetermined timing between the end of period T73 and the start of period T74, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0085] During the period T74 following period T72, the control signal φTXa2 of the first row is set to a high level, and transistor TXa2 is turned on. As a result of this operation, the signal charge held in the capacitor CHa of the pixel PX of the first row (the charge transferred from the photodiode PDa of the pixel PX to the capacitor CHa) is transferred to and held in the floating capacitance FD.

[0086] At a predetermined timing between the end of period T74 and the start of period T75, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0087] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0088] During the period T75 following period T72, the control signal φFDRST on the first line is set to a high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0089] At a predetermined timing between the end of period T75 and the start of period T76, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0090] During the period T76 following period T72, the control signal φTXb2 of the first row is set to a high level, and the transistor TXb2 is turned on. As a result of this operation, the signal charge held in the capacitor CHb of the pixel PX of the first row (the charge transferred from the photodiode PDb of the pixel PX to the capacitor CHb) is transferred to and held in the floating capacitance FD.

[0091] At a predetermined timing between the end of period T76 and the end of period T72, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0092] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0093] Similarly, the second row is read during period T63. The control signal for the second row in period T63 is the same as the control signal for the first row in period T62. Similarly, when focus detection signals are output from all rows, the series of periods ends.

[0094] As can be understood from the above explanation, a focus detection signal can be obtained using the solid-state image sensor in this comparative example. When obtaining a focus detection signal, as with obtaining an image signal, a global electronic shutter with the same exposure timing for all pixels PX is possible.

[0095] Thus, this embodiment, like the comparative example described above, enables imaging using a global electronic shutter and allows obtaining a focus detection signal.

[0096] In this embodiment, when obtaining a focus detection signal, the exposure periods of photodiodes PDa and PDb are staggered for each row of pixels PX, and even within the same row of pixels PX, the exposure periods of photodiode PDa and photodiode PDb are staggered. In contrast, in the comparative example, a focus detection signal can be obtained using a global electronic shutter with the exposure timing of all pixels PX being the same. Therefore, in the comparative example, the accuracy of focus detection is improved even when the subject is moving quickly, compared to this embodiment.

[0097] However, in the comparative example, each pixel PX requires two capacitors CHa and CHb and two transistors TXa2 and TXb2, whereas in this embodiment, each pixel PX only requires one capacitor CH and one transistor TX2 as corresponding elements, thus reducing the number of components in each pixel PX by one capacitor and one transistor compared to the comparative example. Therefore, according to this embodiment, the area ratio of photodiodes PDa and PDb in each pixel PX (i.e., aperture ratio) can be increased compared to the comparative example, and consequently, images with a higher signal-to-noise ratio can be captured.

[0098] Thus, according to this embodiment, imaging using a global electronic shutter can be achieved and a focus detection signal can be obtained. Furthermore, although the focus detection accuracy for fast-moving subjects is slightly lower compared to the comparative example, it is possible to capture images with a larger aperture ratio and a higher signal-to-noise ratio.

[0099] In addition, in the present invention, a reset transistor may be added as a reset unit to reset the charge accumulated in the photodiode Pda by switching the connection between the cathode of the photodiode Pda and the power supply voltage VDD on and off, or a reset transistor may be added as a reset unit to reset the charge accumulated in the photodiode Pda by switching the connection between the cathode of the photodiode Pda and the power supply voltage VDD on and off. This also applies to each embodiment described later.

[0100] [Second Embodiment]

[0101] Figure 8 is a circuit diagram showing one pixel PX of a solid-state image sensor used in an electronic camera according to a second embodiment of the present invention, and corresponds to Figure 3. Figure 9 is a schematic plan view showing the main parts of the pixel PX shown in Figure 8, and corresponds to Figure 4.

[0102] In Figures 8 and 9, elements that are the same as or corresponding to the elements in Figures 3 and 4 are denoted by the same reference numerals, and redundant explanations are omitted. The differences between this embodiment and the first embodiment are described below.

[0103] The difference between the solid-state image sensor in this embodiment and the solid-state image sensor 4 in the first embodiment is that in the first embodiment, each pixel PX has two photodiodes PDa and PDb and two transistors TXa1 and TXb1 which serve as two first switches to electrically connect and disconnect each of these to the first node N1, respectively, whereas in this embodiment, each pixel PX has four photodiodes PDa, PDb, PDc and PDd and four transistors TXa1, TXb1, TXc1 and TXd1 which serve as four first switches to electrically connect and disconnect each of these to the first node N1, respectively.

[0104] In this embodiment, the gate of transistor TXc1 is connected in common to each pixel row, and a control signal φTXc1 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. Similarly, the gate of transistor TXd1 is connected in common to each pixel row, and a control signal φTXd1 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. Like the other transistors TXa1, TXb1, TX2, AMP, FDRST, and SEL, transistors TXc1 and TXd1 are nMOS transistors.

[0105] In this embodiment, a single microlens 30 is positioned on the light-incident side of each of the four photodiodes PDa, PDb, PDc, and PDd, as shown in Figure 4. The four photodiodes PDa, PDb, PDc, and PDd are positioned symmetrically with respect to the center line X-X' (a line including the diameter) of the microlens 30 extending in the row direction of the pixel PX when viewed from the light-incident side, and also symmetrically with respect to the center line Y-Y' (a line including the diameter) of the microlens 30 extending in the column direction of the pixel PX when viewed from the light-incident side.

[0106] As a result, the incident light guided by the microlens 30 is pupil-split and incident on each photodiode PDa, PDb, PDc, and PDd. Therefore, by summing the photocharges of two PDa and PDc and outputting a signal, and by summing the photocharges of two PDb and PDd and outputting a signal, a focus detection signal can be obtained using incident light pupil-split in the column direction. Similarly, by summing the photocharges of two PDa and PDb and outputting a signal, and by summing the photocharges of two PDc and PDd and outputting a signal, a focus detection signal can be obtained using incident light pupil-split in the row direction. On the other hand, by summing the photocharges of four photodiodes PDa, PDb, PDc, and PDd and outputting a signal, an image signal can be obtained.

[0107] Figure 10(a) is a timing chart showing an example of the readout operation of the solid-state image sensor in this embodiment when reading out an image signal. Period T81 is the period during which all pixels PX in all rows are driven simultaneously. That is, during period T81, the same control signal is output from the vertical scanning circuit 22 for all rows. Period T82 is the period during which the first row is read out, and period T83 is the period during which the second row is read out, and the control signal shown in this figure is output only for the selected row. In this example, in order to acquire a still image, the series of periods from period T81 to the readout period of the last row is repeated twice. The first series of periods is a reset period to eliminate unwanted charges from the photodiodes PDa, PDb, PDc, and PDd and reset them, and the second series of periods is the actual readout period for each row. The series of periods may be repeated three or more times to acquire a moving image.

[0108] First, during period T91 within period T81, the control signals φTXa1, φTXb1, φTXc1, and φTXd1 of all rows are set to high level, and the transistors TXa1, TXb1, TXc1, and TXd1 of all rows are turned on. This operation causes the charge accumulated in the photodiodes PDa, PDb, PDc, and PDd of each pixel PX to be transferred to the capacitor CH of the respective pixel PX, where it is added up and held. The charge transferred to the capacitor CH during period T91 of the first series of periods is the unwanted charge accumulated in the photodiodes PDa, PDb, PDc, and PDd. On the other hand, the charge transferred to the capacitor CH during period T91 of the second series of periods is the signal charge that forms the captured image. The period from the end of period T91 of the first series of periods to the start of period T91 of the second series of periods becomes the exposure period, and this exposure period is the same for all rows and at the same timing. Therefore, all pixel PX can acquire image information without timing discrepancies, enabling imaging with a global electronic shutter.

[0109] The following explanation describes the second series of periods following the exposure period, but the same applies to the first series of periods.

[0110] During period T92 within period T82, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T92, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0111] During period T93 within period T92, the control signal φFDRST on the first line is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0112] At a predetermined timing between the end of period T93 and the start of period T94, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0113] During the period T94 following period T92, the control signal φTX2 of the first row is set to a high level, and transistor TX2 is turned on. As a result of this operation, the signal charge held in capacitor CH of the pixel PX of the first row (the charge transferred from the photodiodes PDa, PDb, PDc, and PDd of the pixel PX to capacitor CH and then added together) is transferred to and held in the floating capacitance section FD.

[0114] At a predetermined timing between the end of period T94 and the end of period T92, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0115] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0116] Similarly, the second row is read during period T83. The control signal for the second row in period T83 is the same as the control signal for the first row in period T82. In the same manner, once image signals are output from all rows, the series of periods ends, and the acquisition of one frame of image is completed.

[0117] As can be understood from the above explanation, each pixel PX has four photodiodes PDa, PDb, PDc, and PDd, but can output an image signal as usual. Moreover, a global electronic shutter is possible with the exposure timing of all pixel PX being the same.

[0118] Figure 10(b) is a timing chart showing an example of the readout operation of the solid-state image sensor in this embodiment when reading out the focus detection signal. Period T101 is the period during which the first row is read out, and period T102 is the period during which the second row is read out. The control signal shown in this figure is output only for the selected row. In this example, in order to acquire the focus detection signal, a series of periods from period T101 to the readout period of the last row is repeated twice. The first series of periods is a reset period in which unwanted charges are removed from the photodiodes PDa, PDb, PDc, and PDd and they are reset, and the second series of periods is the actual readout period for each row.

[0119] The following explanation will primarily describe the second series of periods, but the same principles apply to the first series of periods.

[0120] During period T111 within period T101, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T111, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0121] During period T112 within period T111, the control signal φFDRST on the first line is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0122] During the period T113 following period T111, the control signals φTXa1 and φTXc1 of the first row are set to high level, and transistors TXa1 and TXc1 are turned on. This operation causes the charge accumulated in the photodiodes PDa and PDc of the first row pixel PX to be transferred to the capacitor CH of the same pixel PX, where the charges are added together and held. The charge transferred to capacitor CH during period T113 of the first series of periods is the unwanted charge accumulated in the photodiodes PDa and PDc. On the other hand, the charge transferred to capacitor CH during period T113 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T113 of the first series of periods to the start of period T113 of the second series of periods is the exposure period for the photodiodes PDa and PDc of the first row pixel PX.

[0123] At a predetermined timing between the end of period T112 and the start of period T114, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0124] During the period T114 following period T111, the control signal φTX2 of the first row is set to a high level, and transistor TX2 is turned on. As a result of this operation, the signal charge held in capacitor CH of the pixel PX of the first row (the charge transferred from the photodiodes PDa and PDc of the pixel PX to capacitor CH and then added together) is transferred to and held in the floating capacitance section FD.

[0125] At a predetermined timing between the end of period T114 and the start of period T115, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0126] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0127] During the period T115 following period T111, the control signal φFDRST on the first line is set to a high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0128] During the period T116 following period T111, the control signals φTXb1 and φTXd1 of the first row are set to high level, and transistors TXb1 and TXd1 are turned on. This operation causes the charge accumulated in the photodiodes PDb and PDd of the first row pixel PX to be transferred to the capacitor CH of the same pixel PX, where they are added together and held. The charge transferred to capacitor CH during period T116 of the first series of periods is the unwanted charge accumulated in the photodiodes PDb and PDd. On the other hand, the charge transferred to capacitor CH during period T116 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T116 of the first series of periods to the start of period T116 of the second series of periods is the exposure period for the photodiodes PDb and PDd of the first row pixel PX.

[0129] At a predetermined timing between the end of period T115 and the start of period T117, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0130] During the period T117 following period T111, the control signal φTX2 of the first row is set to a high level, and transistor TX2 is turned on. As a result of this operation, the signal charge held in capacitor CH of the pixel PX of the first row (the charge transferred from the photodiodes PDb and PDd of the pixel PX to capacitor CH and then added together) is transferred to and held in the floating capacitance section FD.

[0131] At a predetermined timing between the end of period T117 and the end of period T111, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0132] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0133] Similarly, the second row is read during period T102. The control signal for the second row during period T102 is the same as the control signal for the first row during period T101. In the same manner, when focus detection signals are output from all rows, the series of periods ends.

[0134] As can be understood from the above explanation, the solid-state image sensor in this embodiment can obtain a focus detection signal. When obtaining a focus detection signal, the exposure periods of the photodiodes PDa, PDB, PDc, and PDd are shifted for each row of pixels PX, and even for pixels PX in the same row, the exposure periods of the photodiodes PDa and PDc are different from those of the photodiodes PDb and PDd.

[0135] The example shown in Figure 10(b) is an example of obtaining a focus detection signal using incident light with pupil division in the row direction by summing the photocharges of two PDa and PDc and outputting a signal, as well as summing the photocharges of two PDb and PDd and outputting a signal. In Figure 10(b), if the control signals φTXa1 and φTXb1 are set to high levels during period T113 while the control signals φTXc1 and φTXd1 are set to low levels, and the control signals φTXa1 and φTXb1 are set to low levels during period T116 while the control signals φTXc1 and φTXd1 are set to high levels, then the photocharges of two PDa and PDb are summed and outputted, as well as the photocharges of two PDc and PDd and outputted, thereby obtaining a focus detection signal using incident light with pupil division in the row direction.

[0136] This embodiment also provides the same advantages as the first embodiment.

[0137] [Third Embodiment]

[0138] Figure 11 is a circuit diagram showing two adjacent pixels PX in the row direction of a solid-state image sensor used in an electronic camera according to the third embodiment of the present invention, and corresponds to Figure 3. In Figure 11, elements that are the same as or corresponding to elements in Figure 3 are denoted by the same reference numerals, and redundant explanations are omitted. The differences between this embodiment and the first embodiment are described below.

[0139] In this embodiment, for every two adjacent pixels PX in the column direction (referred to as a "pixel block BL"), these two pixels PX share a set of floating capacitance FD, amplification transistor AMP, reset transistor FDRST, selection transistor SEL, and node N2. One row of pixel block BL corresponds to two rows of pixels PX.

[0140] In Figure 11, the photodiodes PDa and PDb, transistors TXa1 and TXb1, and node N1 of one pixel PX in pixel block BL are denoted as PDa(A), PDb(A), TXa1(A), TXb1(A), and node N1(A), respectively, while the photodiodes PDa and PDb, transistors TXa1 and TXb1, and node N1 of the other pixel PX in pixel block BL are denoted as PDa(B), PDb(B), TXa1(B), TXb1(B), and node N1(B), respectively, to distinguish between the two. Furthermore, the control signals supplied to the gates of transistors TXa1(A), TXb1(A), and TX2(A) are denoted as φTXa1(A), φTXb1(A), and φTX2(A), respectively, and the control signals supplied to the gates of transistors TXa1(B), TXb1(B), and TX2(B) are denoted as φTXa1(B), φTXb1(B), and φTX2(B), to distinguish between the two.

[0141] Figure 12(a) is a timing chart showing an example of the readout operation of the solid-state image sensor in this embodiment when reading out an image signal. Period T121 is the period during which all rows of pixel blocks BL are driven simultaneously. That is, during period T121, the same control signal is output from the vertical scanning circuit 22 for all rows of pixel blocks BL. Period T122 is the period during which the first row of pixel blocks BL is read out, and period T123 is the period during which the second row of pixel blocks BL is read out, with the control signal shown in this figure being output only for the selected row. In this example, in order to acquire a still image, the series of periods from period T121 to the readout period of the last row is repeated twice. The first series of periods is a reset period to eliminate unwanted charges from the photodiodes PDa(A), PDb(A), PDa(B), and PDb(B) and reset them, and the second series of periods is the actual readout period for each row of pixel blocks BL. The series of periods may be repeated three or more times to acquire a moving image.

[0142] First, during period T131 within period T121, the control signals φTXa1(A), φTXb1(A), φTXa1(B), and φTXb1(B) of all rows are set to high level, and the transistors TXa1(A), TXb1(A), TXa1(B), and TXb1(B) of all pixel blocks BL are turned ON. As a result of this operation, the charges accumulated in the photodiodes PDa(A) and PDb(A) of pixels PX(A) of all pixel blocks BL are transferred to the capacitor CH(A) of those pixels PX(A), summed up, and held, and the charges accumulated in the photodiodes PDa(B) and PDb(B) of pixels PX(B) of all pixel blocks BL are transferred to the capacitor CH(B) of those pixels PX(B), summed up, and held. The charge transferred to capacitor CH(A) during period T131 of the first series of periods is unwanted charge accumulated in photodiodes PDa(A) and PDb(A), and the charge transferred to capacitor CH(B) during period T131 of the first series of periods is unwanted charge accumulated in photodiodes PDa(B) and PDb(B). On the other hand, the charge transferred to capacitor CH(A) during period T131 of the second series of periods is signal charge that forms the captured image, and the charge transferred to capacitor CH(B) during period T131 of the second series of periods is signal charge that forms the captured image. The period from the end of period T131 of the first series of periods to the start of period T131 of the second series of periods becomes the exposure period, and this exposure period is the same for all rows and at the same timing. Therefore, all pixels PX can acquire image information without timing shift, and imaging with a global electronic shutter is realized.

[0143] The following explanation describes the second series of periods following the exposure period, but the same applies to the first series of periods.

[0144] During period T132 within period T122, the control signal φSEL of the first row pixel block BL is set to a high level, and the selection transistor SEL is turned on. As a result, the first row pixel block BL is selected, and during this period T132, a signal is output from the first row pixel block BL to the vertical signal line 24.

[0145] During period T133 within period T132, the control signal φFDRST of the first row pixel block BL is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0146] At a predetermined timing between the end of period T133 and the start of period T134, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0147] During the period T134 following period T132, the control signal φTX2(A) of the first row pixel block BL is set to a high level, and the transistor TX2(A) is turned on. As a result of this operation, the signal charge held in the capacitor CH(A) of the pixel PX(A) of the first row pixel block BL (the charge transferred from the photodiodes PDa(A) and PDb(A) of the pixel PX(A) to the capacitor CH(A) and added together) is transferred to and held in the floating capacitance section FD.

[0148] At a predetermined timing between the end of period T134 and the start of period T135, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0149] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0150] During the period T135 following period T132, the control signal φFDRST of the first row pixel block BL is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0151] During the period T136 following period T132, the control signal φTX2(B) of the first row pixel block BL is set to a high level, turning on the transistor TX2(B). This operation causes the signal charge held in the capacitor CH(B) of the pixel PX(B) of the first row pixel block BL (the charge transferred from the photodiodes PDa(B) and PDb(B) of the pixel PX(B) to the capacitor CH(B) and added together) to be transferred to and held in the floating capacitance section FD.

[0152] At a predetermined timing between the end of period T136 and the end of period T132, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0153] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0154] Similarly, the second row of pixel block BL is read out during period T123. The control signal for the second row of pixel block BL during period T123 is the same as the control signal for the first row of pixel block BL during period T122. In the same manner, once image signals are output from all rows of pixel block BL, the series of periods ends, and the acquisition of one frame of image is completed.

[0155] As can be understood from the above explanation, although each pixel PX has two photodiodes PDa and PDb, it can output an image signal as usual. Moreover, a global electronic shutter is possible with the exposure timing of all pixel PX being the same.

[0156] Figure 12(b) is a timing chart showing an example of the readout operation of the solid-state image sensor in this embodiment when reading out a focus detection signal. Period T141 is the period during which the first row of pixel blocks BL is read out, and period T142 is the period during which the second row of pixel blocks BL is read out. The control signal shown in this figure is output only for the selected row. In this example, in order to acquire the focus detection signal, a series of periods from period T141 to the readout period of the last row is repeated twice. The first series of periods is a reset period in which unwanted charges are removed from the photodiodes PDa(A), PDb(A), PDa(B), and PDb(B) and reset, and the second series of periods is the actual readout period for each row of pixel blocks BL.

[0157] The following explanation will primarily describe the second series of periods, but the same principles apply to the first series of periods.

[0158] During period T151 within period T141, the control signal φSEL of the first row pixel block BL is set to a high level, and the selection transistor SEL is turned on. As a result, the first row pixel block BL is selected, and during this period T151, a signal is output from the first row pixel block BL to the vertical signal line 24.

[0159] During period T152 within period T151, the control signal φFDRST of the first row pixel block BL is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0160] During the period T153 following period T151, the control signal φTXa1(A) of the first row of pixel block BL is set to a high level, turning on the transistor TXa1(A). This operation transfers the charge accumulated in the photodiode PDa(A) of the first row of pixel block BL to the capacitor CH(A) of the same pixel block BL and holds it there. The charge transferred to the capacitor CH(A) during period T153 of the first series of periods is the unwanted charge accumulated in the photodiode PDa(A). On the other hand, the charge transferred to the capacitor CH(A) during period T153 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T153 of the first series of periods to the start of period T153 of the second series of periods is the exposure period for the photodiode PDa(A) of the first row of pixel block BL.

[0161] At a predetermined timing between the end of period T152 and the start of period T154, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0162] During the period T154 following period T151, the control signal φTX2(A) of the first row pixel block BL is set to a high level, and the transistor TX2(A) is turned on. As a result of this operation, the signal charge held in the capacitor CH(A) of the pixel PX(A) of the first row pixel block BL (the charge transferred from the photodiode PDa(A) of the pixel PX(A) to the capacitor CH(A)) is transferred to and held in the floating capacitance section FD.

[0163] At a predetermined timing between the end of period T154 and the start of period T155, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0164] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0165] During the period T155 following period T151, the control signal φFDRST of the first row pixel block BL is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0166] During the period T156 following period T151, the control signal φTXb1(A) of the first row of pixel block BL is set to high level, turning on the transistor TXb1(A). This operation transfers the charge accumulated in the photodiode PDb(A) of pixel PX(A) of the first row of pixel block BL to the capacitor CH(A) of the same pixel PX(A) and holds it there. The charge transferred to the capacitor CH(A) during period T156 of the first series of periods is the unwanted charge accumulated in the photodiode PDb(A). On the other hand, the charge transferred to the capacitor CH(A) during period T156 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T156 of the first series of periods to the start of period T156 of the second series of periods is the exposure period for the photodiode PDb(A) of pixel PX(A) of the first row of pixel block BL.

[0167] At a predetermined timing between the end of period T155 and the start of period T157, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0168] During the period T157 following period T151, the control signal φTX2(A) of the first row pixel block BL is set to a high level, and the transistor TX2(A) is turned on. As a result of this operation, the signal charge held in the capacitor CH(A) of the pixel PX(A) of the first row pixel block BL (the charge transferred from the photodiode PDb(A) of the pixel PX(A) to the capacitor CH(A)) is transferred to and held in the floating capacitance section FD.

[0169] At a predetermined timing between the end of period T157 and the start of period T158, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0170] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0171] During the period T158 following period T151, the control signal φFDRST of the first row pixel block BL is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0172] During the period T159 following period T151, the control signal φTXa1(B) of the first row of pixel block BL is set to a high level, turning on the transistor TXa1(B). This operation transfers the charge accumulated in the photodiode PDa(B) of the first row of pixel block BL to the capacitor CH(B) of the same pixel block BL and holds it there. The charge transferred to the capacitor CH(B) during period T159 of the first series of periods is the unwanted charge accumulated in the photodiode PDa(B). On the other hand, the charge transferred to the capacitor CH(B) during period T159 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T159 of the first series of periods to the start of period T159 of the second series of periods is the exposure period for the photodiode PDa(B) of the first row of pixel block BL.

[0173] At a predetermined timing between the end of period T158 and the start of period T160, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0174] During the period T160 following period T151, the control signal φTX2(B) of the first row pixel block BL is set to a high level, and the transistor TX2(B) is turned on. As a result of this operation, the signal charge held in the capacitor CH(B) of the pixel PX(B) of the first row pixel block BL (the charge transferred from the photodiode PDa(B) of the pixel PX(B) to the capacitor CH(B)) is transferred to and held in the floating capacitance section FD.

[0175] At a predetermined timing between the end of period T160 and the start of period T161, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0176] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0177] During the period T161 following period T151, the control signal φFDRST of the first row pixel block BL is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N2 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0178] During the period T162 following period T151, the control signal φTXb1(B) of the first row of pixel block BL is set to high level, turning on the transistor TXb1(B). This operation transfers the charge accumulated in the photodiode PDb(B) of pixel PX(B) of the first row of pixel block BL to the capacitor CH(B) of that pixel PX(B) and holds it there. The charge transferred to the capacitor CH(B) during period T162 of the first series of periods is the unwanted charge accumulated in the photodiode PDb(B). On the other hand, the charge transferred to the capacitor CH(B) during period T162 of the second series of periods is the signal charge that forms the focus detection signal. The period from the end of period T162 of the first series of periods to the start of period T162 of the second series of periods is the exposure period for the photodiode PDb(B) of pixel PX(B) of the first row of pixel block BL.

[0179] At a predetermined timing between the end of period T161 and the start of period T163, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0180] During the period T163 following period T151, the control signal φTX2(B) of the first row pixel block BL is set to a high level, turning on the transistor TX2(B). This operation causes the signal charge held in the capacitor CH(B) of the pixel PX(B) of the first row pixel block BL (the charge transferred from the photodiode PDb(B) of the pixel PX(B) to the capacitor CH(B)) to be transferred to and held in the floating capacitance section FD.

[0181] At a predetermined timing between the end of period T163 and the end of period T151, the potential appearing at the gate of the amplification transistor AMP of the first row of pixel block BL is amplified by the amplification transistor AMP of the pixel block BL, then output to the vertical signal line 24 corresponding to the pixel block BL via the selection transistor SEL of the pixel block BL, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0182] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0183] Similarly, the second row of pixel block BL is read out during period T142. The control signal for the second row of pixel block BL during period T142 is the same as the control signal for the first row of pixel block BL during period T141. In the same manner, when focus detection signals are output from all rows of pixel block BL, the series of periods ends.

[0184] As can be understood from the above explanation, the solid-state image sensor in this embodiment can obtain a focus detection signal. When obtaining a focus detection signal, the exposure periods of the photodiodes PDa(A), PDb(A), PDa(B), and PDb(B) are shifted for each row of the pixel block BL, and even for pixels PX in the same row of the pixel block BL, the exposure periods of the photodiodes PDa(A), PDb(A), PDa(B), and PDb(B) are shifted.

[0185] This embodiment also provides the same advantages as the first embodiment. Furthermore, in this embodiment, since two pixels PX share a set of floating capacitance units FD, amplification transistors AMP, reset transistors FDRST and selection transistors SEL, the aperture ratio can be increased, and consequently, the signal-to-noise ratio can be increased.

[0186] In this embodiment, for every two adjacent pixels PX in the column direction, those two pixels PX share one set of floating capacitance unit FD, amplification transistor AMP, reset transistor FDRST, selection transistor SEL, and node N2. However, in the present invention, for example, every three or more predetermined number of adjacent pixels PX in the column direction, those predetermined number of pixels PX may share one set of floating capacitance unit FD, amplification transistor AMP, reset transistor FDRST, selection transistor SEL, and node N2. Furthermore, in the present invention, modifications similar to those used to modify the first embodiment may be applied to the second embodiment.

[0187] [Fourth Embodiment]

[0188] Figure 13 is a circuit diagram showing one pixel PX of a solid-state image sensor used in an electronic camera according to the fourth embodiment of the present invention, and corresponds to Figure 3. In Figure 13, elements that are the same as or corresponding to elements in Figure 3 are denoted by the same reference numerals, and redundant explanations are omitted. The differences between this embodiment and the first embodiment are described below.

[0189] In this embodiment, as shown in Figure 13, each pixel PX includes first and second photodiodes PDa and PDb as first and second photoelectric conversion units that generate and store charge corresponding to incident light guided by the same microlens 30, a transistor TX11 as a first switch that electrically connects and disconnects the first photodiode PDa and the first node N11, a capacitor CH provided at the first node N11 as a first charge holding unit to which the charge generated and stored by the first photodiode PDa is transferred and held, a transistor TX12 as a second switch that electrically connects and disconnects the first node N11 and the second node N12, and a capacitor that electrically connects the second node N12 and the third node N13. The system includes a transistor TX13 as a third switch for blocking, a transistor TX14 as a fourth switch for electrically connecting and disconnecting the second photodiode PDb and the second node N12, a floating capacitance FD as a second charge holding unit provided at the third node N13 where charge is transferred and held from capacitor CH and / or the second photodiode PDb, an amplifying transistor AMP as an amplification unit that outputs a signal corresponding to the charge held in the floating capacitance FD, a reset transistor FDRST as a reset unit that resets the potential of the third node N13, and a selection transistor SEL as a selection unit that selects the pixel PX, all connected as shown in Figure 13. Transistors TX12 and TX13 electrically connect and disconnect the capacitor CH and the floating capacitance FD. Transistor TX4, together with transistor TX13, electrically connects and disconnects the second photodiode PDb. In this embodiment, capacitor CH may have a structure with metal electrodes on both sides, or it may have other structures. The first charge holding component is not limited to a capacitor CH; for example, a storage diode or a MOS capacitor may also be used.

[0190] In this embodiment, each pixel PX has the same structure and can output focus detection signals and image signals at different timings. However, the embodiment is not limited to this, and the solid-state image sensor in this embodiment may be configured such that a focus detection area is provided in a predetermined part, pixels having the circuit shown in Figure 3 are arranged in this area to generate focus detection signals, and pixels having only one photoelectric conversion unit are arranged in the other areas to generate only image signals.

[0191] The gate of transistor TX11 is connected in common to each pixel row, and the control signal φTX11 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of transistor TX12 is connected in common to each pixel row, and the control signal φTX12 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of transistor TX13 is connected in common to each pixel row, and the control signal φTX13 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of transistor TX14 is connected in common to each pixel row, and the control signal φTX14 is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of reset transistor FDRST is connected in common to each pixel row, and the control signal φFDRST is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23. The gate of selection transistor SEL is connected in common to each pixel row, and the control signal φSEL is supplied to it from the vertical scanning circuit 22 via a predetermined wiring of the control line 23.

[0192] In this embodiment, transistors TX11, TX12, TX13, TX14, AMP, FDRST, and SEL are all nMOS transistors.

[0193] Figure 14(a) is a timing chart showing an example of the readout operation of the solid-state image sensor in this embodiment when reading out an image signal. Period T171 is the period during which all pixels PX in all rows are driven simultaneously. That is, during period T171, the same control signal is output from the vertical scanning circuit 22 for all rows. Period T172 is the period during which the first row is read out, and period T173 is the period during which the second row is read out, and the control signal shown in this figure is output only for the selected row. In this example, in order to acquire a still image, the series of periods from period T171 to the readout period of the last row is repeated twice. The first series of periods is a reset period to eliminate unwanted charges from the photodiodes PDa and PDb and reset them, and the second series of periods is the actual readout period for each row. The series of periods may be repeated three or more times to acquire a moving image.

[0194] First, during period T181 within period T171, the control signals φTX11, φTX12, and φTX14 of all rows are set to high level, and the transistors TX11, TX12, and TX14 of all rows are turned ON. This operation transfers the charge accumulated in the photodiodes PDa and PDb of each pixel PX to the capacitor CH of that pixel PX, where it is added up and held. The charge transferred to capacitor CH during period T181 of the first series of periods is the unwanted charge accumulated in the photodiodes PDa and PDb. On the other hand, the charge transferred to capacitor CH during period T11 of the second series of periods is the signal charge that forms the captured image. The period from the end of period T181 of the first series of periods to the start of period T181 of the second series of periods becomes the exposure period, and this exposure period is the same for all rows and at the same timing. Therefore, all pixels PX can acquire image information without timing misalignment, and imaging using a global electronic shutter is realized.

[0195] The following explanation describes the second series of periods following the exposure period, but the same applies to the first series of periods.

[0196] During period T182 within period T172, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T182, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0197] During period T183 within period T182, the control signal φFDRST on the first line is set to a high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N13 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0198] At a predetermined timing between the end of period T183 and the start of period T184, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0199] During the period T184 following period T182, the control signals φTX12 and φTX13 of the first row are set to a high level, and transistors TX12 and TX13 are turned on. As a result of this operation, the signal charge held in the capacitor CH of the pixel PX of the first row (the charge transferred from the photodiodes PDa and PDb of the pixel PX to the capacitor CH and then added together) is transferred to and held in the floating capacitance section FD.

[0200] At a predetermined timing between the end of period T184 and the end of period T182, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0201] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital image signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output as digital image signals to the outside (digital signal processing unit 6 in Figure 1).

[0202] Similarly, the second row is read during period T173. The control signal for the second row in period T173 is the same as the control signal for the first row in period T172. In the same manner, once image signals are output from all rows, the series of periods ends, and the acquisition of one frame of image is completed.

[0203] As can be understood from the above explanation, although each pixel PX has two photodiodes PDa and PDb, it can output an image signal as usual. Moreover, a global electronic shutter is possible with the exposure timing of all pixel PX being the same.

[0204] Figure 14(b) is a timing chart showing an example of the readout operation of the solid-state image sensor in this embodiment when reading out the focus detection signal. Period T191 is the period during which the first row is read out, and period T192 is the period during which the second row is read out. The control signal shown in this figure is output only for the selected row. In this example, in order to acquire the focus detection signal, a series of periods from period T191 to the readout period of the last row is repeated twice. The first series of periods is a reset period to eliminate unwanted charges from the photodiodes PDa and PDb and reset them, and the second series of periods is the actual readout period for each row.

[0205] The following explanation will primarily describe the second series of periods, but the same principles apply to the first series of periods.

[0206] During period T201 within period T191, the control signal φSEL for the first row is set to a high level, and the selection transistor SEL is turned on. As a result, the pixel PX of the first row is selected, and during this period T201, a signal is output from the pixel PX of the first row to the vertical signal line 24.

[0207] During period T202 within period T201, the control signal φFDRST on the first line is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N13 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0208] At a predetermined timing between the end of period T202 and the start of period T203, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0209] During the period T203 following period T201, the control signals φTX11, φTX13, and φTX14 of the first row are set to high levels, and transistors TX11, TX13, and TX14 are turned on. This operation causes the charge accumulated in the photodiode PDa of the first row pixel PX to be transferred to and held in the capacitor CH of the same pixel PX, while the charge accumulated in the photodiode PDb of the first row pixel PX is transferred to and held in the floating capacitance FD of the same pixel PX. The charge transferred to capacitor CH during period T203 of the first series of periods is the unwanted charge accumulated in photodiode PDa. Also, the charge transferred to floating capacitance FD during period T203 of the first series of periods is the unwanted charge accumulated in photodiode PDb. On the other hand, the charge transferred to capacitor CH during period T203 of the second series of periods is the signal charge that forms the focus detection signal. Furthermore, the charge transferred to the floating capacitance unit FD during period T203 of the second series of periods is a signal charge that forms the focus detection signal. The period from the end of period T203 in the first series of periods to the start of period T203 in the second series of periods is the exposure period for the photodiodes PDa and PDb of the first row of pixels PX. Thus, the exposure periods for the photodiodes PDa and PDb of the same pixel PX are the same and occur at the same timing.

[0210] At a predetermined timing between the end of period T203 and the start of period T204, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0211] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0212] During the period T204 following period T201, the control signal φFDRST on the first line is set to high level, and the reset transistor FDRST is turned on. This operation resets the potential of node N13 (the potential of the floating capacitance FD and the gate potential of the amplification transistor AMP) to the power supply voltage VDD.

[0213] At a predetermined timing between the end of period T204 and the start of period T205, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as a dark signal by the CDS circuit 27.

[0214] During the period T205 following period T201, the control signals φTX12 and φTX13 of the first row are set to a high level, and transistors TX12 and TX13 are turned on. As a result of this operation, the signal charge held in the capacitor CH of the pixel PX of the first row (the charge transferred from the photodiode PDa of the pixel PX to the capacitor CH) is transferred to and held in the floating capacitance FD of the pixel PX.

[0215] At a predetermined timing between the end of period T205 and the end of period T201, the potential appearing at the gate of the amplification transistor AMP of the first row pixel PX is amplified by the amplification transistor AMP of the pixel PX, then output to the vertical signal line 24 corresponding to the pixel PX via the selection transistor SEL of the pixel PX, amplified by the column amplifier 26, and then sampled as an optical signal by the CDS circuit 27.

[0216] Subsequently, the CDS circuit 27 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled optical signal. The A / D converter 28 converts this difference-corresponding signal into a digital signal and holds it. The digital signals held by each A / D converter 28 are horizontally scanned by the horizontal readout circuit 29 and output to the outside (digital signal processing unit 6 in Figure 1) as a digital focus detection signal.

[0217] Similarly, the second row is read during period T192. The control signal for the second row in period T192 is the same as the control signal for the first row in period T191. In the same manner, when focus detection signals are output from all rows, the series of periods ends.

[0218] As can be understood from the above explanation, the solid-state image sensor in this embodiment can obtain a focus detection signal. When obtaining a focus detection signal, the exposure periods of photodiodes PDa and PDb are shifted for each row of pixels PX, and for pixels PX in the same row, the exposure periods of photodiode PDa and photodiode PDb coincide.

[0219] Thus, this embodiment, like the comparative example described with reference to Figures 6 and 7, enables imaging using a global electronic shutter and allows obtaining a focus detection signal.

[0220] In this embodiment, when obtaining a focus detection signal, the exposure periods of photodiodes PDa and PDb are staggered for each row of pixels PX, whereas in the comparative example, a focus detection signal can be obtained using a global electronic shutter with the exposure timing of all pixels PX being the same. Therefore, in the comparative example, the accuracy of focus detection is improved even when the subject is moving quickly, compared to this embodiment.

[0221] However, in the comparative example, two capacitors CHa and CHb are required for each pixel PX, whereas in this embodiment, only one capacitor CH is needed for each pixel PX, thus reducing the number of capacitors in each pixel PX compared to the comparative example. Therefore, according to this embodiment, the area ratio of photodiodes PDa and PDb in each pixel PX (i.e., aperture ratio) can be increased compared to the comparative example, and consequently, images with a higher signal-to-noise ratio can be captured. As can be seen from the comparison between Figure 13 and Figure 6, the number of transistors required for each pixel PX is the same in both this embodiment and the comparative example.

[0222] Thus, according to this embodiment, imaging using a global electronic shutter can be achieved and a focus detection signal can be obtained. Furthermore, although the focus detection accuracy for fast-moving subjects is slightly lower compared to the comparative example, it is possible to capture images with a larger aperture ratio and a higher signal-to-noise ratio.

[0223] As can be seen from comparing Figure 3 and Figure 6, this embodiment requires one more transistor as a component of each pixel PX compared to the first embodiment. However, in the first embodiment, when obtaining a focus detection signal, the exposure period of photodiode PDa and the exposure period of photodiode PDb are out of sync even for pixels PX in the same row, whereas in this embodiment, when reading out a focus detection signal, the exposure period of photodiode PDa and the exposure period of photodiode PDb coincide for pixels PX in the same row. Therefore, according to this embodiment, the accuracy of focus detection is improved even when the subject is moving quickly, compared to the first embodiment.

[0224] Although various embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, in the present invention, the solid-state image sensor is not limited to being composed of a single chip, but may have a structure in which multiple chips are joined together. [Explanation of Symbols]

[0225] 1. Electronic camera 4. Solid-state image sensor 22 Vertical scanning circuit (control unit) PX pixels PD photodiode TXa1, TXb1, TX2, TXa2, TXb2, TX11~TX12 Transistors (Switches) AMP (amplifying transistor) RST Reset Transistor CH Capacitor (first charge holding part) FD Floating Capacitor Section (Second Charge Holding Section) SEL Select Transistor

Claims

1. The first microlens into which light emitted from the optical system is incident, A microlens into which light emitted from the optical system is incident, comprising a second microlens positioned next to the first microlens in the column direction, A first photoelectric conversion unit that converts light transmitted through the first microlens into electric charge, A second photoelectric conversion unit that converts light transmitted through the first microlens into an electric charge, A third photoelectric conversion unit that converts light transmitted through the second microlens into an electric charge, A fourth photoelectric conversion unit that converts light transmitted through the second microlens into an electric charge, A first transfer unit that transfers the charge converted by the first photoelectric conversion unit, A second transfer unit that transfers the charge converted by the second photoelectric conversion unit, A third transfer unit that transfers the charge converted by the third photoelectric conversion unit, A fourth transfer unit that transfers the charge converted by the fourth photoelectric conversion unit, A first charge holding unit that holds the charge transferred from the first photoelectric conversion unit by the first transfer unit and the charge transferred from the second photoelectric conversion unit by the second transfer unit, A second charge holding unit that holds the charge transferred from the third photoelectric conversion unit by the third transfer unit and the charge transferred from the fourth photoelectric conversion unit by the fourth transfer unit, A fifth transfer unit that transfers the charge held in the first charge holding unit, A sixth transfer unit that transfers the charge held in the second charge holding unit, A third charge holding unit that holds the charge transferred from the first charge holding unit by the fifth transfer unit and the charge transferred from the second charge holding unit by the sixth transfer unit, The output unit has a transistor including a gate electrically connected to the third charge holding unit, and when outputting a signal for detecting the focus of the optical system, it outputs a first signal based on the charge held in the third charge holding unit and converted by the first photoelectric conversion unit, a second signal based on the charge held in the third charge holding unit and converted by the second photoelectric conversion unit, a third signal based on the charge held in the third charge holding unit and converted by the third photoelectric conversion unit, and a fourth signal based on the charge held in the third charge holding unit and converted by the fourth photoelectric conversion unit. An image sensor equipped with the following features.

2. In the image sensor according to claim 1, An image sensor comprising a control unit that controls the first transfer unit and the second transfer unit so that when outputting a signal for detecting the focus of the optical system, the timing at which the charge converted in the first photoelectric conversion unit is transferred to the first charge holding unit by the first transfer unit and the timing at which the charge converted in the second photoelectric conversion unit is transferred to the first charge holding unit by the second transfer unit are different.

3. In the image sensor according to claim 1 or claim 2, When the output unit outputs a signal for generating an image of the captured subject, it outputs a fifth signal based on the charge held in the third charge holding unit, which is the charge converted by the first photoelectric conversion unit and the charge converted by the second photoelectric conversion unit. Image sensor.

4. In the image sensor according to any one of claims 1 to 3, The second photoelectric conversion unit is positioned next to the first photoelectric conversion unit in the row direction. Image sensor.

5. In the image sensor according to any one of claims 1 to 3, The second photoelectric conversion unit is arranged next to the first photoelectric conversion unit in the row direction. Image sensor.

6. In the image sensor according to claim 2, When the control unit outputs a signal for detecting the focus of the optical system, it controls the third transfer unit and the fourth transfer unit so that the timing at which the charge converted in the third photoelectric conversion unit is transferred to the second charge holding unit by the third transfer unit and the timing at which the charge converted in the fourth photoelectric conversion unit is transferred to the second charge holding unit by the fourth transfer unit are different. Image sensor.

7. In the image sensor according to claim 4, The fourth photoelectric conversion unit is positioned next to the third photoelectric conversion unit in the row direction. Image sensor.

8. In the image sensor according to claim 5, The fourth photoelectric conversion unit is positioned next to the third photoelectric conversion unit in the row direction. Image sensor.

9. In the image sensor according to any one of claims 1 to 8, An image sensor having signal lines that are electrically connected to the output unit and on which the first signal and the second signal are output.

10. In the image sensor according to claim 9, An image sensor comprising a conversion unit that converts the first signal output on the signal line and the second signal output on the signal line into digital signals.

11. An imaging device comprising an image sensor according to any one of claims 1 to 10.

12. In the imaging apparatus according to claim 11, An imaging device comprising a focus calculation unit that calculates the amount of defocus of the optical system using the first signal and the second signal.

13. In the imaging apparatus according to claim 12, An imaging device comprising an adjustment unit that adjusts the focus of the optical system based on the amount of defocus calculated by the focus calculation unit.

Images