Semiconductor equipment

Abstract

To inhibit occurrence of burrs on a rear surface.SOLUTION: A semiconductor device 10 has spacers 24a, 24b which are provided protruding downward from a lower surface of a metal plate 23 at four corners of the metal plate 23 in a plan view. Even if such an insulation circuit board 20 is housed in a cavity and sealed with a sealing member 50, the sealing member 50 is inhibited from penetrating into the four corners on a rear surface of the insulation circuit board 20. Accordingly, burrs are inhibited from occurring at the four corners on the rear surface of the insulation circuit board 20. The burrs are inhibited from occurring to inhibit deterioration of heat radiation performance of the semiconductor device 10 and thus increase of manufacturing costs of the semiconductor device 10 is inhibited. Therefore, deterioration of reliability of the semiconductor device 10 is prevented.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device includes a power device and is used as a power conversion device. The power device is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Further, in the semiconductor device, a semiconductor chip including the power device and an insulating circuit board are sealed by a sealing member.

[0003] In manufacturing a semiconductor device, first, an insulating circuit board to which a semiconductor chip is joined is disposed in a cavity within a predetermined mold. A sealing member is injected into the cavity to fill the cavity with the sealing member. By detaching the mold, a semiconductor device in which the semiconductor chip and the insulating circuit board are sealed by the sealing member is obtained.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Insulated circuit boards to which semiconductor chips are bonded can warp downwards due to heating during sealing with a sealing material. This creates gaps between the warped insulated circuit board and the cavity placement surface. The gaps are particularly large at the four corners of the insulated circuit board. The sealing material filled into the cavity also enters these gaps. Once filling is complete and the sealing material solidifies, the sealing material that has entered the gaps becomes burrs. Because burrs have low thermal conductivity, semiconductor devices with burrs on their underside have reduced heat dissipation. Furthermore, removing burrs increases manufacturing costs due to the process. If burrs are not properly removed, the remaining burrs can cause excessive stress on the semiconductor device. Consequently, the reliability of the semiconductor device is reduced due to the burrs.

[0006] This invention has been made in view of these points, and aims to provide a semiconductor device in which the generation of burrs on the back surface is suppressed. [Means for solving the problem]

[0007] According to one aspect of the present invention, a semiconductor chip, a rectangular metal plate, a rectangular insulating plate, and a circuit pattern are stacked in order, the semiconductor chip is placed on the circuit pattern on the front surface, an insulating circuit board is curved downwards with the metal plate on the back surface facing downwards, and the insulating circuit board is provided protruding downwards from the four corners of the metal plate in a plan view, and curved downwards in a side view. Back side A semiconductor device is provided, having a spacer portion that is flush with the central part or protrudes below the central part, and a sealing member that seals the front surface of the insulating circuit board and the side of the insulating circuit board and the spacer side facing the outside of the spacer portion, wherein the spacer portion is separate from the metal plate and the sealing member. [Effects of the Invention]

[0008] According to the disclosed technology, burr generation is suppressed, a decrease in heat dissipation is prevented, and a decrease in the reliability of the semiconductor device can be suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view of the semiconductor device according to the first embodiment. [Figure 2] This is a side cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] This is a rear view of the semiconductor device according to the first embodiment. [Figure 4] This is a plan view (part 1) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] This is a side cross-sectional view (part 1) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] This is a plan view (part 2) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] This is a side cross-sectional view (part 2) showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] This is a side cross-sectional view of a semiconductor device to which the heat dissipation unit of the first embodiment is attached. [Figure 9] This is a rear view of a semiconductor device according to Modification 1 of the First Embodiment. [Figure 10] This is a side cross-sectional view of a semiconductor device according to Modification 1 of the first embodiment. [Figure 11] This is a rear view of a semiconductor device of a modified example 2 of the first embodiment. [Figure 12] This is a side cross-sectional view of a semiconductor device according to a modified example 2 of the first embodiment. [Figure 13] This is a side cross-sectional view of a semiconductor device according to a modified example 3 of the first embodiment. [Figure 14] This is a side cross-sectional view of a semiconductor device according to Modification 4-1 of the first embodiment. [Figure 15] This is a rear view of a semiconductor device according to Modification 4-1 of the first embodiment. [Figure 16] This is a cross-sectional view (part 1) showing the manufacturing process of a semiconductor device of modified example 4-1 of the first embodiment. [Figure 17] This is a cross-sectional view (part 2) showing the manufacturing process of a semiconductor device of modified example 4-1 of the first embodiment. [Figure 18]Cross-sectional view (part 3) showing the manufacturing process of the semiconductor device according to Modification Example 4-1 of the First Embodiment. [Figure 19] Back view (part 1) of the semiconductor device according to Modification Example 4-2 of the First Embodiment. [Figure 20] Back view (part 2) of the semiconductor device according to Modification Example 4-2 of the First Embodiment. [Figure 21] Side cross-sectional view of the semiconductor device according to Modification Example 5 of the First Embodiment. [Figure 22] Side cross-sectional view of the semiconductor device according to the Second Embodiment. [Figure 23] Side cross-sectional view showing the manufacturing process of the semiconductor device according to the Second Embodiment. [Figure 24] Side cross-sectional view of the semiconductor device with the heat dissipation unit attached according to the Second Embodiment. [Figure 25] Side cross-sectional view of the semiconductor device according to the modification of the Second Embodiment. [Figure 26] Side cross-sectional view showing the manufacturing process of the semiconductor device according to the modification of the Second Embodiment.

Embodiments for Carrying Out the Invention

[0010] The embodiments will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the surface facing upwards (+Z direction) in the semiconductor device 10 in Figures 1 to 3. Similarly, "up" refers to the direction upwards (+Z direction) in the semiconductor device 10 in Figures 1 to 3. "Back surface" and "bottom surface" refer to the surface facing downwards (-Z direction) in the semiconductor device 10 in Figures 1 to 3. Similarly, "down" refers to the direction downwards (-Z direction) in the semiconductor device 10 in Figures 1 to 3. The same directionality will be used in other drawings as needed. "Front surface," "top surface," "up," "back surface," "bottom surface," "down," and "side" are merely convenient expressions to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. Also, in the following description, "main component" refers to a case where it contains 80 vol% or more.

[0011] [First Embodiment] The semiconductor device of the first embodiment will be described below with reference to the drawings, using Figures 1 to 3. Figure 1 is a plan view of the semiconductor device of the first embodiment, Figure 2 is a side cross-sectional view of the semiconductor device of the first embodiment, and Figure 3 is a rear view of the semiconductor device of the first embodiment. Figure 1 is a plan view showing the semiconductor device 10 in perspective. Figure 2 is a cross-sectional view taken along the dashed line YY in Figure 1.

[0012] The semiconductor device 10 comprises an insulating circuit board 20, semiconductor chips 31 and 32, lead frames 40, 41a to 41j, 43 and 44, bonding wires 45, and a sealing member 50. The semiconductor chips 31 and 32 are arranged on the front surface (top surface) of the insulating circuit board 20. The semiconductor chips 31 and 32 are sealed from the front surface and sides of the insulating circuit board 20 by the sealing member 50. The insulating circuit board 20 is curved downwards with its back surface facing downwards. The curvature of the insulating circuit board 20 will be described later. The insulating circuit board 20 has spacer portions 24a to 24d at each of its four corners, which protrude downwards.

[0013] The insulated circuit board 20 is rectangular in shape when viewed from above. The insulated circuit board 20 includes an insulating plate 21, circuit patterns 22a and 22b provided on the front surface (top surface) of the insulating plate 21, and a metal plate 23 provided on the back surface (bottom surface) of the insulating plate 21. Semiconductor chips 31 and 32 are mechanically and electrically connected to the front surface (top surface) of the circuit patterns 22a and 22b by solder 33a.

[0014] The insulating plate 21 has a rectangular shape when viewed from above. The corners of the insulating plate 21 may also be chamfered to an R-shape or C-shape. The insulating plate 21 is made of a ceramic material with good thermal conductivity. The ceramic material is, for example, made of a material mainly composed of aluminum oxide, aluminum nitride, or silicon nitride. The thickness of the insulating plate 21 is between 0.2 mm and 2.0 mm.

[0015] The circuit patterns 22a and 22b are formed across the entire surface of the insulating plate 21, excluding the edges. Preferably, in a plan view, the outer edges of the circuit patterns 22a and 22b on the insulating plate 21 overlap with the outer edges of the metal plate 23 on the insulating plate 21. This maintains a stress balance between the insulating circuit board 20 and the metal plate 23 on the back of the insulating plate 21. This suppresses excessive warping, cracking, and other damage to the insulating plate 21.

[0016] Furthermore, the thickness of the circuit patterns 22a and 22b is 0.1 mm or more and 2.0 mm or less. The circuit patterns 22a and 22b are made of a metal with excellent conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. In addition, the surfaces of the circuit patterns 22a and 22b may be plated to improve corrosion resistance. The plating material used in this case may be, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. The circuit patterns 22a and 22b on the insulating plate 21 are obtained by forming a metal plate on the front surface of the insulating plate 21 and performing an etching or other treatment on this metal plate. Alternatively, the circuit patterns 22a and 22b cut out from a metal plate in advance may be pressed onto the front surface of the insulating plate 21. Note that the circuit patterns 22a and 22b are just examples. The number, shape, size, etc. of the circuit patterns may be appropriately selected as needed.

[0017] The metal plate 23 has a rectangular shape when viewed from above. Its corners may be chamfered to an R-shape or C-shape. The metal plate 23 is smaller than the insulating plate 21 and covers the entire surface of the insulating plate 21, excluding the edges. The metal plate 23 is mainly composed of a metal with excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. The thickness of the metal plate 23 is between 0.1 mm and 2.0 mm. Plating may be performed to improve the corrosion resistance of the metal plate 23. Examples of plating materials used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0018] As such an insulated circuit board 20, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board can be used. Furthermore, when bonding semiconductor chips 31 and 32 to the circuit patterns 22a and 22b of the insulated circuit board 20 with solder 33a, a heat treatment is applied. In the insulated circuit board 20, the insulating plate 21, the circuit patterns 22a and 22b, and the metal plate 23 have different coefficients of thermal expansion. When the insulated circuit board 20 is heated, it warps so that the center of the metal plate 23 is convex downwards (-Z direction) (see, for example, the insulated circuit board 20 in Figure 5).

[0019] Furthermore, spacer portions 24a to 24d are formed at the four corners of the back surface of the metal plate 23 of the insulating circuit board 20, protruding downwards (in the -Z direction). Each of the spacer portions 24a to 24d is rectangular in plan view (XY plane). Each of the spacer portions 24a to 24d is rectangular in cross-sectional view (XZ plane or YZ plane). Each of the spacer portions 24a to 24d may be a rectangular prism. One corner of each of the spacer portions 24a to 24d coincides with a corner of the metal plate 23, and the two sides constituting that corner correspond to the sides of the metal plate 23, and are provided at the four corners of the metal plate 23. For this reason, the shape of the spacer portions 24a to 24d in plan view (XY plane) is not limited to a rectangle, but may have two orthogonal sides corresponding to the region including the corner of the metal plate 23. Examples of such spacer portions 24a to 24d may be L-shaped or right-angled triangles. Various modifications of the spacer sections 24a to 24d will be described later.

[0020] Alternatively, spacer portions 24a to 24d are formed near the four corners on the back surface of the metal plate 23 of such an insulating circuit board 20, protruding downwards (in the -Z direction). The outer edges of the spacer portions 24a to 24d are formed on the back surface of the metal plate 23 of the insulating circuit board 20, at least outside the area corresponding to the bonding area of ​​the semiconductor chips 31 and 32 when viewed from above. In this case, it is sufficient to have two sides parallel to the two sides that constitute the corners of the metal plate 23. Examples of such spacer portions 24a to 24d include rectangular, L-shaped, and right-angled triangular shapes.

[0021] Furthermore, the height of the spacer portions 24a to 24d is greater than or equal to the warp amount Hc of the insulating circuit board 20 and less than or equal to the warp amount Hc + 200 μm. The warp amount Hc is the height from position P0, which is the center of the insulating circuit board 20 that is warped downwards, to position P1, which is the edge of the insulating circuit board 20 (metal plate 23), as shown in Figure 2. Also, the warp amount Hc is the height from the lowest position P0 (-Z direction) on the back surface of the metal plate 23 to the highest position P1 (+Z direction), with the XY plane, which is the front surface of the semiconductor chips 31 and 32, as the reference plane. The warp amount Hc depends on the material of the insulating circuit board 20, etc. The warp amount Hc is, for example, 50 μm or more and 200 μm or less. In Figure 2, the back surfaces of the spacer portions 24a to 24d, which are located at the four corners of the insulating circuit board 20, are shown to be substantially flush with the center of the back surface of the insulating circuit board 20. Furthermore, the front surfaces of the spacer portions 24a to 24d (the surfaces that contact the metal plate 23) may be inclined to accommodate the curvature of the metal plate 23. This allows the back surfaces of the spacer portions 24a to 24d, located at the four corners of the back surface of the insulating circuit board 20, to be kept substantially horizontal.

[0022] Furthermore, the spacer portions 24a to 24d are made of a material with excellent thermal conductivity. Such materials mainly consist of metals or ceramics. Such metals are, for example, copper, aluminum, tin, or alloys containing at least one of these. It is also preferable that such metals are of the same type as the metal plate 23. Furthermore, the spacer portions 24a to 24d may be integrally formed with the metal plate 23. Such ceramics are materials mainly composed of aluminum oxide, aluminum nitride, or silicon nitride. In addition, the surfaces of the spacer portions 24a to 24d may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0023] The semiconductor chips 31 and 32 include switching elements made of silicon or silicon carbide. These switching elements are, for example, IGBTs and power MOSFETs. If the semiconductor chips 31 and 32 are IGBTs, they have a collector electrode as the main electrode on their back surface. They also have a gate electrode as a control electrode and an emitter electrode as the main electrode on their front surface. If the semiconductor chips 31 and 32 are power MOSFETs, they have a drain electrode as the main electrode on their back surface. They also have a gate electrode as a control electrode and a source electrode as the main electrode on their front surface. The back surfaces of the semiconductor chips 31 and 32 are mechanically and electrically joined to circuit patterns 22a and 22b via solder 33a. Lead frames 42 and 44 are mechanically and electrically joined to the main electrodes on the front surface of the semiconductor chips 31 and 32 via solder 33b. Furthermore, bonding wires 45 are mechanically and electrically joined to the control electrodes on the front surfaces of the semiconductor chips 31 and 32 as appropriate.

[0024] Alternatively, the semiconductor chips 31 and 32 include diodes made of silicon or silicon carbide. The diodes are, for example, FWDs (Free Wheeling Diodes) such as SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes. Such semiconductor chips 31 and 32 have an output electrode (cathode electrode) as the main electrode on their back surface and an input electrode (anode electrode) as the main electrode on their front surface. The back surfaces of the above semiconductor chips 31 and 32 are mechanically and electrically joined to the circuit patterns 22a and 22b via solder 33a. Lead frames 42 and 44 are also mechanically and electrically joined to the main electrodes on the front surfaces of the semiconductor chips 31 and 32 via solder 33b.

[0025] Furthermore, instead of semiconductor chips 31 and 32, RC (Reverse-Conducting) IGBTs, which combine the functions of IGBTs and FWDs, may be used. Also, auxiliary emitter electrodes may be provided on the front surface of semiconductor chips 31 and 32 as control electrodes. Additionally, temperature-sensing electrodes and current-sensing electrodes may be provided on the front surface of semiconductor chips 31 and 32 as control electrodes. In this case, bonding wires 45 are appropriately joined mechanically and electrically to each control electrode. Moreover, the first embodiment merely shows the case where two sets of semiconductor chips 31 and 32 are provided. The number of sets is not limited to two, and can be provided according to the specifications of the semiconductor device 10, etc.

[0026] The lead frames 40, 41a-41j, 43, and 44 have one end electrically connected to the semiconductor chips 31 and 32 inside the sealing member 50. The other ends of the lead frames 40, 41a-41j, 43, and 44 extend individually. These other ends may be external connection terminals connected to external equipment. The semiconductor device 10 may be a device that constitutes a single-phase inverter circuit. In that case, the other end of lead frame 40 may be an output terminal in the semiconductor device 10. The other ends of lead frames 41a-41j may be control terminals in the semiconductor device 10. The other end of lead frame 43 may be a positive-side input terminal (P terminal). The other end of lead frame 44 may be a negative-side input terminal (N terminal). The lead frames 40, 41a-41j, 42-44 are made of a metal with excellent conductivity. Such a metal may be, for example, copper, aluminum, or an alloy containing at least one of these. Furthermore, the surfaces of the lead frames 40, 41a-41j, and 42-44 may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0027] One end of the lead frame 40 is joined to the circuit pattern 22b inside the sealing member 50 via solder 33b as a joining member. The joining member is not limited to solder 33b, but may be a sintered body. Alternatively, one end of the lead frame 40 is directly joined to the circuit pattern 22b inside the sealing member 50 by, for example, laser welding or ultrasonic welding. The other end of the lead frame 40 extends outward (+X direction) from the sealing side surface 50e of the sealing member 50. The other end of the lead frame 40 may be an external connection terminal (output terminal) connected to an external device not shown. The other end of the lead frame 40 is located above (+Z direction) the one end of the lead frame 40. The lead frame 40 includes an intermediate section that connects the one end and the other end. This intermediate section extends vertically upward (+Z direction) or diagonally upward from the one end and is connected to the other end. Furthermore, the other end of the lead frame 40 is located above (in the +Z direction) the front surface of the semiconductor chips 31 and 32.

[0028] One end of each lead frame 41a to 41d is electrically connected to the semiconductor chip 32 via bonding wires 45 inside the sealing member 50. The other end of each lead frame 41a to 41d extends outward (+X direction) from the sealing side surface 50e of the sealing member 50. The other end of each lead frame 41a to 41d may be an external connection terminal (control terminal) connected to an external device not shown. One end of each lead frame 41f to 41j is electrically connected to the semiconductor chip 31 via bonding wires 45 inside the sealing member 50. The other end of each lead frame 41f to 41j extends outward (+X direction) from the sealing side surface 50e of the sealing member 50. The ends of each lead frame 41a to 41d and lead frames 41f to 41j may be at the same height (Z direction). In other words, the lead frames 41a to 41d and lead frames 41f to 41j may be straight lines in side view. Furthermore, the other ends of lead frames 41a-41d and lead frames 41f-41j may be located above (+Z direction) the front surface of semiconductor chips 31 and 32.

[0029] The lead frame 42 is sealed by a sealing member 50. One end of the lead frame 42 is joined to the main electrode of the semiconductor chip 31 via solder 33b as a bonding member. The other end of the lead frame 42 is mechanically and electrically joined to the circuit pattern 22b via solder 33b as a bonding member. Note that the bonding member is not limited to solder 33b, but may be a sintered body. Alternatively, the other end of the lead frame 42 is directly joined to the circuit pattern 22b by, for example, laser welding or ultrasonic welding.

[0030] One end of the lead frame 43 is electrically and mechanically connected to the circuit pattern 22a inside the sealing member 50 via solder 33b as a joining member. The joining member is not limited to solder 33b; it may also be a sintered body. Alternatively, one end of the lead frame 43 is directly joined to the circuit pattern 22a inside the sealing member 50 by, for example, laser welding or ultrasonic welding. The other end of the lead frame 43 extends outward (-X direction) from the sealing side surface 50d of the sealing member 50. The other end of the lead frame 43 may be an external connection terminal (P terminal) connected to an external device not shown.

[0031] One end of the lead frame 44 is mechanically and electrically joined to the main electrode of the semiconductor chip 32 via solder 33b as a bonding member inside the sealing member 50. The bonding member is not limited to solder 33b; it may also be a sintered body. The other end of the lead frame 44 extends outward (in the -X direction) from the sealing side surface 50d of the sealing member 50. The other end of the lead frame 44 may be an external connection terminal (N terminal) connected to an external device (not shown).

[0032] The other end of each lead frame 43, 44 is located above (in the +Z direction) the other end of each lead frame 43, 44. Each lead frame 43, 44 has an intermediate section connecting the other end. This intermediate section extends vertically upward (in the +Z direction) or diagonally upward from each end and connects to the other end. Furthermore, the other ends of lead frames 43, 44 are located above (in the +Z direction) the front surface of the semiconductor chips 31, 32. Note that lead frames 40, 41a~41j, 42, 43, 44 are examples. The shape, size, extension direction, etc. may be appropriately selected as needed.

[0033] The bonding wire 45 is primarily composed of a metal with excellent conductivity. The metal is, for example, aluminum, copper, or an alloy containing at least one of these. In the case of the bonding wire 45, it is composed of copper or a copper alloy. Furthermore, its diameter is preferably between 25 μm and 1 mm.

[0034] The sealing member 50 is shaped like a rectangular parallelepiped. The sealing member 50 has a sealing top surface 50a, sealing sides 50b to 50e, and a sealing bottom surface 50f. The joints of the sealing sides 50b to 50e may be rounded. The sealing member 50 seals the insulating circuit board 20, the semiconductor chips 31 and 32, and the lead frames 40, 41a to 41j, and 42 to 44. The sealing member 50 also seals a portion of the lead frames 40, 41a to 41j, 43, and 44. Furthermore, the sealing member 50 seals the entire circumference of the side of the insulating circuit board 20, as well as the side portions (spacer sides) facing the outside of the spacer portions 24a to 24d. In the first embodiment, the sealing bottom surface 50f is on the same plane as the bottom surfaces of the spacer portions 24a to 24d and the center of the back surface of the insulating circuit board 20.

[0035] Such a sealing member 50 comprises a thermosetting resin and a filler contained in the thermosetting resin. The thermosetting resin is, for example, an epoxy resin, a phenolic resin, or a maleimide resin. An example of such a sealing member is an epoxy resin containing a filler. Inorganic materials are used as the filler. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0036] Next, the manufacturing method of the semiconductor device 10 will be explained using Figures 4 to 7. Figures 4 and 6 are plan views showing the manufacturing process of the semiconductor device according to the first embodiment, and Figures 5 and 7 are side cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. Note that the frame portion of the tie bar 46, which will be described later, is omitted in Figures 5 to 7. Also, Figure 5 is a side cross-sectional view along the dashed-dotted line XX in Figure 6, and Figure 6 is a plan cross-sectional view along the dashed-dotted line XX in Figure 5. Figure 7 corresponds to the side cross-sectional view in Figure 6.

[0037] First, the components of the semiconductor device 10 are prepared. The components include, for example, an insulating circuit board 20, semiconductor chips 31 and 32, lead frames 40, 41a to 41j, 42 to 44, and spacer parts 24a to 24d. When the semiconductor chips 31 and 32 are joined to the circuit patterns 22a and 22b of the insulating circuit board 20 via solder 33a, as previously described, heating causes a downward convex warp relative to the insulating circuit board 20. Also, the lead frames 40, 41a to 41j, 43, and 44 are integrally connected by a tie bar 46, which is a frame-shaped member. The lead frames 40, 42 to 44 are joined to the insulating circuit board 20 and the semiconductor chips 31 and 32 as shown in Figure 4, and the parts corresponding to lead frames 41a to 41j and the semiconductor chips 31 and 32 are mechanically and electrically joined with bonding wires 45. The insulating circuit board 20, to which the semiconductor chips 31, 32 and lead frames 40, 42~44 are bonded, may be convex in the downward direction (-Z direction). The amount of warping Hc in this case is smaller than the amount of warping Hc after resin encapsulation. The amount of warping Hc depends on the material of the insulating circuit board 20, but is, for example, between 10 μm and 150 μm.

[0038] Next, the insulating circuit board 20, on which the semiconductor chips 31, 32 and lead frames 40, 41a~41j, 42~44 are joined in this manner, is set in the sealing mold 60 as shown in Figures 5 and 6. The sealing mold 60 is mainly composed of a material that has hardness and heat resistance and a small coefficient of thermal expansion. Such a material is, for example, steel. The sealing mold 60 is, for example, cubic in shape and comprises a mold top surface 60a, mold sides 60b~60e, and a mold bottom surface 60f. The sealing mold 60 is also heated to a predetermined temperature at which the sealing resin hardens. This predetermined temperature is, for example, 100°C or higher and 200°C or lower.

[0039] The sealing mold 60 includes an upper mold 61 and a lower mold 62 that can be separated at the mold sides 60b to 60e. The upper mold 61 and the lower mold 62 each have recesses formed so as not to penetrate the bottom. By combining the recesses of the upper mold 61 and the lower mold 62, an internal space (cavity 63b) is formed. The upper mold 61 consists of a frame portion and an upper lid portion. On the back surface of the frame portion of the upper mold 61 (the contact surface with the lower mold 62), there is a groove that serves as a gate 63a into which the sealing member 50 is introduced and an outlet (not shown) for which excess resin is discharged. The lower mold 62 consists of a frame portion opposite to the frame portion of the upper mold 61 and a lower bottom portion. The bottom surface of the recess of the lower mold 62 has a placement surface 63c on which the insulating circuit board 20 is placed. The placement surface 63c is flat (parallel to the XY plane). The front surface of the frame portion of the lower mold 62 (the contact surface with the upper mold 61) is provided with grooves for which the lead frames 40, 41a to 41j, 43, 44 and tie bars 46 are arranged.

[0040] The insulating circuit board 20 is placed in the recess of the lower mold 62, and the upper mold 61 is placed on the lower mold 62, thereby housing the semiconductor chips 31, 32 and the insulating circuit board 20 in the cavity 63b. At this time, the lead frames 40, 41a~41j, 43, 44 and tie bars 46 are placed in the grooves on the front surface of the frame portion of the lower mold 62, and the insulating circuit board 20 is placed on the placement surface 63c.

[0041] Furthermore, the lower mold 62 has four pressing holes formed at positions opposite to the four corners of the metal plate 23 of the insulating circuit board 20. In Figure 5, of the four pressing holes, the pressing holes 62a and 62b along the mold sides 60b and 60c are shown. Spacer parts 24a to 24d are positioned on the pressing holes on the placement surface 63c, respectively. Pressing pins are provided in the pressing holes of the lower mold 62 so as to be movable in the Z direction. In Figure 5, the pressing pins 64a and 64b provided in the pressing holes 62a and 62b are shown. The pressing pins are initially housed inside the pressing holes and are controlled to protrude simultaneously from all pressing holes at a predetermined speed at a predetermined timing. After the sealing member 50 has hardened, the pressing pins 64a and 64b can be made to protrude upward (in the +Z direction) from the bottom surface of the lower mold 62, thereby allowing the insulating circuit board 20 and semiconductor chips 31, 32, etc., sealed with the sealing member 50 to be removed from the lower mold 62.

[0042] Furthermore, when the insulating circuit board 20 is placed on the placement surface 63c of the lower mold 62, spacer portions 24a to 24d are provided at the four corners of the metal plate 23. At this time, the tips of the pressing pins 64a and 64b form the same plane as the placement surface 63c of the lower mold 62. That is, the spacer portions 24a to 24d are located on the pressing holes 62a and 62b of the placement surface 63c, respectively. Alternatively, the tips of the pressing pins 64a and 64b may be made to protrude by a predetermined amount from the placement surface 63c of the lower mold 62, so that the spacer portions 24a to 24d catch on the tips of the pressing pins 64a and 64b. By doing so, when the sealing member 50 is injected, displacement of the spacer portions 24a to 24d and tilting of the insulating circuit board 20 can be prevented, and the insulating circuit board 20 can be stably sealed.

[0043] Furthermore, when the insulating circuit board 20 is set in the upper mold 61, a gate 63a is formed at least above (+Z direction) the semiconductor chips 31 and 32. In Figure 5, the gate 63a is located above the portion of the upper mold 61 corresponding to the lead frame 40. In Figure 5, the gate 63a is parallel to the X direction and communicates with the cavity 63b. Also, as shown in Figure 6, the gate 63a is formed approximately in the center of the left side of the upper mold 61 and facing the lead frame 40 of the tie bar 46.

[0044] In this manner, the mold is opened to separate the upper mold 61 and the lower mold 62, and the insulating circuit board 20 is set in the lower mold 62. Then, the upper mold 61 is placed over the lower mold 62 by clamping, thereby setting the insulating circuit board 20 in the cavity 63b of the sealing mold 60. At this time, the insulating circuit board 20 is heated by the sealing mold 60, causing it to warp downwards. The spacer portions 24a to 24d, which are located at the four corners of the insulating circuit board 20, are in direct contact with the placement surface 63c, and the metal plate 23 of the insulating circuit board 20 is slightly raised from the placement surface 63c except for the four corners. In this case, the gap between the center of the metal plate 23 and the placement surface 63c is, for example, between 10 μm and 200 μm.

[0045] The sealing mold 60 is maintained at a predetermined temperature, and the uncured sealing member 50 is injected through the gate 63a. The gate 63a is formed between the lead frames 43 and 44. The sealing member 50 injected from the gate 63a fills the cavity 63b along the dashed arrows shown in Figures 5 and 6. That is, the sealing member 50 injected from the gate 63a is injected into the cavity 63b from between the lead frames 43 and 44. Subsequently, it flows onto the insulating circuit board 20 and semiconductor chips 31 and 32 from above, advancing from the mold side 60d towards the mold side 60e. As the sealing member 50 advances in this manner, it also spreads to the mold sides 60b and 60c. In this way, the sealing member 50 seals the insulating circuit board 20 and semiconductor chips 31 and 32. That is, the insulating circuit board 20 and semiconductor chips 31 and 32 are pressed towards the placement surface 63c by the sealing member 50. As a result, the back surface of the metal plate 23 of the insulating circuit board 20, which was floating above the placement surface 63c, is pressed against the placement surface 63c, and the area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the placement surface 63c.

[0046] Furthermore, when the sealing member 50 is injected into the cavity 63b, it reaches the side of the insulating circuit board 20, as shown by the dashed line in Figure 7, and fills the space between the side of the insulating circuit board 20 and the cavity 63b. At this time, although the insulating circuit board 20 is curved downwards, spacer portions 24a to 24d are provided at the four corners of the metal plate 23. Also, the insulating circuit board 20 is pressed against the placement surface 63c by the sealing member 50. The sealing member 50 that has filled the space between the side of the insulating circuit board 20 and the cavity 63b cannot get between the curved corners of the insulating circuit board 20 and the placement surface 63c (see Figure 3).

[0047] If spacer portions 24a to 24d are not provided, the four corners of the insulating circuit board 20 are curved upward (+Z direction), creating a gap between the four corners of the metal plate 23 and the placement surface 63c. The sealing member 50 can enter through this gap. Furthermore, the entry of the sealing member 50 through the gap can cause the insulating circuit board 20 to be pressed upward (+Z direction), potentially causing the sealing member 50 to enter near the center of the insulating circuit board 20. If the sealing member 50 solidifies in this position, the sealing member 50 in the gap will become a burr. Since burrs have low thermal conductivity, the heat dissipation of the semiconductor device 10 with burrs on its underside will be reduced. In particular, if the sealing member 50 solidifies in a position near the center of the insulating circuit board 20, which is on the underside of the semiconductor chips 31 and 32, the semiconductor chips 31 and 32 may be damaged due to overheating during operation of the semiconductor device 10. In addition, removing the burrs would be a complicated process and would increase manufacturing costs. Therefore, burrs can reduce the reliability of the semiconductor device 10. Also, even if spacer portions 24a to 24d are provided, the sealing member 50 may, in some cases, enter from the inside of the spacer portions 24a to 24d. However, because the sealing member 50 flows onto the insulating circuit board 20 from above, the insulating circuit board 20 is pressed against the placement surface 63c, so it does not enter to the center of the metal plate 23 which is on the underside of the semiconductor chips 31 and 32, and even if burrs are generated, they are only small enough that they do not significantly reduce the reliability of the semiconductor device 10. Therefore, the sealing member 50 seals the sides of the insulating circuit board 20 and the sides (spacer sides) facing the outside of the spacer portions 24a to 24d.

[0048] After injecting the sealing member 50, the sealing mold 60 is opened while the sealing member 50 is hardened or semi-hardened, causing the pressing pins 64a and 64b to protrude. This allows the semiconductor device 10, with the insulating circuit board 20 and semiconductor chips 31 and 32 sealed inside, to be removed from the sealing mold 60. Finally, any excess resin remaining on the gate 63a and outlet is removed, and the tie bar 46 is cut off to obtain the semiconductor device 10 shown in Figures 1 to 3.

[0049] Next, the case in which a heat dissipation unit is attached to the back surface (sealing bottom surface 50f) of such a semiconductor device 10 will be explained using Figure 8. Figure 8 is a side cross-sectional view of a semiconductor device to which the heat dissipation unit of the first embodiment is attached. Note that Figure 8 shows the case in which a heat dissipation unit is attached to a semiconductor device 10 corresponding to the side cross-sectional view in Figure 2.

[0050] A heat dissipation unit 56 is provided on the back surface of the semiconductor device 10 via a thermal interface material (TIM) 55. The semiconductor device 10 and the heat dissipation unit 56 may be fastened together with bolts or the like (not shown). The heat dissipation unit 56 is made of a metal with excellent thermal conductivity. Such metals include, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. As the heat dissipation unit 56, for example, fins, a heat sink composed of multiple fins, or a water cooling device can be applied. Figure 8 illustrates the case where heat dissipation fins are attached. The surface of the heat dissipation unit 56 may be plated to improve corrosion resistance. The plating material used in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. The TIM 55 is a thermal grease or heat dissipation sheet. The thermal grease is, for example, silicone mixed with a filler. The filler is, for example, a ceramic or a metal. Furthermore, the heat dissipation sheet may be, for example, a graphite sheet, an acrylic sheet, or a silicone sheet mixed with a filler. The filler may also be, for example, a ceramic or a metal. Note that TIM55 is not limited to these and may also be a metal such as solder or brazing material.

[0051] Thus, even if the back surface of the semiconductor device 10 is warped and not flat due to the spacer portions 24a to 24d, forming the TIM 55 on the back surface of the semiconductor device 10 suppresses the gap between the back surface of the semiconductor device 10 and the front surface of the heat dissipation unit 56, allowing for bonding. Therefore, the heat dissipation unit 56 can be properly attached to the back surface of the semiconductor device 10.

[0052] The semiconductor device 10 described above has semiconductor chips 31 and 32, a rectangular metal plate 23, a rectangular insulating plate 21, and circuit patterns 22a and 22b stacked in order, with the semiconductor chips 31 and 32 arranged on the circuit patterns 22a and 22b on the front side, and an insulating circuit board 20 that curves downwards with the metal plate 23 on the back side facing downwards. Furthermore, the semiconductor device 10 has spacer portions 24a to 24d that protrude downwards from the four corners of the metal plate 23 in a plan view. Even when such an insulating circuit board 20 is housed in a cavity 63b and sealed with a sealing member 50, the penetration of the sealing member 50 into the four corners on the back side of the insulating circuit board 20 is suppressed. As a result, the generation of burrs on the four corners on the back side of the insulating circuit board 20 is suppressed. By suppressing the generation of burrs, the decrease in the heat dissipation performance of the semiconductor device 10 is suppressed, and the increase in the manufacturing cost of the semiconductor device 10 is also suppressed. Therefore, a decrease in the reliability of the semiconductor device 10 is prevented.

[0053] Furthermore, the heat dissipation unit 56 can be attached to the back surface of the semiconductor device 10 via the TIM 55. Even if the back surface of the semiconductor device 10 is not flat due to warping and spacer portions 24a to 24d, the TIM 55 ensures secure contact with the heat dissipation unit 56. This improves the heat dissipation performance of the semiconductor device 10. The following describes various forms of spacer sections 24a to 24d.

[0054] [Example 1] In Modification 1, a case in which a spacer portion is provided along the outer edge (including the four corners) of the metal plate 23 of the insulating circuit board 20 will be explained using Figures 9 and 10. Figure 9 is a rear view of the semiconductor device of Modification 1 of the first embodiment, and Figure 10 is a side cross-sectional view of the semiconductor device of Modification 1 of the first embodiment. Note that Figure 10 is a cross-sectional view taken along the dashed line YY in Figure 9. Note that the same reference numerals are used for components that are the same as those in the semiconductor device 10.

[0055] In the semiconductor device 10a, the spacer portion 24 is formed in an annular shape along the outer edge of the metal plate 23 of the insulating circuit board 20, surrounding the center of the metal plate 23. The spacer portion 24 may be formed on each side of the outer edge of the metal plate 23, or it may be formed integrally in an annular shape surrounding the center of the metal plate 23. Modification example 1 illustrates the case where the spacer portion 24 is formed on each side of the outer edge of the metal plate 23.

[0056] Furthermore, the spacer portion 24 is positioned to conform to the curvature of the insulating circuit board 20. That is, as shown in Figure 10, the spacer portion 24 is positioned such that, in a side view, it is higher from the point corresponding to the center of the metal plate 23 to the points corresponding to the four corners of the metal plate 23. In this case, the height refers to the height from the placement surface 63c to the metal plate 23 when the spacer portion 24 is placed on the placement surface 63c.

[0057] When manufacturing the semiconductor device 10a, the insulating circuit board 20 is placed on the placement surface 63c of the lower mold 62 of the sealing mold 60 via a spacer portion 24 (see Figure 5). In this case as well, the spacer portion 24 is supported on the four corners of the metal plate 23 of the insulating circuit board 20. The sealing member 50 is injected from the gate 63a to fill the cavity 63b with the sealing member 50. The insulating circuit board 20 and semiconductor chips 31 and 32 are pressed toward the placement surface 63c by the sealing member 50, and the back surface of the metal plate 23 of the insulating circuit board 20 is pressed against the placement surface 63c, so that the area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the placement surface 63c. As a result, the penetration of the sealing member 50 between the metal plate 23 and the placement surface 63c is suppressed more than when manufacturing the semiconductor device 10. The semiconductor device 10a manufactured in this way has a more reliable suppression of burr formation and a reduced decrease in reliability than the semiconductor device 10.

[0058] [Differentiation 2] In Modification 2, a case in which more spacers than those on the semiconductor device 10 are provided on the outer edge of the metal plate 23 of the insulating circuit board 20 will be explained using Figures 11 and 12. Figure 11 is a rear view of the semiconductor device of Modification 2 of the first embodiment, and Figure 12 is a side cross-sectional view of the semiconductor device of Modification 2 of the first embodiment. Note that Figure 12 is a cross-sectional view along the dashed line YY in Figure 11. Note that the same reference numerals are used for components that are the same as those in the semiconductor device 10.

[0059] In semiconductor device 10b, compared to semiconductor device 10, spacer portions 24f to 24i are formed in the center of the outer edge of the metal plate 23 of the insulating circuit board 20 between spacer portions 24a to 24d. In modified example 2, one spacer portion 24f to 24i is formed on each of the outer edges of the metal plate 23 of the insulating circuit board 20 between spacer portions 24a to 24d. There may be two or more spacers, not just one. Alternatively, a different number of spacer portions may be formed on the outer edge of the insulating circuit board 20 where greater warping occurs compared to the other outer edges.

[0060] Furthermore, the spacer portions 24a-24d and 24f-24i are of a height that conforms to the curvature of the insulating circuit board 20. That is, as shown in Figure 12, the spacer portions 24a-24d are taller than the spacer portions 24f-24i when viewed from the side. In this case, the height refers to the height from the placement surface 63c to the metal plate 23 when the spacer portions 24a-24d and 24f-24i are placed on the placement surface 63c.

[0061] When manufacturing the semiconductor device 10b, the insulating circuit board 20 is placed on the placement surface 63c of the lower mold 62 of the sealing mold 60 via spacer portions 24a to 24d and 24f to 24i. The lower mold 62 is provided with pressing holes and pressing pins according to the spacer portions 24a to 24d and 24f to 24i to be placed.

[0062] In this case as well, the sealing member 50 is injected from the gate 63a to fill the cavity 63b with the sealing member 50. The insulating circuit board 20 and semiconductor chips 31 and 32 are pressed toward the placement surface 63c by the sealing member 50, and the back surface of the metal plate 23 of the insulating circuit board 20 is pressed against the placement surface 63c, so that the area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the placement surface 63c. As a result, the penetration of the sealing member 50 between the metal plate 23 and the placement surface 63c is suppressed more than when manufacturing the semiconductor device 10. The semiconductor device 10b manufactured in this way reliably suppresses the generation of burrs and suppresses the decrease in reliability compared to the semiconductor device 10.

[0063] [Difference 3] In Modification 3, a case in which a spacer portion is integrally formed on the outer edge of the metal plate 23 of the insulating circuit board 20 will be explained using Figure 13. Figure 13 is a side cross-sectional view of the semiconductor device of Modification 3 of the first embodiment. Note that Figure 13 corresponds to the position of the cross-section in Figure 2. Note that the same reference numerals are used for the same components as in the semiconductor device 10.

[0064] Spacer portions 24a to 24d are formed at the four corners of the metal plate 23 of the insulating circuit board 20 of the semiconductor device 10c, and are integrated with the metal plate 23. The spacer portions 24a to 24d are obtained by half-etching the main surface of the metal plate 23 so that protrusions remain at the four corners of the metal plate 23. In addition to the spacer portions 24a to 24d, the metal plate 23 of the insulating circuit board 20 may also have annular spacer portions as in Modification 1, or multiple spacer portions formed between the four corners of the metal plate 23 as in Modification 2.

[0065] When manufacturing such a semiconductor device 10c, the same effect as that of the semiconductor device 10 can be obtained by the spacer portions 24a to 24d.

[0066] [Modification 4-1] Modification 4-1 describes a case where a spacer portion composed of multiple micro-protrusions is provided along the outer edge of the metal plate 23 of the insulating circuit board 20, using Figures 14 and 15. Figure 14 is a side cross-sectional view of the semiconductor device of Modification 4-1 of the first embodiment, and Figure 15 is a rear view of the semiconductor device of Modification 4-1 of the first embodiment. Note that Figure 14 corresponds to the position of the cross-section in Figure 2. Note that the same reference numerals are used for components that are the same as those in the semiconductor device 10.

[0067] In the semiconductor device 10d, the spacer portion 24 is formed along the outer edge of the metal plate 23 of the insulating circuit board 20, surrounding the center of the metal plate 23. This spacer portion 24 is composed of a plurality of micro-protrusions formed along the outer edge of the metal plate 23 of the insulating circuit board 20. Each micro-protrusion has a flattened, rounded tip. As shown in Figure 15, multiple such micro-protrusions are formed along the outer edge of the metal plate 23 of the insulating circuit board 20, surrounding the center of the metal plate 23.

[0068] In the semiconductor device 10d, the sealing member 50 seals the entire circumference of the side of the insulating circuit board 20, as well as the side of the fine protrusion facing the outside of the spacer portion 24 (spacer side). In the semiconductor device 10d as well, the sealing bottom surface 50f is on the same plane as the tip of the spacer portion 24 and the center of the back surface of the insulating circuit board 20.

[0069] Next, a method for manufacturing such a semiconductor device 10d will be described using Figures 16 to 18. Figures 16 to 18 are cross-sectional views showing the manufacturing process of a semiconductor device of modified example 4-1 of the first embodiment.

[0070] First, multiple thorn-like micro-protrusions are formed along the outer edge of the metal plate 23 of the insulating circuit board 20 by metal processing (see Figure 14 for the formation locations). That is, each micro-protrusion has a pointed tip that protrudes high. In this case, metal processing such as texturing, laser processing, or sandblasting may be performed. Furthermore, the multiple spire-shaped micro-protrusions are formed so that their tips face towards the center, taking into account the warping of the insulating circuit board 20.

[0071] As shown in Figure 4, lead frames 40, 41a~41j, 43, 44 and lead frame 42, which are connected to semiconductor chips 31, 32 and tie bars 46, are bonded to such an insulated circuit board 20.

[0072] Next, the insulating circuit board 20, with the lead frames 40, 41a~41j, 42~44 etc. joined in this manner, is set in the sealing mold 60 as shown in Figure 16. The entire back surface of the insulating circuit board 20 (metal plate 23) housed in the cavity 63b is raised from the placement surface 63c by multiple spacer portions 24. Note that the lower mold 62 of the sealing mold 60 in Modified Example 4-1 does not have pressing holes or pressing pins.

[0073] In this manner, the molten sealing member 50 is injected into the sealing mold 60 in which the insulating circuit board 20 is set, through the gate 63a. The insulating circuit board 20 warps downwards due to heating.

[0074] The sealing member 50 injected from gate 63a fills the cavity 63b along the dashed arrow shown in Figure 17 (see Figure 6 for a plan view). As described in Figures 5 and 6 of the first embodiment, the insulating circuit board 20 and semiconductor chips 31 and 32 are pressed toward the placement surface 63c by the sealing member 50. As a result, the multiple spire-shaped micro-protrusions of the spacer portion 24 are crushed, as shown in Figure 18. The back surface of the metal plate 23 of the insulating circuit board 20, which was floating above the placement surface 63c, is pressed against the placement surface 63c, and the area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the placement surface 63c. In addition, the multiple crushed micro-protrusions become densely packed with each other, filling the gaps between the micro-protrusions.

[0075] Furthermore, when the sealing member 50 is injected into the cavity 63b, as explained in Figure 7 of the first embodiment, it reaches the side of the insulating circuit board 20 and fills the space between the side of the insulating circuit board 20 and the cavity 63b. At this time, although the insulating circuit board 20 is curved downwards, a spacer portion 24 is provided on the outer edge of the metal plate 23. Also, the insulating circuit board 20 is pressed against the placement surface 63c by the sealing member 50. The multiple spire-shaped micro-protrusions of the spacer portion 24 are further crushed, as shown in Figure 18. The sealing member 50 that has filled the space between the side of the insulating circuit board 20 and the cavity 63b cannot get between the four corners of the curved insulating circuit board 20 and the placement surface 63c. Therefore, the sealing member 50 seals the side of the insulating circuit board 20 and the side of the micro-protrusions facing the outside of the spacer portion 24. In this way, the insulating circuit board 20 and semiconductor chips 31, 32, etc. are sealed, and by cutting off the excess frame parts such as the tie bar 46, the semiconductor device 10d shown in Figures 14 and 15 is obtained.

[0076] Note that Modification 4-1 merely shows a case where multiple micro-protrusions are formed along the outer edge of the metal plate 23 of the insulating circuit board 20 as the spacer portion 24. However, the spacer portion 24 may also be formed by forming multiple micro-protrusions in the four corner regions of the metal plate 23 of the insulating circuit board 20, as shown in Figure 3. Alternatively, as explained in Modification 2, multiple micro-protrusions may be formed in the four corner regions and multiple regions between the four corners of the metal plate 23 of the insulating circuit board 20 as the spacer portion 24.

[0077] [Modification 4-2] Modification 4-2 describes a case in which multiple protrusions, having a different shape from the multiple micro-protrusions in Modification 4-1, are formed on the outer edge of the metal plate 23 of the insulating circuit board 20 by metal processing, using Figures 19 and 20. Figures 19 and 20 are rear views of the semiconductor device of Modification 4-2 of the first embodiment. The same reference numerals are used for components that are the same as those in the semiconductor device 10.

[0078] In the semiconductor device 10d shown in Figure 19, the spacer portion 24 is an annular protrusion formed along the outer edge of the back surface of the metal plate 23, surrounding the center of the metal plate 23. The tip of each protrusion is flattened and rounded. In Figure 19, as an example, it shows a case where three rows of protrusions are formed. It is not limited to three rows; two or more rows are acceptable. Also, similar to the first modification, the spacer portion 24 is of a height that follows the curvature of the insulating circuit board 20. That is, in a side view, the spacer portion 24 is higher from the point corresponding to the center of the metal plate 23 to the points corresponding to the four corners of the metal plate 23. Furthermore, in the semiconductor device 10d of Figure 19, the cross-sections of the multiple annular protrusions formed on the outer edge of the metal plate 23 of the insulating circuit board 20 before sealing have a spire-like shape at their tips.

[0079] Furthermore, in the semiconductor device 10d shown in Figure 20, unlike in Figure 19, the spacer portion 24 has annular, dashed-line-shaped protrusions formed along the outer edge of the back surface of the metal plate 23, surrounding the center of the metal plate 23. In Figure 20, as an example, it shows a case where three such protrusions are formed. Also, in Figure 20, the continuous portion of the inner protrusions corresponds to the defective portion of the outermost protrusion, and the continuous portion of the innermost protrusion is formed at the corner of the metal plate 23. That is, in Figure 20, the spacer portion 24 has multiple protrusions formed in a staggered pattern. Also, in the semiconductor device 10d in Figure 20, the cross-sections of the multiple annular protrusions formed on the outer edge of the metal plate 23 of the insulating circuit board 20 before sealing have a spire-like shape at their tips.

[0080] When manufacturing the semiconductor device 10d shown in Figures 19 and 20, similar to Modification 4-1, when the insulating circuit board 20, to which the lead frames 40, 41a~41j, 42~44 etc. are joined, is set in the sealing mold 60, the entire back surface of the insulating circuit board 20 (metal plate 23) is lifted from the placement surface 63c by the spacer portion 24 (see Figure 16). Note that the lower mold 62 of the sealing mold 60 in Modification 4-2 does not have pressing holes or pressing pins. Furthermore, when the sealing member 50 is injected from the gate 63a, the insulating circuit board 20 and semiconductor chips 31, 32 are pressed toward the placement surface 63c by the sealing member 50. As a result, the multiple spire-shaped protrusions of the spacer portion 24 are crushed (see Figure 18). The back surface of the metal plate 23 of the insulating circuit board 20, which was floating above the placement surface 63c, is pressed against the placement surface 63c, and the area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the placement surface 63c. In addition, the multiple crushed protrusions become densely packed with each other, filling the gaps between the protrusions.

[0081] Furthermore, when the sealing member 50 is injected into the cavity 63b, as described in Figure 7 of the first embodiment, the sealing member 50 seals the side of the insulating circuit board 20 and the side of the protrusion facing the outside of the spacer portion 24. In this way, the insulating circuit board 20 and semiconductor chips 31, 32, etc. are sealed, and the semiconductor device 10d is obtained by cutting off excess frame parts such as the tie bar 46.

[0082] [Difference 5] In Modification 5, a case is described using Figure 21 in which a spacer portion composed of a group of aggregated particles is provided along the outer edge of the metal plate 23 of the insulating circuit board 20. Figure 21 is a side cross-sectional view of the semiconductor device of Modification 5 of the first embodiment. Note that Figure 21 corresponds to the position of the cross-section in Figure 2. Note that the same reference numerals are used for components that are the same as those in the semiconductor device 10.

[0083] In the semiconductor device 10e, the spacer portion 24 is formed along the outer edge of the metal plate 23 of the insulating circuit board 20, surrounding the central part of the metal plate 23. This spacer portion 24 is a group of particles that have aggregated along the outer edge of the metal plate 23 of the insulating circuit board 20.

[0084] In the semiconductor device 10e, the sealing member 50 seals the entire circumference of the side of the insulating circuit board 20, as well as the side of the particle group facing the outside of the spacer portion 24 (spacer side). In the semiconductor device 10e as well, the sealing bottom surface 50f is on the same plane as the tip of the spacer portion 24 and the center of the back surface of the insulating circuit board 20.

[0085] Furthermore, Modification 5 merely shows a case where the spacer portion 24 is formed along the outer edge of the metal plate 23 of the insulating circuit board 20. However, the spacer portion 24 may also be formed by forming particle groups in the four corner regions of the metal plate 23 of the insulating circuit board 20, as shown in Figure 3. Alternatively, as explained in Modification 2, the spacer portion 24 may be formed by forming particle groups in the four corner regions and multiple regions between the four corners of the metal plate 23 of the insulating circuit board 20.

[0086] The spacer portion 24 on the outer edge of the back surface of such a metal plate 23 is formed by spraying multiple particles. These particles are made of metal and elastic material. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. The elastic material is, for example, silicone rubber.

[0087] When manufacturing the semiconductor device 10e shown in Figure 21, a spacer portion 24 is formed in advance by spraying multiple particles in an annular pattern along the outer edge of the back surface of the metal plate 23 of the insulating circuit board 20. When the insulating circuit board 20, to which the lead frames 40, 41a~41j, 42~44, etc. are joined, with the spacer portion 24 formed in this way, is set in the sealing mold 60, the entire back surface of the insulating circuit board 20 (metal plate 23) is lifted from the placement surface 63c by the spacer portion 24 (see Figure 16). Note that the lower mold 62 of the sealing mold 60 in Modification 5 does not have pressing holes or pressing pins. Also, heating causes the insulating circuit board 20 to warp downwards. Furthermore, when the sealing member 50 is injected from the gate 63a, the insulating circuit board 20 and semiconductor chips 31, 32 are pressed toward the placement surface 63c by the sealing member 50. As a result, the back surface of the metal plate 23 of the insulating circuit board 20, which was floating above the placement surface 63c, is pressed against the placement surface 63c, and the area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the placement surface 63c.

[0088] Furthermore, when the sealing member 50 is injected into the cavity 63b, as described in Figure 7 of the first embodiment, the sealing member 50 seals the side of the insulating circuit board 20 and the side of the particles facing the outside of the spacer portion 24. In this way, the insulating circuit board 20 and semiconductor chips 31, 32, etc. are sealed, and the semiconductor device 10e is obtained by cutting off excess frame parts such as the tie bar 46.

[0089] [Second Embodiment] The semiconductor device of the second embodiment will be described with reference to Figure 22. Figure 22 is a side cross-sectional view of the semiconductor device of the second embodiment. Note that Figure 22 is a side cross-sectional view corresponding to Figure 2. In addition, the semiconductor device of the second embodiment uses the same reference numerals as the semiconductor device 10 of the first embodiment for the same components.

[0090] In the semiconductor device 10f, the spacer portions 24a to 24d protrude downward (in the -Z direction) from the center of the sealing bottom surface 50f and the metal plate 23. The spacer portions 24a to 24d are made of the same material as the spacer portions 24a to 24d of the semiconductor device 10. However, the spacer portions 24a to 24d are longer than the spacer portions 24a to 24d of the semiconductor device 10. The other components of the semiconductor device 10f are also the same as those of the semiconductor device 10.

[0091] Next, the manufacturing method of the semiconductor device 10f will be explained using Figure 23. Figure 23 is a side cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment. Similar to the first embodiment, the lead frame 42 is joined to the semiconductor chips 31 and 32 bonded to the insulating circuit board 20, and the lead frames 40, 43, and 44 connected to the tie bar 46 are joined to the insulating circuit board 20 as shown in Figure 4. Then, the lead frames 41a to 41j connected to the tie bar 46 and the semiconductor chips 31 and 32 are mechanically and electrically connected by bonding wires 45.

[0092] Next, the insulating circuit board 20, with the lead frames 40, 41a~41j, 42~44 etc. joined in this manner, is set in the sealing mold 60 via the spacer portions 24a~24d. The sealing mold 60 has the same configuration as in the first embodiment. However, a recess 63d is formed in the lower mold 62 at the location corresponding to the spacer portions 24a~24d on the placement surface 63c. That is, pressing holes 62a and 62b are formed at the bottom of the recess 63d. The opening area of ​​this recess 63d corresponds to the area of ​​the spacer portions 24a~24d in a plan view. The depth of the recess 63d is the depth to which the spacer portions 24a~24d are inserted when the center of the metal plate 23 of the insulating circuit board 20 contacts the placement surface 63c. Pressing pins 64a and 64b are placed in the pressing holes 62a and 62b. The tips of the pressure pins 64a and 64b are positioned so that they are at the same level as or below the bottom of the recess 63d (in the -Z direction).

[0093] When the insulated circuit board 20, to which lead frames 40, 41a~41j, 42~44, etc. are joined, is placed on the placement surface 63c of the lower mold 62, spacer portions 24a~24d are provided at the four corners of the metal plate 23. That is, as shown in Figure 23, the spacer portions 24a~24d are fitted into the recesses 63d of the placement surface 63c. In this case, the spacer portions 24a~24d cause the metal plate 23 of the insulated circuit board 20 to be slightly raised from the placement surface 63c, except for the four corners. In this case, the gap between the center of the metal plate 23 and the placement surface 63c is, for example, 10 μm or more and 200 μm or less.

[0094] From this state, the sealing member 50 is injected from the gate 63a into the cavity 63b, similar to the first embodiment. The injected sealing member 50 presses the insulating circuit board 20 toward the placement surface 63c, sealing the sides of the insulating circuit board 20. The sealing member 50 further seals the sides (spacer sides) facing the outside of the spacer portions 24a to 24d protruding from the recess 63d. After sealing, the insulating circuit board 20 and the like, sealed with the sealing member 50, can be removed from the lower mold 62 by moving the pressing pins 64a and 64b upward. In this way, the insulating circuit board 20 and semiconductor chips 31, 32, etc. are sealed, and by cutting off the tie bars 46 and other excess frame parts, the semiconductor device 10f shown in Figure 22 is obtained.

[0095] Next, the case in which a heat dissipation unit 56 is attached to the back surface (sealing bottom surface 50f) of such a semiconductor device 10f will be explained using Figure 24. Figure 24 is a side cross-sectional view of a semiconductor device to which the heat dissipation unit of the second embodiment is attached. Note that Figure 24 shows the case in which a heat dissipation unit is attached to a semiconductor device 10f corresponding to the side cross-sectional view in Figure 22.

[0096] A heat dissipation unit 56 is provided on the back surface of the semiconductor device 10f via a TIM 55. The heat dissipation unit 56 is configured in the same way as the heat dissipation unit 56 of the first embodiment. However, the heat dissipation unit 56 has an alignment portion 56a formed at a position corresponding to the spacer portions 24a to 24d of the semiconductor device 10f. The alignment portion 56a is formed in a concave shape with a size that allows the spacer portions 24a to 24d to be fitted into it.

[0097] TIM 55 is applied to the back surface of the semiconductor device 10f. Alternatively, it may be applied to the placement area of ​​the semiconductor device 10f on the heat dissipation unit 56, avoiding the alignment portion 56a. In this case, the spacer portions 24a to 24d protrude from the TIM 55. When attaching the semiconductor device 10f to the heat dissipation unit 56, the spacer portions 24a to 24d are fitted into the alignment portion 56a. This ensures that the semiconductor device 10f is securely positioned on the heat dissipation unit 56. Furthermore, the semiconductor device 10f positioned in this manner is prevented from shifting position from the heat dissipation unit 56. Therefore, the heat dissipation unit 56 can be properly and securely attached to the back surface of the semiconductor device 10f.

[0098] [Differentiation] The modified example describes a case where a different sealing mold is used than that of the second embodiment. First, the modified semiconductor device will be described using Figure 25. Figure 25 is a side cross-sectional view of the modified semiconductor device of the second embodiment. Note that Figure 25 is a side cross-sectional view corresponding to Figure 2. In addition, the modified semiconductor device uses the same reference numerals as the semiconductor device 10 of the first embodiment for the same components.

[0099] In semiconductor device 10g, the sealing bottom surface 50f is located above the bottom surfaces of the spacer portions 24a to 24d and the center of the metal plate 23 that curves downward. The other components of semiconductor device 10g are the same as those of semiconductor device 10.

[0100] Next, the manufacturing method of the semiconductor device 10g will be explained with reference to Figure 26. Figure 26 is a side cross-sectional view showing the manufacturing process of a modified semiconductor device according to the second embodiment. Similar to the first embodiment, the lead frame 42 is joined to the semiconductor chips 31 and 32 bonded to the insulating circuit board 20, and the lead frames 40, 43, and 44 connected to the tie bar 46 are joined to the insulating circuit board 20 as shown in Figure 4. Then, the lead frames 41a to 41j connected to the tie bar 46 and the semiconductor chips 31 and 32 are electrically and mechanically connected by bonding wires 45.

[0101] Next, the insulating circuit board 20, with the lead frames 40, 41a~41j, 42~44 etc. joined in this manner, is set in the sealing mold 60 via spacer portions 24a~24d. The sealing mold 60 has the same configuration as in the first embodiment. However, a recess 63e is formed in the area on the placement surface 63c of the lower mold 62 where the insulating circuit board 20 is placed. The recess 63e is cube-shaped. In a plan view of the recess 63e, pressing holes (in Figure 26, pressing holes 62a and 62b through which pressing pins 64a and 64b are inserted are shown) are formed at the four corners.

[0102] When the insulated circuit board 20, to which lead frames 40, 41a~41j, 42~44, etc. are joined, is placed on the placement surface 63c of the lower mold 62, spacer portions 24a~24d are provided at the four corners of the metal plate 23. That is, as shown in Figure 26, the spacer portions 24a~24d are located at the four corners of the recess 63e of the placement surface 63c. In this case, the spacer portions 24a~24d cause the metal plate 23 of the insulated circuit board 20 to be slightly raised from the bottom surface of the recess 63e, except for the four corners. In this case, the gap between the center of the metal plate 23 and the placement surface 63c is, for example, 10 μm or more and 200 μm or less.

[0103] From this state, the sealing member 50 is injected from the gate 63a into the cavity 63b, similar to the first embodiment. The injected sealing member 50 presses the insulating circuit board 20 toward the placement surface 63c, sealing the sides of the insulating circuit board 20. The sealing member 50 further seals the sides (spacer sides) facing the outside of the spacer portions 24a to 24d protruding from the recess 63e. In this way, the insulating circuit board 20 and semiconductor chips 31, 32, etc. are sealed, and by cutting off excess frame parts such as tie bars 46, the semiconductor device 10g shown in Figure 25 is obtained.

[0104] Even with such a semiconductor device 10g, the spacer portions 24a to 24d are fitted into the alignment portion 56a via the TIM 55, similar to Figure 24. This ensures that the semiconductor device 10g is securely positioned on the heat dissipation unit 56. Furthermore, the semiconductor device 10g positioned in this manner is prevented from shifting position from the heat dissipation unit 56. Therefore, the heat dissipation unit 56 can be properly and securely attached to the back surface of the semiconductor device 10g.

[0105] In the second embodiment, the spacer portions 24a to 24d are not limited to those attached to the four corners of the metal plate 23. The spacer portions in the modified examples 1 to 5 of the first embodiment can also be applied. In this case, the recesses formed in the lower mold 62 of the sealing mold 60 can be made different depending on the shape of the spacer portion. [Explanation of symbols]

[0106] 10,10a~10g Semiconductor equipment 20 Insulated circuit board 21 Insulating board 22a, 22b Circuit Patterns 23 Metal plate 24, 24a~24i Spacer section 31,32 Semiconductor chips 33a, 33b solder 40, 41a~41j, 42~44 Lead Frames 45 Bonding wires 46 Tie Bar 50 Sealing member 50a Sealing top surface 50b~50e Sealing side 50f sealed bottom 55 Thermal Interface Materials (TIM) 56 Heat dissipation unit 56a Alignment section 60 Sealing mold 60a Top surface of the mold 60b~60e Mold side 60f mold bottom 61 Upper mold 62 Lower mold 62a, 62b Pressing holes 63a Gate 63b Cavity 63c Placement plane 63d, 63e recess 64a, 64b Pressing pins

Claims

1. Semiconductor chips and A rectangular metal plate, a rectangular insulating plate, and a circuit pattern are stacked in order, the semiconductor chip is placed on the circuit pattern on the front surface, and the insulating circuit board on the back surface is curved downwards with the metal plate facing downwards, Spacer portions are provided at each of the four corners of the metal plate in a plan view, protruding downwards, and in a side view, are convex downwards and are on the same plane as the center of the back surface of the metal plate included in the insulating circuit board, or protruding downwards from the center; A sealing member that seals the front surface of the insulating circuit board and the side of the insulating circuit board and the spacer side facing the outside of the spacer portion, It has, The spacer portion is separate from the metal plate and the sealing member. Semiconductor equipment.

2. The sealing bottom surface of the sealing member is in the same plane as the central part. The semiconductor device according to claim 1.

3. The bottom surface of the spacer portion protrudes below the bottom surface of the sealing member. The semiconductor device according to claim 2.

4. The spacer portion is formed along the outer edge of the metal plate, including the four corners, surrounding the central part. The semiconductor device according to any one of claims 1 to 3.

5. The spacer portion is formed not only at the four corners of the metal plate, but also at one or more of the outer edges between the four corners. The semiconductor device according to any one of claims 1 to 3.

6. The height of the spacer portion is configured to become thicker as it approaches the four corners. The semiconductor device according to claim 4 or 5.

7. The spacer portion is formed by a plurality of micro-protrusions, The semiconductor device according to any one of claims 1 to 6.

8. The spacer portion is formed in a thin, annular shape in plan view, and is formed in multiple locations on the outer edge of the metal plate, surrounding the central part of the metal plate. The semiconductor device according to any one of claims 1 to 6.

9. Each of the aforementioned spacer portions is further formed in a dashed line shape and is formed in a staggered pattern around the central part of the metal plate, with multiple spacers formed on the outer edge of the metal plate. The semiconductor device according to any one of claims 1 to 6.

10. The spacer portion is formed by a group of particles that have aggregated from multiple particles sprayed onto the metal plate. The semiconductor device according to any one of claims 1 to 9.

11. The insulating circuit board further comprises a heat dissipation unit installed via a thermal interface material on the back surface of the metal plate, including the spacer portion. The semiconductor device according to any one of claims 1 to 10.

12. The heat dissipation unit further comprises a heat dissipation unit having an alignment portion formed with an opening corresponding to the spacer portion, and the spacer portion being fitted into the alignment portion and installed on the back surface of the metal plate of the insulating circuit board, including the spacer portion, via a thermal interface material. The semiconductor device according to any one of claims 1 to 10.

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