Manufacturing method for semiconductor devices
By forming rounded trench openings using anisotropic etching with a higher mask selectivity, the method addresses electric field concentration and connection failures in semiconductor devices, enhancing electrode connectivity and reducing on-resistance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2025-07-30
- Publication Date
- 2026-05-26
AI Technical Summary
Existing semiconductor devices face issues with electric field concentration at the trench openings and potential connection failures due to isotropic etching processes that widen the trench openings and reduce connectivity between electrodes.
The method involves forming a rounded portion at the trench openings using anisotropic etching with a higher selectivity ratio for the mask than the semiconductor substrate, thereby minimizing the etching of the substrate and maintaining electrode connectivity.
This approach suppresses electric field concentration and reduces the risk of connection failures by preserving the integrity of the semiconductor substrate between trenches, allowing for shorter trench lengths and lower on-resistance.
Smart Images
Figure 0007865433000001 
Figure 0007865433000002 
Figure 0007865433000003
Abstract
Description
[Technical Field]
[0001] The present invention relates to a method for manufacturing a semiconductor device having a trench gate structure. [Background technology]
[0002] Conventionally, semiconductor devices on which semiconductor elements such as MOSFETs (metal oxide semiconductor field effect transistors) are formed have been proposed. Specifically, these semiconductor devices include a semiconductor substrate having a drift layer, with a base layer formed on one side of the semiconductor substrate and a source region formed on the surface of the base layer. Furthermore, multiple trenches are formed in the semiconductor substrate, penetrating the source region and the base layer and extending along one direction in the plane direction of the semiconductor substrate. A trench gate structure is then formed by arranging a gate insulating film and a gate electrode in these trenches.
[0003] A drain region is located on the other side of the semiconductor substrate. A first electrode is located on one side of the semiconductor substrate so as to be electrically connected to the source region and the base layer. A second electrode is located on the other side of the semiconductor substrate so as to be electrically connected to the drain region.
[0004] In semiconductor devices like the one described above, electric field concentration is likely to occur at the opening end of the trench. For this reason, for example, Patent Document 1 proposes forming a rounded portion at the opening end of the trench.
[0005] Specifically, in this method, a mask is formed on one surface of the semiconductor substrate, and the mask is patterned to create openings so that the areas of the semiconductor substrate where the trenches will be formed are exposed. Next, anisotropic etching is performed using the mask to form trenches in the semiconductor substrate. Then, the openings of the mask are widened to expose the ends of the trench openings from the mask. After that, isotropic etching is performed to form rounded portions at the ends of the trench openings. Note that the isotropic etching when forming the rounded portions is performed under conditions where the selectivity ratio of the semiconductor substrate is higher than that of the mask. [Prior art documents] [Patent Documents]
[0006] [Patent Document 1] Japanese Patent Publication No. 2012-4360 [Overview of the project] [Problems that the invention aims to solve]
[0007] Incidentally, in semiconductor devices like the one described above, reducing on-resistance by shortening the length between adjacent trenches has been considered. However, when rounded edges are formed at the opening ends of the trenches as described above, the isotropic etching process, which has a high selectivity for the semiconductor substrate, tends to remove the portion of the semiconductor substrate that is exposed from the mask. Furthermore, when rounded edges are formed at the opening ends of the trenches as described above, the isotropic etching process, which has a high selectivity for the semiconductor substrate, may also remove the portion of the semiconductor substrate located near the opening of the mask. In other words, the opening ends of the trenches may be widened overall. As a result, the portion of the semiconductor substrate located between adjacent trenches becomes smaller, which may reduce connectivity between the first electrode and the source region, potentially leading to connection failures.
[0008] In view of the above, the present invention aims to provide a method for manufacturing a semiconductor device that can suppress the occurrence of electric field concentration at the open end of the trench while also suppressing the occurrence of connection failures of the first electrode. [Means for solving the problem]
[0009] Claim 1, for achieving the above objective, provides a method for manufacturing a semiconductor device having a plurality of trench gate structures, comprising: preparing a semiconductor substrate (10) having one surface (10a); forming a trench (16) from the one surface side with one direction in the plane direction of the semiconductor substrate as the longitudinal direction; and arranging a gate insulating film (17) and a gate electrode (18) in the trench to form a plurality of trench gate structures. The method for forming the trench involves: placing a mask (30) on one surface of the semiconductor substrate; patterning the mask to form an opening (31) so that the region of the semiconductor substrate where the trench is to be formed is exposed; performing etching using the mask to form the trench; and performing etching with the mask in place to form a rounded portion (160) at the opening end (16a) of the trench. The method for forming the rounded portion at the opening end of the trench involves etching under conditions where the selectivity ratio of the mask is higher than that of the semiconductor substrate, and the method for forming the trench involves anisotropic etching under conditions where the selectivity ratio of the semiconductor substrate is higher than that of the mask.
[0010] According to this method, etching is performed under conditions where the selectivity ratio of the mask is higher than that of the semiconductor substrate to form the rounded portion. Therefore, when forming the rounded portion, one side of the semiconductor substrate is less likely to be etched, and the reduction of one side of the semiconductor substrate located between the trenches can be suppressed. Consequently, poor connection between the first electrode and one side of the semiconductor substrate can be suppressed. In addition, since the rounded portion is formed at the opening end of the trench, electric field concentration at the opening end of the trench can be suppressed.
[0011] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]
[0012] [Figure 1] It is a perspective cross-sectional view of the SiC semiconductor device in the first embodiment. [Figure 2A] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device shown in FIG. 1. [Figure 2B] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 2A. [Figure 2C] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 2B. [Figure 2D] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 2C. [Figure 2E] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 2D. [Figure 2F] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 2E. [Figure 3] It is a plan view showing a wafer-shaped semiconductor substrate. [Figure 4] It is a view showing the depth of the trench. [[ID=二十九]]
Embodiments for Carrying Out the Invention
[0013] Hereinafter, embodiments of the present invention will be described based on the drawings. In each of the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.
[0014] (First Embodiment) The first embodiment will be described with reference to the drawings. Note that the semiconductor device of this embodiment is preferably applied, for example, as a device mounted on a vehicle such as an automobile and used to drive various electronic devices for vehicles. Further, in this embodiment, a silicon carbide (hereinafter also referred to as SiC) semiconductor device in which an inversion-type MOSFET having a trench gate structure is formed will be described. Note that in this embodiment, the configuration of the cell region in which the MOSFET is formed will be described, but an actual SiC semiconductor device is provided with an outer peripheral region in which a structure such as an FLR (abbreviation for Field Limiting Ring) structure is formed so as to surround the cell region.
[0015] Hereinafter, in the plane direction of the substrate 11 to be described later, one direction will be defined as the X-axis direction, the direction intersecting one direction in the plane direction of the substrate will be defined as the Y-axis direction, and the direction orthogonal to the X-axis direction and the Y-axis direction will be defined as the Z-axis direction for explanation. In this embodiment, the X-axis direction and the Y-axis direction are orthogonal to each other.
[0016] As shown in FIG. 1, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device includes an n + , + , - -type substrate 11 made of SiC. In this embodiment, as the substrate 11, for example, it has an off-angle of 0 to 8° with respect to the (0001) Si plane, and the n-type impurity concentration such as nitrogen or phosphorus is 1.0×10 19 / cm 3 and the thickness is about 300 μm. Note that the substrate 11 constitutes the drain region in this embodiment and corresponds to the high-concentration layer.
[0017] On the surface of the substrate 11, an n - -type drift layer 12 and a p-type base layer 13 made of SiC are sequentially epitaxially grown. And in the surface layer portion of the base layer 13, an n + -type source region 14 and a p + -type contact region 15 are formed. In this embodiment, the source region 14 and the contact region 15 are alternately formed along the longitudinal direction of the trench 16 to be described later (that is, the Y-axis direction). Note that in this embodiment, the source region 14 corresponds to the impurity region.
[0018] The drift layer 12, for example, has an n-type impurity concentration of 0.5 to 2.0×10 16 / cm 3 and the thickness is 5 to 14 μm. The base layer 13 is the portion where the channel region is formed. For example, the p-type impurity concentration is about 3.0×10 17 / cm 3 and the thickness is 0.5 to 2 μm. The source region 14 has a higher impurity concentration than the drift layer 12. For example, the n-type impurity concentration in the surface layer portion is 2.5×10 18~1.0×10 19 / cm 3 The thickness is set to 0.5 to 2 μm. The contact region 15 has a higher impurity concentration than the base layer 13, with a p-type impurity concentration of 1.0 × 10⁻⁶. 18 ~1.0×10 20 / cm 3 It is stated that the impurity concentration and film thickness of the drift layer 12, base layer 13, source region 14, and contact region 15 are arbitrary and not limited to those stated above.
[0019] In this embodiment, the semiconductor substrate 10 is composed of the substrate 11, drift layer 12, base layer 13, source region 14, contact region 15, etc., as described above. In this embodiment, one side 10a of the semiconductor substrate 10 is composed of the source region 14 and contact region 15, and the other side 10b of the semiconductor substrate 10 is composed of the substrate 11.
[0020] Multiple trenches 16 are formed in the semiconductor substrate 10, penetrating the source region 14, the contact region 15, and the base layer 13 to reach the drift layer 12. Specifically, the multiple trenches 16 extend along the Y-axis and are arranged at equal intervals along the X-axis to form a stripe pattern. In addition, each trench 16 has a rounded portion 160 formed at its open end 16a.
[0021] Furthermore, a gate insulating film 17 is formed on the inner wall surface of the trench 16, and a gate electrode 18 made of doped poly-Si or the like is formed on the gate insulating film 17. This constitutes a trench gate structure. The gate insulating film 17 is formed by thermal oxidation of the inner wall surface of the trench 16 or by performing CVD (chemical vapor deposition). The thickness of the gate insulating film 17 is approximately 100 nm on both the side and bottom surfaces of the trench 16.
[0022] In this embodiment of the SiC semiconductor device, the gate insulating film 17 and gate electrode 18 are not located on the open end 16a side of the trench 16. Specifically, on the side surface of the trench 16, the gate insulating film 17 and gate electrode 18 are not located from the side of one surface 10a of the semiconductor substrate 10 to an intermediate position in the source region 14 and contact region 15 along the Z-axis direction. In other words, the portion of the open end 16a on the side surface of the trench 16 is exposed from the gate insulating film 17 and gate electrode 18. The gate insulating film 17 and gate electrode 18 are formed on the open end 16a of the trench 16, for example, at the end of the trench 16 in the longitudinal direction, and are drawn out onto one surface 10a of the semiconductor substrate 10. The gate electrode 18 drawn out onto one surface 10a of the semiconductor substrate 10 is electrically connected to gate wiring, etc. (not shown).
[0023] An interlayer insulating film 19 is formed on the open end 16a side of the trench 16 so as to cover the gate electrode 18, gate insulating film 17, etc. However, in this embodiment, the interlayer insulating film 19 is arranged only within the trench 16 and is not formed on one surface 10a of the semiconductor substrate 10. In this embodiment, by arranging the interlayer insulating film 19 in this way, it is possible to make it easier to narrow the spacing between adjacent trenches 16 compared to the following SiC semiconductor device. That is, in the SiC semiconductor device of this embodiment, it is possible to make it easier to narrow the spacing between adjacent trenches 16 compared to the case in which the interlayer insulating film 19 is arranged on one surface 10a of the semiconductor substrate 10 and contact holes are formed to expose the source region 14 and contact region 15. The interlayer insulating film 19 is made of BPSG (abbreviation for Borophosphosilicate Glass), etc.
[0024] An upper electrode 20 is formed on one surface 10a of the semiconductor substrate 10, which is electrically connected to the source region 14 and the contact region 15. In this embodiment, the upper electrode 20 corresponds to the first electrode.
[0025] The upper electrode 20 of this embodiment is composed of multiple metals, such as Ni / Al. The portion of the multiple metals that contacts the n-type SiC (i.e., the source region 14) is composed of a metal capable of ohmic contact with the n-type SiC. Furthermore, at least the portion of the multiple metals that contacts the p-type SiC (i.e., the contact region 15) is composed of a metal capable of ohmic contact with the p-type SiC.
[0026] A lower electrode 21 is formed on the other side 10b of the semiconductor substrate 10, which is electrically connected to the substrate 11. In this embodiment, the lower electrode 21 corresponds to the second electrode.
[0027] In this embodiment, the SiC semiconductor device has a trench gate structure which is an inverted type n-channel MOSFET. + The type corresponds to the first conductivity type, p type, p + This type corresponds to the second conductivity type.
[0028] In such a SiC semiconductor device, when the gate voltage applied to the gate electrode 18 is equal to or greater than the threshold voltage of the insulated gate structure, current flows between the upper electrode 20 and the lower electrode 21, resulting in an ON state. Conversely, when the gate voltage applied to the gate electrode 18 is less than the threshold voltage, the SiC semiconductor device enters an OFF state where no current flows between the upper electrode 20 and the lower electrode 21.
[0029] Next, the manufacturing method of the SiC semiconductor device described above will be explained with reference to Figures 2A to 2F. Figures 2A to 2F are cross-sectional views in which the Y-axis direction in Figure 1 is the normal direction.
[0030] First, as shown in Figure 2A, a semiconductor substrate 10 is prepared having a substrate 11, a drift layer 12, a base layer 13, a source region 14, and a contact region 15. In this embodiment, as the semiconductor substrate 10, a wafer-shaped semiconductor substrate 10 is prepared in which each chip formation region R is demarcated by a dicing line DL, as shown in Figure 3. Figures 2A to 2F show a cross-section of the semiconductor substrate 10 in one chip formation region R. The contact region 15 is formed in a different cross-section than that shown in Figure 2A.
[0031] Next, as shown in Figure 2B, the mask 30 and the resist 40 are arranged in order on one surface 10a of the semiconductor substrate 10. In this embodiment, the mask 30 is made of SiO2 (i.e., an oxide film) formed by a method such as CVD (Chemical Vapor Deposition).
[0032] Next, as shown in Figure 2C, photolithography and etching are performed to pattern the mask 30 so that the area of the semiconductor substrate 10 where the trench 16 is to be formed is exposed, thereby forming an opening 31.
[0033] Then, as shown in Figure 2D, after removing the resist 40 by ashing or the like, trenches 16 are formed in the semiconductor substrate 10 by anisotropic etching using the mask 30. The anisotropic etching here is performed under conditions where the selectivity ratio of the semiconductor substrate 10 is higher than that of the mask 30. After this process is completed, the open end 16a of the trench 16 is not exposed by the mask 30.
[0034] Next, as shown in Figure 2E, wet etching is performed to widen the opening 31 of the mask 30 and expose the opening end 16a of the trench 16. In other words, the opening 31 of the mask 30 is retracted to expose the opening end 16a of the trench 16. In this embodiment, wet etching is performed under conditions where the selectivity ratio of the mask 30 is higher than that of the semiconductor substrate 10, so that the semiconductor substrate 10 is less likely to be etched.
[0035] Then, as shown in Figure 2F, etching using the mask 30 is performed to form a rounded portion 160 at the open end 16a of the trench 16. In this embodiment, the rounded portion 160 at the open end 16a of the trench 16 is formed by performing anisotropic etching under conditions where the selectivity ratio of the mask 30 is higher than that of the semiconductor substrate 10. In other words, the rounded portion 160 at the open end 16a of the trench 16 is formed by performing anisotropic etching under conditions where the semiconductor substrate 10 is difficult to erode. This forms a rounded portion 160 that consists of only a small amount of the open end 16a being removed. Furthermore, since this process is performed under conditions where the semiconductor substrate 10 is difficult to erode, by exposing only the vicinity of the open end 16a, one surface 10a of the semiconductor substrate 10 is less likely to be eroded, and the reduction of one surface 10a of the semiconductor substrate 10 located between the trenches 16 can be suppressed. However, in this process, as will be described later, the bottom surface of the trench 16 is also slightly removed.
[0036] Furthermore, when performing anisotropic etching, for example, a mixed gas containing CF-based gas and SF-based gas is used as the etching gas, and the selectivity ratio can be adjusted by adjusting the flow rates of the CF-based gas and SF-based gas. Specifically, increasing the flow rate of the CF-based gas can increase the selectivity ratio of SiO2 (i.e., mask 30), and increasing the flow rate of the SF-based gas can increase the selectivity ratio of SiC (i.e., semiconductor substrate 10). For this reason, in this embodiment, the flow rate of the CF-based gas is increased so that the selectivity ratio of SiO2 is higher than that of SiC.
[0037] In this embodiment, a wafer-shaped semiconductor substrate 10 is used, and the inventors obtained the results shown in Figure 4. Figure 4 shows the depth of the trench 16 along the line IV-IV in Figure 3.
[0038] Specifically, as shown in Figure 4, when forming the trench 16 in the process shown in Figure 2D, etching gas flows more easily to the outer edge of the wafer, so it was confirmed that the trench 16 becomes deeper towards the outer edge of the wafer. In other words, when forming the trench 16, it was confirmed that the semiconductor substrate 10 is more easily eroded towards the outer edge of the wafer. On the other hand, when forming the rounded portion 160 at the opening end 16a of the trench 16 in the process shown in Figure 2F, although the exact reason is unclear, it was confirmed that the bottom surface of the trench 16 is more easily eroded towards the center of the wafer (i.e., the trench 16 tends to become deeper). In other words, it was confirmed that the parts of the semiconductor substrate 10 that are easily eroded are reversed when forming the trench 16 and when forming the rounded portion 160 at the opening end 16a of the trench 16. Therefore, in this embodiment, by forming the trench 16 as described above and forming a rounded portion 160 at the open end 16a of the trench 16, the variation in the final depth of the trench 16 in the plane of the wafer can be reduced.
[0039] Subsequently, although not specifically shown in the diagram, the mask 30 is removed by etching or the like, and a general semiconductor manufacturing process is carried out to form the gate insulating film 17, gate electrode 18, interlayer insulating film 19, upper electrode 20, lower electrode 21, etc., thereby manufacturing the SiC semiconductor device.
[0040] According to the embodiment described above, the rounded portion 160 is formed by etching the mask 30 under conditions where the selectivity ratio is higher than that of the semiconductor substrate 10. As a result, one surface 10a of the semiconductor substrate 10 is less likely to be etched, and the reduction of one surface 10a of the semiconductor substrate 10 located between the trenches 16 can be suppressed. In other words, the reduction of the source region 14 and contact region 15 exposed from one surface 10a of the semiconductor substrate 10 can be suppressed. Therefore, the occurrence of connection failures between the upper electrode 20 and the source region 14 and contact region 15 can be suppressed. Furthermore, since the reduction of the source region 14 and contact region 15 exposed from one surface 10a of the semiconductor substrate 10 can be suppressed, the length between adjacent trenches 16 can be shortened to reduce on-resistance. And, since the rounded portion 160 is formed at the open end 16a of the trench 16, the occurrence of electric field concentration at the open end 16a of the trench 16 can be suppressed.
[0041] (1) In this embodiment, anisotropic etching is performed by forming a rounded portion 160 at the opening end 16a of the trench 16. This suppresses damage to the side surface of the trench 16. Furthermore, it makes it less likely for the material to be etched down to the lower part of the mask 30, and also suppresses the reduction of the source region 14 and contact region 15 exposed from one surface 10a of the semiconductor substrate 10.
[0042] (2) In this embodiment, a wafer-shaped semiconductor substrate 10 is used. When forming the trenches 16, anisotropic etching is performed under conditions where the selectivity ratio of the semiconductor substrate 10 is higher than that of the mask 30. When forming the rounded portion 160 at the open end 16a of the trenches 16, anisotropic etching is performed under conditions where the selectivity ratio of the mask 30 is higher than that of the semiconductor substrate 10. Therefore, the parts of the semiconductor substrate 10 that are easily etched are reversed when forming the trenches 16 and when forming the rounded portion 160 at the open end 16a of the trenches 16. Consequently, variations in the final depth of the trenches 16 in the plane of the wafer can be reduced.
[0043] (Second Embodiment) A second embodiment will now be described. This embodiment differs from the first embodiment in that the etching process for forming the rounded portion 160 at the open end 16a of the trench 16 is modified. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.
[0044] In this embodiment, after forming the trench 16 by performing the process shown in Figure 2D, the process shown in Figure 2F is performed without performing the process shown in Figure 2E to form a rounded portion 160 at the open end 16a of the trench 16. Specifically, in this embodiment, isotropic etching such as CDE (Chemical Dry Etching) is performed to form a rounded portion 160 at the open end 16a of the trench 16. In this process as well, isotropic etching is performed under conditions where the selectivity ratio of the mask 30 is higher than that of the semiconductor substrate 10. In this case, since the mask 30 is easily removed from the opening 31 side, as shown in Figure 2F, the mask 30 is removed from the opening side to form a rounded portion 160 at the open end 16a of the trench 16. In this case, since the selectivity ratio of the mask 30 is set to be higher than that of the semiconductor substrate 10, a rounded portion 160 can be formed by slightly removing only the corners of the open end 16a. Furthermore, since the mask 30 is set to have a higher selectivity than the semiconductor substrate 10, it is possible to suppress the removal of the portion of the semiconductor substrate 10 located below the mask 30 during isotropic etching. In addition, in CDE, the conditions can be easily adjusted so that the mask 30 has a higher selectivity than the semiconductor substrate 10 by appropriately adjusting the flow rate of the etching gas.
[0045] Subsequently, the SiC semiconductor device is manufactured by removing the mask 30 and forming the gate insulating film 17, etc., in the same manner as in the first embodiment described above.
[0046] According to the embodiment described above, since the rounded portion 160 is formed by etching the mask 30 under conditions where the selectivity ratio is higher than that of the semiconductor substrate 10, the same effects as in the first embodiment can be obtained.
[0047] (1) In this embodiment, to form a rounded portion 160 at the open end 16a of the trench 16, isotropic etching is performed using the same mask 30 used when forming the trench 16. Therefore, there is no need to widen the open end 16a of the trench 16, and the manufacturing process can be simplified.
[0048] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of this disclosure.
[0049] For example, in the first embodiment described above, an n-channel type trench gate MOSFET with a first conductivity type of n-type and a second conductivity type of p-type was used as an example. However, this is merely one example, and for example, a p-channel type trench gate MOSFET with the conductivity types of each component reversed compared to the n-channel type may also be used. Furthermore, the SiC semiconductor device may have a configuration in which IGBTs with a similar structure are formed in addition to MOSFETs. In the case of IGBTs, the n in each of the above embodiments + The substrate 11 of type p + Aside from changing the collector layer type, it is the same as the vertical MOSFET described in each of the embodiments above.
[0050] Furthermore, in the first embodiment described above, an example was given in which the semiconductor substrate 10 is made of SiC. However, the semiconductor substrate 10 may be made of a silicon substrate or other compound semiconductor substrates, etc. [Explanation of Symbols]
[0051] 10 Semiconductor substrates 10a one side 16 Trench 16a Open end 17 Gate insulating film 18 Guard gate 160 Rounding section
Claims
1. A method for manufacturing a semiconductor device having multiple trench gate structures, To prepare a semiconductor substrate (10) having one side (10a), A trench (16) is formed from the aforementioned one side, with one direction in the plane direction of the semiconductor substrate as the longitudinal direction, The plurality of trench gate structures are formed by arranging a gate insulating film (17) and a gate electrode (18) in the trench, By forming the trench, The mask (30) is placed on one surface of the semiconductor substrate, The mask is patterned to form an opening (31) such that the region of the semiconductor substrate in which the trench is to be formed is exposed, By performing etching using the mask, the trench is formed in the semiconductor substrate, By performing etching with the mask in place, a rounded portion (160) is formed at the opening end (16a) of the trench, By forming a rounded portion at the opening end of the trench, the etching is performed under conditions in which the selectivity ratio of the mask is higher than that of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the trench is formed and anisotropic etching is performed under conditions where the selectivity ratio of the semiconductor substrate is higher than that of the mask.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a rounded portion is formed at the open end of the trench, thereby widening the opening of the mask and exposing the open end of the trench.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the rounded portion is formed at the opening end of the trench by performing anisotropic etching under conditions in which the selectivity ratio of the mask is higher than that of the semiconductor substrate.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is prepared in the form of a wafer in which a plurality of chip formation regions (R) are demarcated by dicing lines (DL).