Switching element

Abstract

To suppress current concentration in the vicinity of each connection region.SOLUTION: A switching element in which when a semiconductor substrate is viewed from above, a connection region connecting a body region and a deep region form a plurality of columns linearly arranged along a second direction. An intersection between an inter-trench semiconductor layer and a column includes a connection intersection where the connection region is provided and a non-connection intersection where no connection region is provided. The standard number of non-connected intersections are placed in the interval between adjacent connected intersections. The standard number is 3 or 4. When counting Manhattan distances in units of intersections, the Manhattan distance to the connected intersection at each non-connected intersection is 1.SELECTED DRAWING: Figure 6

Description

Technical Field

[0005] , , ,

[0001] The technology disclosed in this specification relates to a switching element.

[0002] Patent Document 1 discloses a trench gate type switching element. In this switching element, a plurality of p-type deep layers are provided inside an n-type drift layer. In the thickness direction of the semiconductor substrate, each deep layer is disposed below the lower end of the trench. Note that in the thickness direction of the semiconductor substrate, each deep layer may be disposed in a range including the lower end of the trench. Further, the switching element of Patent Document 1 has a plurality of p-type connection regions. Each connection region connects each deep layer to a p-type body layer. By providing the deep layer and the connection region in this manner, the electric field applied to the gate insulating film covering the lower end of the trench can be suppressed.

[0003] <000001​​​​​​​​​​​​​​​​​​​​​​​

[0006] During the operation of a switching element, recovery current and avalanche current may flow from the drift region to each connection region. In the switching element described in Patent Document 1, when recovery current and avalanche current flow in the drift region, current tends to concentrate near each connection region. This specification proposes a technique to suppress current concentration near each connection region in a switching element in which multiple connection regions are arranged in a distributed manner. [Means for solving the problem]

[0007] The switching element disclosed herein comprises a semiconductor substrate, a gate insulating film, a gate electrode, and a source electrode. A plurality of trenches are provided on the upper surface of the semiconductor substrate. Each of the trenches extends linearly in a first direction on the upper surface of the semiconductor substrate. Each of the trenches is spaced apart on the upper surface of the semiconductor substrate in a second direction intersecting the first direction. The gate insulating film covers the inner surface of each of the trenches. The gate electrode is disposed within each of the trenches and is insulated from the semiconductor substrate by the gate insulating film. The source electrode is in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched between the plurality of trenches. Each inter-trench semiconductor layer has an n-type source region in contact with the gate insulating film and the source electrode, and a p-type body region in contact with the gate insulating film below the source region. The semiconductor substrate has a drift region, a plurality of deep regions, and a plurality of connection regions. The drift region is distributed across the lower part of the plurality of inter-trench semiconductor layers and is an n-type region in contact with the gate insulating film below the body region within each inter-trench semiconductor layer. The plurality of deep regions are arranged in the area surrounded by the drift region, spaced apart from the body region and located below the body region, and are p-type regions located in the thickness direction of the semiconductor substrate, including the lower end of the trench or located below the lower end of the trench. The plurality of connection regions are p-type regions connecting the body region and the deep regions. When the semiconductor substrate is viewed from above, the connection regions are arranged in a linear fashion with spacing along the second direction, and the plurality of rows are spaced apart in the first direction. When the semiconductor substrate is viewed from above, the intersections of the plurality of inter-trench semiconductor layers and the plurality of rows have a connection intersection where the connection region is provided and a non-connection intersection where the connection region is not provided. In the first and second directions, the connecting intersection and the non-connecting intersection are repeatedly arranged according to a reference pattern.Within the range in which the connection intersections and non-connection intersections are repeatedly arranged according to the aforementioned reference pattern, the connection intersections and non-connection intersections satisfy the following conditions: · In each inter-trench semiconductor layer, the connection intersections are arranged in the first direction such that a reference number of non-connection intersections are arranged in the intervals between adjacent connection intersections; · In the row, the connection intersections are arranged in the second direction such that a reference number of non-connection intersections are arranged in the intervals between adjacent connection intersections; · The reference number is 3 or 4; · When counting the Manhattan distance in units of the intersections, the Manhattan distance to the connection intersection at each non-connection intersection is 1.

[0008] In a switching element, if there are non-connected intersections that are extremely far from the connected intersections, recovery current and avalanche current are less likely to flow near the non-connected intersections that are extremely far from the connected intersections. In this case, the density of recovery current and avalanche current becomes high near the connected region. In contrast, in the switching element disclosed herein, the Manhattan distance from each non-connected intersection to a connected intersection is 1 within the range in which connected and non-connected intersections are repeatedly arranged according to a reference pattern. That is, there are no non-connected intersections that are extremely far from the connected intersections. Therefore, in this switching element, current concentration near each connected region is suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] A perspective view of the switching element of Example 1, including longitudinal sections along the x and y directions. [Figure 2] A cross-sectional view showing a longitudinal section along the x-direction at a position including the deep region of the switching element of Example 1 (position along line II-II in Figure 6). [Figure 3] A cross-sectional view showing a longitudinal section along the x-direction at a position that does not include the deep region of the switching element in Example 1 (position along line III-III in Figure 6). [Figure 4]A cross-sectional view showing a longitudinal section along the y-direction at a position that does not include the trench of the switching element in Example 1 (position of line IV-IV in Figure 6). [Figure 5] A cross-sectional view showing a longitudinal section along the y-direction at the location including the trench of the switching element in Example 1 (the location of the VV line in Figure 6). [Figure 6] A plan view showing the arrangement of the connection and disconnection intersections of the switching elements in Example 1. [Figure 7] A diagram showing the reference pattern P. [Figure 8] A diagram showing multiple reference patterns P arranged adjacent to each other. [Figure 9] A diagram showing the baseline pattern of the comparative example. [Figure 10] A perspective view of the switching element of the first modified example, including longitudinal sections along the x and y directions. [Figure 11] A perspective view of the switching element of Example 2, including longitudinal sections along the x and y directions. [Figure 12] A plan view showing the arrangement of the connection and disconnection intersections of the switching elements in Example 2. [Figure 13] A perspective view of the switching element of Example 3, including longitudinal sections along the x and y directions. [Figure 14] A plan view showing the arrangement of the connection and disconnection crossings of the switching elements in Example 3. [Figure 15] A perspective view of the switching element of Example 4, including longitudinal sections along the x and y directions. [Figure 16] A plan view showing the arrangement of the connection and disconnection intersections of the switching elements in Example 4. [Figure 17] A perspective view of the switching element of the second modified example, including longitudinal sections along the x and y directions. [Figure 18] A diagram showing the reference pattern Q when the reference number is 4. [Figure 19] A diagram showing multiple reference patterns Q arranged adjacent to each other. [Modes for carrying out the invention]

[0010] In a switching element according to an example disclosed in this specification, a plurality of the deep regions may extend linearly along the second direction and be arranged at intervals in the first direction such that each of the deep regions extends along the column corresponding thereto when the semiconductor substrate is viewed from above.

[0011] In a switching element according to an example disclosed in this specification, each of the connection regions may be in contact with the gate insulating film on side surfaces of the trenches located on both sides thereof.

[0012] In this configuration, at the intersection where each connection region exists, an inversion layer formed in the body layer does not function as a channel. According to the configuration disclosed in this specification, since each connection region can be dispersedly arranged, intersections that do not function as channels can be dispersedly arranged. Therefore, the main current flowing when the switching element is on can be dispersed and flow in the semiconductor substrate.

[0013] In a switching element according to an example disclosed in this specification, a p-type contact region connecting the body region and the source electrode may be provided above each of the connection regions.

Example

[0014] The switching element 10 of Embodiment 1 shown in Figure 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si or GaN. Hereinafter, the direction parallel to the upper surface 12a of the semiconductor substrate 12 will be called the x-direction, the direction parallel to the upper surface 12a and perpendicular to the x-direction will be called the y-direction, and the thickness direction of the semiconductor substrate 12 will be called the z-direction. Multiple trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the x-direction on the upper surface 12a. Each trench 14 is spaced apart in the y-direction on the upper surface 12a. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is placed inside each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An interlayer insulating film 20 is placed inside each trench 14. Each interlayer insulating film 20 covers the upper surface of the gate electrode 18.

[0015] As shown in Figures 2-5, a source electrode 22 is provided on the upper part of the semiconductor substrate 12. Note that the source electrode 22 is not shown in Figure 1. The source electrode 22 covers the upper surface of the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0016] Figure 6 shows the upper surface 12a of the semiconductor substrate 12. As described above, multiple trenches 14 extending linearly in the x-direction are arranged on the upper surface 12a at intervals in the y-direction. The inter-trench semiconductor layer 30 shown in Figure 6 represents a semiconductor layer sandwiched between two trenches 14 (i.e., a semiconductor layer located between two trenches 14). Each inter-trench semiconductor layer 30 extends linearly in the x-direction on the upper surface 12a. Each inter-trench semiconductor layer 30 is arranged at intervals in the y-direction on the upper surface 12a.

[0017] As shown in Figure 1, the semiconductor substrate 12 has a source region 40, a body region 42, a drift region 44, and a drain region 46.

[0018] The source region 40 is an n-type region having a high n-type impurity concentration. The source region 40 is located within the inter-trench semiconductor layer 30. As shown in Figures 2 and 3, the source region 40 is in contact with the source electrode 22 within the inter-trench semiconductor layer 30. The source region 40 is in contact with the gate insulating film 16 on the sides of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0019] The body region 42 is a p-type region having a low p-type impurity concentration. The body region 42 is located within the inter-trench semiconductor layer 30. As shown in Figures 2 and 3, the body region 42 is located within the inter-trench semiconductor layer 30 and is situated below the source region 40. The body region 42 is in contact with the gate insulating film 16 below the source region 40. That is, the body region 42 is in contact with the gate insulating film 16 on the sides of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0020] The drift region 44 is an n-type region with a low n-type impurity concentration. As shown in Figures 2 and 3, the drift region 44 is distributed across the lower part of multiple inter-trench semiconductor layers 30. As shown in Figure 3, the upper end of the drift region 44 extends into each inter-trench semiconductor layer 30. Within each inter-trench semiconductor layer 30, the drift region 44 is in contact with the body region 42 from below. The drift region 44 is in contact with the gate insulating film on the lower side of the body region 42. That is, the drift region 44 is in contact with the gate insulating film 16 on the sides of the trenches 14 provided on both sides of each inter-trench semiconductor layer 30.

[0021] The drain region 46 is an n-type region with a high n-type impurity concentration. The n-type impurity concentration in the drain region 46 is higher than that of the drift region 44. As shown in Figures 2-5, the drain region 46 is in contact with the drift region 44 from below. The drain region 46 is in contact with the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0022] The semiconductor substrate 12 has multiple p-type deep regions 50. As shown in Figures 2 and 4, each deep region 50 is located within a range surrounded by drift regions 44. Each deep region 50 is located below the body region 42, with a gap between them. The drift regions 44 are distributed in the gaps between each deep region 50 and the body region 42. In Figure 6, the dot-hatched areas indicate the distribution range of the deep regions 50. As shown in Figure 6, when the semiconductor substrate 12 is viewed from above, each deep region 50 extends linearly in the y-direction. When the semiconductor substrate 12 is viewed from above, each deep region 50 is located with a gap in the x-direction. As shown in Figures 1, 2, and 5, each deep region 50 is located within a range that includes the lower end of the trench 14 in the z-direction. Therefore, each deep region 50 is in contact with the gate insulating film 16 at the lower end of each trench 14.

[0023] As shown in Figure 1, the semiconductor substrate 12 has a plurality of connection regions 52 and a plurality of contact regions 54. As shown in Figures 1, 2, and 4, the connection region 52 is a p-type region connecting the body region 42 and the deep region 50. The contact region 54 is a p-type region connecting the body region 42 and the source electrode 22. That is, the contact region 54 extends upward from the body region 42 and is in contact with the source electrode 22 at its upper end. In this embodiment, the contact region 54 and the connection region 52 extend continuously in the z direction. That is, the contact region 54 is located above the connection region 52. The semiconductor substrate 12 has a plurality of sets of contact regions 54 and deep regions 50. Each deep region 50 is connected to the source electrode 22 via the connection region 52 and the contact region 54.

[0024] In Figure 6, the areas hatched with diagonal lines represent sets of connection areas 52 and contact areas 54. These sets of connection areas 52 and contact areas 54 are partially located on the upper part of the deep area 50. As shown in Figure 6, when the semiconductor substrate 12 is viewed from above, the multiple connection areas 52 are arranged to form multiple rows 53 that extend linearly in the y-direction. In Figure 6, the rows 53 extending in the y-direction overlap with the deep area 50. The multiple rows 53 are spaced apart in the x-direction.

[0025] The intersection 60 shown in Figure 6 is the portion where the inter-trench semiconductor layer 30 and the row 53 intersect when the semiconductor substrate 12 is viewed from above. As described above, each inter-trench semiconductor layer 30 extends linearly in the x direction, and each row 53 extends linearly in the y direction. Therefore, when the semiconductor substrate 12 is viewed from above, multiple intersections 60 are arranged in a matrix along the x and y directions. As shown in Figure 6, a set of connection region 52 and contact region 54 is provided in some of the multiple intersections 60. As shown in Figures 1, 2, and 6, each connection region 52 is in contact with the gate insulating film 16 on the side surfaces of the trenches 14 located on both sides of the intersection 60. The contact region 54 is in contact with the gate insulating film 16 on the side surfaces of the trenches 14 located on both sides of the intersection 60. Hereinafter, the intersection 60 provided with a connection region 52 will be referred to as a connected intersection 60a, and the intersection 60 without a connection region 52 will be referred to as an unconnected intersection 60b.

[0026] The reference pattern P in Figure 6 shows the arrangement pattern of connecting intersections 60a and non-connecting intersections 60b. Connecting intersections 60a and non-connecting intersections 60b are provided so that the reference pattern P is repeated in the x and y directions. Figure 7 schematically shows the reference pattern P. Each cell in Figure 7 represents an intersection 60. In Figure 7, cells hatched with diagonal lines are connecting intersections 60a, and blank cells are non-connecting intersections 60b. Figure 8 shows multiple reference patterns P arranged in a matrix in the x and y directions. In Figure 8, the central reference pattern P is denoted by reference numeral P1, and the surrounding reference patterns P2 to P9 are denoted by reference numeral P2 to P9. The reference pattern P is set to satisfy the following conditions 1 to 4 within the range in which connecting intersections 60a and non-connecting intersections 60b are repeatedly arranged according to the reference pattern P.

[0027] (Condition 1) In each inter-trench semiconductor layer 30, connection intersections 60a are arranged at regular intervals in the x-direction, and three non-connection intersections 60b are arranged within each interval. That is, as shown in Figures 7 and 8, in each inter-trench semiconductor layer 30, the connection intersections 60a are arranged at intervals in the x-direction such that one connection intersection 60a appears for every three non-connection intersections 60b.

[0028] (Condition 2) In each row 53, connecting intersections 60a are arranged at regular intervals in the y direction, and three non-connecting intersections 60b are arranged within each interval. That is, as shown in Figures 7 and 8, in each row 53, the connecting intersections 60a are arranged at intervals in the y direction such that one connecting intersection 60a appears for every three non-connecting intersections 60b.

[0029] (Condition 3) Within the range in which the reference pattern P is continuous, the Manhattan distance from each non-connecting intersection 60b to a connecting intersection 60a (more specifically, to the nearest connecting intersection 60a) is 1 for all non-connecting intersections 60b.

[0030] Note that the Manhattan distance referred to here is the value counted in units of 60 intersections. For example, in Figure 8, the unconnected intersection 60b-1 is adjacent to the connected intersection 60a in the y direction, so the Manhattan distance of the unconnected intersection 60b-1 to the connected intersection 60a is 1. Also, in Figure 8, the unconnected intersection 60b-2 is adjacent to the connected intersection 60a in the x direction, so the Manhattan distance of the unconnected intersection 60b-2 to the connected intersection 60a is 1. In Figure 8, the unconnected intersection 60b-3 is adjacent to the adjacent reference pattern in the y direction. P3 Since it is adjacent to the connecting intersection 60a, the Manhattan distance from the non-connecting intersection 60b-3 to the connecting intersection 60a is 1. In all non-connecting intersections 60b within the central reference pattern P1 shown in Figure 8, the Manhattan distance to the connecting intersection 60a is 1. Thus, within the range where the reference pattern P is continuous, the Manhattan distance to the connecting intersection 60a is 1 for all non-connecting intersections 60b within the reference pattern P.

[0031] In the following, the position of each cell within the reference pattern P in Figure 7 is represented by coordinates (x,y). In Figure 7, the leftmost column is represented as x=1, and the rightmost column as x=4. Also, in Figure 7, the bottommost row is represented as y=1, and the topmost row as y=4. In pattern P, the cells at coordinates (1,4), (2,3), (3,4), and (4,3) are connected intersections 60a, and the other cells are disconnected intersections 60b. By following such a reference pattern P, the Manhattan distance between each disconnected intersection 60b within the continuous range of the reference pattern P can be set to 1.

[0032] The switching element 10 in Example 1 is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). Under normal circumstances, a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, an inversion layer is formed in the body region 42, and the source region 40 and the drift region 44 are connected by the inversion layer. As a result, the switching element 10 turns on, and current flows from the drain electrode 24 to the source electrode 22. At the connection intersection 60a, a contact region 54 and a connection region 52 are provided above and below the body region 42, so almost no current flows through the connection intersection 60a. At the non-connection intersection 60b, current flows through the inversion layer. In the switching element 10 of Example 1, only a portion of the multiple intersections 60 are connection intersections 60a, and the remaining intersections 60 are non-connection intersections 60b. Because there are few connection intersections 60a, a high density of current can be supplied to the semiconductor substrate 12 when the switching element 10 is turned on. Therefore, the on-resistance of the switching element 10 is low.

[0033] When the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the switching element 10 turns off and the current stops. When the switching element 10 turns off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44, and a depletion layer spreads from the body region 42 to the drift region 44. Also, since the deep region 50 is connected to the body region 42 by the connection region 52, the potential of the deep region 50 is approximately equal to the potential of the body region 42. Therefore, a reverse voltage is applied to the pn junction at the interface between the deep region 50 and the drift region 44, and a depletion layer spreads from the deep region 50 to the drift region 44. The depletion layer extending from the deep region 50 prevents a high electric field from being applied to the gate insulating film 16 at the lower end of each trench 14.

[0034] In some cases, a higher potential is applied to the source electrode 22 than to the drain electrode 24. In this case, the diode formed by the pn junction at the interface between the body region 42 and the drift region 44 (a so-called body diode) turns on, and current flows from the source electrode 22 to the drain electrode 24. When the body diode is on, holes flow from the body region 42 into the drift region 44, so many holes exist in the drift region 44. Subsequently, when the potential of the drain electrode 24 becomes higher than the potential of the source electrode 22, the body diode turns off. Then, the holes present in the drift region 44 flow to the deep region 50, as shown by arrow 100 in Figure 2. The holes that flowed from the drift region 44 to the deep region 50 flow to the source electrode 22 via the connection region 52 and the contact region 54. The current generated when the body diode turns off in this way is called the recovery current. As shown in Figure 2, at the connection crossover 60a where the connection region 52 is provided, the recovery current flows more easily into the drift region 44 than at the non-connection crossover 60b where the connection region 52 is not provided.

[0035] Furthermore, an overvoltage may be applied to the switching element 10 in a direction in which the drain electrode 24 is at a higher potential than the source electrode 22. In this case, an avalanche current is generated in the drift region 44. The avalanche current flows into the deep region 50, as shown by the arrow 100 in Figure 2. The avalanche current that flows from the drift region 44 into the deep region 50 flows to the source electrode 22 via the connection region 52 and the contact region 54. As shown in Figure 2, in the connection crossover 60a where the connection region 52 is provided, the avalanche current flows more easily into the drift region 44 than in the non-connection crossover 60b where the connection region 52 is not provided.

[0036] As explained above, recovery current and avalanche current flow more easily into the drift region 44 at the connected intersection 60a than at the unconnected intersection 60b. At the unconnected intersection 60b, the further the distance to the connected intersection 60a, the less likely recovery current and avalanche current are to flow.

[0037] Figure 9 shows the reference pattern of the switching element of the comparative example. In the reference pattern shown in Figure 9, the non-connected intersections 60b-4 are not adjacent to any of the connected intersections 60a. Therefore, the Manhattan distance from the non-connected intersection 60b-4 to the connected intersection 60a is 2. In this way, recovery current and avalanche current are less likely to flow at the non-connected intersection 60b-4, where the Manhattan distance to the connected intersection 60a is far. Therefore, in the reference pattern of Figure 9, avalanche current concentration is likely to occur at the connected intersection 60a. For this reason, the avalanche withstand capability of the switching element of the comparative example may decrease. In contrast, in the switching element 10 of Example 1, the Manhattan distance from the connected intersection 60a is 1 at all non-connected intersections 60b within the range in which the reference pattern P is continuous. Therefore, avalanche current concentration is less likely to occur at the connected intersection 60a in the switching element 10 of Example 1. Therefore, the switching element of Example 1 can reduce the stress on the semiconductor substrate 12 when an avalanche current flows. Consequently, the structure of the switching element of Example 1 can achieve higher reliability.

[0038] As shown in Figure 10, a gap may be provided between the connection region 52 and the gate insulating film 16, and the drift region 44 may be distributed within that gap. Alternatively, as shown in Figure 10, a gap may be provided between the contact region 54 and the gate insulating film 16, and the source region 40 may be provided within that gap. With this configuration, when the switching element is turned on, current also flows through the connection intersection 60a. Therefore, the on-resistance of the switching element can be further reduced. [Examples]

[0039] Figures 11 and 12 show the switching element 200 of Example 2. In Example 2, each deep region 50 extends linearly in the x-direction. Multiple deep regions 50 are spaced apart in the y-direction. Each deep region 50 is located at the bottom of the central part in the y-direction of the inter-trench semiconductor layer 30.

[0040] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Figure 12, the multiple connection regions 52 are arranged to form multiple columns 53 that extend linearly in the y direction. The multiple columns 53 are spaced apart in the x direction.

[0041] As shown in Figure 12, the set of connection region 52 and contact region 54 is provided in a portion of the multiple intersections 60. Similar to Embodiment 1, the connection intersection 60a and the non-connection intersection 60b are arranged according to the same reference pattern P as in Figures 7 and 8. That is, the connection intersection 60a and the non-connection intersection 60b are arranged to satisfy the above-described conditions 1 to 3. Therefore, in Embodiment 2 as well, within the range where the reference pattern P is continuous, there are no non-connection intersections 60b where the Manhattan distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 200 of Embodiment 2, concentration of recovery current and avalanche current is less likely to occur at the connection intersection 60a. The structure of the switching element in Embodiment 2 enables high reliability.

[0042] In Example 2, as in Figure 10, a drift region 44 may be distributed between the connection region 52 and the gate insulating film 16. Also, as in Figure 10, a source region 40 may be provided between the contact region 54 and the gate insulating film 16. [Examples]

[0043] Figures 13 and 14 show the switching element 300 of Embodiment 3. In Embodiment 3, each deep region 50 extends linearly in the x-direction. Multiple deep regions 50 are spaced apart in the y-direction. Each deep region 50 is located at the bottom of the trench 14.

[0044] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Figure 14, the multiple connection regions 52 are arranged to form multiple columns 53 that extend linearly in the y direction. The multiple columns 53 are spaced apart in the x direction.

[0045] As shown in Figure 14, the set of connection area 52 and contact area 54 is provided in a portion of the multiple intersections 60. Similar to Embodiment 1, the connection intersection 60a and the non-connection intersection 60b are arranged according to the same reference pattern P as in Figures 7 and 8. That is, the connection intersection 60a and the non-connection intersection 60b are arranged to satisfy the above-described conditions 1 to 3. Therefore, in Embodiment 3 as well, within the range where the reference pattern P is continuous, there are no non-connection intersections 60b where the Manhattan distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 300 of Embodiment 3, concentration of recovery current and avalanche current is less likely to occur at the connection intersection 60a. The structure of the switching element in Embodiment 3 enables high reliability. [Examples]

[0046] Figures 15 and 16 show the switching element 400 of Embodiment 4. The switching element 400 of Embodiment 4 has two types of deep regions 50x and 50y. Each deep region 50y extends linearly in the y direction. Multiple deep regions 50y are spaced apart in the x direction. Each deep region 50y is located at a depth that includes the lower end of the trench 14. Each deep region 50x is located below each deep region 50y. Each deep region 50x extends linearly in the x direction. Multiple deep regions 50x are spaced apart in the y direction. The upper end of each deep region 50x is located at a depth that overlaps with the lower end of each deep region 50y. Each deep region 50x and each deep region 50y are connected to each other at the point where they intersect.

[0047] Each deep region 50y is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Figure 16, the multiple connection regions 52 are arranged to form multiple columns 53 that extend linearly in the y direction. In Figure 16, the columns 53 extending in the y direction overlap with the deep regions 50y. The multiple columns 53 are spaced apart in the x direction.

[0048] As shown in Figure 16, the set of connection area 52 and contact area 54 is provided in a portion of the multiple intersections 60. Similar to Example 1, the connection intersection 60a and the non-connection intersection 60b are arranged according to the same reference pattern P as in Figures 7 and 8. That is, the connection intersection 60a and the non-connection intersection 60b are arranged to satisfy the above-described conditions 1 to 3. Therefore, in Example 4 as well, within the range where the reference pattern P is continuous, there are no non-connection intersections 60b where the Manhattan distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 400 of Example 4, concentration of recovery current and avalanche current is less likely to occur at the connection intersection 60a. The structure of the switching element in Example 4 enables high reliability.

[0049] Furthermore, in Example 4, the deep regions 50x and 50y extend along the x and y directions. Therefore, the deep regions 50x and 50y within each disconnected intersection 60b are connected to the connected region 52 by current paths within a Manhattan distance of 1. In this way, since the deep regions 50x and 50y within each disconnected intersection 60b are connected to the connected region 52 by short current paths, the potential of the deep regions 50x and 50y can be stabilized.

[0050] In the above-described embodiment 4, the deep region 50y was positioned above the deep region 50x. However, the deep region 50x may also be positioned above the deep region 50y. Furthermore, the deep region 50x and the deep region 50y may be positioned at the same depth.

[0051] In the above-described embodiments 1 to 4, each deep region 50 was positioned at a depth that included the lower end of the trench 14. However, each deep region 50 may be positioned below the lower end of the trench 14. For example, in embodiment 1, as shown in Figure 17, each deep region 50 may be positioned below the lower end of the trench 14.

[0052] Furthermore, in the above-described embodiments 1 to 4, a contact area 54 was provided above the connection area 52. However, the positions of the connection area 52 and the contact area 54 may be offset in the x-direction. Also, the number of connection areas 52 and the number of contact areas 54 may be different.

[0053] Furthermore, in the above-described embodiments 1 to 4, the connecting intersection 60a and the non-connecting intersection 60b were arranged according to the reference pattern P shown in Figures 7 and 8. However, the connecting intersection 60a and the non-connecting intersection 60b may be arranged in any way as long as they follow a reference pattern that satisfies the above conditions 1 to 3. For example, a reference pattern may be adopted in which the reference pattern P shown in Figures 7 and 8 is shifted in the x and y directions, or a reference pattern may be adopted in which the reference pattern P is rotated 90 degrees to the right or 180 degrees to the left or right, or a reference pattern may be adopted in which the reference pattern P is flipped vertically or horizontally.

[0054] Furthermore, in the above-described embodiments 1 to 4, three non-connecting intersections 60b were arranged in the x and y directions, at intervals between connecting intersections 60a. That is, the number of non-connecting intersections 60b arranged within the interval (i.e., the reference number) was 3. However, the reference number may be 4. That is, four non-connecting intersections 60b may be arranged in the x and y directions, at intervals between connecting intersections 60a. In this case, the connecting intersections 60a and non-connecting intersections 60b may be arranged according to the reference pattern Q shown in Figures 18 and 19. In the reference pattern Q, the cells at coordinates (1,5), (2,2), (3,4), (4,1), and (5,3) are connecting intersections 60a, and the other cells are non-connecting intersections 60b. Within the range in which the reference pattern Q is repeated, the Manhattan distance to the connecting intersection 60a is 1 for all non-connecting intersections 60b within the reference pattern Q. Furthermore, a reference pattern may be adopted in which the reference pattern Q is shifted in the x and y directions, or a reference pattern may be adopted in which the reference pattern Q is rotated 90 or 180 degrees to the right or left, or a reference pattern may be adopted in which the reference pattern Q is flipped vertically or horizontally.

[0055] The components of the technology disclosed herein are listed below. (Composition 1) A switching element, A semiconductor substrate, wherein a plurality of trenches are provided on the upper surface of the semiconductor substrate, each of the trenches extends linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches is spaced apart in a second direction intersecting the first direction on the upper surface of the semiconductor substrate, The gate insulating film covering the inner surface of each trench, A gate electrode is disposed within each of the trenches and is insulated from the semiconductor substrate by the gate insulating film, The source electrode in contact with the upper surface of the semiconductor substrate, It has, The semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched between a plurality of trenches, Each trench-inter-semiconductor layer The gate insulating film and the n-type source region in contact with the source electrode, A p-shaped body region in contact with the gate insulating film on the lower side of the source region, It has, The aforementioned semiconductor substrate Distributed across the lower part of multiple inter-trench semiconductor layers, within each inter-trench semiconductor layer, there is an n-type drift region that is in contact with the gate insulating film on the lower side of the body region, A plurality of p-shaped deep regions are arranged in the area surrounded by the drift region, spaced apart from the body region and located below the body region, and in the thickness direction of the semiconductor substrate, the area includes the lower end of the trench or is located below the lower end of the trench, Multiple p-shaped connection regions connecting the body region and the deep region, It has, When the semiconductor substrate is viewed from above, the connection regions are arranged in a linear fashion with spacing between them along the second direction, and the multiple rows are arranged with spacing between them in the first direction. When the semiconductor substrate is viewed from above, the intersections of the multiple trench-inter-semiconductor layers and the multiple rows have a connected intersection where the connecting region is provided and a non-connected intersection where the connecting region is not provided. In the first and second directions, the connecting intersection and the non-connecting intersection are repeatedly arranged according to a reference pattern. Within the range in which the connection intersection and the non-connection intersection are repeatedly arranged according to the aforementioned reference pattern, the connection intersection and the non-connection intersection meet the following conditions, namely, Within each of the trench-inter-semiconductor layers, the connection intersections are arranged in the first direction such that a standard number of non-connection intersections are arranged in the spacing between adjacent connection intersections. Within the row, the connection intersections are arranged in the second direction such that the standard number of non-connection intersections are arranged in the intervals between adjacent connection intersections. • The aforementioned reference number is 3 or 4, When counting Manhattan distance in units of the aforementioned intersection, if the Manhattan distance to the aforementioned connecting intersection is 1 at each non-connecting intersection, The conditions that are met, Switching element. (Configuration 2) The switching element according to configuration 1, wherein, when the semiconductor substrate is viewed from above, a plurality of deep regions are arranged in a straight line along the second direction and spaced apart in the first direction, such that each deep region extends along the corresponding row. (Composition 3) The switching element according to configuration 1 or 2, wherein each of the connection regions is in contact with the gate insulating film on the sides of the trenches located on both sides thereof. (Composition 4) A switching element according to any one of configurations 1 to 3, wherein a p-type contact region connecting the body region and the source electrode is provided above each of the aforementioned connection regions.

[0056] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0057] 14: Trench, 18: Token gate, 30: Inter-trench semiconductor layer, 42: Body region, 44: Drift region, 50: Deep region, 52: Connection region, 53: Column, 54: Contact region, 60: Intersection, 60a: Connection intersection, 60b: Disconnection intersection

Claims

1. A switching element, A semiconductor substrate (12) wherein a plurality of trenches (14) are provided on the upper surface of the semiconductor substrate, each of the trenches extends linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches is spaced apart in a second direction that intersects the first direction on the upper surface of the semiconductor substrate, The gate insulating film (16) covering the inner surface of each trench, A gate electrode (18) is disposed within each of the trenches and is insulated from the semiconductor substrate by the gate insulating film, The source electrode (22) in contact with the upper surface of the semiconductor substrate, It has, The semiconductor substrate has a plurality of inter-trench semiconductor layers (30) sandwiched between a plurality of trenches, Each trench-inter-semiconductor layer The gate insulating film and the n-type source region (40) in contact with the source electrode, A p-shaped body region (42) in contact with the gate insulating film on the lower side of the source region, It has, The aforementioned semiconductor substrate Distributed across the lower part of multiple inter-trench semiconductor layers, each inter-trench semiconductor layer has an n-type drift region (44) that is in contact with the gate insulating film on the lower side of the body region, A plurality of p-shaped deep regions (50) are arranged in the area surrounded by the drift region, spaced apart from the body region and located below the body region, and in the thickness direction of the semiconductor substrate, the range includes the lower end of the trench or is located below the lower end of the trench, A plurality of p-shaped connection regions (52) connecting the body region and the deep region, It has, When the semiconductor substrate is viewed from above, the connection regions are arranged in a linear fashion with spacing between them along the second direction, and the multiple rows are arranged with spacing between them in the first direction. When the semiconductor substrate is viewed from above, the intersections (60) between the multiple trench-inter-semiconductor layers and the multiple rows have a connected intersection (60a) where the connecting region is provided and a non-connected intersection (60b) where the connecting region is not provided. In the first and second directions, the connecting intersection and the non-connecting intersection are repeatedly arranged according to a reference pattern (P). Within the range in which the connection intersection and the non-connection intersection are repeatedly arranged according to the aforementioned reference pattern, the connection intersection and the non-connection intersection meet the following conditions, namely, - Within each trench-inter-semiconductor layer, the connection intersections are arranged in the first direction such that a standard number of non-connection intersections are arranged in the spacing between adjacent connection intersections. - Within the row, the connection intersections are arranged in the second direction such that the standard number of non-connection intersections are arranged in the intervals between adjacent connection intersections. - The aforementioned standard number is 3 or 4, - When counting Manhattan distance in units of the aforementioned intersection, if the Manhattan distance to the aforementioned connecting intersection is 1 at each non-connecting intersection, The conditions that are met, Switching element.

2. The switching element according to claim 1, wherein, when the semiconductor substrate is viewed from above, a plurality of deep regions are arranged in a straight line along the second direction and spaced apart in the first direction, such that each deep region extends along the corresponding row.

3. The switching element according to claim 1 or 2, wherein each of the connection regions is in contact with the gate insulating film on the side surfaces of the trenches located on both sides thereof.

4. The switching element according to claim 1 or 2, wherein a p-type contact region (54) for connecting the body region and the source electrode is provided above each of the aforementioned connection regions.

5. A switching element, A semiconductor substrate (12) wherein a plurality of trenches (14) are provided on the upper surface of the semiconductor substrate, each of the trenches extends linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches is spaced apart in a second direction that intersects the first direction on the upper surface of the semiconductor substrate, The gate insulating film (16) covering the inner surface of each trench, A gate electrode (18) is disposed within each of the trenches and is insulated from the semiconductor substrate by the gate insulating film, The source electrode (22) in contact with the upper surface of the semiconductor substrate, It has, The semiconductor substrate has a plurality of inter-trench semiconductor layers (30) sandwiched between a plurality of trenches, Each trench-inter-semiconductor layer The gate insulating film and the n-type source region (40) in contact with the source electrode, A p-shaped body region (42) in contact with the gate insulating film on the lower side of the source region, It has, The aforementioned semiconductor substrate Distributed across the lower part of multiple inter-trench semiconductor layers, each inter-trench semiconductor layer has an n-type drift region (44) that is in contact with the gate insulating film on the lower side of the body region, A plurality of p-shaped deep regions (50) are arranged in the area surrounded by the drift region, spaced apart from the body region and located below the body region, and in the thickness direction of the semiconductor substrate, the range includes the lower end of the trench or is located below the lower end of the trench, A plurality of p-shaped connection regions (52) connecting the body region and the deep region, It has, When the semiconductor substrate is viewed from above, each of the deep regions extends linearly along the second direction, and a plurality of the deep regions are arranged at intervals in the first direction. When the semiconductor substrate is viewed from above, the intersections (60) between the multiple trench-inter-semiconductor layers and the multiple deep regions have a connected intersection (60a) where the connecting region is provided and a non-connected intersection (60b) where the connecting region is not provided. In the first and second directions, the connecting intersection and the non-connecting intersection are repeatedly arranged according to a reference pattern (P). Within the range in which the connection intersection and the non-connection intersection are repeatedly arranged according to the aforementioned reference pattern, the connection intersection and the non-connection intersection meet the following conditions, namely, - Within each trench-inter-semiconductor layer, the connection intersections are arranged in the first direction such that a standard number of non-connection intersections are arranged in the spacing between adjacent connection intersections. - Within the range overlapping with each of the deep regions, the connection intersections are arranged in the second direction such that the reference number of non-connection intersections are arranged in the intervals between adjacent connection intersections. - The aforementioned standard number is 3 or 4, - When counting Manhattan distance in units of the aforementioned intersection, if the Manhattan distance to the aforementioned connecting intersection is 1 at each non-connecting intersection, The conditions that are met, Switching element.

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