Semiconductor equipment

Abstract

To provide a semiconductor device that reduces an on-resistance.SOLUTION: An embodiment is provided with a semiconductor portion, a first electrode, a second electrode, a first control electrode, a second control electrode, a conductive member, and a bonding member. The first electrode, the second electrode, the first control electrode, and the second control electrode are provided on the semiconductor portion. The conductive member is provided under the semiconductor portion. The bonding member is provided between the semiconductor portion and the conductive member. A thin portion has a thickness thinner than a mounting portion. In a plan view, the semiconductor portion and the conductive member are rectangular, and the conductive member includes the mounting portion on which the semiconductor portion is mounted and the thin portion surrounding the mounting portion. Vertices of the semiconductor portion are located in the thin portion.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] There is known a semiconductor device in which two transistors having electrically separated source electrodes are formed on a single common semiconductor substrate, and the semiconductor substrate serves as the drain electrodes of the two transistors.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention aim to provide a semiconductor device with reduced on-resistance.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment is a semiconductor portion having a first surface and a second surface located opposite to the first surface, and comprising: a first region provided between the first surface and the second surface, a second region provided between the first surface and the second surface, and a semiconductor substrate connecting the first region and the second region; a first electrode provided on the first surface in the first region, a second electrode provided on the first surface in the second region, away from the first electrode, a first control electrode provided in the first region for controlling the current flowing between the first electrode and the semiconductor substrate, a second control electrode provided in the second region for controlling the current flowing between the second electrode and the semiconductor substrate; a conductive member having a third surface arranged opposite to the second surface and a fourth surface located opposite to the third surface, and electrically connected to the semiconductor substrate via the third surface; and a conductive bonding member provided between the semiconductor substrate and the conductive member. The conductive member includes a mounting portion provided between the third and fourth surfaces, and a thin-walled portion having a fifth surface located opposite the fourth surface, the thickness between the fifth surface and the fourth surface being thinner than the thickness of the mounting portion. The joining member is provided between the second and third surfaces, and also between the second and fifth surfaces. In plan view, the outer periphery of the conductive member and the outer periphery of the semiconductor portion are rectangular, the four first vertices of the conductive member are arranged to correspond to the four second vertices of the semiconductor portion, the outer periphery of the conductive member coincides with the outer periphery of the semiconductor portion or is located outside the outer periphery of the semiconductor portion, and at least one of the four second vertices is arranged to be located within the region of the thin-walled portion. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 2] This is a schematic side view illustrating a semiconductor device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view along line III-III in Figure 1. [Figure 4]This is a schematic side view illustrating a part of a semiconductor device according to the first embodiment. [Figure 5] This is a schematic side view illustrating a part of a semiconductor device used in a comparative example. [Figure 6] This is a schematic side view illustrating a part of a semiconductor device used in a comparative example. [Figure 7] This is a schematic side view illustrating a part of a semiconductor device according to the first embodiment. [Figure 8] This is a schematic plan view illustrating a semiconductor device according to a modified example of the first embodiment. [Figure 9] This is a schematic plan view illustrating a semiconductor device according to another modification of the first embodiment. [Figure 10] This is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 11] This is a schematic perspective view illustrating a conductive member, which is part of a semiconductor device according to the second embodiment. [Figure 12] This is a schematic diagram illustrating a part of a semiconductor device according to the second embodiment. [Figure 13] This is a schematic diagram illustrating a part of a semiconductor device according to the second embodiment. [Figure 14] This is a schematic side view illustrating a semiconductor device according to a modified example of the second embodiment. [Figure 15] This is a schematic perspective view illustrating a part of a semiconductor device according to a modified example of the second embodiment. [Figure 16] This is a schematic side view illustrating a semiconductor device according to another modification of the second embodiment. [Figure 17] This is a schematic perspective view illustrating a part of a semiconductor device according to another modification of the second embodiment. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Note that the carrier concentration is considered to be the effective impurity concentration. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] (First Embodiment) Figure 1 is a schematic plan view illustrating a semiconductor device according to the first embodiment. Figure 2 is a schematic side view illustrating a semiconductor device according to the first embodiment. Figure 3 is a schematic cross-sectional view along the line III-III in Figure 1. As shown in FIGS. 1 to 3, the semiconductor device 1 according to the present embodiment includes a semiconductor portion 50, a first electrode 10, a second electrode 20, a first control electrode 71, a second control electrode 72, a conductive member 30, and a bonding member 80. The first electrode 10 is electrically connected to the first source pad S1. The second electrode 20 is electrically connected to the second source pad S2. The first electrode 10 and the second electrode 20 each function as a source electrode. The first control electrode 71 is electrically connected to the first gate pad G1. The second control electrode 72 is connected to the second gate pad G2. The first control electrode 71 and the second control electrode 72 function as gate electrodes.

[0009] The semiconductor portion 50 is disposed on the conductive member 30. The bonding member 80 is disposed between the semiconductor portion 50 and the conductive member 30. The semiconductor portion 50 has a first surface 51 and a second surface 52. The second surface 52 is a surface located on the opposite side of the first surface 51.

[0010] Hereinafter, explanations may be given using a three-dimensional coordinate system of XYZ. The X-axis and the Y-axis are perpendicular to each other. The plane including the X-axis and the Y-axis is assumed to be parallel to the first surface 51 or the second surface 52. The Z-axis is perpendicular to the X-axis and the Y-axis. The direction from the second surface 52 toward the first surface 51 is defined as the positive direction of the Z-axis. The positive direction of the Z-axis may be referred to as "up" or "above", and the negative direction of the Z-axis may be referred to as "down" or "below", but these references do not indicate the direction of gravity. The cases of viewing from "above" and "below" may be referred to as a plan view. Also, the case of viewing from a direction perpendicular to the XY plane may be referred to as a side view.

[0011] A conductive layer 56 is provided on the second surface 52 of the semiconductor portion 50. The conductive layer 56 is in ohmic connection with the semiconductor portion 5​​​The conductive layer 56 is electrically connected to the semiconductor substrate 53. As will be described later in relation to Figure 3, the semiconductor device 1 includes a first transistor Q1 and a second transistor Q2, and the first transistor Q1 and the second transistor Q2 are electrically connected by a common semiconductor substrate 53, conductive layer 56, bonding member 80 and conductive member 30. The first transistor Q1 and the second transistor Q2 have electrically isolated first electrodes 10 and second electrodes 20, and when the first transistor Q1 and the second transistor Q2 are turned on, conductivity occurs between the first electrode 10 and the second electrode 20 via the semiconductor substrate 53, conductive layer 56, bonding member 80 and conductive member 30. In other words, the first transistor Q1 and the second transistor Q2 constitute a bidirectional switch.

[0013] In the semiconductor section 50, the semiconductor substrate 53 corresponds to the common drain electrode of the first transistor Q1 and the second transistor Q2. Electrically, the semiconductor substrate 53, which is the common drain electrode of the first transistor Q1 and the second transistor Q2, is laminated on the conductive layer 56, the bonding member 80, and the conductive member 30.

[0014] The conductive member 30 is formed of a metal or the like with high conductivity. The conductive member 30 has a sufficiently long length in the Z-axis direction, i.e., a sufficient thickness. For example, the thickness of the conductive member 30 is about the same as to about seven times the thickness of the semiconductor part 50, and is about 0.05 mm to 0.3 mm. The conductivity of the conductive member 30 is sufficiently higher than that of the first semiconductor layer 54, the semiconductor substrate 53, the conductive layer 56, and the bonding member 80. By connecting the conductive member 30 in parallel to the common drain electrode of the first transistor Q1 and the second transistor Q2, the semiconductor device 1 functions as a bidirectional switch with low on-resistance.

[0015] The configuration of the conductive member 30 will now be described. As shown in Figure 1, the outer circumference of the conductive member 30 is a rectangle with four vertices (first vertices) 33a to 33d in a plan view. The outer circumference of the conductive member 30 is a rectangle formed by sides L33ab to L33da in a plan view. Side L33ab is a straight line between vertices 33a and 33b. Side L33bc is a straight line between vertices 33b and 33c. Side L33cd is a straight line between vertices 33c and 33d. Side L33da is a straight line between vertices 33d and 33a. The conductive member 30 is a rectangular plate-like member in this manner.

[0016] The conductive member 30 has a thin-walled portion 32 and a mounting portion 34. The thin-walled portion 32 is provided continuously with the mounting portion 34 at the outer edge of the conductive member 30 and surrounds the mounting portion 34. In plan view, the boundary between the thin-walled portion 32 and the mounting portion 34 is a rectangle having four vertices 35a to 35d. The boundary between the thin-walled portion 32 and the mounting portion 34 is sometimes called the outer perimeter of the mounting portion 34. The outer perimeter of the mounting portion 34 is a rectangle formed by sides L35ab to L35da. Side L35ab is a straight line between vertices 35a and 35b. Side L35bc is a straight line between vertices 35b and 35c. Side L35cd is a straight line between vertices 35c and 35d. Side L35da is a straight line between vertices 35d and 35a. The mounting portion 34 is a rectangular area enclosed by four vertices 35a to 35d and four edges L35ab to L35da. The thin-walled portion 32 is the area between the rectangular area enclosed by four vertices 33a to 33d and four edges L33ab to L33da and the outer periphery of the mounting portion 34.

[0017] As shown in Figure 2, the conductive member 30 has a third surface 31a, a fourth surface 31b, and a fifth surface 31c. The third surface 31a of the conductive member 30 is a substantially flat surface over its entire surface and is positioned opposite the second surface 52 of the semiconductor portion 50. The third surface 31a is the surface of the mounting portion 34. The fourth surface 31b is the surface located on the opposite side of the third surface 31a. The fourth surface 31b is a substantially flat surface over its entire surface. The fifth surface 31c is the surface of the thin-walled portion 32. The fifth surface 31c is located on the same side as the third surface 31a and on the opposite side of the fourth surface 31b. Note that in Figure 2, the notation for the conductive layer 56 is omitted to avoid illustration complexity. Similarly, the notation for the conductive layer 56 is omitted in Figures 4 to 7, 12 and 13.

[0018] The thickness of the mounting portion 34 is approximately constant throughout the entire mounting portion 34. The thickness of the thin-walled portion 32 is thinner than the thickness of the mounting portion 34. The thickness of the thin-walled portion 32 is the length from the third surface 31a to the fifth surface 31c along the Z-axis. The thickness of the mounting portion 34 is the length from the third surface 31a to the fourth surface 31b along the Z-axis. In the specific example in Figure 2, the thin-walled portion 32 has the same thickness as the mounting portion 34 at the boundary between the thin-walled portion 32 and the mounting portion 34, and gradually becomes thinner from the boundary toward the outer edge of the thin-walled portion 32. The fifth surface 31c, which is a surface of the thin-walled portion 32, is a curved surface, and in a side view, the fifth surface 31c is part of a circular or elliptical arc with its center on the fifth surface 31c side.

[0019] The shape of the thin-walled section is not limited to this example and may take other forms. For example, the thickness of the thin-walled section may be reduced linearly from the boundary between the thin-walled section and the mounting section. Alternatively, the thickness of the thin-walled section may be reduced in a stepped manner from the boundary between the thin-walled section and the mounting section.

[0020] The semiconductor portion 50 is a rectangular plate-shaped member having vertices (second vertices) 53a to 53d in a plan view. The outer perimeter of the semiconductor portion 50 in a plan view is a rectangle formed by edges L53ab to L53da. Edge L53ab is a straight line between vertices 53a and 53b. Edge L53bc is a straight line between vertices 53b and 53c. Edge L53cd is a straight line between vertices 53c and 53d. Edge L53da is a straight line between vertices 53d and 53a.

[0021] In a plan view, the semiconductor portion 50 is positioned such that its outer periphery is located between the outer periphery of the mounting portion 34 and the outer periphery of the thin-walled portion 32. That is, the vertices 53a to 53d of the semiconductor portion 50 are located between the vertices 35a to 35d of the mounting portion 34 and the vertices 33a to 33d of the thin-walled portion 32, respectively. The edges L53ab to L53da of the semiconductor portion 50 are located between the edges L35ab to L35da of the mounting portion 34 and the edges L33ab to L33da of the thin-walled portion 32, respectively. From the viewpoint of equalizing the stress generated when thermal stress is applied to the semiconductor device 1, preferably, the edges L53ab to L53da of the semiconductor portion 50 are positioned approximately parallel to the edges L33a to L33d of the thin-walled portion 32, respectively, and approximately parallel to the edges L35a to L35d of the mounting portion 34, respectively.

[0022] A bonding member 80 is provided between the second surface 52 of the semiconductor part 50 and the third surface 31a of the conductive member 30. The bonding member 80 is also provided between the second surface 52 of the semiconductor part 50 and the fifth surface 31c of the conductive member 30.

[0023] In the conductive member 30, the length in the Z-axis direction from the third surface 31a to the fifth surface 31c is shorter than the length in the Z-axis direction from the third surface 31a to the fourth surface 31b. Therefore, the thickness of the joining member 80 between the second surface 52 and the fifth surface 31c is greater than the thickness of the joining member 80 between the second surface 52 and the third surface 31a.

[0024] The bonding member 80 is, for example, solder, conductive adhesive, or conductive paste. The conductive member 30 is formed of, for example, an alloy containing Cu or Al. The semiconductor part 50 is formed of Si or the like. The linear expansion coefficients of the bonding member 80 and the conductive member 30 are greater than those of the semiconductor part 50. Therefore, when thermal stress is applied to the semiconductor device 1 containing these, stress concentrates in the semiconductor part 50 due to the difference in linear expansion of the semiconductor part 50, bonding member 80, and conductive member 30. The stress due to thermal stress may concentrate at the outer edge of the semiconductor part 50, and may concentrate more at the corners including the vertices 53a to 53d of the semiconductor part 50.

[0025] The elastic modulus of the bonding member 80 is smaller than that of the conductive member 30 and the semiconductor part 50. In other words, the bonding member 80 is softer than the conductive member 30 and the semiconductor part 50. Therefore, even if thermal stress is applied to the semiconductor device 1 and the conductive member 30 deforms according to its coefficient of thermal expansion, the bonding member 80 can mitigate that deformation and alleviate the concentration of stress on the semiconductor part 50. In the semiconductor device 1 according to this embodiment, a thin-walled portion 32 of the conductive member 30 is formed near the outer edge of the semiconductor part 50 such that the thickness of the bonding member 80 is increased, so that the concentration of stress due to thermal stress can be mitigated throughout the semiconductor part 50.

[0026] On the other hand, the thickness of the bonding member 80 is sufficiently thin between the mounting portion 34 of the conductive member 30 and the semiconductor portion 50. When the conductivity of the bonding member 80 is lower than that of the conductive member 30, the thickness of the bonding member 80 in the mounting portion 34 can be reduced to lower the electrical resistance between the semiconductor portion 50 and the conductive member 30, making it possible to lower the on-resistance of the semiconductor device 1. In addition, because the bonding member 80 is sufficiently thin between the mounting portion 34 and the semiconductor portion 50, thermal resistance is reduced, which suppresses heat generation in the semiconductor device 1 and suppresses the increase in on-resistance that occurs with rising temperature.

[0027] Figure 4 is a schematic side view illustrating a part of the semiconductor device according to this embodiment. Figures 5 and 6 are schematic side views illustrating a part of a comparative semiconductor device. Figures 4 to 6 show the relationship between the depth of the thin-walled portion 32 of the conductive member 30 and the thickness of the bonding member 80 in the semiconductor device 1 according to this embodiment. In Figures 4 to 6, H1 to H3 represent the depth of the thin-walled portion 32. The depth of the thin-walled portion 32 is the length obtained by subtracting the length from the edge portion L33da to the fourth face 31b from the length from the third face 31a to the fourth face 31b, in the direction parallel to the Z axis. Figure 4 shows an example where the depth H1 of the thin-walled section 32 is appropriate. Figure 5 shows an example where the depth H2 of the thin-walled section 32 is too shallow. Figure 6 shows an example where the depth H3 of the thin-walled section 32 is too deep. As shown in Figures 4 to 6, the relationship between depths H1 to H3 is H2

[0028] As shown in Figure 4, when the depth H1 of the thin-walled portion 32 is appropriate, the thickness of the joining member 80 introduced into the thin-walled portion 32 is approximately equal to the depth H1. Furthermore, the joining member 80 does not extend beyond the position of the edge portion L53da of the semiconductor portion 50.

[0029] As shown in Figure 5, if the depth H2 of the thin-walled portion 32 is too shallow, the thickness of the bonding member 80 introduced into the thin-walled portion 32 is approximately equal to the depth H2. On the other hand, the bonding member 80 may extend beyond the edge L53da of the semiconductor portion 50 and reach the side surface of the semiconductor portion 50. If the depth H2 is even shallower, the bonding member 80 introduced into the thin-walled portion 32 may crawl up from the side surface of the semiconductor portion 50 to the upper surface. Electrodes with different potentials may be formed on the side surface or upper surface of the semiconductor portion 50, and the protruding bonding member 80 may cause a short-circuit failure of the semiconductor device 1.

[0030] ​As shown in Figure 6, if the depth H3 of the thin-walled portion 32 is too deep, the thickness of the bonding member 80 introduced into the thin-walled portion 32 will be less than the depth H3. Therefore, the mitigating effect of the bonding member 80 against stress concentration due to expansion and contraction of the conductive member 30 due to thermal stress is reduced. If the bonding member 80 is solder or the like, a smaller contact area between the bonding member 80 and the fifth surface 31c results in a smaller wetted area, which may cause the bonding member 80 to flow to the side of the semiconductor portion 50, potentially leading to a short-circuit failure of the semiconductor device 1, similar to the example shown in Figure 5.

[0031] As described above, the thin-walled portion 32 may have an appropriate depth. Figure 7 is a schematic side view illustrating a part of the semiconductor device according to the first embodiment. Figure 7 shows an example of setting an appropriate depth H1 for the thin-walled portion 32. In the semiconductor device 1 according to this embodiment, it is preferable that the following relationship between the shape of the conductive member 30 and the shape of the semiconductor portion 50 is satisfied in order to set an appropriate depth H1 for the thin-walled portion 32. That is, the relationship between the shape of the conductive member 30 and the shape of the semiconductor portion 50 is that the thickness of the conductive member 30 is about 1 to 7 times the thickness of the semiconductor portion 50, and the thickness of the conductive member 30 is about 0.05 mm to 0.30 mm. Also, the position of the edge portion L53da of the semiconductor portion 50 is about the same as or about 0.1 mm inward from the position of the edge portion L33da of the conductive member 30.

[0032] Length d is the length from the position on the X-axis of edge L35da to the position on the X-axis of edge L33da, and is the length of the thin-walled portion 32 in the X-axis direction. Length d / 2 is half the length from the position on the X-axis of edge L35da to the position on the X-axis of edge L33da. In this example, the thickness of the thin-walled portion 32 decreases towards the outer edge, so the depth H1' at d / 2 is thinner than the depth H1 at d.

[0033] θ represents the angle with respect to the second surface 52 at the boundary between the mounting portion 34 and the thin portion 32, that is, at the side portion L35da. When the joining member 80 is solder or the like, an angle at which the joining member 80 is sufficiently wetted on the fifth surface 31c is set so that a joining member 80 with a sufficient volume is introduced into the thin portion 32. Let θL be the wetting contact angle of the joining member 80. Then, the angle θ preferably satisfies the following formula (1).

[0034] θ = θL ± 10% (1)

[0035] When the joining member 80 is solder or the like, after satisfying formula (1), H1 preferably satisfies the following formula (2).

[0036] H1 = 5h ± 3h (2) Here, h is the thickness of the joining member 80 in the mounting portion 34. The thickness of the joining member 80 is the length from the second surface 52 to the third surface 31a along the Z-axis direction. As in this example, when H1’ < H1, it is preferable that H1’ satisfies formula (2) when H1 in formula (2) is replaced with H1’.

[0037] It is preferable to satisfy at least one of formula (1) and formula (2), and more preferably to satisfy both. By satisfying the relationship between formula (1) and formula (2), a joining member 80 with an appropriate thickness can be provided in the thin portion 32.

[0038] In FIGS. 4 to 7, an example when viewed from the direction of the side portion L33da was described. Similarly, when viewed from other side portions, a joining member 80 with an appropriate thickness can be provided in the thin portion 32 by satisfying the relationship between formula (1) and formula (2).

[0039] Next, the configurations of the first transistor Q1 and the second transistor Q2 will be described. Returning to FIG. 3, the description will be continued. As shown in Figure 3, the semiconductor section 50 includes a semiconductor substrate 53, a first semiconductor layer 54 provided on the semiconductor substrate 53, a second semiconductor layer 13 and a third semiconductor layer 14 provided within the first semiconductor layer 54, a fourth semiconductor layer 15 provided within the second semiconductor layer 13, and a fifth semiconductor layer 16 provided within the third semiconductor layer 14.

[0040] The semiconductor substrate 53 is, for example, an n-type silicon substrate. The first semiconductor layer 54 is, for example, an n-type silicon layer. The n-type impurity concentration of the first semiconductor layer 54 is lower than the n-type impurity concentration of the semiconductor substrate 53. The first semiconductor layer 54 is, for example, epitaxially grown on the semiconductor substrate 53.

[0041] The second semiconductor layer 13 and the third semiconductor layer 14 are, for example, p-type silicon layers. The first semiconductor layer 54 is in contact with the bottom surface and side surface of the second semiconductor layer 13, and the bottom surface and side surface of the third semiconductor layer 14.

[0042] The fourth semiconductor layer 15 and the fifth semiconductor layer 16 are, for example, n-type silicon layers. The n-type impurity concentration in the fourth semiconductor layer 15 and the fifth semiconductor layer 16 is higher than the n-type impurity concentration in the first semiconductor layer 54. The second semiconductor layer 13 is in contact with the bottom and side surfaces of the fourth semiconductor layer 15. The third semiconductor layer 14 is in contact with the bottom and side surfaces of the fifth semiconductor layer 16.

[0043] The surfaces of the first semiconductor layer 54, the second semiconductor layer 13, the third semiconductor layer 14, the fourth semiconductor layer 15, and the fifth semiconductor layer 16 constitute the first surface 51 of the semiconductor portion 50. The back surface of the semiconductor substrate 53 constitutes the second surface 52 of the semiconductor portion 50.

[0044] The semiconductor portion 50 has a first region 61 and a second region 62 between the first surface 51 and the second surface 52. The first region 61 and the second region 62 are aligned along the X-axis direction of the semiconductor portion 50.

[0045] The semiconductor substrate 53 and the first semiconductor layer 54 are provided in common to the first region 61 and the second region 62. The second semiconductor layer 13 and the fourth semiconductor layer 15 are provided in the first region 61. The third semiconductor layer 14 and the fifth semiconductor layer 16 are provided in the second region 62.

[0046] The first region 61 is provided with a plurality of first control electrodes 71, which are gate electrodes. The first control electrodes 71 are, for example, trench gates and extend along the Z-axis within the first region 61. The top, side, and bottom surfaces of the first control electrodes 71 are covered with an insulating film 73. The side surfaces of the first control electrodes 71 face the second semiconductor layer 13 via the insulating film 73.

[0047] The second region 62 is provided with a plurality of second control electrodes 72, which are gate electrodes. The second control electrodes 72 are, for example, trench gates and extend within the second region 62 along the Z-axis direction. The top, side, and bottom surfaces of the second control electrodes 72 are covered with an insulating film 74. The side surfaces of the second control electrodes 72 face the third semiconductor layer 14 via the insulating film 74.

[0048] For example, multiple first control electrodes 71 are arranged spaced apart in the X-axis direction, and each of the multiple first control electrodes 71 extends in the Y-axis direction. Similarly, multiple second control electrodes 72 are arranged spaced apart in the X-axis direction, and each of the multiple second control electrodes 72 extends in the Y-axis direction.

[0049] A first electrode 10, which is a source electrode, is provided on the first surface 51 of the first region 61 of the semiconductor portion 50. The first electrode 10 has a first metal portion 11 that is in contact with the fourth semiconductor layer 15 on the first surface 51 of the semiconductor portion 50, and a first source pad S1 provided on the first metal portion 11.

[0050] The area of ​​the first metal part 11 is larger than the area of ​​the first source pad S1. The area of ​​the first metal part 11 represents the area where the first metal part 11 is in contact with the first surface 51 of the semiconductor part 50, or the surface area of ​​the first metal part 11. The area of ​​the first source pad S1 represents the surface area of ​​the first source pad S1. In other words, at least a portion of the area of ​​the first metal part 11 in the XY plane is larger than at least a portion of the area of ​​the first source pad S1 in the XY plane.

[0051] The first metal portion 11 mainly contains, for example, aluminum and functions as a contact layer that reduces contact resistance with the semiconductor portion 50. The outermost surface of the first source pad S1 contains, for example, a gold film with excellent solder wettability. Between the gold film and the first metal portion 11, a nickel film is formed to enhance the adhesion between the two.

[0052] A first wiring layer 77 is provided on the first surface 51 in the first region 61 of the semiconductor portion 50. The first wiring layer 77 is electrically connected to the first control electrode 71. An insulating film 75 is provided between the first wiring layer 77 and the first electrode 10, and between the first wiring layer 77 and the semiconductor portion 50.

[0053] A second electrode 20, which is a source electrode, is provided on the first surface 51 in the second region 62 of the semiconductor portion 50. The second electrode 20 has a third metal portion 21 that is in contact with the fifth semiconductor layer 16 on the first surface 51 of the semiconductor portion 50, and a second source pad S2 provided on the third metal portion 21.

[0054] The area of ​​the third metal portion 21 is larger than the area of ​​the second source pad S2. The area of ​​the third metal portion 21 represents the area where the third metal portion 21 is in contact with the first surface 51 of the semiconductor portion 50, or the surface area of ​​the third metal portion 21 (the top surface in Figure 3). The area of ​​the second source pad S2 represents the surface area of ​​the second source pad S2 (the top surface in Figure 3). In other words, at least a portion of the area of ​​the third metal portion 21 in the XY plane is larger than at least a portion of the area of ​​the second source pad S2 in the XY plane.

[0055] The third metal portion 21 mainly contains, for example, aluminum and functions as a contact layer that reduces contact resistance with the semiconductor portion 50. The outermost surface of the second source pad S2 contains, for example, a gold film with excellent solder wettability. A nickel film is formed between the gold film and the third metal portion 21 to enhance the adhesion between the two.

[0056] A second wiring layer 78 is provided on the first surface 51 in the second region 62 of the semiconductor portion 50. The second wiring layer 78 is electrically connected to the second control electrode 72. An insulating film 76 is provided between the second wiring layer 78 and the second electrode 20, and between the second wiring layer 78 and the semiconductor portion 50.

[0057] An insulating film 80 is provided on the first surface 51 of the semiconductor portion 50. The insulating film 80 covers the first metal portion 11 of the first electrode 10 and the third metal portion 21 of the second electrode 20. The insulating film 80 also covers the side surface of the first source pad S1 of the first electrode 10 and the side surface of the second source pad S2 of the second electrode 20. The surface of the first source pad S1 of the first electrode 10 and the surface of the second source pad S2 of the second electrode 20 are exposed from the insulating film 80.

[0058] A conductive layer 56 is provided on the second surface 52 of the semiconductor portion 50. The conductive layer 56 is provided in common to the first region 61 and the second region 62 of the semiconductor portion 50, and electrically connects the first region 61 and the second region 62. The conductive layer 56 contains a metal with a lower resistivity than the semiconductor substrate 53 and contains a metal that is ohmic connected to the semiconductor substrate 53 which contains Si. The conductive layer 56 contains Ag, Ti, Ni, etc.

[0059] The semiconductor device 1 has a first transistor Q1 and a second transistor Q2 that share a semiconductor substrate 53, as described above. The first transistor Q1 and the second transistor Q2 are adjacent to each other in the X direction. The first transistor Q1 and the second transistor Q2 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors).

[0060] The first electrode 10 functions as the source electrode of the first transistor Q1, and the fourth semiconductor layer 15 functions as a source layer electrically connected to the first electrode 10. When a predetermined voltage is applied to the first control electrode 71, a channel is formed in the portion of the second semiconductor layer 13 facing the first control electrode 71.

[0061] The second electrode 20 functions as the source electrode of the second transistor Q2, and the fifth semiconductor layer 16 functions as a source layer electrically connected to the second electrode 20. When a predetermined voltage is applied to the second control electrode 72, a channel is formed in the portion of the third semiconductor layer 14 facing the second control electrode 72.

[0062] The first electrode 10 and the second electrode 20 are positioned apart from each other and are electrically isolated.

[0063] For example, two first source pads S1 are provided on the first metal portion 11 of the first electrode 10. For example, two second source pads S2 are provided on the third metal portion 21 of the second electrode 20.

[0064] Furthermore, on the first surface 51 of the semiconductor portion 50, there is a first gate pad G1 electrically connected to a first control electrode 71 via a first wiring layer 77, and a second gate pad G2 electrically connected to a second control electrode 72 via a second wiring layer 78. The periphery of the first gate pad G1 and the periphery of the second gate pad G2 are covered with an insulating film 79, and the surfaces of the first gate pad G1 and the second gate pad G2 are exposed from the insulating film 79.

[0065] The semiconductor device 1 of this embodiment is incorporated into a charge / discharge protection circuit for, for example, a Li-ion battery and used as a bidirectional switch. In the semiconductor device 1 of this embodiment, a conductive member 30 is placed facing the second surface 52 of the semiconductor part 50 via a bonding member 80, and the semiconductor part 50 and the conductive member 30 are electrically connected. The conductive member 30 is configured to have sufficiently high conductivity, so that the voltage drop when current flows bidirectionally through the series circuit of the first transistor Q1 and the second transistor Q2 can be reduced.

[0066] In the above description, the first transistor Q1 and the second transistor Q2 are assumed to have a trench gate structure, but they are not limited to this and can have any other suitable transistor structure. For example, the first transistor Q1 and the second transistor Q2 may have a planar gate structure.

[0067] The effects of the semiconductor device 1 according to this embodiment will be described. The semiconductor device 1 according to this embodiment includes a semiconductor section 50, a first electrode 10, a second electrode 20, a first control electrode 71, a second control electrode 72, a conductive member 30, and a bonding member 80. In the semiconductor section 50, the semiconductor substrate 53 and the first semiconductor layer 54 function as common drain electrodes for the two transistors Q1 and Q2. In other words, the drain electrodes of transistors Q1 and Q2 are electrically connected by sharing the semiconductor substrate 53 and the first semiconductor layer 54. On the second surface 52, which is the back surface of the semiconductor section 50, a conductive member 30 is arranged via a conductive bonding member 80, and the conductive member 30 is electrically connected to the semiconductor substrate 53 of the semiconductor section 50. The conductivity of the conductive member 30 is sufficiently higher than that of the semiconductor substrate 53 and the first semiconductor layer 54. Therefore, the drain electrodes of the two transistors Q1 and Q2 are electrically connected with low resistance, and the semiconductor device 1 can function as a low on-resistance bidirectional switch.

[0068] The conductive member 30 has a mounting portion 34 and a thin-walled portion 32, the thin-walled portion 32 being provided around the mounting portion 34. The thickness of the thin-walled portion 32 is thinner than the thickness of the mounting portion 34. In a plan view, the outer periphery of the semiconductor portion 50 is the region of the thin-walled portion 32. A bonding member 80 is provided between the mounting portion 34 and the semiconductor portion 50, and the bonding member 80 is also provided between the thin-walled portion 32 and the semiconductor portion 50. Since the thickness of the thin-walled portion 32 is thinner than the thickness of the mounting portion 34, the thickness of the bonding member 80 in the thin-walled portion 32 is thicker than the thickness of the bonding member 80 in the mounting portion 34. The elastic modulus of the bonding member 80 is lower than that of the semiconductor portion 50 and the conductive member 30. Therefore, when thermal stress is applied to the semiconductor device 1, the conductive member 30 expands and contracts more than the semiconductor portion 50. The contraction of the conductive member 30 is mitigated by the bonding member 80. The stress caused by the expansion and contraction of the conductive member 30 is concentrated near the outer edge of the semiconductor portion, so the joint member 80 introduced into the thin-walled portion 32 alleviates the stress concentration.

[0069] The thickness of the bonding member 80 in the mounting section 34 is thinner than the thickness of the bonding member 80 in the thin-walled section 32. Even if the conductivity of the bonding member 80 is lower than that of the conductive member 30, the electrical resistance between the semiconductor section 50 and the conductive member 30 can be kept sufficiently low. Furthermore, even if the thermal conductivity of the bonding member 80 is lower than that of the conductive member 30, the thermal resistance between the semiconductor section 50 and the conductive member 30 can be kept sufficiently low.

[0070] A semiconductor device is known in which two transistors are connected in series using a semiconductor substrate as a common drain electrode (for example, Patent Document 1). The on-resistance of the semiconductor device can be reduced by connecting a metal plate with high conductivity to the semiconductor substrate in order to reduce the electrical resistance of the drain electrode.

[0071] When semiconductor devices are mounted on circuit boards and other components of electronic devices, they may pass through a solder bath. Solder baths can reach temperatures exceeding 200°C, subjecting semiconductor devices to significant thermal stress. Furthermore, semiconductor devices are required to pass reliability tests, such as temperature cycling tests within their storage temperature range and temperature shock tests within a specified temperature range.

[0072] The conductive member 30 can be made of a material having a higher conductivity than the semiconductor portion 50 and the bonding member 80, and making the conductive member 30 sufficiently thick is effective in achieving a sufficiently low resistance value. On the other hand, increasing the thickness of the conductive member 30 increases the volume of the conductive member 30, so the volume that increases due to the coefficient of thermal expansion also increases, and the stress generated accordingly also increases. In the semiconductor device 1 according to this embodiment, by providing a thin-walled portion 32 on the outer edge of the conductive member 30 and increasing the volume of the bonding member 80 in the thin-walled portion 32, the deformation of the semiconductor portion 50 due to the stress generated by the increase in the volume of the conductive member 30 can be mitigated. Therefore, even under thermal stress conditions, the semiconductor device 1 according to this embodiment can mitigate the concentration of stress on the semiconductor portion 50, making it possible to achieve both low on-resistance and a heat-resistant environment.

[0073] (Variation 1) Figure 8 is a schematic plan view illustrating a semiconductor device according to a modified example of the first embodiment. As shown in Figure 8, the semiconductor device 101a according to this modified example differs from the semiconductor device 1 shown in Figure 1 in the configuration of the conductive member 130a. The other configurations are the same as those of semiconductor device 1, and the same reference numerals are used for the same components, and detailed explanations are omitted.

[0074] The conductive member 130a of the semiconductor device 101a has a thin-walled portion 132 and a mounting portion 134. The thin-walled portion 132 is provided on the outer edge of the conductive member 130a and surrounds the mounting portion 134. In plan view, the boundary between the thin-walled portion 132 and the mounting portion 134 is a rectangle having eight vertices 135a to 135h. The boundary between the thin-walled portion 132 and the mounting portion 134 is an octagon formed by sides L135a to L135h. Sides L135a to L135h are straight lines between two adjacent vertices. Sides L135a, L135c, L135e, and L135g have shorter lengths than the other sides.

[0075] The mounting portion 34 is an octagonal section enclosed by eight vertices 135a to 135h and eight edges L135a to L135h. The thin-walled portion 132 is the section between the rectangular section enclosed by four vertices 33a to 33d and four edges L33ab to 33da and the mounting portion 134.

[0076] Although not shown in the figures, the shape of the thin-walled portion 132 in a side view is, for example, similar to the semiconductor device 1 shown in Figures 1 and 2, such that it gradually thins out from the boundary between the thin-walled portion 132 and the mounting portion 134 towards the outer edge.

[0077] In a plan view, the semiconductor portion 50 is positioned such that its outer periphery is located between the outer periphery of the mounting portion 134 and the outer periphery of the thin-walled portion 132. In the semiconductor device 101a according to this modified example, since the outer periphery of the mounting portion 134 is octagonal, the vertices of the semiconductor portion 50 are positioned further away from the edges of the mounting portion 134 than in the case of the semiconductor device 1 shown in Figure 1. For example, at vertex 53a, the shortest distance between vertex 53a and edge L135a is longer than the shortest distance between edge L33ab and edge L53ab. In other words, in the semiconductor device 101a according to this modification, the volume of the bonding member 80 can be made sufficiently larger at the corners including the vertices of the semiconductor portion 50 than at other outer edge portions of the semiconductor portion 50.

[0078] When stress simulations are performed using a model in which the semiconductor part and the conductive part are joined via a bonding member, stress is more concentrated at the corners including the vertices of the semiconductor part. Therefore, in the semiconductor device 101a according to this modified example, the volume of the bonding member 80 covering the corners including the vertices of the semiconductor part 50 is increased by increasing the region of the thin-walled part 132 that includes the vertices 33a to 33d of the thin-walled part 132. This makes it possible to more effectively mitigate the concentration of stress on the semiconductor part 50 when thermal stress is applied.

[0079] (Modification 2) Figure 9 is a schematic plan view illustrating a semiconductor device according to another modification of the first embodiment. As shown in Figure 9, the semiconductor device 101b according to this modified example differs from the semiconductor device 1 shown in Figure 1 in the configuration of the conductive member 130b. The other configurations are the same as those of semiconductor device 1, and the same reference numerals are used for the same components, and detailed explanations are omitted.

[0080] The conductive member 130b of the semiconductor device 101b has thin-walled portions 132a to 132d and a mounting portion 134a. The outer circumference of the thin-walled portion 132a is a right triangle containing vertices 33a, 135a1, and 135b1. The outer circumference of the thin-walled portion 132b is a right triangle containing vertices 33b, 135c1, and 135d1. The outer circumference of the thin-walled portion 132c is a right triangle containing vertices 33c, 135e1, and 135f1. The outer circumference of the thin-walled portion 132d is a right triangle containing vertices 33d, 135g1, and 135h1.

[0081] Although not shown in the figures, the side view shape of the thin-walled portions 132a to 132d is similar to that of the semiconductor device 1 shown in Figures 1 and 2, for example, in that the thin-walled portions 132a to 132d gradually become thinner from the boundary between them and the mounting portion 134 towards the outer edge.

[0082] In a plan view, the semiconductor portion 50 is positioned such that the outer periphery of the semiconductor portion is located inside the outer periphery of the conductive member 130b. In the semiconductor device 101b according to this modified example, the corners containing the vertices 53a to 53d of the semiconductor portion 50 are positioned within the thin-walled portions 132a to 132d, respectively. Specifically, the vertex 53a of the semiconductor portion 50 is positioned inside a right-angled triangle containing vertices 33a, 135a1, and 135b1. The vertex 53b of the semiconductor portion 50 is positioned inside a right-angled triangle containing vertices 33b, 135c1, and 135d1. The vertex 53c of the semiconductor portion 50 is positioned inside a right-angled triangle containing vertices 33c, 135e1, and 135f1. The vertex 53d of the semiconductor portion 50 is positioned inside a right-angled triangle containing vertices 33d, 135g1, and 135h1.

[0083] As explained in relation to Figure 6, when stress simulations are performed using a model in which the semiconductor part and the conductive member are joined, stress is more concentrated at the corners, including the vertices of the semiconductor part. Depending on the thickness and shape of the semiconductor part, the material of the conductive member, etc., there may be cases where stress is hardly concentrated at the edges of the semiconductor part 50, but concentrated mainly at the corners of the semiconductor part 50. In such cases, the concentration of stress at the corners of the semiconductor part 50 can be alleviated by applying the conductive member 130b of this modified example. In this modified example, since thin-walled portions 132a to 132d are formed only at the corners of the conductive member 130b, there is an advantage in that the molding process of the conductive member 130b is made easier.

[0084] Furthermore, depending on the thickness and shape of the semiconductor portion, the material of the conductive member, etc., stress may not necessarily concentrate at all four corners of the semiconductor portion 50. Also, due to misalignment that may occur when the semiconductor portion 50, the bonding member 80, and the conductive member 30 are joined together, stress may concentrate at some of the four corners of the semiconductor portion 50. For this reason, a thin-walled portion of the conductive member may be provided at the position corresponding to the corner where stress is concentrated, based on stress simulations or the like.

[0085] (Second embodiment) Figure 10 is a schematic plan view illustrating a semiconductor device according to the second embodiment. Figure 11 is a schematic perspective view illustrating a conductive member, which is part of a semiconductor device according to the second embodiment. As shown in Figure 10, the semiconductor device 201 according to this embodiment differs from the semiconductor device 1 shown in Figure 1 in the configuration of the conductive member 230. The other configurations are the same as those of semiconductor device 1, and the same reference numerals are used for the same components, and detailed explanations are omitted.

[0086] As shown in Figure 10, the semiconductor device 201 includes a conductive member 230 instead of the conductive member 30 shown in Figure 1. As shown in Figures 10 and 11, the conductive member 230 has thin-walled portions 132a to 132d, a mounting portion 234, and grooved portions 236a to 236d. The thin-walled portions 132a to 132d are the same as the thin-walled portions 132a to 132d of the modified example described in relation to Figure 9, and a detailed explanation is omitted.

[0087] In the conductive member 230, grooves 236a to 236d are provided in the mounting portion 234. The grooves 236a to 236d are provided on the side of the third surface 231a of the conductive member 230, so as to form recesses in the third surface 231a. The third surface 231a is the surface positioned opposite the second surface 52 of the semiconductor portion 50. Groove 236a is provided from the center of gravity C of the conductive member 230 toward the thin-walled portion 132a. Groove 236b is provided from the center of gravity C of the conductive member 230 toward the thin-walled portion 132b. Groove 236c is provided from the center of gravity C of the conductive member 230 toward the thin-walled portion 132c. Groove 236d is provided from the center of gravity C of the conductive member 230 toward the thin-walled portion 132d.

[0088] The width W1 of the grooves 236a to 236d is preferably narrower than the width W2 of the thin-walled sections 132a to 132d. The width W2 of the thin-walled section 132a is the length between the two vertices 135a1 and 135b1 adjacent to vertex 33a. The same applies to the other thin-walled sections 132b to 132d. By doing so, it is possible to smoothly introduce the joining member 80 into the thin-walled sections 132a to 132d, and a joining member 80 with sufficient volume can be formed in the thin-walled sections 132a to 132d.

[0089] Figures 12 and 13 are schematic diagrams illustrating a part of a semiconductor device according to the second embodiment. Figure 12 shows the relationship between the depth of the thin-walled portion 132a, the depth of the groove portion 236a, and the thickness of the semiconductor portion 50 of the conductive member 230. Length d1 is the shortest distance from the line segment connecting vertices 135a1 and 135b1 in Figure 11 to vertex 33a. Length d3 is the shortest distance from the line segment connecting vertices 135a1 and 135b1 to vertex 53a. Length d2 is the shortest distance from vertex 53a to vertex 33a. Therefore, d1 = d2 + d3. Thickness Tsi is the thickness of the semiconductor portion 50. Thickness Tm is the thickness of the conductive member 230. Td is the length along the Z-axis from the third surface 231a to the bottom 236aB of the groove 236a, and represents the depth of the groove 236a.

[0090] In the semiconductor device 201 according to this embodiment, in order to alleviate the stress concentration when thermal stress is applied at the corner portion of the semiconductor portion 50, including the vertex 53a of the semiconductor portion 50, it is preferable that the relationship between these shapes is within an appropriate range. Specifically, the relationship between these shapes is the relationship between the width W1 of the groove portion 236a and the width W2 of the thin-walled portion 132a. This relationship is shown in Figure 10. Another relationship between these shapes is specifically the position of the vertex 53a of the semiconductor portion 50 in the thin-walled portion 132a. This is shown as the relationship between d2 and d3 in Figure 12. Furthermore, another relationship between these shapes is the relationship between the thickness Tm of the conductive member 230 and the depth Td of the groove portion 236a. Regarding these relationships, it is preferable that the following relationships are satisfied, as in the first embodiment. In other words, the thickness Tm of the conductive member 230 is approximately 1 to 7 times the thickness Tsi of the semiconductor part 50, the thickness Tm of the conductive member 230 is approximately 0.05 mm to 0.30 mm, and d2 is approximately 0 mm to 0.1 mm.

[0091] The first condition for relieving stress concentration is given by the following equation (3). W1 ≤ W2 (3) By making the width W1 of the groove 236a narrower than the width W2 of the thin-walled portion 132a, it becomes possible to form a joint member 80 with sufficient volume in the thin-walled portion 132a.

[0092] The second condition for relieving stress concentration is given by equation (4) below. d2 <d3 (4) By satisfying equation (4), when stress concentrates at the corners including the vertices of the semiconductor portion 50, the expansion and contraction of the conductive member 230 due to thermal stress can be mitigated by the joining member 80 having sufficient volume.

[0093] The third condition for relieving stress concentration is given by the following equation (5). Td = (1 / 10) × Tm ~ (1 / 1.3) × Tm (5) When stress concentrates near the groove 236a, the sufficient depth of the groove 236a allows the expansion and contraction of the conductive member 230 due to thermal stress to be mitigated by the joining member 80 of sufficient volume. Furthermore, to prevent the thickness of the conductive member 230 in the groove 236a from becoming too thin, taking into account variations during the manufacturing of the conductive member 230, an upper limit is set in equation (5).

[0094] It is preferable that all the conditions in equations (3) to (5) be satisfied, but some of the conditions may be satisfied depending on the thickness and shape of the semiconductor part, the material of the conductive member, etc.

[0095] Figure 13 shows the relationship between the thickness Tsi of the semiconductor part 50, the thickness Tm' of the conductive member 230, and the depth Td' of the groove 236a, with the depth of the groove 236a being based on the second surface 52 of the semiconductor part 50. In other words, as shown in Figure 13, the thickness Tm' of the conductive member 230 and the depth Td' of the groove 236a are shown based on the thickness of the conductive member 230, including the bonding member 80 between the second surface 52 and the third surface 231a.

[0096] If the thermal conductivity of the joining member 80 is lower than that of the conductive member 230, it is preferable that the thickness of the joining member 80 between the second surface 52 and the third surface 231a be thinner.

[0097] It is preferable that all the conditions in equations (3) to (5) be satisfied, but some of the conditions may be satisfied depending on the thickness and shape of the semiconductor part, the material of the conductive material, etc. For example, stress simulations may be performed for each product to determine where stress is concentrated, and then the conditions may be set to satisfy appropriate values.

[0098] The effects of the semiconductor device 201 according to this embodiment will be described. The semiconductor device 201 according to this embodiment provides the same effects as the semiconductor device 1 according to the first embodiment. In addition, it provides the following effects. The semiconductor device 201 according to this embodiment includes a conductive member 230. The conductive member 230 has thin-walled portions 132a to 132d, a mounting portion 134, and groove portions 236a to 236d. The groove portions 236a to 236d are provided from the mounting portion 134 toward the thin-walled portions 132a to 132d, respectively. By providing the groove portions 236a to 236d, the bonding member 80 can be sufficiently introduced into the thin-walled portions 132a to 132d.

[0099] With respect to the grooves 236a to 236d, by appropriately satisfying equations (3) to (5) or equations (3) and (4), it becomes possible to form a joining member 80 with sufficient volume to the thin-walled portions 132a to 132d, and by arranging the grooves in areas where stress is concentrated, it becomes possible to effectively alleviate stress concentration.

[0100] (Variation 1) Figure 14 is a schematic side view illustrating a semiconductor device according to a modified example of the second embodiment. Figure 15 is a schematic perspective view illustrating a part of a semiconductor device according to a modified example of the second embodiment. As shown in Figure 14, the semiconductor device 201a according to this modified example differs from the semiconductor device 201 shown in Figure 10 in the configuration of the conductive member 230a. The other configurations are the same as those of semiconductor device 201, and the same reference numerals are used for the same components, and detailed explanations are omitted.

[0101] As shown in Figure 14, the semiconductor device 201a includes a conductive member 230a instead of the conductive member 230 shown in Figure 10. As shown in Figures 14 and 15, the conductive member 230a has thin-walled portions 132a to 132d, a mounting portion 234, grooves 236a to 236d, and a recess 237. The thin-walled portions 132a to 132d, the mounting portion 234, and the grooves 236a to 236d are the same as in the second embodiment described in relation to Figures 10 and 11, and a detailed description is omitted.

[0102] In the conductive member 230a, a recess 237 is provided in the mounting portion 234. The recess 237 is located near the center of the mounting portion. The grooves 236a to 236d are provided extending from the recess 237 towards the thin-walled portions 132a to 132d, respectively.

[0103] The recess 237 is set to the same depth as the grooves 236a to 236d. Therefore, it is preferable that the depths of the recess 237 and the grooves 236a to 236d correspond to the depth Td or depth Td' described in relation to Figures 12 and 13, and that their values ​​are set to satisfy the conditions of equation (5).

[0104] In the process of joining the conductive member 230a to the semiconductor part 50, by providing a recess 237 in the mounting portion 234 of the conductive member 230b, it becomes possible to supply a bonding member 80 of sufficient volume between the conductive member 230a and the semiconductor part 50. By providing a bonding member 80 with sufficient volume in a wider area between the conductive member 230a and the semiconductor part 50, it is possible to achieve the effect of alleviating stress concentration over a wider area.

[0105] The shape of the recess 237 in plan view can be appropriately and arbitrarily set, not limited to the specific examples shown in Figures 14 and 15, depending on the thickness and shape of the semiconductor part, the material of the conductive member, etc.

[0106] (Modification 2) Figure 16 is a schematic side view illustrating a semiconductor device according to another modification of the second embodiment. Figure 17 is a schematic perspective view illustrating a part of a semiconductor device according to another modification of the second embodiment. As shown in Figure 16, the semiconductor device 201b according to this modified example differs from the semiconductor device 201 shown in Figure 10 in the configuration of the conductive member 230b. The other configurations are the same as those of semiconductor device 201, and the same reference numerals are used for the same components, and detailed explanations are omitted.

[0107] As shown in Figure 16, the semiconductor device 201b includes a conductive member 230b instead of the conductive member 230 shown in Figure 10. As shown in Figures 16 and 17, the conductive member 230b has thin-walled portions 132a to 132d, a mounting portion 234, and groove portions 236a1 to 236d1. The thin-walled portions 132a to 132d and the mounting portion 134 are the same as in the second embodiment described in relation to Figures 10 and 11, and a detailed description is omitted.

[0108] In this modified example, unlike the grooves 236a to 236d of the conductive member 230 described in relation to Figures 10 and 11, the grooves 236a1 to 236d1 of the conductive member 230b are not connected at the center of gravity C, which is the central part of the mounting portion 234, and are separated from each other. Each of the grooves 236a1 to 236d1 extends from a position away from the center of gravity C of the mounting portion 234 to the thin-walled portions 132a to 132d.

[0109] In this modified example, since no groove is formed near the center of the mounting portion 134, the thickness of the bonding member 80 between the conductive member 230b and the semiconductor portion 50 can be reduced. Since the bonding member 80 may have lower conductivity and thermal conductivity than the conductive member 230b, reducing the thickness of the bonding member 80 makes it possible to suppress an increase in resistance and heat generation. On the other hand, it becomes possible to form a bonding member 80 with sufficient volume in the thin-walled portions 132a to 132d via the grooves 236a1 to 236d1.

[0110] In this way, a semiconductor device with reduced on-resistance can be realized.

[0111] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other.

[0112] The embodiments include the following aspects:

[0113] (Note 1) A semiconductor portion having a first surface and a second surface located opposite the first surface, the semiconductor portion having a first region provided between the first surface and the second surface, a second region provided between the first surface and the second surface, and a semiconductor substrate connecting the first region and the second region, A first electrode provided on the first surface in the first region, In the second region, a second electrode is provided on the first surface, separated from the first electrode, A first control electrode is provided in the first region and controls the current flowing between the first electrode and the semiconductor substrate, A second control electrode is provided in the second region and controls the current flowing between the second electrode and the semiconductor substrate, A conductive member having a third surface positioned opposite the second surface and a fourth surface located on the opposite side of the third surface, and electrically connected to the semiconductor substrate via the third surface, A conductive bonding member provided between the semiconductor substrate and the conductive member, Equipped with, The conductive member is A mounting section provided between the third surface and the fourth surface, A thin-walled portion having a fifth surface located on the opposite side of the fourth surface, the thickness between the fifth surface and the fourth surface being thinner than the thickness of the mounting portion, Includes, The joining member is provided between the second surface and the third surface, and also between the second surface and the fifth surface, In plan view, The shape of the outer circumference of the conductive member and the shape of the outer circumference of the semiconductor part are both rectangular. The four first vertices of the conductive member are arranged to correspond to the four second vertices of the semiconductor portion. The outer circumference of the conductive member coincides with the outer circumference of the semiconductor portion, or is located outside the outer circumference of the semiconductor portion. A semiconductor device in which at least one of the four second vertices is located within the region of the thin-walled portion.

[0114] (Note 2) The semiconductor device according to Appendix 1, wherein, in a plan view, each of the four second vertices is positioned within the region of the thin-walled portion.

[0115] (Note 3) In a plan view, the semiconductor portion is arranged such that the outer periphery of the semiconductor portion surrounds the boundary between the thin-walled portion and the mounting portion, and is located outside the boundary, as described in Appendix 2.

[0116] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein, in a plan view, the thin portion has a triangular outer perimeter shape including at least one of the four first vertices.

[0117] (Note 5) A semiconductor portion having a first surface and a second surface located opposite the first surface, the semiconductor portion having a first region provided between the first surface and the second surface, a second region provided between the first surface and the second surface, and a semiconductor substrate connecting the first region and the second region, A first electrode provided on the first surface in the first region, In the second region, a second electrode is provided on the first surface, separated from the first electrode, A first control electrode is provided in the first region and controls the current flowing between the first electrode and the semiconductor substrate, A second control electrode is provided in the second region and controls the current flowing between the second electrode and the semiconductor substrate, It has a third surface positioned opposite the second surface, and a fourth surface located on the opposite side of the third surface, A conductive member electrically connected to the semiconductor substrate via the third surface, A conductive bonding member disposed between the semiconductor substrate and the conductive member, Equipped with, The conductive member is A mounting section provided between the third surface and the fourth surface, A plurality of thin-walled portions having a fifth surface located on the opposite side of the fourth surface, the thickness between the fifth surface and the fourth surface being thinner than the thickness of the mounting portion, Includes, The joining member is provided between the second surface and the third surface, and also between the second surface and the fifth surface, In plan view, The outer periphery of the conductive member and the semiconductor part are each rectangular. The four first vertices of the conductive member are arranged to correspond to the four second vertices of the semiconductor portion. The outer circumference of the conductive member coincides with the outer circumference of the semiconductor portion, or is located outside the outer circumference of the semiconductor portion. The four first vertices are semiconductor devices, each located within the region of the plurality of thin-walled portions.

[0118] (Note 6) The conductive member has a groove provided on the third surface, The groove portion is provided extending from the mounting portion to the thin-walled portion, The joining member is provided between the second surface and the third surface and is also provided within the groove portion, as described in Appendix 5.

[0119] (Note 7) The conductive member has a recess provided on the third surface, The groove is provided extending from the recess to the thin-walled portion, The joining member is provided between the second surface and the third surface, and is also provided within the recess, as described in Appendix 6 of the semiconductor device.

[0120] (Note 8) The conductive member has a plurality of grooves provided on the third surface, The plurality of grooves are separated from each other and are arranged toward the four first vertices, The joining member is provided between the second surface and the third surface, and is also provided within the plurality of grooves, as described in Appendix 5 of the semiconductor device. [Explanation of Symbols]

[0121] 1, 101a, 101b, 201, 201a, 201b... Semiconductor device, 10... First electrode, 20... Second electrode, 30, 130a, 130b, 230, 230a, 230b... Conductive member, 31a... Third surface, 31b... Fourth surface, 31c... Fifth surface, 32, 132, 132a~132d... Thin-walled section, 34, 134, 134a, 234... Mounting section, 33a~3 3d, 35a~35d, 53a~53d, 135a~135h, 135a1~135h1...vertices, 50...semiconductor part, 51...first surface, 52...second surface, 53...semiconductor substrate, 61...first region, 62...second region, 71...first control electrode, 72...second control electrode, 80...bonding member, 236a~236d, 236a1~236d1...grooves, 237...recesses

Claims

1. A semiconductor portion having a first surface and a second surface located opposite the first surface, the semiconductor portion having a first region provided between the first surface and the second surface, a second region provided between the first surface and the second surface, and a semiconductor substrate connecting the first region and the second region, A first electrode provided on the first surface in the first region, In the second region, a second electrode is provided on the first surface, separated from the first electrode, A first control electrode is provided in the first region and controls the current flowing between the first electrode and the semiconductor substrate, A second control electrode is provided in the second region and controls the current flowing between the second electrode and the semiconductor substrate, A conductive member having a third surface positioned opposite the second surface and a fourth surface located on the opposite side of the third surface, and electrically connected to the semiconductor substrate via the third surface, A conductive bonding member provided between the semiconductor substrate and the conductive member, Equipped with, The conductive member is A mounting section provided between the third surface and the fourth surface, A thin-walled portion having a fifth surface located on the opposite side of the fourth surface, the thickness between the fifth surface and the fourth surface being thinner than the thickness of the mounting portion, Includes, The joining member is provided between the second surface and the third surface, and also between the second surface and the fifth surface, In plan view, The shape of the outer circumference of the conductive member and the shape of the outer circumference of the semiconductor part are both rectangular. The four first vertices of the conductive member are arranged to correspond to the four second vertices of the semiconductor portion. The outer circumference of the conductive member is located outside the outer circumference of the semiconductor portion. In a plan view, each of the four second vertices is positioned within the area of ​​the thin-walled portion. In a plan view, the thin portion has a triangular outer perimeter shape that includes one of the four first vertices.

2. A semiconductor portion having a first surface and a second surface located opposite the first surface, the semiconductor portion having a first region provided between the first surface and the second surface, a second region provided between the first surface and the second surface, and a semiconductor substrate connecting the first region and the second region, A first electrode provided on the first surface in the first region, In the second region, a second electrode is provided on the first surface, separated from the first electrode, A first control electrode is provided in the first region and controls the current flowing between the first electrode and the semiconductor substrate, A second control electrode is provided in the second region and controls the current flowing between the second electrode and the semiconductor substrate, It has a third surface positioned opposite the second surface, and a fourth surface located on the opposite side of the third surface, A conductive member electrically connected to the semiconductor substrate via the third surface, A conductive bonding member disposed between the semiconductor substrate and the conductive member, Equipped with, The conductive member is A mounting section provided between the third surface and the fourth surface, A plurality of thin-walled portions having a fifth surface located opposite to the fourth surface, the thickness between the fifth surface and the fourth surface being thinner than the thickness of the mounting portion, Includes, The joining member is provided between the second surface and the third surface, and also between the second surface and the fifth surface, In plan view, The outer periphery of the conductive member and the semiconductor part are each rectangular. The four first vertices of the conductive member are arranged to correspond to the four second vertices of the semiconductor portion. The outer circumference of the conductive member coincides with the outer circumference of the semiconductor portion, or is located outside the outer circumference of the semiconductor portion. The four first vertices are each located within the regions of the plurality of thin-walled sections, The conductive member has a plurality of grooves provided on the third surface, The plurality of grooves are separated from each other and are arranged toward the four first vertices, The joining member is provided between the second surface and the third surface, and is also provided within the plurality of grooves, which are semiconductor devices.

3. The semiconductor device according to claim 2, wherein the groove is provided extending from the mounting portion to the thin-walled portion.

4. The conductive member has a recess provided on the third surface, The groove is provided extending from the recess to the thin-walled portion, The bonding member is provided in the recess, as described in claim 3.

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