Semiconductor integrated circuit equipment

Abstract

In this semiconductor integrated circuit device, wirings (26a, 26b) extending in an X direction are formed on a metal wiring layer. The wirings (26a, 26b) are disposed on both X-direction sides of a resistor element (RU), and are connected to the resistor element (RU). The wiring (26a) is connected to a PAD, and a wiring (27) is connected to a VSS. An anode and a cathode of an ESD protection diode (1a) are alternately formed in a Y direction. The resistor element (RU) and the wirings (26a, 26b) overlap the cathode of the ESD protection diode (1a) when viewed from above, and the wiring (27) overlaps the anode of the ESD protection diode (1a) when viewed from above.

Description

Technical Field

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[0001] The present disclosure relates to a semiconductor integrated circuit device in which a core region and an I / O region are arranged on a chip, and particularly to a layout structure of I / O cells arranged in the I / O region.

Background Art

[0002] In a semiconductor integrated circuit, input / output cells (I / O cells) are arranged around a core region, and signals are input / output to / from the outside of the semiconductor integrated circuit device and power is supplied through the I / O cells.

[0003] In recent miniaturization processes, it has been widely practiced to form the gate of a transistor using a high-k gate insulating film and a metal gate. As a result, it has become difficult to use a non-silicided polysilicon resistor formed in the FEOL (Front End of Line: substrate process) as a resistance element. Currently, as a resistance element, a resistance element formed of a metal compound such as titanium nitride formed between metal wiring layers in the BEOL (Back End of Line: wiring process) is used.

[0004] In Patent Document 1, a semiconductor integrated circuit device is disclosed in which a resistance element formed between metal wiring layers in the BEOL is arranged above, for example, a diode element as an ESD (Electro-Static Discharge) protection element.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In miniaturization processes, the ESD resistance of semiconductor integrated circuits decreases, and detailed consideration of the wiring structure is necessary in their design to improve ESD resistance as much as possible. However, such consideration is not made in Patent Document 1.

[0007] This disclosure aims to provide a configuration for improving ESD resistance in semiconductor integrated circuit devices that use resistive elements formed at BEOL. [Means for solving the problem]

[0008] In a first aspect of this disclosure, a semiconductor integrated circuit device comprising an output circuit, the output circuit comprising an external output terminal, a first ESD (Electro-Static Discharge) protection diode whose first node is connected to the external output terminal and whose second node is connected to a first power supply, and a wiring process (BEOL: Back End of The first ESD protection diode is composed of a plurality of resistive elements formed in a first wiring layer formed in a Line, and comprises a first protection resistor with one end connected to the external output terminal, and a first output transistor connected between the other end of the first protection resistor and the first power supply, and in the second wiring layer, first, second, and third wirings are formed extending in a first direction, the first and second wirings are arranged on both sides of the resistive element in the first direction in a plan view and are connected to the resistive element respectively, the first wiring is connected to the external output terminal, the third wiring is connected to the first power supply, the first and second nodes of the first ESD protection diode are formed alternately in a second direction perpendicular to the first direction, the resistive element and the first and second wirings overlap with the first node of the first ESD protection diode in a plan view, and the third wiring overlaps with the second node of the first ESD protection diode in a plan view.

[0009] In this embodiment, the output circuit comprises an external output terminal, a first ESD protection diode with a first node connected to the external output terminal and a second node connected to a first power supply, a first protection resistor with one end connected to the external output terminal, and a first output transistor connected between the other end of the first protection resistor and the first power supply. The first protection resistor is composed of a plurality of resistive elements formed in a first wiring layer formed in the wiring process (BEOL). In the second wiring layer, the first and second wirings are arranged on both sides of the resistive element in a first direction in a plan view and are connected to the resistive element, respectively, with the first wiring connected to the external output terminal and the third wiring connected to the first power supply. The first ESD protection diode has first and second nodes formed alternately in a second direction perpendicular to the first direction, the resistive elements and the first and second wirings overlap with the first node of the first ESD protection diode in a plan view, and the third wiring overlaps with the second node of the first ESD protection diode in a plan view. In other words, since the second node of the first ESD protection diode, which is connected to the first power supply, overlaps with the third wiring connected to the first power supply in a plan view, the resistance of the path from the first power supply to the first ESD protection diode can be suppressed. This allows the first ESD protection diode to function effectively and improves ESD immunity. [Effects of the Invention]

[0010] According to this disclosure, the ESD resistance of semiconductor integrated circuit devices using resistive elements formed at BEOL can be further improved. [Brief explanation of the drawing]

[0011] [Figure 1] A schematic plan view showing the overall configuration of a semiconductor integrated circuit device according to the embodiment. [Figure 2] Circuit diagram of the output circuit according to the first embodiment [Figure 3] Overview example of IO cell layout in the first embodiment [Figure 4] Figure 3 is a plan view showing the details of the I / O cell layout. [Figure 5] Plan view showing details of the IO cell layout of FIG. 3 [Figure 6] Plan view showing details of the IO cell layout of FIG. 3 [Figure 7] Plan view showing the layout of the ESD protection diode [Figure 8] Plan view showing the layout of the output transistor [Figure 9] Cross-sectional view showing details of the IO cell layout of FIG. 3 [Figure 10] Plan view showing the layout of the ESD protection diode [Figure 11] Plan view showing the layout of the output transistor [Figure 12] Circuit configuration diagram of the output circuit according to the second embodiment [Figure 13] Schematic example of the IO cell layout in the second embodiment [Figure 14] Plan view showing details of the IO cell layout of FIG. 13 [Figure 15] Schematic example of the IO cell layout in the modification

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following description, "VDD" and "VSS" shall refer to the power supply voltage or the power supply itself. Also, the transistors shall be formed on a P-type substrate and an N-type well. Note that the transistors may be formed on a P-type well or an N-type substrate.

[0013] (First Embodiment) FIG. 1 is a plan view schematically showing the overall configuration of a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device 1 shown in FIG. 1 includes a core region 2 in which an internal core circuit is formed, and an I / O region 3 provided between the core region 2 and the chip edge, in which an interface circuit (I / O circuit) is formed. In the I / O region 3, an I / O cell row 10A is provided so as to annularly surround the peripheral portion of the semiconductor integrated circuit device 1. Although the illustration is simplified in FIG. 1, a plurality of I / O cells 10 constituting the interface circuit are arranged in the I / O cell row 10A. Although not shown in FIG. 1, a plurality of external connection pads are arranged in the semiconductor integrated circuit device 1. Note that the IO cell row 10A may be provided in a part of the peripheral portion of the semiconductor integrated circuit device 1.

[0014] The I / O cell 10 includes a signal I / O cell and a power supply I / O cell. The signal I / O cell includes circuits necessary for signal exchange between the outside of the semiconductor integrated circuit device 1 or between the core region 2, such as a level shifter circuit, an output buffer circuit, an ESD protection circuit, and the like. The power supply I / O cell supplies each power supply supplied to the external connection pad to the inside of the semiconductor integrated circuit device 1 and includes an ESD protection circuit and the like.

[0015] FIG. 2 is a circuit configuration diagram of an output circuit 11 included in the I / O cell 10. Although the actual output circuit includes circuit elements other than those shown in FIG. 2, the description is omitted in FIG. 2.

[0016] The output circuit 11 shown in FIG. 2 includes an external output terminal PAD, output transistors P1, N1, ESD (ElectroStatic Discharge) protection diodes 1a, 1b, and protection resistors Rsn, Rsp. The output transistor P1 is a P-type transistor, and the output transistor N1 is an N-type transistor.

[0017] Output transistors P1 and N1 output an output signal to the external output terminal PAD according to the signal received at their gates. Output transistor P1 has its source connected to VDD and its drain connected to the external output terminal PAD via a protective resistor Rsp. Output transistor N1 has its source connected to VSS and its drain connected to the external output terminal PAD via a protective resistor Rsn. In this embodiment, the protective resistors Rsp and Rsn are composed of multiple resistive elements formed in the wiring layer formed during the BEOL (Back End of Line: wiring process). The node between output transistor N1 and protective resistor Rsn is denoted as node A, and the node between output transistor P1 and protective resistor Rsp is denoted as node B.

[0018] ESD protection diode 1a is located between VSS and the external output terminal PAD, with its anode connected to VSS and its cathode connected to the external output terminal PAD. ESD protection diode 1b is located between VDD and the external output terminal PAD, with its anode connected to the external output terminal PAD and its cathode connected to VDD. When high-voltage noise is input to the external output terminal PAD, current flows through ESD protection diodes 1a and 1b to VDD and VSS, thereby protecting output transistors P1 and N1.

[0019] Figure 3 shows an example of an I / O cell layout. The layout in Figure 3 corresponds to I / O cell 10a, one of the I / O cells 10 lined up along the bottom edge of the semiconductor integrated circuit device 1 in Figure 1. I / O cells generally have a high power supply voltage region that includes ESD protection circuits and output buffers for outputting signals to the outside of the semiconductor integrated circuit device, and a low power supply voltage region that includes circuits for inputting and outputting signals into the semiconductor integrated circuit device. In Figure 3, I / O cell 10a is divided into a low power supply voltage region 31 and a high power supply voltage region 32 in the Y direction. Here, the X direction is the direction along the outer edge of the semiconductor integrated circuit device 1, and the Y direction is the direction perpendicular to the X direction. The low power supply voltage region 31 is on the core region 2 side, and the high power supply voltage region 32 is on the chip edge side.

[0020] The IO cell 10a shown in Figure 3 constitutes the output circuit 11 shown in Figure 2. In the high power supply voltage region 32, output transistor N1, ESD protection diode 1a, ESD protection diode 1b, and output transistor P1 are arranged in order from the tip edge. Resistor elements RU are arranged in an array in the XY direction above output transistors N1, P1 and ESD protection diodes 1a, 1b. The resistor elements RU arranged above output transistor N1 and ESD protection diode 1a are connected to each other to form a protection resistor Rsn. The resistor elements RU arranged above output transistor P1 and ESD protection diode 1b are connected to each other to form a protection resistor Rsp. The connection configuration of the resistor elements RU may be series connection, parallel connection, or a combination of series and parallel connection.

[0021] Figures 4-8 are plan views showing the detailed layout of the IO cell. Figures 4-8 are enlarged and hierarchically shown views of the ESD protection diode 1a and output transistor N1 in Figure 3. Figure 9 is a cross-sectional view showing the cross-sectional structure along line X-X' in Figure 4.

[0022] Figure 4 shows the structures of the M5, M4, and RMetal wiring layers. The RMetal wiring layer is formed between the M4 and M3 wiring layers and is a wiring layer for forming resistive elements RU. The RMetal wiring layer is formed during the BEOL (Back End of Line) wiring process. The resistive elements RU formed on the RMetal wiring layer are connected to the wiring of the M4 wiring layer via vias.

[0023] In the M5 wiring layer, M5 wirings 21, 22, and 23 extending in the Y direction are formed. M5 wiring 21 corresponds to an external output terminal PAD and is connected to an I / O pad (not shown). M5 wiring 22 corresponds to node A, and M5 wiring 23 is connected to VSS. In the M4 wiring layer, M4 wirings 26a, 26b, and 27 extending in the X direction are formed. M4 wiring 27 is connected to M5 wiring 23 via a via. That is, M4 wiring 27 is connected to VSS.

[0024] A resistive element RU is formed in the RMetal wiring layer. Both ends of the resistive element RU in the X direction are connected to M4 wirings 26a and 26b via vias. M4 wiring 26a is connected to M5 wiring 21 via via, and M4 wiring 26b is connected to M5 wiring 22 via via. That is, the resistive element RU is connected between the external output terminal PAD and node A via the path M5 wiring 21 (PAD) → via (M5-M4) → M4 wiring 26a → via (M4-RMetal) → resistive element RU → via (M4-RMetal) → M4 wiring 26b → via (M5-M4) → M5 wiring 22 (A). Multiple resistive elements RU constitute a protective resistor Rsn.

[0025] Furthermore, at the location where the ESD protection diode 1a is positioned, the M4 wiring 27 supplying VSS extends in the X direction between the resistive elements RU in the Y direction. In other words, the M4 wiring 27 is not divided by the presence of the resistive elements RU.

[0026] Figure 5 shows the lower part of Figure 4, illustrating the structure of the M3 and M2 wiring layers. In Figure 5, the M3 and M2 wirings extend in the X direction. Also, vias (M4-M3) and vias (M3-M2) are formed at the same position in a plan view.

[0027] The M2 wiring 51 connected to the external output terminal PAD is connected to the M5 wiring 21 via vias and M3 and M4 wiring. The M2 wiring 52 connected to node A is connected to the M5 wiring 22 via vias and M3 and M4 wiring. The M2 wiring 53 and M3 wiring 54 supplying VSS are located in the same position in plan view and are connected to the M4 wiring 27 via vias.

[0028] The ESD protection diode 1a is connected to the PAD via an M2 wiring 51 (not shown) via an M1 wiring (not shown). This M1 wiring is formed in the same position as the M2 wiring 51 in a plan view. The ESD protection diode 1a is also connected to the M2 wiring 54 (not shown) via an M2 wiring 54 (not shown) that supplies VSS. The output transistor N1 is connected to the M2 wiring 52 (not shown) via a metal wiring layer and vias (not shown). The output transistor N1 is also connected to the M2 wiring 54 (not shown) via a metal wiring layer and vias (not shown) that supplies VSS.

[0029] Figure 6 shows the lower layer of Figure 5, illustrating the positional relationship between the M2 wiring layer and the anode and cathode of the ESD protection diode 1a. As shown in Figure 6, the cathode of the ESD protection diode 1a is positioned to overlap with the M2 wiring 51 connected to the external output terminal PAD, and the anode is positioned to overlap with the M2 wiring 53 that supplies VSS, and the cathode is positioned to overlap with VSS. In other words, the resistive element RU and the cathode of the ESD protection diode 1a are positioned to overlap in a plan view.

[0030] In order to satisfy the above positional relationship, it is preferable that the placement pitch of the cathode of the ESD protection diode 1a, the placement pitch of the anode of the ESD protection diode 1a, and the placement pitch of the resistor element RU are equal in the Y direction.

[0031] Figure 7 shows the layout of area LD1 in Figure 6, i.e., the ESD protection diode 1a. As shown in Figure 7, the ESD protection diode 1a comprises an anode portion 31 formed by a P-conducting fin 32 and cathode portions 33a and 33b formed by N-conducting fins 34a and 34b. The fins 32, 34a and 34b extend in the X direction. The anode portion 31 is connected to VSS, and the cathode portions 33a and 33b are connected to the external output terminal PAD. The diode is formed between the P-conducting fin 32 and the N-conducting fins 34a and 34b.

[0032] Figure 8 shows the layout of area LT1 in Figure 6, i.e., the output transistor N1. As shown in Figure 8, the output transistor N1 is formed by multiple N-conductive fins 61 extending in the X direction and arranged in the Y direction, and multiple gate wirings 62 extending in the Y direction and arranged in the X direction. The overlapping fins 61 and gate wirings 62 in a plan view form the transistor. Each transistor is connected in parallel by wiring (not shown). The drain of each transistor is connected to the external output terminal PAD via a protective resistor Rsn.

[0033] The ESD protection diode 1b and output transistor P1 also have the same layout as described above. That is, the layouts in Figures 4 to 6 can be inverted vertically (in the Y direction), VSS can be changed to VDD, and node A can be changed to node B. In the case of the ESD protection diode 1b, the cathode connected to VDD is positioned at a location that overlaps with the M2 wiring supplying VDD, and the anode is positioned at a location that overlaps with the M2 wiring connected to the external output terminal PAD. That is, the anode of the ESD protection diode 1b and the resistor element RU are positioned at a location that overlaps in a plan view. For the ESD protection diode 1b as well, it is preferable that the placement pitch of the cathode and the placement pitch of the anode are equal to the placement pitch of the resistor element RU in the Y direction.

[0034] Figure 10 shows the layout of the ESD protection diode 1b. The ESD protection diode 1b comprises a cathode portion 36 formed by an N-conducting fin 37 and anode portions 38a and 38b formed by P-conducting fins 39a and 39b. The fins 37, 39a and 39b extend in the X direction. The cathode portion 36 is connected to VDD, and the anode portions 38a and 38b are connected to the external output terminal PAD. The diode is formed between the N-conducting fin 37 and the P-conducting fins 39a and 39b.

[0035] Figure 11 shows the layout of the output transistor P1. It consists of multiple P-conductivity fins 66, each extending in the X direction and aligned in the Y direction, and multiple gate wirings 67, each extending in the Y direction and aligned in the X direction. The overlapping fins 66 and gate wirings 67 in plan view form the transistor. Each transistor is connected in parallel by wiring (not shown). The drain of each transistor is connected to the external output terminal PAD via a protective resistor Rsp.

[0036] According to this embodiment, the following effects can be obtained. Specifically, in the configuration according to this embodiment, the terminals of the ESD protection diodes 1a and 1b that are connected to the power supply VSS and VDD (i.e., the anode of ESD protection diode 1a and the cathode of ESD protection diode 1b) are arranged so as not to overlap with the resistive element RU. As a result, the resistance of the path from the power supply VSS and VDD to the ESD protection diodes 1a and 1b can be suppressed, so that the ESD protection diodes 1a and 1b can be made to work effectively and the ESD immunity can be improved.

[0037] Furthermore, in the Y direction, the arrangement pitch of the anodes and cathodes of the ESD protection diodes 1a and 1b is equal to the arrangement pitch of the resistor element RU. Therefore, the terminals of the ESD protection diodes 1a and 1b that are connected to the power supply can be placed in a plan view overlapping with the upper wiring that supplies the power. As a result, the terminals of the ESD protection diodes 1a and 1b that are connected to the power supply can be connected from the upper wiring in a downward direction, eliminating the need for connection wiring extending in the Y direction. Consequently, the resistance of the path from the power supply to the ESD protection diodes 1a and 1b can be suppressed.

[0038] Furthermore, the anode and cathode terminals of the ESD protection diodes 1a and 1b that are connected to the external signal terminal PAD (i.e., the cathode of ESD protection diode 1a and the anode of ESD protection diode 1b) are positioned to overlap with the wiring connected to the external signal terminal PAD (for example, M4 wiring 26a). This suppresses the resistance in the path from the external signal terminal PAD to the ESD protection diodes 1a and 1b, allowing the ESD protection diodes 1a and 1b to function effectively and improving ESD immunity.

[0039] (Second Embodiment) Figure 12 is a circuit diagram of the output circuit 12 according to this embodiment. The circuit configuration of Figure 12 is almost the same as the circuit configuration of Figure 2 in the first embodiment, but the insertion position of the protective resistor is different. That is, in the output circuit 12 of Figure 12, a protective resistor Rs is provided instead of the protective resistors Rsn and Rsp in Figure 2. In Figure 12, the drains of output transistors P1 and N1 are connected to each other, and the protective resistor Rs is provided between the external output terminal PAD and the drains of output transistors P1 and N1. The node between the drains of output transistors P1 and N1 and the protective resistor Rs is referred to as node C.

[0040] Figure 13 shows an example of an I / O cell layout. The I / O cell layout in Figure 13 is similar to the I / O cell layout in Figure 3 in the first embodiment. However, the protective resistor Rs is formed by connecting the resistor elements RU, which are located above the output transistors N1, P1 and the ESD protection diodes 1a, 1b, to each other. The connection configuration of the resistor elements RU may be series connection, parallel connection, or a combination of series and parallel connection.

[0041] Figure 14 is a plan view showing the detailed layout of the IO cell, and is an enlarged view of the ESD protection diode 1a and output transistor N1 in Figure 13. Figure 14 shows the structure of the M5 wiring layer, M4 wiring layer, and RMetal wiring layer. Note that the structure and cross-sectional structure of the layers below Figure 14 are the same as in the first embodiment and are therefore omitted from the illustration.

[0042] The layout in Figure 14 is the same as the layout in Figure 4 in the first embodiment. The only difference is that the M5 wiring 22 corresponds to node C instead of node A. Also, the layout of the layers below Figure 14 is the same as the layout shown in the first embodiment, except that the wiring etc. that was connected to node A is now connected to node C.

[0043] Furthermore, the layout of the ESD protection diode 1b and output transistor P1 in Figure 13 is basically the same as in the first embodiment, with the difference being that the wiring connected to node B is now connected to node C. The M5 wiring 22 in Figure 14 and the M5 wiring corresponding to node C in the ESD protection diode 1b and output transistor P1 section are connected in common.

[0044] In this embodiment, the same effects as in the first embodiment can be obtained. Specifically, the anode and cathode terminals of the ESD protection diodes 1a and 1b that are connected to the power supplies VSS and VDD are arranged so as not to overlap with the resistive element RU. As a result, the resistance in the path from the power supplies VSS and VDD to the ESD protection diodes 1a and 1b can be suppressed, allowing the ESD protection diodes 1a and 1b to function effectively and improving ESD resistance.

[0045] Furthermore, in the Y direction, the arrangement pitch of the anodes and cathodes of the ESD protection diodes 1a and 1b is equal to the arrangement pitch of the resistor element RU. Therefore, the terminals of the ESD protection diodes 1a and 1b that are connected to the power supply can be placed in a plan view overlapping with the upper wiring that supplies the power. As a result, the terminals of the ESD protection diodes 1a and 1b that are connected to the power supply can be connected from the upper wiring in a downward direction, eliminating the need for connection wiring extending in the Y direction. Consequently, the resistance of the path from the power supply to the ESD protection diodes 1a and 1b can be suppressed.

[0046] Furthermore, the anode and cathode terminals of the ESD protection diodes 1a and 1b that are connected to the external signal terminal PAD (i.e., the cathode of ESD protection diode 1a and the anode of ESD protection diode 1b) are positioned to overlap with the wiring connected to the external signal terminal PAD (for example, M4 wiring 26a). This suppresses the resistance in the path from the external signal terminal PAD to the ESD protection diodes 1a and 1b, allowing the ESD protection diodes 1a and 1b to function effectively and improving ESD immunity.

[0047] (modified version) Figure 15 shows an overview of an IO cell layout according to a modified example. As shown in Figure 15, the resistor element RU may be placed in the low power supply voltage region 31. This allows for the configuration of a protective resistor requiring a larger area.

[0048] In the above-described embodiment, the ESD protection diodes 1a and 1b and the output transistors N1 and P1 are configured as fins, but the invention is not limited to this configuration.

[0049] Furthermore, although the output circuit in the above-described embodiment is assumed to consist of a single-stage transistor for both the P-type transistor and the N-type output transistor, it is not limited to this configuration. For example, a configuration with multiple stages of transistors, such as two or three stages, connected in series may also be used. In addition, the output circuit in the above-described embodiment may be an input / output circuit that includes an input circuit.

[0050] Furthermore, in the above-described embodiment, the RMetal wiring layer is formed between the M4 wiring layer and the M3 wiring layer, but it is not limited to this. The RMetal wiring layer can be formed in BEOL. [Industrial applicability]

[0051] This disclosure describes how semiconductor integrated circuit devices using resistive elements formed at BEOL can have their ESD resistance improved, which is useful for improving the performance of system LSIs, for example. [Explanation of Symbols]

[0052] 1a, 1b ESD protection diodes 11,12 Output Circuit 26a, 26b, 27 M4 wiring N1, P1 Output transistors PAD External Output Terminal Rsn,Rsp,Rs Protection resistance RU Resistor

Claims

1. A semiconductor integrated circuit device equipped with an output circuit, The output circuit described above is External output terminal, The first node is connected to the external output terminal, and the second node is connected to the first power supply, and the first ESD (Electro-Static Discharge) protection diode is connected to the first power supply. It is composed of multiple resistive elements formed in the first wiring layer formed in the wiring process (BEOL: Back End of Line), and one end of the first protective resistor is connected to the external output terminal, The system comprises a first output transistor connected between the other end of the first protective resistor and the first power supply, In the second wiring layer, first, second, and third wirings extending in the first direction are formed, and the first and second wirings are arranged on both sides of the resistive element in the first direction in a plan view and are connected to the resistive element, respectively, and the first wiring is connected to the external output terminal, and the third wiring is connected to the first power supply, The first ESD protection diode has the first and second nodes formed alternately in a second direction perpendicular to the first direction. The resistive element and the first and second wirings overlap the first node of the first ESD protection diode in a plan view, and the third wiring overlaps the second node of the first ESD protection diode in a plan view. Semiconductor integrated circuit equipment.

2. In the semiconductor integrated circuit apparatus according to claim 1, In the second direction, the arrangement pitch of the first node of the first ESD protection diode, the arrangement pitch of the second node of the first ESD protection diode, and the arrangement pitch of the resistive element are equal to each other. Semiconductor integrated circuit equipment.

3. In the semiconductor integrated circuit apparatus according to claim 1, The plurality of resistive elements are arranged in an array in the first and second directions within the first wiring layer. Semiconductor integrated circuit equipment.

4. In the semiconductor integrated circuit apparatus according to claim 1, The output circuit described above is The first node is connected to the second power supply, and the second node is connected to the external output terminal, and the second ESD protection diode is connected to the external output terminal. A second protective resistor is composed of a plurality of resistive elements formed in the first wiring layer, with one end connected to the external output terminal, The system comprises a second output transistor connected between the other end of the second protective resistor and the second power supply. Semiconductor integrated circuit equipment.

5. In the semiconductor integrated circuit apparatus according to claim 1, The output circuit described above is The first node is connected to the second power supply, and the second node is connected to the external output terminal, and the second ESD protection diode is connected to the external output terminal. The system comprises a second output transistor connected between the other end of the first protective resistor and the second power supply. Semiconductor integrated circuit equipment.

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