Positioning method and method for manufacturing a semiconductor device
The method addresses chipping issues in semiconductor wafer grinding by using cut marks of varying widths and a light-based detection system to improve positioning accuracy and prevent chipping during the manufacturing process.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2022-08-31
- Publication Date
- 2026-05-27
AI Technical Summary
Chipping during the back grinding of semiconductor wafers affects the positioning accuracy, making it difficult to determine the precise position of the wafer.
A positioning method that involves forming cut marks with different widths on a semiconductor wafer, where a wider cut mark is used to facilitate the separation of a stepped portion during grinding, and a light-based system is used to detect the position of the wafer based on the width of light passing through these marks.
This method improves the accuracy and reliability of determining the wafer position by preventing chipping and enabling precise detection of notches, thereby enhancing the manufacturing process.
Smart Images
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Abstract
Description
Technical Field
[0001] This embodiment relates to a positioning method and a method for manufacturing a semiconductor device.
Background Art
[0002] During the back grinding of a semiconductor wafer, chipping or the like may occur. The chipping of the semiconductor wafer may affect the positioning of the semiconductor wafer.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] Provided are a positioning method and a method for manufacturing a semiconductor device that can more appropriately determine the position of a wafer. [[ID=|36]]
Means for Solving the Problems
[0005] The positioning method according to this embodiment is a positioning method for a wafer having a plurality of diced chips and attached to a tape. Further, this positioning method includes irradiating light onto a wafer having a first cut mark provided between chips and a second cut mark having a width different from the width of the first cut mark. Further, this positioning method includes receiving the irradiated light at a position facing the light irradiation position with the wafer interposed therebetween. Further, this positioning method includes determining the position of the wafer based on the width of the light received after passing through the wafer.
Brief Description of the Drawings
[0006] [Figure 1A] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 1B] This is a cross-sectional view following Figure 1A, showing an example of a semiconductor device manufacturing method. [Figure 1C] Figure 1B is a cross-sectional view showing an example of a semiconductor device manufacturing method. [Figure 1D] Figure 1C is a cross-sectional view showing an example of a semiconductor device manufacturing method. [Figure 1E] Figure 1D is a cross-sectional view showing an example of a semiconductor device manufacturing method. [Figure 2A] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 2B] This is a cross-sectional view showing an example of a semiconductor device manufacturing method, following Figure 2A. [Figure 2C] Figure 2B is a cross-sectional view showing an example of a semiconductor device manufacturing method. [Figure 2D] Figure 2C is a cross-sectional view showing an example of a semiconductor device manufacturing method. [Figure 3A] This is a top view showing an example of the arrangement and shape of cut marks according to the first embodiment. [Figure 3B] This is a view diagram showing an example of the shape of the stepped portion separated by the cut marks according to the first embodiment. [Figure 4] This is a cross-sectional view showing an example of a method for forming a cut mark according to the first embodiment. [Figure 5] This figure shows an example of the configuration of a position determination device according to the first embodiment. [Figure 6A] This figure shows an example of the arrangement of cut marks and notches according to the first embodiment. [Figure 6B] Figure 6A is a cross-sectional view of a semiconductor wafer. [Figure 6C] Figure 6A is a cross-sectional view of a semiconductor wafer. [Figure 7] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first comparative example. [Figure 8] This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second comparative example. [Figure 9] This is a top view showing an example of the arrangement and shape of cut marks in the second comparative example. [Figure 10] It is a top view showing an example of the arrangement and shape of the cut marks according to the first modification. [Figure 11] It is a figure showing an example of the arrangement of the cut marks and the notch according to the second modification. [Figure 12] It is a figure showing an example of the arrangement of the cut marks and the notch according to the second embodiment. [Figure 13] It is a figure showing an example of the arrangement of the cut marks and the notch according to the third embodiment.
Mode for Carrying Out the Invention
[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and the drawings, the same elements as those described above with respect to the previous drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.
[0008] (First Embodiment) The method for manufacturing a semiconductor device according to the first embodiment includes singulating a bonded semiconductor wafer into a plurality of semiconductor chips CH and picking up the semiconductor chips CH and mounting them on a substrate or the like.
[0009] First, a method for bonding a semiconductor wafer will be described.
[0010] FIGS. 1A to 1E are cross-sectional views showing an example of the method for manufacturing a semiconductor device according to the first embodiment.
[0011] First, as shown in FIG. 1A, two semiconductor wafers W1 and W2 are prepared.
[0012] Figure 1A shows the X and Y directions parallel to and perpendicular to the surfaces of semiconductor wafers W1 and W2, and the Z direction perpendicular to the surfaces of semiconductor wafers W1 and W2. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.
[0013] The semiconductor wafer W1 has a surface F1 and a surface F2. The semiconductor wafer W1 also has a substrate S1 and a semiconductor element E1. The substrate S1 is, for example, a silicon substrate. The semiconductor element E1 is provided on surface F1. Surface F2 is the surface opposite to surface F1.
[0014] The semiconductor wafer W2 has a surface F3 and a surface F4. The semiconductor wafer W2 also has a substrate S2 and a semiconductor element E2. The substrate S2 is, for example, a silicon substrate. The semiconductor element E2 is provided on surface F3. Surface F4 is the surface opposite to surface F3.
[0015] Next, as shown in Figure 1B, the surface F1 of semiconductor wafer W1 and the surface F3 of semiconductor wafer W2 are bonded together. Semiconductor wafers W1 and W2 are joined at the bonding interface S.
[0016] Next, as shown in Figure 1C, edge trimming is performed. That is, a notch C is formed at the outer peripheral edge of the bonded semiconductor wafers W1 and W2, extending from the surface F2 side to semiconductor wafer W2. By forming the notch C, chipping of the outer peripheral edge of the substrate S1 can be suppressed in the subsequent back surface grinding process of the substrate S1.
[0017] Next, as shown in Figure 1D, the back surface of the substrate S1 is ground. That is, the semiconductor wafer W1 is polished from the side F2.
[0018] Further polishing is performed, and as shown in Figure 1E, a semiconductor wafer W is completed with semiconductor wafers W1 and W2 bonded together. As shown in the enlarged view of Figure 1E, there is an outer perimeter step between the top surface F2 of the semiconductor wafer W and the bottom surface of the notch C. That is, a stepped portion (overhang portion) S2s exists on the semiconductor wafer W2.
[0019] Next, a method for separating a bonded semiconductor wafer W into multiple semiconductor chips CH will be described.
[0020] Figures 2A to 2D are cross-sectional views showing an example of a semiconductor device manufacturing method according to the first embodiment. Figures 2A to 2D show a portion of the cross-section of a semiconductor wafer W.
[0021] Figure 2A shows a bonded semiconductor wafer W, similar to Figure 1E. A film P is also provided on the semiconductor element E1 of the semiconductor wafer W1. Film P is a surface protective film such as PI (Polyimide).
[0022] Next, as shown in Figure 2B, cut marks T1 and T2 are formed.
[0023] The cut marks T1 are formed on the scribe lines of the bonded semiconductor wafers W1 and W2. The cut marks T1 are formed to separate (fragment) the semiconductor chip CH.
[0024] Cut mark T2 is a different cut mark from cut mark T1. Cut mark T2 is formed to cut off the stepped portion S2s. Cut mark T2 is formed to improve the grinding quality of the semiconductor wafer W and to improve the recognition of the notch N when positioning the semiconductor wafer W, as will be explained later.
[0025] The cut mark T2 is deeper than the cut mark T1 relative to the surface F2. As a result, in the back surface grinding process of the substrate S2, which will be explained later with reference to Figures 2C and 2D, the polishing position reaches the cut mark T2 before the cut mark T1. This allows the semiconductor chip CH to be separated after the stepped portion S2s is cut off and falls away.
[0026] Next, as shown in Figure 2C, the back surface of the substrate S2 is ground. That is, the semiconductor wafer W2 is polished from the side F4. Note that Figure 2C is upside down compared to Figure 2B. Also, tape TP is shown in Figure 2C. Tape TP is a protective tape such as back grinding tape.
[0027] As shown in Figure 2C, for example, when the polishing position reaches the cut mark T2, the stepped portion S2s falls off and separates from the bonded semiconductor wafer W. This is because the portion not cut at the cut mark T2 is cut by the thinning of the substrate S2 and the grinding load. The stepped portion S2s is then bonded to the tape TP.
[0028] Further backside grinding is continued, and as shown in Figure 2D, when the polishing position reaches the cut mark T1, the bonded semiconductor wafer W is separated into multiple semiconductor chips CH. After separation, backside grinding is completed.
[0029] Next, we will describe the arrangement and shape of the cut marks T2.
[0030] Figure 3A is a top view showing an example of the arrangement and shape of the cut mark T2 according to the first embodiment. Figure 3B is a top view showing an example of the shape of the stepped portion S2s separated by the cut mark T2 according to the first embodiment. Figure 3A is a view of the bonded semiconductor wafer W as seen from the Z direction in the process shown in Figure 2B. Note that the cut mark T1 is omitted in Figure 3A. Also, the difference in area between semiconductor wafer W1 and semiconductor wafer W2 (width of the stepped portion S2s) and the size of the notch N are not limited to the examples shown in Figures 3A and 3B.
[0031] The cut mark T2 is provided on the outer periphery of the semiconductor wafer W, i.e., on the stepped portion S2s. More specifically, the cut mark T2 is positioned such that the stepped portion S2s separated by the cut mark T2 includes a notch N.
[0032] The cut mark T2 is formed at a position corresponding to the position of the notch N on the semiconductor wafer W2. This makes it easier to detect the notch N from the position of the cut mark T2 when determining the position of the semiconductor wafer W, which will be explained later. In the example shown in Figure 3A, the cut mark T2 is formed at a distance D of 10 mm away from the notch N at an angle of 90° (Y direction).
[0033] When viewed from a direction approximately perpendicular to the plane F2 (Z direction), the cut mark T2 has an edge T2e on the bonded semiconductor wafers W1 and W2. Therefore, the cut mark T2 does not cut through the plane of the semiconductor wafer W. The cut mark T2 has, for example, two edges T2e.
[0034] Furthermore, the cut marks T2 do not reach the outer edge of the semiconductor wafer W2. More specifically, the two edges T2e of the cut marks T2 do not reach the outer edge of the semiconductor wafer W2. No cut marks T2 are formed along the dotted line extending from the edges T2e. As a result, the stepped portion S2s is not separated from the semiconductor wafer W in the process shown in Figure 2B, but is separated from the semiconductor wafer W in the back grinding process shown in Figure 2C. As shown in Figure 3B, the contour of the falling stepped portion S2s is crescent-shaped, as indicated by the thick line. Due to the stresses applied during the grinding process, the stepped portion S2s is separated from the semiconductor wafer W2 with the dotted line in Figure 3A as the boundary. The stepped portion S2s that falls and adheres to the tape TP also contains a notch N.
[0035] The cut marks T2 are formed, for example, by an infrared laser, a blade, or an ultraviolet laser. Depending on the formation method, the cut marks T2 are formed from the front or back surface of the semiconductor wafer W.
[0036] Furthermore, the cut mark T2 is, for example, linear.
[0037] Next, we will explain the difference in the methods used to form cut marks T1 and T2.
[0038] Figure 4 is a cross-sectional view showing an example of a method for forming cut marks T1 and T2 according to the first embodiment. Figure 4 shows an example of forming cut marks T1 and T2 by stealth dicing. Figure 4 is also a cross-sectional view taken from a direction substantially perpendicular to the direction in which the cut marks T1 and T2 extend.
[0039] The upper left panel of Figure 4 shows the modified portion (modified layer) LM in the cut mark T1 before back grinding. The upper right panel of Figure 4 shows the modified portion LM in the cut mark T1 after back grinding. The lower left panel of Figure 4 shows the modified portion LM in the cut mark T2 before back grinding. The lower right panel of Figure 4 shows the modified portion LM in the cut mark T2 after grinding. Note that cracks extending from the modified portion LM are omitted in Figure 4.
[0040] In stealth dicing, a modified portion LM is formed in the substrate S2 by a laser beam L. By adjusting the focal position of the laser beam L, the formation position of the modified portion LM can be adjusted. The modified portion LM contained in the cut mark T2 is formed at a deeper position (closer to the semiconductor wafer W1) than the modified portion LM contained in the cut mark T1. The modified portion LM in the cut mark T1 is removed by back grinding. On the other hand, the modified portion LM in the cut mark T2 remains after back grinding. As a result, after back grinding, a cut mark T2 with a width greater than the width of the cut mark T1 can be formed.
[0041] Alternatively, instead of stealth dicing, cut marks T1 and T2 may be formed by blade dicing. In this case, blades of different widths are used for forming cut mark T1 and blades for forming cut mark T2.
[0042] Next, we will explain how to determine the position of the bonded semiconductor wafer W.
[0043] Figure 5 shows an example of the configuration of the positioning device 100 according to the first embodiment. The semiconductor wafer W shown in Figure 5 has a plurality of individual semiconductor chips CH. The semiconductor wafer W is attached to a tape TP.
[0044] The position determination device 100 comprises a light source 110, a light receiving unit 120, and a position determination unit 130.
[0045] The light source 110 irradiates light onto the semiconductor wafer W. More specifically, the light source 110 irradiates light onto the outer edge of the semiconductor wafer W where the notch N is provided.
[0046] The light-receiving unit 120 receives light from the light source 110. The light-receiving unit 120 is, for example, an imaging unit of a camera.
[0047] The light source 110 and the light receiving unit 120 are arranged so as to sandwich the semiconductor wafer W along a direction substantially perpendicular to the semiconductor wafer W.
[0048] The position determination unit 130 determines the position (handling position) of the semiconductor wafer W based on the light reception result from the light receiving unit 120. The position of the semiconductor wafer W includes, for example, the rotation angle of the semiconductor wafer W. The position determination unit 130 detects a notch N from the image captured by the light receiving unit using image recognition. The position determination unit 130 determines the position of the semiconductor wafer W based on the notch N.
[0049] Figure 6A is a diagram showing an example of the arrangement of cut marks T1, T2 and notch N according to the first embodiment. Figure 6A shows the area around cut mark T2 and notch N. Note that Figure 6A is, for example, the light reception result of the light receiving unit 120. Figures 6B and 6C are cross-sectional views of the semiconductor wafer W shown in Figure 6A. Figures 6B and 6C are cross-sectional views along the dashed line AA shown in Figure 6A. Note that Figures 6B and 6C correspond to the processes shown in Figures 2B and 2D, respectively.
[0050] The semiconductor wafer W has cut marks (grooves) T1 and T2. At the position determination point shown in Figure 6A, as shown in Figure 2D, cut marks T1 and T2 penetrate the semiconductor wafer W. Cut mark T1 is provided between semiconductor chips CH. Cut mark T2 has a different width from cut mark T1. The white dotted line corresponds to the dotted line portion in Figure 3A. The width of the white dotted line portion is different from that of cut mark T2. Figure 6B shows a cross-sectional view along the dashed line in Figure 6A. When cut marks T1 are made with a blade, if the blade depth is deeper than the eaves depth D, cut marks T1 are also formed in the eaves. If the blade depth is shallower than the eaves depth D, cut marks T1 are not formed in the eaves. When cut marks T1 are formed with a laser, by switching the laser on and off, it is possible to prevent cut marks T1 from being formed in the eaves regardless of the depth of cut marks T1.
[0051] The light-receiving unit 120 receives light passing through (transmitting) the semiconductor wafer W, and light passing through the outer edge of the semiconductor wafer W. The light passing through the semiconductor wafer W passes through the cut marks T1 and T2.
[0052] In the example shown in Figure 6A, as explained with reference to Figure 4, the width WT2 of the cut mark T2 is greater than the width of the cut mark T1. In this case, the width of the light (luminous beam) passing through the cut mark T2 is greater than the width of the light passing through the cut mark T1.
[0053] In Figure 6A, the width is the width along the X direction, and the width of the cut mark T2 is in a direction approximately perpendicular to the stretching direction.
[0054] The width of the cut mark T1 is, for example, approximately 10 μm. The width of the cut mark T2 WT2 is, for example, approximately 100 μm.
[0055] The position determination unit 130 can detect the cut mark T2, distinguishing it from the cut mark T1 based on the difference in width. The position determination unit 130 determines the position of the semiconductor wafer W based on the cut mark T2. Figure 6C shows a cross-sectional view along the dashed line in Figure 6A after grinding from the back surface and dividing the semiconductor chip CH. If the amount of grinding on the semiconductor wafer W is small and the grinding does not reach the cut mark T1 on the eaves portion, the eaves portion is not divided by the cut mark T1, so when viewed from above, the cut mark T1 on the eaves portion and the cut mark T1 on the device portion will look different. For example, when observing the semiconductor wafer W with light that does not transmit light, the cut mark T1 on the eaves portion cannot be observed. Even in such cases, the cut mark T2 and the cut mark T1 between the semiconductor chips can be distinguished because they have different widths. Alternatively, if the grinding on the back surface is large and reaches the cut mark T1 on the eaves portion, the eaves portion is also divided by the cut mark T1. Even in such cases, the cut marks T2, the cut marks T1 between semiconductor chips, and the cut marks T1 on the overhang portion can be distinguished because they have different widths.
[0056] Next, we will explain the method for determining the position.
[0057] First, the light source 110 irradiates light onto the semiconductor wafer W. More specifically, the light source 110 irradiates light onto the outer periphery of the semiconductor wafer W.
[0058] Next, the light receiving unit 120 receives light from the light source 110. That is, the light receiving unit 120 receives (detects) the irradiated light at a position opposite the light irradiation position, with the semiconductor wafer W in between.
[0059] Next, the position determination unit 130 determines the position of the semiconductor wafer W based on the width of the light received after passing through the semiconductor wafer W. More specifically, the position determination unit 130 detects a cut mark T2 based on the width of the received light. Next, the position determination unit 130 detects a notch N based on the cut mark T2. The position determination unit 130 detects the notch N, for example, by recognizing its outline. Next, the position determination unit 130 determines the position of the semiconductor wafer W based on the notch N.
[0060] The position determination unit 130 may detect the notch N by feeding back information about the position where the cut mark T2 is formed. This can improve the detection accuracy of the notch N.
[0061] As described above, according to the first embodiment, the light source 110 irradiates light onto the semiconductor wafer W having cut marks T1 and T2. Next, the light receiving unit 120, which is positioned opposite the light source 110 with the semiconductor wafer W in between, receives the light irradiated from the light source 110. Next, the position determination unit 130 determines the position of the semiconductor wafer W based on the width of the light that has passed through the semiconductor wafer W and is received by the light receiving unit 120. As a result, the cut mark T2 can be used to determine the position of the semiconductor wafer W, and the position of the semiconductor wafer W can be determined more appropriately.
[0062] In the example shown in Figure 2B, the cut mark T2 has a predetermined depth that does not reach from surface F2 to surface F4. However, it is not limited to this, and the depth of the cut mark T2 may reach from surface F2 to surface F4. In this case, the stepped portion S2s may be separated when the grinding wheel (grinder G) comes into contact with the semiconductor wafer W during back grinding.
[0063] (Comparative Example 1) Figure 7 is a cross-sectional view showing an example of a semiconductor device manufacturing method according to the first comparative example. The first comparative example differs from the first embodiment in that no cut mark T2 is formed.
[0064] Figure 7 shows the backside grinding process shown in Figure 2C. In the example shown in Figure 7, the stepped portion S2s of the substrate S2 may chip off during the backside grinding process. In this case, chipping may occur at the outer edge of the semiconductor wafer W, making it difficult to detect the notch N.
[0065] In contrast, in the first embodiment, the stepped portion S2s separates and falls onto the tape TP before it can chip away. Therefore, chipping at the outer edge of the semiconductor wafer W is suppressed. This makes it possible to suppress chipping near the notch N, and to detect the notch N with higher accuracy and in a shorter time.
[0066] (Comparative Example 2) Figure 8 is a cross-sectional view showing an example of a semiconductor device manufacturing method according to the second comparative example. Figure 9 is a top view showing an example of the arrangement and shape of the cut marks T2a according to the second comparative example. The second comparative example differs from the first embodiment in that the cut marks T2a are formed in a substantially circular shape when viewed from the surface F2.
[0067] In the examples shown in Figures 8 and 9, the cut mark T2a is formed in a substantially circular shape when viewed from a direction substantially perpendicular to the surface F2. The cut mark T2a is formed, for example, using a laser beam L in stealth dicing. In this case, at the start of backside grinding, or during backside grinding, the stepped portion S2s separates from the semiconductor wafer W in a ring shape and falls off. However, in the example shown in Figure 9, there is no end portion T2e and the cut mark T2a is continuous, so the semiconductor wafer W is cut all the way through. In this case, the ring-shaped stepped portion S2s that is adhered to the tape TP may come off due to external impact or the like.
[0068] In contrast, in the first embodiment, the cut mark T2 does not completely cut through the semiconductor wafer W. Because it only partially cuts (half-cuts) the semiconductor wafer W, it can be made more resistant to external impacts.
[0069] (First variation) Figure 10 is a top view showing an example of the arrangement and shape of cut marks T2 and T3 in the first modified example. The first modified example differs from the first embodiment in that cut marks T3 are formed.
[0070] In the process shown in Figure 2B, cut marks T1 and T2 are formed, and one or more cut marks T3 may also be formed. Cut marks T3 are formed at a position further from the notch N of the semiconductor wafer W2 than cut marks T2. Cut marks T3 have a different shape or dimensions from cut marks T2. In the example shown in Figure 10, the width of cut mark T3 is smaller than the width of cut mark T2. Also, the number of cut marks T3 is not limited to the example shown in Figure 10.
[0071] If the outer edge locations prone to chipping are known in advance, a cut mark T3 is formed so as to separate the stepped portion S2s where chipping is likely to occur. This further suppresses chipping on the outer edge of the semiconductor wafer W. As a result, notches N can be more easily detected.
[0072] As in the first modified example, a cut mark T3 may be formed. The positioning method according to the first modified example can obtain the same effects as in the first embodiment.
[0073] (Second variation) Figure 11 shows an example of the arrangement of cut marks T1, T2 and notch N in a second modification. The second modification differs from the first embodiment in that the length of the cut mark T2 in the X direction is further used to detect the cut mark T2.
[0074] In Figure 11, the width is the width along the X direction. In Figure 11, the length is the length along the Y direction.
[0075] The position determination unit 130 determines the position of the semiconductor wafer W based on the width and length of the received light. This allows for more accurate detection of the cut mark T2.
[0076] In Figure 3A, the width of the stepped portion S2s is, for example, approximately 3.4 mm. The length LT2 of the cut mark T2 is, for example, approximately 25 mm. The laser off accuracy (stopping accuracy) in stealth dicing is, for example, approximately 50 μm at a cutting speed of 500 mm / s. Therefore, the cut mark T2 can be formed with a sufficiently small error relative to the length LT2 of the cut mark T2.
[0077] As in the second modified example, the length of the cut mark T2 may be further used to detect the cut mark T2. The position determination method according to the second modified example can obtain the same effects as in the first embodiment.
[0078] (Second Embodiment) Figure 12 shows an example of the arrangement of cut marks T1, T2 and notch N according to the second embodiment. In the second embodiment, the method for detecting notch N is different from that of the first embodiment.
[0079] The position determination unit 130 calculates (determines) a search area Rs for searching for the notch N based on the cut mark T2. The search area Rs is, for example, the area on the outer edge of the semiconductor wafer W from the line extending from the cut mark T2. Next, the position determination unit 130 detects the notch N by searching for it in the search area Rs. This allows the search area to be narrowed down, enabling detection of the notch N with higher accuracy and in a shorter time.
[0080] As in the second embodiment, the method for detecting the notch N may be changed. The position determination method according to the second embodiment can obtain the same effects as the first embodiment. Furthermore, the position determination method according to the second embodiment may be combined with the first and second modifications of the first embodiment.
[0081] (Third embodiment) Figure 13 shows an example of the arrangement of cut marks T1, T2 and notch N according to the third embodiment. In the third embodiment, the method for detecting notch N is different from that of the first embodiment.
[0082] The position determination unit 130 calculates candidate positions for notch N based on a preset arrangement relationship between the cut mark T2 and the position of the cut mark T2 and notch N. In the process shown in Figure 2B, the cut mark T2 is placed at a position based on the arrangement relationship and the position of the notch. The arrangement relationship shown in Figure 13 includes, for example, the distances L1 and L2 between each of the two ends T2e and notch N. The arrangement relationship shown in Figure 13 also includes, for example, the angles A1 and A2 between the line connecting each of the two ends T2e and notch N and the cut mark T2. Next, the position determination unit 130 detects notch N by searching for notch N based on the calculated candidate positions for notch N. This allows the search area to be narrowed, enabling detection of notch N with higher accuracy and in a shorter time.
[0083] Furthermore, the greater the amount of feedback regarding the arrangement relationship, i.e., the position where the cut mark T2 is formed, the more prediction lines can be drawn between the cut mark T2 and the notch N, as shown in Figure 13. As a result, the detection accuracy of the notch N can be improved.
[0084] Figure 13 also shows, as an example, a chip at the outer edge of the semiconductor wafer W near notch N. The presence of a chip near notch N may reduce the detection accuracy of notch N. In the third embodiment, by calculating candidate positions for notch N, notch N can be detected more appropriately even when a chip is present near it.
[0085] As in the third embodiment, the method for detecting the notch N may be changed. The position determination method according to the third embodiment can obtain the same effects as the first embodiment. Furthermore, the position determination method according to the third embodiment may be combined with the first and second modifications of the first embodiment, as well as the second embodiment.
[0086] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]
[0087] 100 Positioning device, 110 Light source, 120 Light receiving unit, 130 Positioning unit, CH Semiconductor chip, E1 Semiconductor element, E2 Semiconductor element, F1~F4 Surface, N Notch, Rs Search area, S1 Substrate, S2 Substrate, T1~T3 Cut marks, TP Tape, W Semiconductor wafer, W1 Semiconductor wafer, W2 Semiconductor wafer
Claims
1. A method for determining the position of a wafer having multiple individual chips attached to a tape, Light is shone onto the wafer having a first cut mark provided between the chips and a second cut mark having a width different from the width of the first cut mark. At a position opposite the light irradiation position across the wafer, the irradiated light is received, The position of the wafer is determined based on the width of the light received after passing through the wafer. It is equipped with the following: Determining the position of the wafer based on the width of the received light is, Based on the width of the received light, the second cut mark is detected. Based on the second cut mark, a notch is detected. Based on the notch, the position of the wafer is determined. It is equipped with the following: Detecting the notch based on the second cut mark means that Based on the second cut mark, the search area for searching the notch is calculated. The notch is detected by searching for the notch in the search area. A method for determining position that includes the following:
2. Detecting the notch based on the second cut mark means that Based on the second cut mark and the predetermined positional relationship between the second cut mark and the position of the notch, candidate positions for the notch are calculated. The notch is detected by searching for the notch based on the candidate position. The position determination method according to claim 1, further comprising the above.
3. The position determination method according to claim 2, wherein the second cut mark is provided at a position based on the arrangement relationship and the position of the notch.
4. The position determination method according to claim 1, further comprising determining the position of the wafer based on the width and length of the received light.
5. The second cut mark is provided on the outer periphery of the wafer, The outer peripheral portion of the wafer is irradiated with light. The position determination method according to claim 1, further comprising the above.