Semiconductor equipment
The asymmetric substrate and lead design in semiconductor devices disperses thermal strain, addressing stress concentration and improving bonding strength and heat dissipation, thus preventing substrate cracking.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2022-01-20
- Publication Date
- 2026-05-27
AI Technical Summary
Existing semiconductor devices experience thermal stress concentration at the interface between the insulating substrate and metal leads, leading to potential substrate cracking due to differing linear expansion coefficients.
The semiconductor device design includes a substrate with dimensions asymmetrical in two orthogonal directions, featuring a first lead with a region overlapping semiconductor elements and a thinner region extending along the second direction, dispersing thermal strain and reducing stress concentration through strategic placement and bonding layers.
This configuration effectively mitigates thermal stress on the substrate, enhancing bonding strength and reducing the risk of cracking while maintaining efficient heat dissipation and electrical connectivity.
Smart Images
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device including a substrate with leads fixed thereto and semiconductor elements mounted on the leads.
Background Art
[0002] Patent Document 1 discloses an example of a semiconductor device. The semiconductor device includes an insulating substrate, a metal pattern fixed to the insulating substrate, and a semiconductor element mounted on the metal pattern.
[0003] In the semiconductor device disclosed in Patent Document 1, when the metal pattern is a lead, the metal pattern may be fixed to the insulating substrate using a bonding layer such as solder. When fixing the metal pattern to the insulating substrate, it is necessary to melt the bonding layer by heat. At this time, due to the difference in the linear expansion coefficients of the insulating substrate and the metal pattern, thermal strain occurs at the interface between the insulating substrate and the metal pattern. As a result, thermal stress is generated in the insulating substrate. If the thermal stress concentrates, cracks may occur in the insulating substrate. Therefore, when the metal pattern is a lead, in order to suppress crack generation in the insulating substrate, it is desirable to take measures to reduce the concentration of thermal stress acting on the insulating substrate.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] In view of the above circumstances, one problem of the present disclosure is to provide a semiconductor device capable of reducing the concentration of thermal stress acting on a substrate with leads fixed thereto.
Means for Solving the Problems
[0006] A semiconductor device provided by this disclosure comprises a substrate having a main surface facing in the thickness direction, a first lead fixed on the main surface and having a mounting surface facing the same side as the main surface in the thickness direction, and a first semiconductor element disposed on the mounting surface, wherein the dimensions of the substrate in a first direction orthogonal to the thickness direction are greater than the dimensions of the substrate in a second direction orthogonal to the thickness direction and the first direction, and the first lead includes a first region overlapping the first semiconductor element when viewed in the thickness direction, and a second region located away from the first semiconductor element when viewed in the thickness direction and at least a portion of which extends along the second direction, wherein the thickness of the second region is less than the thickness of the first region. [Effects of the Invention]
[0007] According to the above configuration, it is possible to reduce the concentration of thermal stress acting on the substrate to which the leads are fixed in the semiconductor device.
[0008] Other features and advantages of this disclosure will become more apparent from the detailed description below, based on the accompanying drawings. [Brief explanation of the drawing]
[0009] [Figure 1] This is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] Figure 1 is a plan view of the semiconductor device shown. [Figure 3] This is a plan view corresponding to Figure 2, and it shows the sealing resin permeating through it. [Figure 4] Figure 1 is a bottom view of the semiconductor device shown. [Figure 5] Figure 1 is a front view of the semiconductor device shown. [Figure 6] Figure 1 is a right side view of the semiconductor device shown. [Figure 7] This is a cross-sectional view along the line VII-VII in Figure 3. [Figure 8] This is a cross-sectional view along the line VIII-VIII in Figure 3. [Figure 9] It is a partially enlarged view of FIG. 3. [Figure 10] It is a cross-sectional view taken along the line X-X of FIG. 9. [Figure 11] It is a cross-sectional view taken along the line XI-XI of FIG. 9. [Figure 12] It is a cross-sectional view taken along the line XI-XI of FIG. 9. [Figure 13] It is a cross-sectional view taken along the line XI-XI of FIG. 9. [Figure 14] It is a partially enlarged plan view of a semiconductor device according to a first modification of the first embodiment of the present disclosure, corresponding to FIG. 9. [Figure 15] It is a partially enlarged plan view of a semiconductor device according to a second modification of the first embodiment of the present disclosure, corresponding to FIG. 9. [Figure 16] It is a partially enlarged plan view of a semiconductor device according to a third modification of the first embodiment of the present disclosure, corresponding to FIG. 9. [Figure 17] It is a partially enlarged plan view of a semiconductor device according to a fourth modification of the first embodiment of the present disclosure, corresponding to FIG. 9. [Figure 18] It is a partially enlarged plan view of a semiconductor device according to a fifth modification of the first embodiment of the present disclosure, corresponding to FIG. 9. [Figure 19] It is a plan view of a semiconductor device according to the second embodiment of the present disclosure, showing through the encapsulating resin. [Figure 20] It is a partially enlarged view of FIG. 19. [Figure 21] It is a plan view of a semiconductor device according to the third embodiment of the present disclosure, showing through the encapsulating resin. [Figure 22] It is a plan view of a semiconductor device according to the fourth embodiment of the present disclosure, showing through the encapsulating resin.
Embodiments for Carrying Out the Invention
[0010] Embodiments for carrying out the present disclosure will be described based on the accompanying drawings. <\
[0011] A semiconductor device A10 according to a first embodiment of the present disclosure will be described based on Figures 1 to 13. The semiconductor device A10 comprises a substrate 11, a base layer 12, a bonding layer 13, a first lead 21, a plurality of second leads 22, a plurality of third leads 23, a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a conductive bonding layer 39, a plurality of first wires 41, a plurality of second wires 42, and a sealing resin 50. Furthermore, the semiconductor device A10 comprises a plurality of driver leads 24, a first driver 33, a second driver 34, a plurality of diodes 35, a plurality of third wires 43, a plurality of fourth wires 44, a plurality of fifth wires 45, a plurality of sixth wires 46, and a dummy lead 60. Here, for ease of understanding, Figure 3 shows the sealing resin 50 being transparent. In Figure 3, the transparent sealing resin 50 is shown by dashed lines. In Figure 3, lines VII-VII and VIII-VIII are shown by dashed lines.
[0012] In describing the semiconductor device A10, for convenience, the thickness direction of the substrate 11 is referred to as the "thickness direction z". The direction perpendicular to the thickness direction z is referred to as the "first direction x". The direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y".
[0013] The semiconductor device A10 converts the DC power supply voltage applied to the first lead 21 and the third lead 23 into AC power using a plurality of first semiconductor elements 31 and a plurality of second semiconductor elements 32. The converted AC power is output from a plurality of second leads 22 as three phases (U phase, V phase, W phase) with different phases. Furthermore, since the semiconductor device A10 includes a first driver 33 that drives the plurality of first semiconductor elements 31 and a second driver 34 that drives the plurality of second semiconductor elements 32, the semiconductor device A10 is an IPM (Intelligent Power Module). The semiconductor device A10 is used, for example, in a power supply circuit for driving a three-phase AC motor.
[0014] As shown in Figures 3 and 7, the substrate 11 supports a first lead 21 and a plurality of second leads 22. The substrate 11 is electrically insulating. The substrate 11 is made of ceramics, for example, alumina (Al2O3). The material of the substrate 11 is preferably a material with relatively high thermal conductivity. As shown in Figure 7, the substrate 11 has a main surface 11A and a back surface 11B. The main surface 11A faces in the thickness direction z. The back surface 11B faces in the thickness direction z opposite to the main surface 11A. As shown in Figures 4, 7 and 8, the substrate 11 is covered with sealing resin 50 except for the back surface 11B.
[0015] As shown in Figure 3, the first dimension D1 of the substrate 11 in the first direction x is greater than the second dimension D2 of the substrate 11 in the second direction y. Therefore, the first direction x corresponds to the direction of the longer side of the substrate 11.
[0016] As shown in Figure 10, the base layer 12 is laminated on the main surface 11A of the substrate 11. The base layer 12 contains a metallic element, which is silver (Ag). An example of the base layer 12 is a resinate silver paste that has been applied to the main surface 11A and then fired.
[0017] The bonding layer 13 is laminated on top of the base layer 12, as shown in Figure 10. The bonding layer 13 bonds the base layer 12 to the first lead 21 and the multiple second leads 22. The bonding layer 13 contains a metallic element, which is tin (Sn). The bonding layer 13 is a lead-free solder containing, for example, an alloy of tin and antimony (Sb).
[0018] The first lead 21, the multiple second leads 22, and the multiple third leads 23, along with the multiple driver leads 24 and the dummy leads 60, are constructed from the same lead frame. This lead frame is made of copper (Cu) or a copper alloy. Therefore, the composition of the first lead 21, the multiple second leads 22, the multiple third leads 23, the multiple driver leads 24, and the dummy leads 60 includes copper (Cu). In other words, these leads contain copper.
[0019] The first lead 21 is fixed on the main surface 11A of the substrate 11, as shown in Figures 3, 7, and 8. The first lead 21 has a pad portion 211 and a terminal portion 212. The pad portion 211 has a plurality of first semiconductor elements 31 mounted on it. The pad portion 211 has a mounting surface 211A and a facing surface 211B. The mounting surface 211A faces the same side as the main surface 11A in the thickness direction z. The facing surface 211B faces the opposite side of the mounting surface 211A in the thickness direction z. The facing surface 211B faces the main surface 11A. As shown in Figure 10, the facing surface 211B is in contact with the bonding layer 13. The pad portion 211 is fixed to the main surface 11A via the underlayer 12 and the bonding layer 13. The pad portion 211 is covered with a sealing resin 50. The terminal portion 212 is connected to the pad portion 211. As shown in Figures 2, 4, and 5, a portion of the terminal portion 212 is exposed from the sealing resin 50. In semiconductor device A10, the terminal portion 212 corresponds to the P terminal (positive electrode) to which the DC power supply voltage to be converted is applied.
[0020] The multiple second leads 22 are located away from the first lead 21 and fixed on the main surface 11A of the substrate 11, as shown in Figures 3 and 7. The multiple second leads 22 are located next to the first lead 21 in a first direction x and are arranged along the first direction x. Each of the multiple second leads 22 has a pad portion 221 and a terminal portion 222. The pad portion 221 of the multiple second leads 22 individually mounts multiple second semiconductor elements 32. In the thickness direction z, the area of the pad portion 221 is smaller than the area of the pad portion 211 of the first lead 21. The pad portion 221 has a mounting surface 221A and a facing surface 221B. The mounting surface 221A faces the same side as the main surface 11A in the thickness direction z. The facing surface 221B faces the opposite side from the mounting surface 221A in the thickness direction z. The opposing surface 221B faces the main surface 11A. As shown in Figure 10, the opposing surface 221B is in contact with the bonding layer 13. The pad portion 221 is fixed to the main surface 11A via the base layer 12 and the bonding layer 13. The pad portion 221 is covered with sealing resin 50. The terminal portion 222 is connected to the pad portion 221. As shown in Figures 2, 4, and 5, a portion of the terminal portion 222 is exposed from the sealing resin 50. In the semiconductor device A10, three-phase AC power is output from the terminal portions 212 of a plurality of second leads 22.
[0021] The multiple third leads 23 are located away from the first lead 21 and the multiple second leads 22, as shown in Figure 3. The multiple third leads 23 are located opposite the multiple second leads 22 and the first lead 21 in the first direction x. The multiple third leads 23 are supported by the sealing resin 50 rather than the substrate 11. As shown in Figures 2, 4, and 5, a portion of each of the multiple third leads 23 is exposed from the sealing resin 50. In the semiconductor device A10, the multiple third leads 23 are N terminals (negative terminals) to which the DC power supply voltage to be converted is applied.
[0022] As shown in Figures 3 and 7, the multiple first semiconductor elements 31 are arranged on the mounting surface 211A of the pad portion 211 of the first lead 21. As shown in Figures 3 and 7, the multiple second semiconductor elements 32 are individually arranged on the mounting surface 221A of the pad portion 221 of the multiple second lead 22. The multiple first semiconductor elements 31 and the multiple second semiconductor elements 32 are all identical semiconductor elements. The multiple first semiconductor elements 31 and the multiple second semiconductor elements 32 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The MOSFETs are n-channel type and have a vertical structure. Each of the multiple first semiconductor elements 31 and the multiple second semiconductor elements 32 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).
[0023] As shown in Figures 9 and 10, each of the multiple first semiconductor elements 31 has a first electrode 311, a second electrode 312, a gate electrode 313, and a first edge 314. As shown in Figure 10, the first electrode 311 faces the mounting surface 211A of the pad portion 211 of the first lead 21. A voltage corresponding to the power before it is converted by the first semiconductor element 31 is applied to the first electrode 311. In other words, the first electrode 311 corresponds to the drain electrode of the first semiconductor element 31.
[0024] As shown in Figure 10, the second electrode 312 is located on the opposite side of the first electrode 311 in the thickness direction z. A voltage corresponding to the power converted by the first semiconductor element 31 is applied to the second electrode 312. That is, the second electrode 312 corresponds to the source electrode of the first semiconductor element 31. The second electrode 312 includes a plurality of metal plating layers. The second electrode 312 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. Alternatively, the second electrode 312 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.
[0025] As shown in Figures 9 and 10, the gate electrode 313 is located on the same side as the second electrode 312 in the thickness direction z, and is positioned away from the second electrode 312. A gate voltage is applied to the gate electrode 313 to drive the first semiconductor element 31. In the thickness direction z, the area of the gate electrode 313 is smaller than the area of the second electrode 312.
[0026] As shown in Figure 9, the first edge 314 extends along the second direction y when viewed in the thickness direction z. In each of the plurality of first semiconductor elements 31, the first edge 314 includes a pair of segments that are spaced apart from each other in the first direction x.
[0027] As shown in Figures 9 and 10, each of the multiple second semiconductor elements 32 has a first electrode 321, a second electrode 322, a gate electrode 323, and a second edge 324. As shown in Figure 10, the first electrode 321 faces the mounting surface 221A of the pad portion 221 of one of the multiple second leads 22. A voltage corresponding to the power before it is converted by the second semiconductor element 32 is applied to the first electrode 321. In other words, the first electrode 321 corresponds to the drain electrode of the second semiconductor element 32.
[0028] As shown in Figure 10, the second electrode 322 is located on the opposite side of the first electrode 321 in the thickness direction z. A voltage corresponding to the power converted by the second semiconductor element 32 is applied to the second electrode 322. That is, the second electrode 322 corresponds to the source electrode of the second semiconductor element 32. The second electrode 322 includes a plurality of metal plating layers. The second electrode 322 includes a nickel plating layer and a gold plating layer laminated on the nickel plating layer. Alternatively, the second electrode 322 may include a nickel plating layer, a palladium plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.
[0029] As shown in Figures 9 and 10, the gate electrode 323 is located on the same side as the second electrode 322 in the thickness direction z, and is positioned away from the second electrode 322. A gate voltage is applied to the gate electrode 323 to drive the second semiconductor element 32. In the thickness direction z, the area of the gate electrode 323 is smaller than the area of the second electrode 322.
[0030] As shown in Figure 9, the second edge 324 extends along the second direction y when viewed in the thickness direction z. In each of the multiple second semiconductor elements 32, the second edge 324 includes a pair of segments that are spaced apart from each other in the first direction x.
[0031] As shown in Figure 7, the conductive bonding layer 39 bonds the mounting surface 211A of the pad portion 211 of the first lead 21 to the plurality of first semiconductor elements 31. In addition, it individually bonds the mounting surfaces 221A of the pad portions 221 of the plurality of second leads 22 to the plurality of second semiconductor elements 32. The conductive bonding layer 39 is, for example, lead-free solder. The material of the conductive bonding layer 39 may be the same as the material of the bonding layer 13. As shown in Figure 10, the first electrodes 311 of the plurality of first semiconductor elements 31 are bonded to the mounting surface 211A of the pad portion 211 via the conductive bonding layer 39. As a result, the first electrodes 311 of the plurality of first semiconductor elements 31 are electrically connected to the first lead 21. The first electrodes 321 of the plurality of second semiconductor elements 32 are individually bonded to the mounting surface 221A of the pad portions 221 of the plurality of second leads 22 via the conductive bonding layer 39. As a result, the first electrodes 321 of each of the multiple second semiconductor elements 32 are individually conductive to each of the multiple second leads 22.
[0032] As shown in Figure 3, the multiple first wires 41 are individually connected to the second electrodes 312 of the multiple first semiconductor elements 31 and to the terminal portions 222 of the multiple second leads 22. As a result, the second electrodes 312 of the multiple first semiconductor elements 31 are individually electrically connected to the multiple second leads 22. The multiple first wires 41 contain aluminum (Al). Alternatively, the multiple first wires 41 may also contain copper.
[0033] As shown in Figure 3, the multiple second wires 42 are individually connected to the second electrodes 322 of the multiple second semiconductor elements 32 and to the multiple third leads 23. This ensures that the second electrodes 322 of the multiple second semiconductor elements 32 are individually electrically connected to the multiple third leads 23. The multiple second wires 42 contain aluminum. Alternatively, the multiple second wires 42 may contain copper.
[0034] In semiconductor device A10, multiple upper arm circuits are formed by a first lead 21, multiple first semiconductor elements 31, and multiple first wires 41. In addition, multiple lower arm circuits are formed by multiple second leads 22, multiple second semiconductor elements 32, multiple second wires 42, and multiple third leads 23. Therefore, the voltage applied to each gate electrode 313 of the multiple first semiconductor elements 31 is relatively higher than the voltage applied to each gate electrode 323 of the multiple second semiconductor elements 32. Furthermore, in semiconductor device A10, the grounds of the multiple lower arm circuits are different from each other.
[0035] As shown in Figures 7 and 9, the pad portion 211 of the first lead 21 includes a first region 213 and a second region 214. The first region 213 is the portion that overlaps with the plurality of first semiconductor elements 31 when viewed in the thickness direction z. The second region 214 is located away from the plurality of first semiconductor elements 31 when viewed in the thickness direction z.
[0036] As shown in Figure 9, at least a portion of the second region 214 extends along the second direction y. The dimension b of the second region 214 in the first direction x is smaller than the dimension B of each of the multiple first semiconductor elements 31 in the first direction x. In the semiconductor device A10, one side of the second region 214 in the second direction y reaches the periphery 211C of the pad portion 211. Furthermore, in the semiconductor device A10, in the thickness direction z, the first edge 314 of any of the multiple first semiconductor elements 31 is located next to the second region 214 in the first direction x.
[0037] Next, specific examples of the second region 214 will be described, as shown in Figures 11 to 13. The common feature of these examples is that the thickness t2 of the second region 214 is smaller than the thickness t1 of the first region 213.
[0038] In the example shown in Figure 11, the second region 214 is a slit. This slit penetrates the pad portion 211 of the first lead 21 in the thickness direction z. The second region 214 has an inner surface 214A facing the first direction x. The bonding layer 13 and the sealing resin 50 are both in contact with the inner surface 214A.
[0039] In the example shown in Figure 12, the second region 214 is a groove recessed from the mounting surface 211A of the pad portion 211 of the first lead 21. The second region 214 has an inner surface 214A and a bottom surface 214B. The bottom surface 214B connects to the inner surface 214A and faces the same side as the mounting surface 211A in the thickness direction z. The sealing resin 50 is in contact with the inner surface 214A and the bottom surface 214B.
[0040] In the example shown in Figure 13, the second region 214 is a groove recessed from the opposing surface 211B of the pad portion 211 of the first lead 21. The second region 214 has an inner surface 214A and a bottom surface 214B. In this example, the bottom surface 214B faces the same side as the opposing surface 211B in the thickness direction z. The bonding layer 13 is in contact with the inner surface 214A. The sealing resin 50 is in contact with the inner surface 214A and the bottom surface 214B.
[0041] As shown in Figure 3, the multiple driver leads 24 are positioned in the second direction y opposite to the substrate 11 from the terminals 212 of the first lead 21, the terminals 222 of the multiple second leads 22, and the multiple third leads 23. The multiple driver leads 24, like the multiple third leads 23, are supported by the sealing resin 50 rather than the substrate 11. As shown in Figures 2 and 4, a portion of each of the multiple driver leads 24 is exposed from the sealing resin 50.
[0042] As shown in Figure 3, the multiple driver leads 24 include a pad section 241, multiple power supply sections 242, multiple first control sections 243, multiple second control sections 244, and a dummy section 245. The pad section 241 is equipped with a first driver 33 and a second driver 34. Furthermore, the pad section 241 serves as the ground for the first driver 33 and the second driver 34. The multiple power supply sections 242 receive power that forms the basis of the gate voltage for driving the multiple first semiconductor elements 31. The multiple first control sections 243 receive input and output of electrical signals related to the control of the first driver 33. The multiple second control sections 244 receive input and output of electrical signals related to the control of the second driver 34. The dummy section 245 does not conduct to either the first driver 33 or the second driver 34.
[0043] As shown in Figure 8, the first driver 33 is bonded to the pad portion 241 via a conductive bonding layer 39. The first driver 33 is an LSI. As shown in Figure 3, the first driver 33 is located closer to the pad portion 211 of the first lead 21 than the second driver 34. The first driver 33 applies a gate voltage to the gate electrodes 313 of the multiple first semiconductor elements 31.
[0044] The second driver 34, like the first driver 33, is bonded to the pad portion 241 via a conductive bonding layer 39. The second driver 34 is an LSI. As shown in Figure 3, the second driver 34 is located closer to the pad portions 221 of the multiple second leads 22 than the first driver 33. The second driver 34 applies a gate voltage to the gate electrodes 323 of the multiple second semiconductor elements 32.
[0045] As shown in Figure 8, the multiple diodes 35 are individually connected to the multiple power supply units 242 via a conductive junction layer 39. The multiple diodes 35 prevent reverse bias from being applied to the multiple power supply units 242 when the multiple first semiconductor elements 31 are driven.
[0046] As shown in Figure 3, the multiple third wires 43 are connected to the first driver 33 and to the second electrodes 312 and gate electrodes 313 of the multiple first semiconductor elements 31. This allows the first driver 33 to apply a gate voltage to the gate electrodes 313 of the multiple first semiconductor elements 31. Simultaneously, the first driver 33 sets the ground for this gate voltage. The multiple third wires 43 contain, for example, gold.
[0047] As shown in Figure 3, the multiple fourth wires 44 are connected to the second driver 34 and the gate electrodes 323 of the multiple second semiconductor elements 32. This allows the gate voltage to be applied from the second driver 34 to the gate electrodes 323 of the multiple second semiconductor elements 32. The multiple fourth wires 44 contain, for example, gold.
[0048] As shown in Figure 3, the multiple fifth wires 45 are connected to the first driver 33, the pad section 241, the multiple power supply sections 242, the multiple diodes 35, and the multiple first control sections 243. This ensures that the pad section 241, the multiple power supply sections 242, the multiple diodes 35, and the multiple first control sections 243 are electrically connected to the first driver 33. The multiple fifth wires 45 may contain, for example, gold.
[0049] As shown in Figure 3, the multiple sixth wires 46 are connected to the second driver 34, the pad section 241, and the multiple second control units 244. This ensures that the pad section 241 and the multiple second control units 244 are electrically connected to the second driver 34. The multiple sixth wires 46 contain, for example, gold.
[0050] As shown in Figure 3, the dummy lead 60 is positioned away from the substrate 11 when viewed in the thickness direction z. In the first direction x, the dummy lead 60 is positioned on the opposite side of the terminal portions 222 of the multiple second leads 22 to the terminal portions 212 of the first lead 21. As shown in Figures 2, 4, and 6, a portion of the dummy lead 60 is exposed from the sealing resin 50.
[0051] As shown in Figures 7 and 8, the encapsulating resin 50 covers a portion of each of the multiple first semiconductor elements 31 and the multiple second semiconductor elements 32, as well as the first lead 21 and the multiple second leads 22. The encapsulating resin 50 is electrically insulating. The encapsulating resin 50 is made of a material including, for example, a black epoxy resin. The encapsulating resin 50 has a top surface 51, a bottom surface 52, a pair of first side surfaces 53, a pair of second side surfaces 54, and a pair of recesses 55.
[0052] As shown in Figures 7 and 8, the top surface 51 faces the same side as the main surface 11A of the substrate 11 in the thickness direction z. As shown in Figures 7 and 8, the bottom surface 52 faces the opposite side from the top surface 51 in the thickness direction z. As shown in Figure 4, the back surface 11B of the substrate 11 is exposed from the bottom surface 52.
[0053] As shown in Figures 2, 4, and 5, the pair of first sides 53 are located apart from each other in a first direction x. Each of the pair of first sides 53 is connected to a top surface 51 and a bottom surface 52.
[0054] As shown in Figures 2, 4, and 6, the pair of second sides 54 are located apart from each other in the second direction y. Each of the pair of second sides 54 is connected to a top surface 51 and a bottom surface 52. From one of the pair of second sides 54, a portion of each of the terminals 212 of the first lead 21, the terminals 222 of the multiple second leads 22, the multiple third leads 23, and the dummy lead 60 is exposed. From the other of the pair of second sides 54, a portion of each of the multiple driver leads 24 is exposed.
[0055] As shown in Figures 2, 4, and 6, the pair of recesses 55 are recessed in a first direction x from the pair of first side surfaces 53. In the thickness direction z, the pair of recesses 55 extend from the top surface 51 to the bottom surface 52. The pair of recesses 55 ensure a longer creepage distance of the sealing resin 50 from the terminal portion 212 of the first lead 21 and from any of the multiple third leads 23 to any of the multiple driver leads 24. This is advantageous for improving the dielectric strength of the semiconductor device A10.
[0056] Next, semiconductor devices A11 to A15, which are modified versions of semiconductor device A10, will be described based on Figures 14 to 18. In these modified versions, the configuration of the second region 214 of the pad portion 211 of the first lead 21 differs from that of semiconductor device A10.
[0057] Based on Figure 14, a first modified example of semiconductor device A10, semiconductor device A11, will be described.
[0058] As shown in Figure 14, in semiconductor device A11, the second region 214 has a gap portion 214C. For two first semiconductor elements 31 that are spaced apart from each other in the second direction y, the gap portion 214C is located between the first edge 314 of one first semiconductor element 31 and the first edge 314 of the other first semiconductor element 31 when viewed in the thickness direction z.
[0059] Based on Figure 15, a second modified example of semiconductor device A10, semiconductor device A12, will be described.
[0060] As shown in Figure 15, in semiconductor device A12, the second region 214 is contained within the periphery 211C of the pad portion 211. Therefore, both sides of the second region 214 in the second direction y are closed off by other regions of the pad portion 211.
[0061] Based on Figure 16, a third modified example of semiconductor device A10, semiconductor device A13, will be described.
[0062] As shown in Figure 16, in semiconductor device A13, the second region 214 is contained within the periphery 211C of the pad portion 211. Furthermore, the second region 214 has a narrow gap portion 214C.
[0063] Based on Figure 17, a fourth modified example of semiconductor device A10, semiconductor device A14, will be described.
[0064] As shown in Figure 17, in the semiconductor device A14, the second region 214 includes two sections. One of these two sections has a narrow section 214C. The lengths L1 and L2 of these two sections are equal. However, if one of the two sections has a narrow section 214C, the lengths L1 and L2 of these two sections may be different.
[0065] Based on Figure 18, a fifth modified example of semiconductor device A10, semiconductor device A15, will be described.
[0066] As shown in Figure 18, in the semiconductor device A15, the second region 214 includes two sections. Each of these two sections has a narrow section 214C. The lengths L1 and L2 of these two sections are different. However, as long as each of these two sections has a narrow section 214C, the lengths L1 and L2 of these two sections may be equal.
[0067] Next, we will explain the effects and benefits of semiconductor device A10.
[0068] The semiconductor device A10 comprises a substrate 11 and a first lead 21 fixed on the main surface 11A. The dimensions of the substrate 11 in the first direction x (first dimension D1 shown in Figure 3) are larger than the dimensions of the substrate 11 in the second direction y (second dimension D2 shown in Figure 3). The first lead 21 includes a first region 213 that overlaps the first semiconductor element 31 when viewed in the thickness direction z, and a second region 214 that is located away from the first semiconductor element 31 when viewed in the thickness direction z. At least a portion of the second region 214 extends along the second direction y. The thickness t2 of the second region 214 is smaller than the thickness t1 of the first region 213. When heat is applied to the substrate 11 and the first lead 21, in the configuration of the semiconductor device A10, both the expansion and contraction of the substrate 11 and the first lead 21 are greater in the first direction x than in the second direction y. Therefore, the thermal strain at the interface between the substrate 11 and the first lead 21, which is caused by the difference in the coefficient of linear expansion, has a larger component in the first direction x than in the second direction y. With the configuration of the semiconductor device A10, the second region 214 disperses the component of the thermal strain in the first direction x. As a result, the concentration of thermal strain at the interface between the substrate 11 and the first lead 21 is mitigated, and the maximum thermal stress acting on the substrate 11 due to the thermal strain is reduced. Thus, with the semiconductor device A10, it is possible to reduce the concentration of thermal stress acting on the substrate 11 to which the lead (first lead 21) is fixed.
[0069] Specific examples of the second region 214 may be the slit shown in Figure 11, the groove recessed from the mounting surface 211A of the pad portion 211 of the first lead 21 shown in Figure 12, or the groove recessed from the opposing surface 211B of the pad portion 211 shown in Figure 13. If the second region 214 takes the form of either the slit shown in Figure 11 or the groove recessed from the opposing surface 211B shown in Figure 13, the bonding layer 13 will be in contact with the inner surface 214A of the second region 214. As a result, an anchoring effect occurs in the bonding layer 13 with respect to the first lead 21, thereby improving the bonding strength of the first lead 21 to the substrate 11. Furthermore, the second region 214 may take the form of either the slit shown in Figure 11 or the groove recessed from the mounting surface 211A shown in Figure 12. In this case, when the first semiconductor element 31 is bonded to the pad portion 211 during the manufacturing of the semiconductor device A10, the molten conductive bonding layer 39 that spreads over the mounting surface 211A flows into the second region 214. This prevents excessive wetting of the conductive bonding layer 39, thereby suppressing displacement of the first semiconductor element 31 caused by wetting.
[0070] The first semiconductor element 31 has a first edge 314 that extends along a second direction y when viewed in the thickness direction z. When viewed in the thickness direction z, the first edge 314 is located next to the second region 214 in a first direction x. As a result, the first region 213 of the first lead 21, which is located next to the second region 214 in the first direction x, is sandwiched between the substrate 11 and the first semiconductor element 31 in the thickness direction z. Furthermore, the coefficient of linear expansion of the semiconductor substrate included in the first semiconductor element 31 is smaller than the coefficient of linear expansion of the first lead 21. As a result, the thermal expansion and contraction of the first region 213 in a direction perpendicular to the thickness direction z is constrained by the substrate 11 and the first semiconductor element 31. Therefore, the component of the thermal strain in the first direction x at the interface between the substrate 11 and the first lead 21, which is generated by the difference in expansion coefficients, is dispersed and reduced, so that the concentration of thermal stress acting on the substrate 11 can be reduced more effectively.
[0071] The semiconductor device A10 comprises two first semiconductor elements 31 arranged apart from each other in a second direction y. Viewed in the thickness direction z, the second region 214 has a narrow space 214C located between the first edge 314 of one first semiconductor element 31 and the first edge 314 of the other first semiconductor element 31. As a result, the first regions 213 of the first leads 21 located on both sides of the second region 214 in the first direction x are sandwiched between the substrate 11 and the two first semiconductor elements 31 in the thickness direction z. Therefore, on both sides of the second region 214 in the first direction x, thermal strain at the interface between the substrate 11 and the first leads 21 caused by the difference in expansion coefficients is reduced. Consequently, the component of the thermal strain in the first direction x that is dispersed by the second region 214 is less likely to concentrate in the vicinity of the second region 214.
[0072] The semiconductor device A10 further comprises a base layer 12 laminated on the main surface 11A of the substrate 11. The bonding layer 13 bonds the base layer 12 to the first lead 21. Both the base layer 12 and the bonding layer 13 contain metallic elements. This increases the affinity of the bonding layer 13 to the base layer 12, thereby improving the bonding strength of the first lead 21 to the substrate 11. In this case, it is preferable for the base layer 12 to contain silver and the bonding layer 13 to contain tin in order to increase the affinity of the bonding layer 13 to the base layer 12.
[0073] The semiconductor device A10 further comprises a sealing resin 50 that covers a portion of each of the substrate 11 and the first lead 21, and the first semiconductor element 31. The sealing resin 50 is in contact with the second region 214. This creates an anchoring effect in the sealing resin 50. This improves the bonding strength of the sealing resin 50 to the first lead 21.
[0074] The substrate 11 has a back surface 11B that faces away from the main surface 11A in the thickness direction z. The back surface 11B is exposed from the sealing resin 50. This improves the heat dissipation of the semiconductor device A10.
[0075] A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on Figures 19 and 20. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 19 shows the sealing resin 50 being transmitted through. In Figure 19, the transmitted sealing resin 50 is shown by dashed lines.
[0076] The semiconductor device A20 differs from the aforementioned semiconductor device A10 in that it includes a dummy element 36.
[0077] As shown in Figures 19 and 20, the dummy element 36 is positioned on the mounting surface 211A of the pad portion 211 of the first lead 21. The dummy element 36 is positioned away from the second region 214. Furthermore, in the first direction x, the dummy element 36 is positioned on the side of the second region 214 where one of the multiple first semiconductor elements 31 is positioned.
[0078] The dummy element 36 is bonded to the mounting surface 211A of the pad portion 211 via a conductive bonding layer 39. The dummy element 36 is, for example, a diode. Conductivity of the dummy element 36 to the first lead 21 is irrelevant. The coefficient of linear expansion of the semiconductor substrate included in the dummy element 36 is smaller than the coefficient of linear expansion of the first lead 21. It is preferable that the coefficient of linear expansion of the semiconductor substrate is relatively close to the coefficient of linear expansion of each semiconductor substrate of the plurality of first semiconductor elements 31. Furthermore, it is more preferable that the area of the dummy element 36 is relatively close to the area of each of the plurality of first semiconductor elements 31 when viewed in the thickness direction z.
[0079] In semiconductor device A20, the dummy element 36 is located next to any of the multiple first semiconductor elements 31 in the second direction y.
[0080] Next, we will explain the effects and benefits of semiconductor device A20.
[0081] The semiconductor device A20 comprises a substrate 11 and a first lead 21 fixed on the main surface 11A. The dimension of the substrate 11 in the first direction x (first dimension D1 shown in Figure 3) is larger than the dimension of the substrate 11 in the second direction y (second dimension D2 shown in Figure 3). The first lead 21 includes a first region 213 that overlaps the first semiconductor element 31 when viewed in the thickness direction z, and a second region 214 that is located away from the first semiconductor element 31 when viewed in the thickness direction z. At least a portion of the second region 214 extends along the second direction y. The thickness t2 of the second region 214 is smaller than the thickness t1 of the first region 213. Therefore, the semiconductor device A20 also makes it possible to reduce the concentration of thermal stress acting on the substrate 11 to which the lead (first lead 21) is fixed.
[0082] The semiconductor device A20 further includes a dummy element 36 positioned on the mounting surface 211A of the first lead 21 and away from the second region 214. The dummy element 36 is positioned in the first direction x on the side of the second region 214 where the first semiconductor element 31 is positioned. As a result, the first lead 21 is sandwiched between the substrate 11, the first semiconductor element 31 and the dummy element 36 in the thickness direction z. Furthermore, the coefficients of thermal expansion of the semiconductor substrate included in the first semiconductor element 31 and the semiconductor substrate included in the dummy element 36 are smaller than the coefficient of thermal expansion of the first lead 21. As a result, the thermal expansion and contraction of the first lead 21 in the direction perpendicular to the thickness direction z are constrained by the substrate 11, the first semiconductor element 31 and the dummy element 36. Therefore, the thermal strain at the interface between the substrate 11 and the first lead 21 caused by the difference in coefficients of thermal expansion is reduced, and thus the reduction of thermal stress concentration acting on the substrate 11 can be more effectively achieved.
[0083] The dummy element 36 is positioned next to the first semiconductor element 31 in the second direction y. As a result, the thermal expansion and contraction of the first lead 21 by the substrate 11, the first semiconductor element 31, and the dummy element 36 are more strongly constrained in the first direction x than in the second direction y. Therefore, the component of the thermal strain in the first direction x of the thermal strain at the interface between the substrate 11 and the first lead 21 is reduced more significantly. Consequently, the maximum thermal stress acting on the substrate 11 can be effectively reduced.
[0084] A semiconductor device A30 according to a third embodiment of the present disclosure will be described based on Figure 21. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 21 shows the sealing resin 50 being transparent. The transparent sealing resin 50 in Figure 21 is shown by dashed lines.
[0085] The configuration of semiconductor device A30 differs from that of semiconductor device A10 described above in that it has a first lead 21, a plurality of second leads 22, and a third lead 23. Furthermore, semiconductor device A30 does not have a dummy lead 60.
[0086] As shown in Figure 21, each pad portion 221 of the multiple second leads 22 has a base portion 221C and an oblique portion 221D. One of the multiple second semiconductor elements 32 is mounted on the base portion 221C. The oblique portion 221D connects the base portion 221C to the terminal portion 222 of the second lead 22. Viewed in the thickness direction z, the oblique portion 221D is inclined with respect to the second direction y. As a result, in the pad portion 211 of the first lead 21 located next to the second lead 22, the peripheral edge 211C located next to the oblique portion 221D of the second lead 22 is inclined in the same direction as the oblique portion 221D with respect to the second direction y.
[0087] As shown in Figure 21, the third lead 23 is a single component. Multiple second wires 42 are connected to the third lead 23. Therefore, in semiconductor device A30, the ground of multiple lower arm circuits is common.
[0088] Next, we will explain the effects and benefits of semiconductor device A30.
[0089] The semiconductor device A30 comprises a substrate 11 and a first lead 21 fixed on the main surface 11A. The dimension of the substrate 11 in the first direction x (first dimension D1 shown in Figure 3) is larger than the dimension of the substrate 11 in the second direction y (second dimension D2 shown in Figure 3). The first lead 21 includes a first region 213 that overlaps the first semiconductor element 31 when viewed in the thickness direction z, and a second region 214 that is located away from the first semiconductor element 31 when viewed in the thickness direction z. At least a portion of the second region 214 extends along the second direction y. The thickness t2 of the second region 214 is smaller than the thickness t1 of the first region 213. Therefore, the semiconductor device A30 also makes it possible to reduce the concentration of thermal stress acting on the substrate 11 to which the lead (first lead 21) is fixed.
[0090] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described based on Figure 22. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanations are omitted. Here, for ease of understanding, Figure 22 shows the sealing resin 50 being transparent. The transparent sealing resin 50 in Figure 22 is shown by dashed lines.
[0091] The semiconductor device A40 replaces the multiple driver leads 24 with multiple first gate terminals 25, multiple second gate terminals 26, multiple first detection terminals 27, multiple second detection terminals 28, and a pair of temperature detection terminals 29. As shown in Figure 22, these terminals are located in the second direction y on the opposite side of the substrate 11 from the terminal portion 212 of the first lead 21, the terminal portions 222 of the multiple second leads 22, and the third lead 23, and are arranged along the first direction x. A portion of each of these terminals is exposed from one of the second sides 54 of the sealing resin 50. These terminals, together with the first lead 21, the multiple second leads 22, and the third lead 23, are formed from the same lead frame. Furthermore, the semiconductor device A40 replaces the first driver 33, the second driver 34, and the multiple diodes 35 with a thermistor 37. These configurations differ from the semiconductor device A30 described above. Therefore, the semiconductor device A40 is not an IPM, but a general power module. However, in the semiconductor device A40 as well, three-phase AC power is output from the terminal portions 222 of multiple second leads 22.
[0092] As shown in Figure 22, the multiple first gate terminals 25 are located closer to the pad portion 211 of the first lead 21 than the multiple second gate terminals 26. The multiple first gate terminals 25 are fixed to the main surface 11A of the substrate 11 via the underlayer 12 and the bonding layer 13. The multiple third wires 43 are individually connected to the multiple first gate terminals 25 and to the gate electrodes 313 of the multiple first semiconductor elements 31. As a result, each of the multiple first gate terminals 25 is conductive to the gate electrode 313 of any of the multiple first semiconductor elements 31. A gate voltage is applied to the multiple first gate terminals 25 to drive the multiple first semiconductor elements 31.
[0093] As shown in Figure 22, the multiple second gate terminals 26 are located closer to the pad portions 221 of the multiple second leads 22 than the multiple first gate terminals 25. The multiple second gate terminals 26 are fixed to the main surface 11A of the substrate 11 via the underlayer 12 and the bonding layer 13. The multiple fourth wires 44 are individually connected to the multiple second gate terminals 26 and to the gate electrodes 323 of the multiple second semiconductor elements 32. As a result, each of the multiple second gate terminals 26 is conductive to the gate electrode 323 of any of the multiple second semiconductor elements 32. A gate voltage is applied to the multiple second gate terminals 26 to drive the multiple second semiconductor elements 32.
[0094] As shown in Figure 22, each of the multiple first detection terminals 27 is located next to any of the multiple second gate terminals 26 in the first direction x. The multiple first detection terminals 27 are fixed to the main surface 11A of the substrate 11 via the underlayer 12 and the bonding layer 13. Multiple third wires 43 are individually connected to the multiple first detection terminals 27 and to the second electrodes 312 of the multiple first semiconductor elements 31. As a result, each of the multiple first detection terminals 27 is conductive to the second electrode 312 of any of the multiple first semiconductor elements 31. A voltage of the same potential as the voltage applied to the second electrode 312 of any of the multiple first semiconductor elements 31 is applied to each of the multiple first detection terminals 27.
[0095] As shown in Figure 22, each of the multiple second detection terminals 28 is located next to any of the multiple second gate terminals 26 in the first direction x. The multiple second detection terminals 28 are fixed to the main surface 11A of the substrate 11 via the underlayer 12 and the bonding layer 13. The multiple fourth wires 44 are individually connected to the multiple second detection terminals 28 and to the second electrodes 322 of the multiple second semiconductor elements 32. As a result, each of the multiple second detection terminals 28 is conductive to the second electrode 322 of any of the multiple second semiconductor elements 32. A voltage of the same potential as the voltage applied to the second electrode 322 of any of the multiple second semiconductor elements 32 is applied to each of the multiple second detection terminals 28.
[0096] As shown in Figure 22, the pair of temperature sensing terminals 29 are located on the opposite side of the substrate 11 from the third lead 23 in the second direction y. The pair of temperature sensing terminals 29 are joined to the wiring 61 located on the main surface 11A of the substrate 11.
[0097] As shown in Figure 22, the thermistor 37 is connected to the wiring 61. Therefore, the pair of temperature detection terminals 29 are conductive to the thermistor 37 via the wiring 61. This allows the temperature of the substrate 11 during use of the semiconductor device A40 to be detected by applying a voltage to the pair of temperature detection terminals 29.
[0098] Next, we will explain the effects and benefits of semiconductor device A40.
[0099] The semiconductor device A40 comprises a substrate 11 and a first lead 21 fixed on the main surface 11A. The dimension of the substrate 11 in the first direction x (first dimension D1 shown in Figure 3) is larger than the dimension of the substrate 11 in the second direction y (second dimension D2 shown in Figure 3). The first lead 21 includes a first region 213 that overlaps the first semiconductor element 31 when viewed in the thickness direction z, and a second region 214 that is located away from the first semiconductor element 31 when viewed in the thickness direction z. At least a portion of the second region 214 extends along the second direction y. The thickness t2 of the second region 214 is smaller than the thickness t1 of the first region 213. Therefore, the semiconductor device A40 also makes it possible to reduce the concentration of thermal stress acting on the substrate 11 to which the lead (first lead 21) is fixed.
[0100] This disclosure is not limited to the embodiments described above. The specific configuration of each part of this disclosure can be modified in various ways.
[0101] This disclosure includes embodiments described in the following appendix. Note 1. A substrate having a main surface oriented in the thickness direction, It has a mounting surface that faces the same side as the main surface in the thickness direction, and a first lead fixed on the main surface, The system comprises a first semiconductor element disposed on the mounting surface, The dimensions of the substrate in a first direction perpendicular to the thickness direction are greater than the dimensions of the substrate in a second direction perpendicular to the thickness direction and the first direction. The first lead includes a first region that overlaps the first semiconductor element when viewed in the thickness direction, and a second region that is located away from the first semiconductor element when viewed in the thickness direction, and at least a portion of which extends along the second direction. A semiconductor device in which the thickness of the second region is less than the thickness of the first region. Note 2. The semiconductor device according to Appendix 1, wherein one side of the second region in the second direction reaches the periphery of the first lead. Note 3. The first semiconductor element has a first edge that extends along the second direction when viewed in the thickness direction, The semiconductor device according to Appendix 1 or 2, wherein, viewed in the thickness direction, the first edge is located adjacent to the second region in the first direction. Note 4. The invention further comprises two additional semiconductor elements arranged apart from each other in the second direction, The semiconductor device according to Appendix 3, wherein, viewed in the thickness direction, the second region has a narrow portion located between the two additional semiconductor elements. Note 5. The semiconductor device according to any one of the appendices 1 to 4, wherein the dimension of the second region in the first direction is smaller than the dimension of the first semiconductor element in the first direction. Note 6. The semiconductor device according to any one of appendices 1 to 5, wherein the second region is a slit. Note 7. The semiconductor device according to any one of the appendices 1 to 5, wherein the second region is a groove recessed from the mounting surface. Note 8. The first lead has an opposing surface that faces the main surface, The semiconductor device according to any one of appendices 1 to 5, wherein the second region is a groove recessed from the opposing surface. Note 9. The system further comprises a dummy element positioned on the mounting surface and away from the second region, The semiconductor device according to any one of appendices 1 to 8, wherein the dummy element is located on the side of the second region where the first semiconductor element is arranged in the first direction. Note 10. The semiconductor device described in Appendix 9, wherein the dummy element is located next to the first semiconductor element in the second direction. Note 11. The base layer laminated on the main surface, The system further comprises a bonding layer that joins the aforementioned underlayer and the first lead, The semiconductor device according to any one of the appendices 1 to 10, wherein the underlayer and the bonding layer contain a metallic element. Note 12. The aforementioned subsoil contains silver, The bonding layer is a semiconductor device as described in Appendix 11, containing tin. Note 13. The device further comprises a conductive bonding layer that joins the mounting surface and the first semiconductor element. The first semiconductor element is a semiconductor device according to any one of the appendices 1 to 12, which is electrically connected to the first lead. Note 14. A second lead is fixed on the main surface and located away from the first lead, The present invention further comprises a second semiconductor element positioned on the second lead and having electrical conductivity with respect to the second lead, The semiconductor device described in Appendix 13, wherein the second lead is electrically connected to the first semiconductor element. Note 15. The present invention further comprises a third lead located apart from the first and second leads, The semiconductor device described in Appendix 14, wherein the third lead is electrically connected to the second semiconductor element. Note 16. The encapsulating resin further covers a portion of the substrate and the first lead, and the first semiconductor element. The sealing resin is in contact with the second region, and is a semiconductor device according to any one of the appendices 1 to 15. Note 17. The substrate has a back surface that faces the opposite side from the main surface in the thickness direction, The semiconductor device described in Appendix 16, wherein the aforementioned back surface is exposed from the sealing resin. [Explanation of Symbols]
[0102] A10, A20, A30, A40: Semiconductor equipment 11: Substrate 11A: Main surface 11B: Back side 12: Base layer 13: Bonding layer 21: First lead 211: Pad section 211A: Mounting surface 211B: Opposing surface 211C: Periphery 212: Terminal section 213: First area 214:Second area 214A:Inner surface 214B: Bottom surface 214C: Gap 22: Second lead 221: Pad section 221A: Mounting surface 221B: Opposing surface 221C: Base 221D: Slanted section 222: Terminal section 23: Third lead 24: Driver lead 241: Pad section 242: Power supply unit 243: First control unit 244: Second control unit 245: Dummy unit 25: First gate terminal 26: Second gate terminal 27: First detection terminal 28: Second detection terminal 29: Temperature detection terminal 31: First semiconductor element 311: 1st electrode 312: 2nd electrode 313: Gate terminal 314: First edge 32: Second semiconductor element 321: First electrode 322: Second electrode 323: Gate electrode 324: Second edge 33: First driver 34: Second driver 35: Diode 36: Dummy element 37: Thermistor 39: Conductive bonding layer 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 45: Fifth wire 50: Sealing resin 51: Top surface 52: Bottom 53: First side 54: Second side surface 55: Recess 60: Dummy lead 61: Wiring D1: First dimension D2: Second dimension t1, t2: Thickness B, b: Dimensions z: thickness direction x: first direction y: Second direction
Claims
1. A substrate having a main surface facing one side in the thickness direction, It has a mounting surface that faces the same side as the main surface in the thickness direction, and a first lead fixed on the main surface, The system comprises a plurality of first semiconductor elements arranged on the mounting surface, The dimensions of the substrate in a first direction perpendicular to the thickness direction are greater than the dimensions of the substrate in a second direction perpendicular to the thickness direction and the first direction. The first lead includes a plurality of first regions in which the entirety of each of the plurality of first semiconductor elements individually overlap when viewed in the thickness direction, and a second region located away from the plurality of first regions when viewed in the thickness direction, and at least a portion of which extends along the second direction. The thickness of the second region is less than the thickness of each of the plurality of first regions. Viewed in the thickness direction, the plurality of first semiconductor elements are arranged apart from each other along directions that are inclined with respect to both the first and second directions. A semiconductor device wherein two of the plurality of first regions that are adjacent to each other in the first direction are located on opposite sides of each other with respect to the second region in the first direction.
2. The semiconductor device according to claim 1, wherein one side of the second region in the second direction reaches the periphery of the first lead.
3. Each of the plurality of first semiconductor elements has a first edge that extends along the second direction when viewed in the thickness direction, The semiconductor device according to claim 1 or 2, wherein, viewed in the thickness direction, the first edge is located adjacent to the second region in the first direction.
4. The semiconductor device according to claim 3, wherein the second region has a narrow portion sandwiched between the two first regions.
5. The semiconductor device according to any one of claims 1 to 4, wherein the dimension of the second region in the first direction is smaller than the dimension of each of the plurality of first regions in the first direction.
6. The semiconductor device according to any one of claims 1 to 5, wherein the second region is a slit.
7. The semiconductor device according to any one of claims 1 to 5, wherein the second region is a groove recessed from the mounting surface.
8. The first lead has an opposing surface that faces the main surface, The semiconductor device according to any one of claims 1 to 5, wherein the second region is a groove recessed from the opposing surface.
9. The system further comprises a dummy element positioned on the mounting surface and away from the second region, The semiconductor device according to any one of claims 1 to 8, wherein the dummy element is located on the side of the second region where any of the plurality of first semiconductor elements are arranged in the first direction.
10. The semiconductor device according to claim 9, wherein the dummy element is located next to any of the plurality of first semiconductor elements in the second direction.
11. The base layer laminated on the main surface, The system further comprises a bonding layer that joins the aforementioned underlayer and the first lead, The semiconductor device according to any one of claims 1 to 10, wherein the underlayer and the bonding layer contain a metallic element.
12. The aforementioned subsoil contains silver, The semiconductor device according to claim 11, wherein the bonding layer contains tin.
13. The system further comprises a conductive bonding layer that joins the mounting surface and the plurality of first semiconductor elements. The semiconductor device according to any one of claims 1 to 12, wherein the plurality of first semiconductor elements are electrically connected to the first lead.
14. A second lead is fixed on the main surface and located away from the first lead, The present invention further comprises a second semiconductor element positioned on the second lead and having electrical conductivity with respect to the second lead, The semiconductor device according to claim 13, wherein the second lead is electrically connected to any of the plurality of first semiconductor elements.
15. The present invention further comprises a third lead located apart from the first and second leads, The semiconductor device according to claim 14, wherein the third lead is electrically connected to the second semiconductor element.
16. The encapsulating resin further covers a portion of the substrate and the first lead, and the plurality of first semiconductor elements. The semiconductor device according to any one of claims 1 to 15, wherein the sealing resin is in contact with the second region.
17. The substrate has a back surface that faces the opposite side from the main surface in the thickness direction, The semiconductor device according to claim 16, wherein the back surface is exposed from the sealing resin.