High-speed sampler

Abstract

To provide a regeneration circuit which increases a speed of a sampler and increases sensitivity of the sampler, and a method.SOLUTION: A regeneration circuit 150 includes a first transistor 250 coupled to an input 272 of a second inverting circuit 270, and a second transistor 255 coupled to an input 262 of a first inverting circuit 260, a third transistor 610 and a fourth transistor 620. A gate of the first transistor and a gate of the third transistor are coupled to a first input 160, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input 165. The regeneration circuit further includes a third switch 630 and a fourth switch 645. The third switch and the third transistor are coupled in series between a rail 280 and the second transistor, and the fourth switch and the fourth transistor are coupled in series between the rail and the second transistor.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the priority and benefit of non - provisional patent application No. 17 / 805,211, filed with the United States Patent and Trademark Office on June 2, 2022, and the entire content thereof is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes.

Background Art

[0002] Field

[0002] Aspects of the present disclosure generally relate to samplers, and more particularly to high - speed samplers.

[0003] Background

[0003] High - speed samplers can be used in high - speed serializer / deserializer (SerDes) applications. For example, a sampler can be used in a high - speed SerDes to sample a high - speed signal received by a receiver. The sampler can include a regenerative circuit that provides regenerative feedback to the sampler to quickly capture data bits from the received signal. It is desirable to increase the speed of the sampler to sample signals at a higher data rate and / or increase the sensitivity of the sampler to capture data bits from small signals.

Summary of the Invention

[0004]

[0004] Below, a simplified summary of one or more implementations is presented to provide a basic understanding of such implementations. This "Summary of the Invention" is not an overview of the entire scope of all contemplated implementations, nor is it intended to identify the main or critical elements of all implementations or to delineate the scope of all implementations. Its sole purpose is to present, in a simplified form, some concepts of one or more implementations as an introduction to the "Detailed Description of the Invention" presented later.

[0005]

[0005] The first aspect relates to a regenerative circuit. The regenerative circuit includes a first inverting circuit having an input and an output, and a second inverting circuit having an input and an output. The regenerative circuit also includes a first transistor coupled to the input of the second inverting circuit, the gate of which is coupled to the first input, and a second transistor coupled to the input of the first inverting circuit, the gate of which is coupled to the second input. The regenerative circuit further includes a third transistor, the gate of which is coupled to the first input, and a fourth transistor, the gate of which is coupled to the second input. The regeneration circuit further includes a first switch, wherein the first switch and a third transistor are connected in series between a first rail and the first transistor; and a second switch, wherein the second switch and a fourth transistor are connected in series between a first rail and the second transistor.

[0006]

[0006] A second aspect relates to a regenerative circuit. The regenerative circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, the gate of which is coupled to the first input, and a second transistor coupled to the input of the first inverting circuit, the gate of which is coupled to the second input. The regenerative circuit also includes a pull-up circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit, and a pull-down circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit.

[0007]

[0007] A third aspect relates to a method for operating a regeneration circuit of a sampler. The regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, a second transistor coupled to the input of the first inverting circuit, a third transistor, and a fourth transistor. The method includes disabling the regeneration feedback of the first and second inverting circuits during the reset phase. The method also includes enabling the regeneration feedback of the first and second inverting circuits during the regeneration phase, driving the gates of the first transistor and the third transistor with a first voltage, driving the gates of the second transistor and the fourth transistor with a second voltage, and coupling the third transistor to the output of the first inverting circuit or coupling the fourth transistor to the output of the second inverting circuit. [Brief explanation of the drawing]

[0008] [Figure 1]

[0008] An example of a sampler including an input circuit and a regenerative circuit according to a particular aspect of the present disclosure is shown. [Figure 2A]

[0009] This document illustrates exemplary implementations of input circuits according to specific aspects of the present disclosure. [Figure 2B]

[0010] This document illustrates exemplary implementations of a regenerative circuit according to specific aspects of this disclosure. [Figure 2C]

[0011] Another exemplary implementation of the regenerative circuit according to a particular aspect of this disclosure is shown. [Figure 3A]

[0012] This is a timing diagram showing an example of the voltage output from the input circuit to the regeneration circuit according to a particular aspect of this disclosure. [Figure 3B]

[0013] This timing diagram shows another example of the voltage output from the input circuit to the regeneration circuit according to a particular aspect of this disclosure. [Figure 4]

[0014] An example of a regenerative circuit including a pull-up circuit according to a particular aspect of this disclosure is shown. [Figure 5A]

[0015] An example of a regeneration circuit including a pull-down circuit according to a particular aspect of this disclosure is shown. [Figure 5B]

[0016] Another example of a regenerative circuit including a pull-down circuit, according to a particular aspect of this disclosure, is shown. [Figure 6]

[0017] An example of a regenerative circuit including an input transistor providing a pull-up path, according to a particular aspect of this disclosure, is shown. [Figure 7]

[0018] This document illustrates exemplary implementations of input transistors according to specific aspects of this disclosure. [Figure 8]

[0019] This document illustrates exemplary implementations of switches within a regeneration circuit according to specific aspects of this disclosure. [Figure 9A]

[0020] This disclosure illustrates an exemplary implementation of a first inverting circuit within a regenerative circuit according to a particular aspect of this disclosure. [Figure 9B]

[0021] This disclosure illustrates an exemplary implementation of a second inverting circuit within a regenerative circuit according to a particular aspect of this disclosure. [Figure 10]

[0022] This disclosure illustrates an exemplary implementation of a switch in an input circuit according to a particular aspect of this disclosure. [Figure 11]

[0023] Examples of systems in which a particular aspect of this disclosure may be used are given below. [Figure 12]

[0024] This flowchart shows a method for operating a regenerative circuit according to a particular aspect of the present disclosure. [Modes for carrying out the invention]

[0009]

[0025] In connection with the accompanying drawings, the "Modes for Carrying Out the Invention" described below are intended as descriptions of various configurations and are not intended to represent the only configuration capable of practicing the concepts described in this specification. The "Modes for Carrying Out the Invention" include specific details for the purpose of providing a complete understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010]

[0026] FIG. 1 shows an example of a sampler 110 according to a particular aspect of the present disclosure. The sampler 110 can be used, for example, in high-speed SerDes to sample incoming data signals. The sampler 110 may also be referred to as a sense amplifier or by another term. The sampler 110 includes an input circuit 120 and a regeneration circuit 150. The input circuit 120 may also be referred to as an input stage or by another term, and the regeneration circuit 150 may also be referred to as a regeneration stage, a latch (e.g., a cross-coupled latch), or by another term.

[0011]

[0027] As shown in FIG. 1, the input circuit 120 has a first input 130, a second input 135, a first output 140, and a second output 145. The regeneration circuit 150 has a first input 160, a second input 165, a first output 170, and a second output 175. The first input 160 of the regeneration circuit 150 is coupled to the first input 140 of the input circuit 120, and the second input 165 of the regeneration circuit 150 is coupled to the second output 145 of the input circuit 120.

[0012]

[0028] In this example, the input circuit 120 is configured to receive a differential input signal (e.g., a differential data signal) including a first input voltage INP and a second input voltage INN. The first input voltage INP is received at the first input 130, and the second input voltage INN is received at the second input 135. The differential input signal may have small differential voltages where the polarity of the differential voltages represents a bit value (i.e., a small difference between the first input voltage INP and the second input voltage INN). In the SerDes example, the sampler 110 may be integrated on the first chip coupled to a second chip via a link, and the sampler may receive the differential input signal from a transmitter on the second chip via the link.

[0013]

[0029] The input circuit 120 generates a first voltage DINT at the first output 140 and a second voltage NDINT at the second output 145, based on a first input voltage INP and a second input voltage INN. As will be further described below, the input circuit 120 is configured to set the first voltage DINT and the second voltage NDINT to the reset voltage (e.g., supply voltage) during the reset phase and to vary the first voltage DINT and the second voltage NDINT at different rates (e.g., discharge) based on the first input voltage INP and the second input voltage INN during the regeneration phase.

[0014]

[0030] The regeneration circuit 150 is configured to receive a first voltage DINT at a first input 160 and a second voltage NDINT at a second input 165. As will be further described below, during the regeneration phase, the regeneration circuit 150 is configured to use regeneration feedback to convert the first voltage DINT and the second voltage NDINT into differential output voltages. The differential output signal includes a first output voltage OUTP at a first output 170 and a second output voltage OUTN at a second output 175, where the polarity of the differential output voltages represents the captured (i.e., determined) bit value. For high-speed applications, it is desirable for the regeneration circuit 150 to rapidly convert the first voltage DINT and the second voltage NDINT into a large differential output voltage (i.e., a large difference between the first output voltage OUTP and the second output voltage OUTN) during the regeneration phase in order to quickly determine the bit value.

[0015]

[0031] The first output 170 and the second output 175 of the regeneration circuit 150 may be coupled to a latch (not shown) configured to latch the captured bit values ​​from the sampler 110. The latch may include a set-reset (SR) latch or another type of latch.

[0016]

[0032] Figure 2A shows an exemplary implementation of the input circuit 120 in a particular embodiment. The input circuit 120 includes a first input transistor 210, a second input transistor 220, a first switch 230, a second switch 240, and a third switch 245. The second switch 240 is coupled between the upper rail 280 and the first input transistor 210, and the third switch 245 is coupled between the upper rail 280 and the second input transistor 220. The first input transistor 210 is coupled between the second switch 240 and node 226, and the second input transistor 220 is coupled between the third switch 245 and node 226. The first switch 230 is coupled between node 226 and the lower rail 285. In one example, the upper rail 280 may supply a supply voltage VCC, and the lower rail 285 may be coupled to ground. Generally, the upper rail 280 is at a higher potential than the lower rail 285. The upper rail 280 is sometimes referred to as the supply rail or by other terms.

[0017]

[0033] In the example shown in Figure 2A, the first input transistor 210 is implemented as a first n-type field-effect transistor (NFET), and the second input transistor 220 is implemented as a second NFET. It should be understood that the first and second input transistors 210 and 220 are not limited to NFETs and may be implemented as other types of transistors. In this example, the second switch 240 is coupled between the upper rail 280 and the drain of the first input transistor 210, and the first switch 230 is coupled between the source of the first input transistor 210 and the lower rail 285. The gate of the first input transistor 210 is coupled to the first input 130 of the input circuit 120, and thus receives the first input voltage INP. Also in this example, the third switch 245 is coupled between the upper rail 280 and the drain of the second input transistor 220, and the first switch 230 is coupled between the source of the second input transistor 220 and the lower rail 285. The gate of the second input transistor 220 is coupled to the second input 135 of the input circuit 120, and thus receives the second input voltage INN.

[0018]

[0034] The first switch 230 has a control input 235 driven by a timing signal, the second switch 240 has a control input 242 driven by a timing signal, and the third switch 245 has a control input 247 driven by a timing signal. In one example, the first switch 230 is configured to turn on when the timing signal is high and to turn off when the timing signal is low, and each of the second switch 240 and the third switch 245 is configured to turn on when the timing signal is low and to turn off when the timing signal is high. In the example shown in Figure 2A, the timing signal is a clock signal CLK. As used herein, a “clock signal” is a periodic signal that oscillates between a high logic state and a low logic state. In certain embodiments, a high logic state (i.e., a logic state of 1) may correspond to a voltage approximately equal to the supply voltage VCC, and a low logic state (i.e., a logic state of 0) may correspond to a voltage approximately equal to ground.

[0019]

[0035] As used herein, the “control input” of a switch is an input that controls the on / off state of the switch based on a signal (e.g., a voltage signal) at the control input. In the example where the switch is implemented with a transistor, the control input is located at the gate of the transistor. In one example, the first switch 230 may be implemented using an NFET, and the second switch 240 and the third switch 245 may each be implemented using their respective PFETs. However, it should be understood that this disclosure is not limited to this embodiment.

[0020]

[0036] In this example, the first output 140 is coupled to the first node 222 between the second switch 240 and the first input transistor 210, and the second output 145 is coupled to the second node 224 between the third switch 245 and the second input transistor 220. As described above, the input circuit 120 outputs a first voltage DINT at the first output 140 and a second voltage NDINT at the second output 145. In the example in Figure 1, the first output 140 is coupled to the drain of the first input transistor 210, and the second output 145 is coupled to the drain of the second input transistor 220.

[0021]

[0037] Figure 2B shows an exemplary implementation of the regenerative circuit 150 in a particular embodiment. In this example, the regenerative circuit 150 includes a first input transistor 250, a second input transistor 255, a first switch 290, a second switch 295, a first inverting circuit 260, and a second inverting circuit 270. As will be discussed further below, the first inverting circuit 260 and the second inverting circuit 270 are cross-coupled during the regenerative phase to produce regenerative feedback. As used herein, “inverting circuit” is a circuit configured to invert a logic state (i.e., a logic level or logic value) at the input of an inverting circuit and output the inverted logic state at the output of the inverting circuit. A logic state can be represented by a voltage that can represent a logic state of zero at a low voltage (e.g., nearly ground) and a logic state of one at a high voltage (e.g., nearly supply voltage). In certain embodiments, an inverting circuit has a threshold voltage, and when the voltage at the input of the inverting circuit falls below the threshold voltage, the output of the inverting circuit transitions from low to high, and when the voltage at the input of the inverting circuit rises above the threshold voltage, the output of the inverting circuit transitions from high to low. An inverting circuit may also be called an inverter, an inverting circuit, or by other terms.

[0022]

[0038] The first inverting circuit 260 has an input 262, an output 264, a first supply terminal 266, and a second supply terminal 268. The second inverting circuit 270 has an input 272, an output 274, a first supply terminal 276, and a second supply terminal 278. The first supply terminal 266 of the first inverting circuit 260 and the first supply terminal 276 of the second inverting circuit 270 are coupled to the upper rail 280. The second supply terminal 268 of the first inverting circuit 260 and the second supply terminal 278 of the second inverting circuit 270 are coupled to the lower rail 285 (for example, ground).

[0023]

[0039] The first switch 290 is coupled between the input 272 of the second inverting circuit 270 and the output 264 of the first inverting circuit 260, and the second switch 295 is coupled between the input 262 of the first inverting circuit 260 and the output 274 of the second inverting circuit 270. When the first switch 290 and the second switch 295 are turned on, the first inverting circuit 260 and the second inverting circuit 270 are cross-coupled, with the input 272 of the second inverting circuit 260 coupled to the output 264 of the first inverting circuit 260 via the first switch 290, and the input 262 of the first inverting circuit 270 coupled to the output 274 of the second inverting circuit 270 via the second switch 295. As will be further explained below, the first switch 290 and the second switch 295 are turned on during the regeneration phase to enable regeneration feedback for the first inverter 260 and the second inverter 270, and the first switch 290 and the second switch 295 are turned off during the reset phase to disable regeneration feedback for the first inverter 260 and the second inverter 270. Each of the first switch 290 and the second switch 295 may be implemented using their respective transistors (e.g., their respective NFETs), their respective transmission gates, or other types of switches.

[0024]

[0040] The first input transistor 250 is coupled between the input 272 of the second inverting circuit 270 and the lower rail 285. The gate of the first input transistor 250 is coupled to the first input 160 of the regenerative circuit 150. Thus, the gate of the first input transistor 250 is configured to receive a first voltage DINT (i.e., a first input signal to the regenerative circuit 150). In one example, the first input transistor 250 is configured to turn on when the voltage DINT exceeds the threshold voltage of the first input transistor 250 and to turn off when the voltage DINT falls below the threshold voltage of the first input transistor 250. In the example shown in Figure 2B, the first input transistor 250 is implemented as an NFET, with the drain of the first input transistor 250 coupled to the input 272 of the second inverting circuit 270 and the source of the first input transistor 250 coupled to the lower rail 285. Also, the first switch 290 is coupled between the output 264 of the first inverting circuit 260 and the drain of the first input transistor 250. It should be understood that the first input transistor 250 can also be implemented using a different type of transistor. In this example, the first output 170 is coupled to the output 264 of the first inverting circuit 260.

[0025]

[0041] The second input transistor 255 is coupled between the input 262 of the first inverting circuit 260 and the lower rail 285. The gate of the second input transistor 255 is coupled to the second input 165 of the regenerative circuit 150. Thus, the gate of the second input transistor 255 is configured to receive the second voltage NDINT (i.e., the second input signal to the regenerative circuit 150). In one example, the second input transistor 255 is configured to turn on when the voltage NDINT exceeds the threshold voltage of the second input transistor 255 and to turn off when the voltage NDINT falls below the threshold voltage of the second input transistor 255. In the example shown in Figure 2B, the second input transistor 255 is implemented as an NFET, with its drain coupled to the input 262 of the first inverting circuit 260 and its source coupled to the lower rail 285. Additionally, a second switch 295 is coupled between the output 274 of the second inverting circuit 270 and the drain of the second input transistor 255. It should be understood that the second input transistor 255 can also be implemented using a different type of transistor. In this example, the second output 175 is coupled to the output 274 of the second inverting circuit 270.

[0026]

[0042] In the example shown in Figure 2B, the first switch 290 has a control input 292 driven by a timing signal, and the second switch 295 has a control input 297 driven by a timing signal (e.g., a clock signal CLK). In one example, the first switch 290 and the second switch 295 are configured to turn on when the timing signal is high and to turn off when the timing signal is low. Thus, in this example, when the first switch 230 of the input circuit 120 is turned on, the first switch 290 and the second switch 295 are turned on, and when the second switch 240 and the third switch 245 of the input circuit 120 are turned on, the first switch 290 and the second switch 295 are turned off. In an example where each of the first switch 290 and the second switch 295 is implemented by its respective transistor, the respective control inputs 292 and 297 of the first switch 290 and the second switch 295 are located at the gates of their respective transistors. In one example, the first switch 290 and the second switch 295 can each be implemented using their respective NFETs.

[0027]

[0043] Here, the exemplary operation of sampler 110 will be discussed according to a specific embodiment.

[0028]

[0044] When the timing signal (e.g., clock signal CLK) is low, the sampler 110 is in the reset phase. In the reset phase, the first switch 230 of the input circuit 120 is turned off. As a result, the first switch 230 disconnects the first input transistor 210 and the second input transistor 220 of the input circuit 120 from the lower rail 285 (e.g., ground). The second switch 240 and the third switch 245 are turned on. As a result, the second switch 240 couples the first output 140 to the upper rail 280, and the third switch 245 couples the second output 145 to the upper rail 280. This causes the input circuit 120 to pull up the first output 140 and the second output 145 to the supply voltage VCC on the upper rail 280. Therefore, both the first voltage DINT input to the gate of the first input transistor 250 of the regeneration circuit 150, and the second voltage NDINT input to the gate of the second input transistor 255 of the regeneration circuit 150, are pulled up to VCC during the reset phase.

[0029]

[0045] Furthermore, during the reset phase, the first switch 290 and the second switch 295 of the regeneration circuit 150 are turned off. As a result, the regeneration feedback in the regeneration circuit 150 is disabled (i.e., the cross-coupling of the inverting circuits 260 and 270 is disconnected). In addition, (assuming VCC is greater than the threshold voltage of the first input transistor 250 and the threshold voltage of the second input transistor 255) both voltages DINT and NDINT are pulled up to the supply voltage VCC, so both the first input transistor 250 and the second input transistor 255 of the regeneration circuit 150 are turned on. As a result, the inputs 262 and 272 of the inverting circuits 260 and 270 are pulled low (e.g., to ground). This pulls the outputs 264 and 274 of the inverting circuits 260 and 270 high. In this example, the first output 170 and the second output 175 of the regeneration circuit 150 are also pulled high.

[0030]

[0046] When the timing signal (e.g., the clock signal CLK) transitions from low to high, the sampler 110 transitions to the regeneration phase, during which the input circuit 120 senses differential input signals (e.g., differential data signals) at inputs 130 and 135 of the input circuit 120. Figure 3A shows an example of voltages DINT and NDINT during the regeneration phase when the input voltage INP is higher than the input voltage INN, which may represent a bit value of 1. In this example, the timing signal (e.g., the clock signal CLK) transitions from low to high at time T1. Also in this example, the first input transistor 250 and the second input transistor 255 have the same threshold voltage 310 as shown in Figure 3.

[0031]

[0047] At time T1, the first switch 230 is turned on, and the second switch 240 and the third switch 245 are turned off. This allows the first input transistor 210 to pull down the voltage DINT based on the input voltage INP at the first input transistor 210, and the second input transistor 220 to pull down the voltage NDINT based on the input voltage INN at the second input transistor 220. In this example, the voltage DINT is pulled down (i.e., at a faster rate than the voltage NDINT). This is because, in this example, the first input transistor 210 is driven by a higher voltage than the second input transistor 220 (i.e., INP > INN).

[0032]

[0048] At time T2, the voltage DINT falls below the threshold voltage 310, causing the first input transistor 250 of the regeneration circuit 150 to turn off. Since the voltage NDINT is still above the threshold voltage at time T2, the second input transistor 255 of the regeneration circuit 150 remains on at time T2. Starting from time T2, the regeneration feedback of the regeneration circuit 150 pulls up the first output 170 and pulls down the second output 175 (for example, pulling the first output 170 toward the supply voltage VCC and pulling the second output 175 toward ground). The pull-up of the first output 170 and the pull-down of the second output 175 generate a differential output voltage at outputs 170 and 175, where the output voltage OUTP is higher than the output voltage OUTN, which may represent a bit value of 1.

[0033]

[0049] Figure 3A shows the voltages DINT and NDINT when the input voltage INP is higher than the input voltage INN. Figure 3B shows the voltages DINT and NDINT when the input voltage INN is higher than the input voltage INP. In this case, the voltage NDINT at the second output 145 of the input circuit 120 drops at a faster rate than the voltage DINT at the first output 140 of the input circuit 120 during the regeneration phase. As a result, the voltage NDINT falls below the threshold voltage 310 before the voltage DINT, causing the second input transistor 255 to turn off before the first input transistor 250. When this occurs, the regeneration feedback of the regeneration circuit 150 pulls up the second output 175 and pulls down the first output 170, resulting in a large differential output voltage where the output voltage OUTN is higher than the output voltage OUTP, which may represent a zero bit decision.

[0034]

[0050] In both cases, it is desirable that the regeneration circuit 150 rapidly generates a large differential output voltage at outputs 170 and 175 during the regeneration phase in order to quickly determine (i.e., capture) the bit value. A latch (e.g., an SR latch) coupled to outputs 170 and 175 of the regeneration circuit 150 can latch the bit value determined as described above. When the timing signal transitions back from high to low, the sampler 110 enters the reset phase again to reset the sampler 110 for the next bit value.

[0035]

[0051] As described above, in the example of Figure 2B, the first switch 290 and the second switch 295 are used to enable the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270 during the regeneration phase and to disable the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270 during the reset phase. The first switch 290 and the second switch 295 disable the regenerative feedback during the reset phase by disconnecting the cross coupling of the first inverter circuit 260 and the second inverter circuit 270 when the first switch 290 and the second switch 295 are turned off. However, it should be understood that this disclosure is not limited to this embodiment. In general, the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270 can be enabled or disabled using one or more switches located in one or more places within the regeneration circuit 150, one or more of which are controlled by timing signals (e.g., clock signal CLK).

[0036]

[0052] In this regard, Figure 2C shows an exemplary implementation of the regeneration circuit 150, which includes a switch 296 coupled between the upper rail 280 and the power terminals 266 and 276 of the inverting circuits 260 and 270. In this example, the first switch 290 and the second switch 295 shown in Figure 2B are omitted, and the output 264 of the first inverting circuit 260 is coupled to the first input transistor 250, and the output 274 of the second inverting circuit 270 is coupled to the second input transistor 255. The switch 296 may be implemented using a PFET and has a control input 298 driven by the inversion of a timing signal (e.g., an inverting clock signal CLKb). In this example, the switch 296 is configured to be off during the reset phase and on during the regeneration phase. Turning off the switch 296 during the reset phase removes power from the upper rail 280 to the inverting circuits 260 and 270, thereby disabling the regeneration feedback of the first inverting circuit 260 and the second inverting circuit 270. Please understand that this disclosure is not limited to the examples shown in Figures 2B and 2C.

[0037]

[0053] Figure 4 shows an example in which the regeneration circuit 150 further includes a pull-up circuit 405 in a particular embodiment. The pull-up circuit 405 is configured to increase the regeneration gain of the regeneration circuit 150 by providing an additional pull-up path during the regeneration phase. The pull-up circuit 405 includes a first pull-up transistor 410 and a second pull-up transistor 420 in a particular embodiment of the present disclosure.

[0038]

[0054] In the example in Figure 4, the first pull-up transistor 410 is implemented as a first PFET, and the second pull-up transistor 420 is implemented as a second PFET. The source of the first pull-up transistor 410 is coupled to rail 280, the drain of the first pull-up transistor 410 is coupled to input 262 of the first inverting circuit 260, and the gate of the first pull-up transistor 410 is coupled to output 264 of the first inverting circuit 260. The source of the second pull-up transistor 420 is coupled to rail 280, the drain of the second pull-up transistor 420 is coupled to input 272 of the second inverting circuit 270, and the gate of the second pull-up transistor 420 is coupled to output 274 of the second inverting circuit 270.

[0039]

[0055] Here, the exemplary operation of the pull-up circuit 405 will be discussed according to a specific embodiment.

[0040]

[0056] If the voltage DINT drops faster than the voltage NDINT during the regeneration phase (for example, if INP > INN at inputs 130 and 135 of input circuit 120), the first input transistor 250 turns off before the second input transistor 255. This triggers the regeneration feedback of regeneration circuit 150, pulling up the first output 170 and pulling down the second output 175. Since the gate of the second pull-up transistor 420 is coupled to the second output 175, the pull-down of the second output 175 turns on the second pull-up transistor 420. This causes the second pull-up transistor 420 to pull up input 272 of the second inverter circuit 270 toward the supply voltage VCC on rail 280, which helps the second inverter circuit 270 drive its output 274 low. Since the output 274 of the second inverter circuit 270 is coupled to the second output 175, driving the output 274 of the second inverter circuit 270 low helps to further pull down the second output 175, thereby increasing the regeneration gain of the regeneration circuit 150. Thus, in this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input 272 of the second inverter circuit 270 during the regeneration phase, which increases the regeneration gain.

[0041]

[0057] If the voltage NDINT drops faster than the voltage DINT during the regeneration phase (for example, if INN > INP at inputs 130 and 135 of input circuit 120), the second input transistor 255 turns off before the first input transistor 250. This triggers the regeneration feedback of regeneration circuit 150, pulling up the second output 175 and pulling down the first output 170. Since the gate of the first pull-up transistor 410 is coupled to the first output 170, the pull-down of the first output 170 turns on the first pull-up transistor 410. This causes the first pull-up transistor 410 to pull up input 262 of the first inverter circuit 260 toward the supply voltage VCC on rail 280, which helps the first inverter circuit 260 drive its output 264 low. Since the output 264 of the first inverting circuit 260 is coupled to the first output 170, driving the output 264 of the first inverting circuit 260 lower helps to further pull down the first output 170, thereby increasing the regeneration gain of the regeneration circuit 150. In this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input 262 of the first inverting circuit 260 during the regeneration phase, which increases the regeneration gain.

[0042]

[0058] Therefore, the pull-up circuit 405 is configured to provide an additional pull-up path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. The pull-up path is between rail 280 and the input 272 of the second inverter circuit 270 when voltage DINT falls faster than voltage NDINT (e.g., INP > INN), and between rail 280 and the input 262 of the first inverter circuit 260 when voltage NDINT falls faster than voltage DINT (e.g., INN > INN).

[0043]

[0059] To further increase the regeneration gain of the regeneration circuit 150, a pull-down circuit can be added to the regeneration circuit 150. In this regard, Figure 5A shows an example in which the regeneration circuit 150 further includes a pull-down circuit 505 in a particular embodiment. The pull-down circuit 505 is configured to provide an additional pull-down path during the regeneration phase in order to increase the regeneration gain of the regeneration circuit 150, thereby increasing the signal strength at outputs 170 and 175 of the regeneration circuit 150. The pull-down circuit 505 may be used in combination with a pull-up circuit 405 to increase the regeneration gain, as will be further described below. The pull-down circuit 505 includes a first pull-down transistor 510 and a second pull-down transistor 520 in a particular embodiment of the present disclosure.

[0044]

[0060] In the example shown in Figure 5A, the first pull-down transistor 510 is implemented as a first NFET, and the second pull-down transistor 520 is implemented as a second NFET. The drain of the first pull-down transistor 510 is coupled to the input 262 of the first inverting circuit 260, the source of the first pull-down transistor 510 is coupled to the lower rail 285 (e.g., ground), and the gate of the first pull-down transistor 510 is coupled to the input 272 and the first output 170 of the second inverting circuit 270. The drain of the second pull-down transistor 520 is coupled to the input 272 of the second inverting circuit 270, the source of the second pull-down transistor 520 is coupled to the lower rail 285, and the gate of the second pull-down transistor 520 is coupled to the input 262 and the second output 175 of the first inverting circuit 260. In other words, the first pull-down transistor 510 and the second pull-down transistor 520 are cross-coupled.

[0045]

[0061] Here, the exemplary operation of the pull-down circuit 505 will be discussed according to a specific embodiment.

[0046]

[0062] If the voltage DINT drops faster than the voltage NDINT during the regeneration phase (for example, if INP > INN at inputs 130 and 135 of input circuit 120), the first input transistor 250 turns off before the second input transistor 255. This triggers the regeneration feedback of regeneration circuit 150, pulling up the first output 170 and pulling down the second output 175. Since the gate of the first pull-down transistor 510 is coupled to the first output 170, the pull-up of the first output 170 turns on the first pull-down transistor 510. This causes the first pull-down transistor 510 to pull down input 262 of the first inverter circuit 260, which helps the first inverter circuit 260 drive output 264 high. Since the output 264 of the first inverting circuit 260 is coupled to the first output 170, driving the output 264 of the first inverting circuit 260 high helps to further pull up the first output 170, thereby increasing the regeneration gain. In this case, the pull-down circuit 505 provides an additional pull-down path between the input 262 of the first inverting circuit 260 and the lower rail 285 (e.g., ground) during the regeneration phase, which increases the regeneration gain.

[0047]

[0063] If the voltage NDINT drops faster than the voltage DINT during the regeneration phase (for example, if INN > INP at inputs 130 and 135 of input circuit 120), the second input transistor 255 turns off before the first input transistor 250. This triggers the regeneration feedback of regeneration circuit 150, pulling up the second output 175 and pulling down the first output 170. Since the gate of the second pull-down transistor 520 is coupled to the second output 175, the pull-up of the second output 175 turns on the second pull-down transistor 520. This causes the second pull-down transistor 520 to pull down input 272 of the second inverter circuit 270, which helps the second inverter circuit 270 drive output 274 high. Since the output 274 of the second inverter circuit 270 is coupled to the second output 175, driving the output 274 of the second inverter circuit 270 high helps to further pull up the second output 175, thereby increasing the regeneration gain. In this case, the pull-down circuit 505 provides an additional pull-down path between the input 272 of the second inverter circuit 270 and the lower rail 285 (e.g., ground) during the regeneration phase, which increases the regeneration gain.

[0048]

[0064] Therefore, the pull-down circuit 505 is configured to provide an additional pull-down path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. The pull-down path is between the input 262 of the first inverter circuit 260 and the lower rail 285 (e.g., ground) when the voltage DINT falls faster than the voltage NDINT (e.g., INP > INN), and the pull-down path is between the input 272 of the second inverter circuit 270 when the voltage NDINT falls faster than the voltage DINT (e.g., INN > INN).

[0049]

[0065] The pull-down circuit 505 can be used in combination with the pull-up circuit 405 to increase the regeneration gain of the regeneration circuit 150, thereby increasing the signal strength at outputs 170 and 175 of the regeneration circuit 150. For example, if voltage DINT falls faster than voltage NDINT (e.g., INP > INN), the pull-up circuit 405 provides an additional pull-up path to pull up input 272 of the second inverting circuit 270, while the pull-down circuit 505 provides an additional pull-down path to pull down input 262 of the first inverting circuit 260. Therefore, in these embodiments, depending on which of the voltages DINT and NDINT falls faster, and thus depending on the input voltages INP and INN of the input circuit 120, the pull-up circuit 405 pulls up one input of the inverting circuits 260 and 270, and the pull-down circuit 505 pulls down the other input of the inverting circuits 260 and 270.

[0050]

[0066] Another advantage of the pull-up circuit 405 and pull-down circuit 505 is that they continue to provide regenerative gain during the first part of the reset phase before the input transistors 250 and 255 are turned on (i.e., before the input circuit 120 raises voltages DINT and NDINT to exceed the threshold voltages of input transistors 250 and 255). This is because even if switches 290 and 295 are turned off by timing signals (e.g., the clock signal CLK), the pull-up circuit 405 and pull-down circuit 505 continue to provide additional pull-up and additional pull-down paths. The regenerative gain that continues during the first part of the reset phase allows the differential output voltage of the regenerative circuit 150 to continue increasing in order to better determine the corresponding bit values.

[0051]

[0067] It should be understood that the pull-down circuit 505 is not limited to the exemplary implementation shown in Figure 5A. In this regard, Figure 5B shows another exemplary implementation in which the gate of the first pull-down transistor 510 is coupled to the output 264 of the first inverting circuit 260, and the gate of the second pull-down transistor 520 is coupled to the output 274 of the second inverting circuit 270. Similar to the exemplary implementation shown in Figure 5A, the pull-down transistors 510 and 520 in this example provide an additional pull-down path to increase the regeneration gain.

[0052]

[0068] As described above, the pull-up circuit 405 increases the regeneration gain of the regeneration circuit 150 by providing an additional pull-up path during the regeneration phase. The strength of the pull-up path can be increased by increasing the size (e.g., channel width) of the pull-up transistors 410 and 420, thereby further increasing the regeneration gain of the regeneration circuit 150. However, increasing the size of the pull-up transistors 410 and 420 increases the reset time of the regeneration circuit 150, as will be discussed further below, resulting in a trade-off between regeneration and reset.

[0053]

[0069] At the start of the reset phase, the input circuit 120 increases voltages DINT and NDINT, which are input to input transistors 250 and 255 of the regeneration circuit 150. When voltages DINT and NDINT rise to the threshold voltages of input transistors 250 and 255, input transistors 250 and 255 turn on, pulling both inputs 262 and 272 of the inverting circuits 260 and 270 low. However, one of the pull-up transistors 410 and 420 is initially on, resisting the ability of input transistors 250 and 255 to pull both inputs 262 and 272 of the inverting circuits 260 and 270 low, which increases the reset time. Increasing the size of pull-up transistors 410 and 420 to further increase the regeneration gain exacerbates this problem by making it more difficult for input transistors 250 and 255 to pull both inputs 262 and 272 of the inverting circuits 260 and 270 low in order to reset the regeneration circuit 150. Therefore, a trade-off exists between regeneration and reset associated with pull-up transistors 410 and 420.

[0054]

[0070] To address the above, Figure 6 shows an example in which the regeneration circuit 150 further includes a third input transistor 610 and a fourth input transistor 620, which mitigate the trade-off between regeneration and reset and increase sensitivity, as will be further explained below. In this example, the regeneration circuit 150 also includes a third switch 630 and a fourth switch 640.

[0055]

[0071] The gate of the third input transistor 610 is coupled to the first input 160 of the regeneration circuit 150, and thus receives the first voltage DINT. The third input transistor 610 and the third switch 630 are coupled in series between the rail 280 and the first output 170 of the regeneration circuit 150. In the example of Figure 6, the third input transistor 610 is implemented as a PFET, the source of the third input transistor 610 is coupled to the rail 280, and the third switch 630 is coupled between the drain of the third input transistor 610 and the first input transistor 250. In the example where the third input transistor 610 is implemented as a PFET, the third input transistor 610 may be configured to turn on when the first voltage DINT falls below VCC-Vt3, where Vt3 is the threshold voltage of the third input transistor 610.

[0056]

[0072] The third switch 630 has a control input 635 coupled to the input 262 of the first inverting circuit 260. In certain embodiments, the third switch 630 is configured to turn on when the voltage at the control input 635 falls below a threshold of the third switch 630, and to turn off when the voltage at the control input 635 rises above the threshold of the third switch 630, as will be further described below. The third switch 630 may be implemented with each PFET or with another type of switch.

[0057]

[0073] The gate of the fourth input transistor 620 is coupled to the second input 165 of the regeneration circuit 150, and thus receives the second voltage NDINT. The fourth input transistor 620 and the fourth switch 640 are coupled in series between the rail 280 and the second output 175 of the regeneration circuit 150. In the example of Figure 6, the fourth input transistor 620 is implemented as a PFET, the source of the fourth input transistor 620 is coupled to the rail 280, and the fourth switch 640 is coupled between the drain of the fourth input transistor 620 and the second input transistor 255. In the example where the fourth input transistor 620 is implemented as a PFET, the fourth input transistor 620 may be configured to turn on when the second voltage NDINT falls below VCC-Vt4, where Vt4 is the threshold voltage of the fourth input transistor 620. In certain embodiments, Vt3 and Vt4 may be approximately equal.

[0058]

[0074] The fourth switch 640 has a control input 645 coupled to the input 272 of the second inverting circuit 270. In certain embodiments, the fourth switch 640 is configured to turn on when the voltage at the control input 645 falls below a threshold value of the fourth switch 640, and to turn off when the voltage at the control input 645 rises above a threshold value of the fourth switch 640, as will be further described below. The fourth switch 640 may be implemented in each PFET or in another type of switch.

[0059]

[0075] Here, the exemplary operation of the exemplary regeneration circuit 150 shown in Figure 6 will be discussed according to a specific embodiment.

[0060]

[0076] During the reset phase, the input circuit 120 pulls voltages DINT and NDINT to the supply voltage VCC, as discussed above. This turns on the first input transistor 250 and the second input transistor 255 of the regeneration circuit 150, and pulls the inputs 262 and 272 of the inverting circuits 260 and 270 low. This also turns off the third and fourth input transistors 610 and 620 of the regeneration circuit 150, as these transistors are implemented as PFETs. Thus, in this example, the inputs 262 and 272 of the inverting circuits 260 and 270 are reset to low (e.g., nearly ground). In addition, both the third switch 630 and the fourth switch 640 are on. This is because the input transistors 610 and 620 pull the control inputs 635 and 645 of the third and fourth switches 630 and 640 low during the reset phase.

[0061]

[0077] When the sampler 110 transitions to the regeneration phase, a timing signal (e.g., a clock signal CLK) turns on the first switch 290 and the second switch 295, activating the regeneration feedback loop via the inverting circuits 260 and 270. At the start of the regeneration phase, both the first input transistor 250 and the second input transistor 255 are on, and both the third and fourth input transistors 610 and 620 are off. In addition, both the third switch 630 and the fourth switch 640 are on.

[0062]

[0078] If the input voltage INP is higher than the input voltage INN, the first voltage DINT decreases (i.e., discharges) at a faster rate than the second voltage NDINT. This causes the first input transistor 250 to turn off before the second input transistor 255 and the third input transistor 610 to turn on before the fourth input transistor 620. Turning off the first input transistor 250 triggers the regenerative feedback of the regenerative circuit 150, pulling up the first output 170 and pulling down the second output 175 (for example, pulling the first output 170 toward the supply voltage VCC and pulling the second output 175 toward ground). By turning on the third input transistor 610, the third input transistor 610 pulls up the first output 170 via the (turned-on) third switch 630. Thus, in this case, the third input transistor 610 and the third switch 630 provide an additional pull-up path for pulling up the first output 170, which increases the regenerative gain.

[0063]

[0079] Since the control input 645 of the fourth switch 640 is coupled to the first output 170, pulling up the first output 170 turns off the fourth switch 640. This prevents the fourth input transistor 620 from pulling up the second output 175 when the fourth input transistor 620 is finally turned on (i.e., when NDINT falls below VCC-Vt4), allowing the regeneration of the regeneration circuit 150 to pull the second output 175 low.

[0064]

[0080] If the input voltage INN is higher than the input voltage INP, the second voltage NDINT drops (i.e., discharges) at a faster rate than the first voltage DINT. This causes the second input transistor 255 to turn off before the first input transistor 250 and the fourth input transistor 620 to turn on before the third input transistor 610. Turning off the second input transistor 255 triggers the regenerative feedback of the regenerative circuit 150, pulling up the second output 175 and pulling down the first output 170 (for example, pulling the second output 175 toward the supply voltage VCC and pulling the first output 170 toward ground). By turning on the fourth input transistor 620, the fourth input transistor 620 pulls up the second output 175 via the (turned-on) fourth switch 640. Thus, in this case, the fourth input transistor 620 and the fourth switch 640 provide an additional pull-up path for pulling up the second output 175, which increases the regenerative gain.

[0065]

[0081] Since the control input 635 of the third switch 630 is coupled to the second output 175, pulling up the second output 175 turns off the third switch 630. This prevents the third input transistor 610 from pulling up the first output 170 when the third input transistor 610 is finally turned on (i.e., when DINT falls below VCC-Vt3), allowing the regeneration of the regeneration circuit 150 to pull the first output 170 low.

[0066]

[0082] Therefore, the third input transistor 610 and the fourth input transistor 620 provide additional pull-up paths during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. If voltage DINT falls faster than voltage NDINT (e.g., INP > INN), the third input transistor 610 provides an additional pull-up path between the first output 170 and rail 280 via the third switch 630. If voltage NDINT falls faster than voltage DINT (e.g., INN > INN), the fourth input transistor 620 provides an additional pull-up path between the second output 175 and rail 280 via the fourth switch 640.

[0067]

[0083] The third input transistor 610 and the fourth input transistor 620 enable the regeneration circuit 150 to achieve a higher regeneration gain without requiring an increase in the size (e.g., channel width) of the first pull-up transistor 410 and the second pull-up transistor 420, thereby mitigating the trade-off between regeneration and reset associated with the pull-up transistors 410 and 420. This is because the third input transistor 610 and the fourth input transistor 620 provide an additional pull-up path during the regeneration phase, in parallel with the additional pull-up path provided by the pull-up transistors 410 and 420. This increases the pull-up strength of regeneration in the regeneration circuit 150 without requiring an increase in the size of the first pull-up transistor 410 and the second pull-up transistor 420.

[0068]

[0084] In addition, the input circuit 120 turns off both the third input transistor 610 and the fourth input transistor 620 during the reset phase, allowing the first input transistor 250 and the second input transistor 255 to pull both inputs 262 and 272 of the inverting circuits 260 and 270 low to reset the regeneration circuit 150 during the reset phase. This is because the input circuit 120 pulls voltages DINT and NDINT to the supply voltage VCC during the reset phase, thereby turning off both the third input transistor 610 and the fourth input transistor 620. When the input circuit 120 turns off the third input transistor 610 and the fourth input transistor 620 during the reset phase, these transistors no longer resist the ability of the first input transistor 250 and the second input transistor 255 to pull both inputs 262 and 272 of the inverting circuits 260 and 270 low during the reset phase. This further reduces the trade-off between regeneration and reset.

[0069]

[0085] The third input transistor 610 and the fourth input transistor 620 also increase the sensitivity of the sampler 110. This is because the gates of the third input transistor 610 and the fourth input transistor 620 are driven by voltages DINT and NDINT, respectively, which are generated based on the sensed input voltages INP and INN.

[0070]

[0086] In the example shown in Figure 6, the third switch 630 is coupled between the third input transistor 610 and the first input transistor 250. However, it should be understood that this disclosure is not limited to this embodiment. For example, in some implementations, the third switch 630 may be coupled between the third input transistor 610 and the upper rail 280, and the third input transistor 610 may be coupled between the third switch 630 and the first input transistor 250. Generally, the third input transistor 610 and the third switch 630 are coupled in series between the upper rail 280 and the first input transistor 250, with either the third input transistor 610 or the third switch 630 on the upper side. Also, in some implementations, the fourth switch 640 may be coupled between the fourth input transistor 620 and the upper rail 280, and the fourth input transistor 620 may be coupled between the fourth switch 640 and the second input transistor 255. Generally, the fourth input transistor 620 and the fourth switch 640 are connected in series between the upper rail 280 and the second input transistor 255, with either the fourth input transistor 620 or the fourth switch 640 on the upper side.

[0071]

[0087] Figure 7 shows exemplary implementations of the third switch 630 and the fourth switch 640. In this example, the third switch 630 is implemented with a first PFET 710 coupled between the drain of the third input transistor 610 and the first input transistor 250, with the gate of the first PFET 710 coupled to the input 262 of the first inverting circuit 260. Also in this example, the fourth switch 640 includes a second PFET 720 coupled between the drain of the fourth input transistor 620 and the second input transistor 255, with the gate of the second PFET 720 coupled to the input 272 of the second inverting circuit 270. It should be understood that the third switch 630 and the fourth switch 640 are not limited to the exemplary implementations shown in Figure 7, and each of the third switch 630 and the fourth switch 640 may be implemented with a different type of transistor, transmission gate, or different type of switch.

[0072]

[0088] Figure 8 shows an example in which the first switch 290 is implemented with the first NFET 810 and the second switch 295 is implemented with the second NFET 820. In this example, one of the source and drain of the first NFET 810 is coupled to the first input transistor 250 (e.g., the drain of the first input transistor 250), the other of the source and drain of the first NFET 810 is coupled to the output 264 of the first inverter circuit 260, and the gate of the first NFET 810 is coupled to a control input 292 for receiving a timing signal (e.g., a clock signal CLK). One of the source and drain of the second NFET 820 is coupled to the second input transistor 255 (e.g., the drain of the second input transistor 255), the other of the source and drain of the second NFET 820 is coupled to the output 274 of the second inverter circuit 270, and the gate of the second NFET 820 is coupled to a control input 297 for receiving a timing signal (e.g., a clock signal CLK). In this example, the first switch 290 and the second switch 295 are turned on when the timing signal is high and turned off when the timing signal is low. It should be understood that the first switch 290 and the second switch 295 are not limited to the exemplary implementation shown in Figure 8, and each of the first switch 290 and the second switch 295 may be implemented with a different type of transistor, transmission gate, or other type of switch.

[0073]

[0089] In the example shown in Figures 4 to 8, the regeneration circuit 150 includes a first switch 290 and a second switch 295 for enabling the regeneration feedback of the inverting circuits 260 and 270 during the regeneration phase and for deactivating the regeneration feedback of the inverting circuits 260 and 270 during the reset phase. However, it should be understood that this disclosure is not limited to this embodiment. For example, in other implementations, the first switch 290 and the second switch 295 may be omitted, and a switch 296, as shown in Figure 2C, may be used to enable or disable the regeneration feedback of the inverting circuits 260 and 270. In this example, the output 264 of the first inverting circuit 260 is coupled to the first input transistor 250, and the output 274 of the second inverting circuit 270 is coupled to the second input transistor 255. In general, one or more switches may be located in one or more places within the regeneration circuit 150 to enable or disable the regeneration feedback of the inverting circuits 260 and 270.

[0074]

[0090] Figure 9A shows an exemplary implementation of the first inverting circuit 260 in a particular embodiment. In this example, the first inverting circuit 260 is a complementary inverting circuit including a PFET 910 and an NFET 920. The source of the PFET 910 is coupled to the first supply terminal 266, the drain of the PFET 910 is coupled to the output 264, and the gate of the PFET 910 is coupled to the input 262. The drain of the NFET 920 is coupled to the output 264, the gate of the NFET 920 is coupled to the input 262, and the source of the NFET 920 is coupled to the second supply terminal 268. It should be understood that the first inverting circuit 260 is not limited to the example shown in Figure 9A.

[0075]

[0091] Figure 9B shows an exemplary implementation of the second inverting circuit 270 in a particular embodiment. In this example, the second inverting circuit 270 is a complementary inverting circuit including a PFET 930 and an NFET 940. The source of the PFET 930 is coupled to the first supply terminal 276, the drain of the PFET 930 is coupled to the output 274, and the gate of the PFET 930 is coupled to the input 272. The drain of the NFET 940 is coupled to the output 274, the gate of the NFET 940 is coupled to the input 272, and the source of the NFET 940 is coupled to the second supply terminal 278. It should be understood that the second inverting circuit 270 is not limited to the example shown in Figure 9B.

[0076]

[0092] Figure 10 shows exemplary implementations of a first switch 230, a second switch 240, and a third switch 245 in the input circuit 120 according to a specific embodiment. In this example, the first switch 230 is implemented with an NFET 1010, the drain of which is coupled to the sources of input transistors 210 and 220, the gate of which is coupled to the control input 235, and the source of which is coupled to the lower rail 285 (e.g., ground). The second switch 240 is implemented with a first PFET 1015, the source of which is coupled to the upper rail 280, the gate of which is coupled to the control input 242, and the drain of which is coupled to the drain of the first input transistor 210. The third switch 245 is implemented with the second PFET 1020, the source of the second PFET 1020 is coupled to the upper rail 280, the gate of the second PFET 1020 is coupled to the control input 247, and the drain of the second PFET 1020 is coupled to the drain of the second input transistor 220. In this example, the first switch 230 is turned on when the timing signal is high and turned off when the timing signal is low. Also in this example, the second switch 240 and the third switch 24 are turned on when the timing signal is low and turned off when the timing signal is high. It should be understood that the first switch 230, the second switch 240, and the third switch 245 are not limited to the exemplary implementation shown in Figure 10.

[0077]

[0093] Figure 11 shows an example of a system 1105 in which embodiments of the present disclosure may be used. In this example, system 1105 includes a first chip 1110 and a second chip 1115, and SerDes may be used for communication between the first chip 1110 and the second chip 1115. The first chip 1110 includes a serializer 1120, a driver 1130, a first output pin 1140, and a second output pin 1142. The second chip 1115 includes a first receive pin 1150, a second receive pin 1152, a receiver 1160, a sampler 110, a latch 1170, and a deserializer 1180.

[0078]

[0094] In this example, the first chip 1110 and the second chip 1115 are connected via a differential serial link including a first line 1144 and a second line 1146. The first line 1144 is connected between the first output pin 1140 and the first receive pin 1150, and the second line 1146 is connected between the second output pin 1142 and the second receive pin 1152. Each of the first line 1144 and the second line 1146 may be mounted on a substrate (e.g., a printed circuit board) as a metal wire, wire, etc.

[0079]

[0095] On the first chip 1110, the serializer 1120 is configured to receive a parallel data stream (for example, from a processor on the first chip 1110) and convert the parallel data stream into a serial data stream, which is output at output 1125 of the serializer 1120. The driver 1130 has an input 1132 coupled to output 1125 of the serializer 1120, a first output 1134 coupled to a first output pin 1140, and a second output 1136 coupled to a second output pin 1142. The driver 1130 is configured to receive the serial data stream, convert the serial data stream into a differential signal, and drive the first line 1144 and the second line 1146 of a differential serial link with the differential data signal to transmit the differential signal to the second chip 1115. It should be understood that the first chip 1110 may include additional components not shown in Figure 11 (e.g., an impedance matching network coupled to output pins 1140 and 1142, a pre-driver coupled between serializer 1120 and driver 1130, etc.).

[0080]

[0096] On the second chip 1115, the receiver 1160 has a first input 1162 coupled to the first receive pin 1150, a second input 1164 coupled to the second receive pin 1152, a first output 1166 coupled to the first input 130 of the sampler 110, and a second output 1168 coupled to the second input 135 of the sampler 110. The receiver 1160 may include at least one of an amplifier and an equalizer (for example, to compensate for frequency-dependent signal attenuation between the first chip 1110 and the second chip 1115). The sampler 110 receives a differential signal from the receiver 1160 as described above and performs bit determination based on the differential signal.

[0081]

[0097] In the example in Figure 11, the first output 170 of sampler 110 is coupled to the first input 1172 of latch 1170, and the second output 175 of sampler 110 is coupled to the second input 1174 of latch 1170. Latch 1170 has an output 1176 coupled to input 1182 of deserializer 1180. Latch 1170 is configured to latch a bit determination from sampler 110 and output the corresponding bit to deserializer 1180. Deserializer 1180 is configured to convert the bit into a parallel data stream, which may be output to one or more components (not shown) on a second chip 1115 for further processing. It should be understood that the second chip 1115 may include additional components not shown in Figure 11 (e.g., an impedance matching network coupled to receive pins 1150 and 1152, a clock restoration circuit, etc.).

[0082]

[0098] In the example in Figure 11, the second chip 1115 also includes a timing signal circuit 1190 configured to generate a timing signal (e.g., a clock signal CLK) for the sampler 110 and output the timing signal at output 1194. Output 1194 may be coupled to the control inputs of switches 230, 240, and 245 in the input circuit 120 and to the control inputs of switches 290 and 295 in the regeneration circuit 150 of the sampler 110.

[0083]

[0099] In certain embodiments, the timing signal circuit 1190 may use clock data recovery to recover a timing signal (e.g., a clock signal CLK) based on a bit determination of the sampler 110. The input 1192 of the timing signal circuit 1190 may be coupled to the output of the latch 1170 (as shown in the example in Figure 11) or to one or both of the outputs 170 and 175 of the sampler 110 to receive the bit determination.

[0084]

[0100] In certain embodiments, the timing signal circuit 1190 may include a clock generator, which may include a phase-locked loop (PLL), a delay-locked loop (DLL), an oscillator, or any combination thereof, to generate a timing signal (e.g., a clock signal CLK). It should be understood that the timing signal circuit 1190 may be implemented using various types of clock generators.

[0085]

[0101] Figure 12 shows a method 1200 for operating a sampler regeneration circuit according to a particular embodiment. The regeneration circuit (e.g., regeneration circuit 150) includes a first inverting circuit (e.g., first inverting circuit 260) having inputs and outputs, a second inverting circuit (e.g., second inverting circuit 270) having inputs and outputs, a first transistor (e.g., first input transistor 250) coupled to the input of the second inverting circuit, a second transistor (e.g., second input transistor 255) coupled to the input of the first inverting circuit, a third transistor (e.g., third input transistor 610), and a fourth transistor (e.g., fourth input transistor 620).

[0086]

[0102] In block 1210, during the reset phase, the regenerative feedback of the first and second inverting circuits is disabled. For example, disabling the regenerative feedback of the first and second inverting circuits may include disconnecting the output of the first inverting circuit from the first transistor and disconnecting the output of the second inverting circuit from the second transistor. For example, the output of the first inverting circuit can be disconnected from the first transistor by turning off the first switch 290 (e.g., using a timing signal), and the output of the second inverting circuit can be disconnected from the second transistor by turning off the second switch 295 (e.g., using a timing signal). In another example, disabling the regenerative feedback of the first and second inverting circuits may include turning off the switch 296 shown in Figure 2C.

[0087]

[0103] In block 1220, during the regeneration phase, regeneration feedback for the first and second inverting circuits is enabled. For example, enabling regeneration feedback for the first and second inverting circuits may include coupling the output of the first inverting circuit to the first transistor and coupling the output of the second inverting circuit to the second transistor. For example, the output of the first inverting circuit may be coupled to the first transistor by turning on the first switch 290 (e.g., using a timing signal), and the output of the second inverting circuit may be coupled to the second transistor by turning on the second switch 295 (e.g., using a timing signal). In another example, enabling regeneration feedback for the first and second inverting circuits may include turning on the switch 296 shown in Figure 2C.

[0088]

[0104] In block 1230, during the regeneration phase, the gates of the first transistor and the third transistor are driven with a first voltage. For example, the input circuit 120 may drive the gates of the first transistor and the third transistor with a first voltage DINT.

[0089]

[0105] In block 1240, during the regeneration phase, the gates of the second transistor and the fourth transistor are driven by a second voltage. For example, the input circuit 120 may drive the gates of the second transistor and the fourth transistor with a second voltage NDINT.

[0090]

[0106] In block 1250, during the regeneration phase, a third transistor is coupled to the output of the first inverting circuit, or a fourth transistor is coupled to the output of the second inverting circuit. For example, a third switch 630 can couple the third transistor to the output of the first inverting circuit, or a fourth switch 640 can couple the fourth transistor to the output of the second inverting circuit.

[0091]

[0107] In certain embodiments, during the regeneration phase, a first voltage decreases at a first rate and a second voltage decreases at a second rate, with the first rate being different from the second rate. For example, the first rate may be based on a first input signal to the sampler (e.g., INP), and the second rate may be based on a second input signal to the sampler (e.g., INN). In one example, the first input transistor 210 of the input circuit 120 can discharge a first node 222 based on the first input signal INP to drop a first voltage DINT at a first rate, and the second input transistor 220 of the input circuit 120 can discharge a second node 224 based on the second input signal INN to drop a second voltage NDINT at a second rate. In this example, the gate of the first input transistor 210 can be driven by the first input signal INP, and the gate of the second input transistor 220 can be driven by the second input signal INN.

[0092]

[0108] In certain embodiments, if the first input signal is greater than the second input signal (e.g., INP > INN), the first rate is greater than the second rate, and if the second input signal is greater than the first input signal (e.g., INN > INN), the second rate is greater than the first rate.

[0093]

[0109] In certain embodiments, coupling a third transistor to the output of a first inverting circuit, or coupling a fourth transistor to the output of a second inverting circuit, includes coupling the third transistor to the output of the first inverting circuit, or coupling the fourth transistor to the output of the second inverting circuit, based on the voltage at the input of the first inverting circuit. For example, the control input 635 of the third switch 630 may be coupled to the input 262 of the first inverting circuit 260, and the control input 645 of the fourth switch 640 may be coupled to the input 272 of the second inverting circuit 270.

[0094]

[0110] Method 1200 may also include pulling up the first voltage and the second voltage to the supply voltage during the reset phase. For example, the first voltage DINT and the second voltage NDINT can be pulled up to the supply voltage VCC by turning on the second switch 240 and the third switch 245 of the input circuit 120 during the reset phase.

[0095]

[0111] Implementation examples are described in the following numbered clauses.

[0112] Article 1.

[0113] A first inverting circuit having inputs and outputs,

[0114] A second inverting circuit having inputs and outputs,

[0115] A first transistor coupled to the input of a second inverting circuit, wherein the gate of the first transistor is coupled to the first input,

[0116] A second transistor coupled to the input of the first inverting circuit, wherein the gate of the second transistor is coupled to the second input,

[0117] A third transistor, wherein the gate of the third transistor is coupled to the first input,

[0118] A fourth transistor, wherein the gate of the fourth transistor is coupled to the second input,

[0119] A first switch, wherein the first switch and a third transistor are connected in series between a first rail and the first transistor,

[0120] A regeneration circuit comprising a second switch, wherein the second switch and a fourth transistor are coupled in series between a first rail and the second transistor.

[0121] Article 2.

[0122] The first switch is coupled between the drain of the third transistor and the drain of the first transistor.

[0123] The regeneration circuit as described in Clause 1, wherein the second switch is coupled between the drain of the fourth transistor and the drain of the second transistor.

[0124] Article 3.

[0125] The source of the third transistor is coupled to the first rail.

[0126] The source of the fourth transistor is coupled to the first rail.

[0127] The source of the first transistor is coupled to the second rail.

[0128] The regenerative circuit described in Clause 2, wherein the source of the second transistor is coupled to the second rail.

[0129] Clause 4. The regeneration circuit described in Clause 3, wherein the second rail is connected to ground.

[0130] Article 5.

[0131] The first transistor comprises a first n-type field-effect transistor (NFET),

[0132] The second transistor is equipped with a second NFET,

[0133] The third transistor is equipped with the first p-type field-effect transistor (PFET),

[0134] A regenerative circuit as described in any one of clauses 1 to 4, wherein the fourth transistor comprises a second PFET.

[0135] Article 6.

[0136] The first switch has a control input coupled to the input of the first inverting circuit.

[0137] The regenerative circuit according to any one of clauses 1 to 5, wherein the second switch has a control input coupled to the input of the second inverting circuit.

[0138] Article 7.

[0139] The first switch comprises a first p-type field-effect transistor (PFET) having a gate coupled to the input of the first inverting circuit.

[0140] The regenerative circuit according to clause 6, wherein the second switch comprises a second PFET having a gate coupled to the input of the second inverting circuit.

[0141] Article 8.

[0142] A third switch coupled between the first transistor and the output of the first inverting circuit,

[0143] The regenerative circuit according to any one of clauses 1 to 7, further comprising a fourth switch coupled between a second transistor and the output of a second inverting circuit.

[0144] Article 9.

[0145] A third switch has a control input configured to receive a timing signal,

[0146] The regeneration circuit according to Clause 8, wherein the fourth switch has a control input configured to receive a timing signal.

[0147] Clause 10. A regenerative circuit as described in Clause 9, wherein the timing signal includes a clock signal.

[0148] Article 11.

[0149] A first inverting circuit having inputs and outputs,

[0150] A second inverting circuit having inputs and outputs,

[0151] A first transistor coupled to the input of a second inverting circuit, wherein the gate of the first transistor is coupled to the first input,

[0152] A second transistor coupled to the input of the first inverting circuit, wherein the gate of the second transistor is coupled to the second input,

[0153] A pull-up circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit,

[0154] A regeneration circuit comprising a pull-down circuit coupled to the input of a first inverting circuit and the input of a second inverting circuit.

[0155] Clause 12. The pull-up circuit is,

[0156] A third transistor coupled between the input of the first inverting circuit and the rail, wherein the gate of the third transistor is coupled to the output of the first inverting circuit,

[0157] The regenerative circuit according to Clause 11, comprising a fourth transistor coupled between the input of a second inverting circuit and a rail, the gate of the fourth transistor coupled to the output of the second inverting circuit.

[0158] Article 13.

[0159] The third transistor comprises the first p-type field-effect transistor (PFET),

[0160] The regenerative circuit described in Clause 12, wherein the fourth transistor comprises a second PFET.

[0161] Article 14.

[0162] The source of the first PFET is coupled to the rail, and the drain of the first PFET is coupled to the input of the first inverting circuit.

[0163] The regenerative circuit described in Clause 13, wherein the source of the second PFET is coupled to a rail and the drain of the second PFET is coupled to the input of the second inverting circuit.

[0164] Clause 15. A pull-down circuit is,

[0165] A third transistor coupled between the input of the first inverting circuit and the rail, wherein the gate of the third transistor is coupled to the input of the second inverting circuit or the output of the first inverting circuit,

[0166] The regenerative circuit according to clause 11, comprising a fourth transistor coupled between the input of a second inverting circuit and a rail, the gate of the fourth transistor being coupled to the input of a first inverting circuit or the output of a second inverting circuit.

[0167] Article 16.

[0168] The third transistor comprises the first n-type field-effect transistor (NFET),

[0169] The regenerative circuit described in Clause 15, wherein the fourth transistor comprises the second NFET.

[0170] Article 17.

[0171] The drain of the first NFET is coupled to the input of the first inverting circuit, and the source of the first NFET is coupled to the rail.

[0172] The regenerative circuit described in Clause 16, wherein the drain of the second NFET is coupled to the input of the second inverting circuit and the source of the second NFET is coupled to a rail.

[0173] Clause 18. A regeneration circuit as described in any one of Clauses 15 to 17, wherein the rail is connected to ground.

[0174] Article 19.

[0175] A first switch coupled between the first transistor and the output of the first inverting circuit,

[0176] A regenerative circuit according to any one of clauses 11 to 18, comprising a second switch coupled between a second transistor and the output of a second inverting circuit.

[0177] Article 20.

[0178] The first switch has a control input configured to receive a timing signal,

[0179] The regeneration circuit according to Clause 19, wherein the second switch has a control input configured to receive a timing signal.

[0180] Clause 21. A method for operating a sampler regeneration circuit, the regeneration circuit comprising a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, a second transistor coupled to the input of the first inverting circuit, a third transistor, a fourth transistor, and the method,

[0181] During the reset phase,

[0182] Disabling the regenerative feedback of the first and second inverting circuits,

[0183] During the regeneration phase,

[0184] To enable regenerative feedback in the first and second inverting circuits,

[0185] The gates of the first transistor and the third transistor are driven by a first voltage,

[0186] The gates of the second transistor and the fourth transistor are driven by a second voltage,

[0187] A method comprising coupling a third transistor to the output of a first inverting circuit, or coupling a fourth transistor to the output of a second inverting circuit.

[0188] Clause 22. The method according to Clause 21, wherein during the regeneration phase, a first voltage decreases at a first rate, a second voltage decreases at a second rate, and the first rate is different from the second rate.

[0189] Clause 23. The method according to Clause 22, wherein the first rate is based on a first input signal to the sampler and the second rate is based on a second input signal to the sampler.

[0190] Clause 24. The method according to Clause 23, wherein if the first input signal is greater than the second input signal, the first rate is greater than the second rate, and if the second input signal is greater than the first input signal, the second rate is greater than the first rate.

[0191] Clause 25. The third transistor may be coupled to the output of the first inverting circuit, or the fourth transistor may be coupled to the output of the second inverting circuit.

[0192] If the first rate is greater than the second rate, the third transistor is coupled to the output of the first inverting circuit.

[0193] The method according to any one of clauses 22 to 24, including coupling a fourth transistor to the output of the second inverting circuit if the second rate is greater than the first rate.

[0194] Clause 26. The third transistor may be coupled to the output of the first inverting circuit, or the fourth transistor may be coupled to the output of the second inverting circuit.

[0195] The method according to any one of the claims 22 to 25, comprising coupling a third transistor to the output of the first inverting circuit based on the voltage at the input of the first inverting circuit, or coupling a fourth transistor to the output of the second inverting circuit based on the voltage at the input of the second inverting circuit.

[0196] Clause 27. The method according to any one of Clauses 21 to 26, further comprising pulling up the first voltage and the second voltage to the supply voltage during the reset phase.

[0197] Article 28.

[0198] The first transistor comprises a first n-type field-effect transistor (NFET),

[0199] The second transistor is equipped with a second NFET,

[0200] The third transistor comprises the first p-type field-effect transistor (PFET),

[0201] The method according to any one of the clauses 21 to 27, wherein the fourth transistor comprises a second PFET.

[0202] Article 29.

[0203] Disabling the regenerative feedback of the first and second inverting circuits

[0204] The output of the first inverting circuit is disconnected from the first transistor,

[0205] This includes disconnecting the output of the second inverting circuit from the second transistor,

[0206] Enabling the regenerative feedback of the first and second inverting circuits is

[0207] The output of the first inverting circuit is coupled to the first transistor,

[0208] The method according to any one of the clauses 21 to 28, comprising coupling the output of a second inverting circuit to a second transistor.

[0209] Clause 30. A pull-down circuit is,

[0210] A fifth transistor coupled between the input of the first inverting circuit and the second rail, wherein the gate of the fifth transistor is coupled to the input of the second inverting circuit or the output of the first inverting circuit,

[0211] The method according to any one of claims 12 to 14, further comprising a sixth transistor coupled between the input of a second inverting circuit and a second rail, the gate of the sixth transistor being coupled to the input of a first inverting circuit or the output of a second inverting circuit.

[0212] Article 31.

[0213] The fifth transistor comprises the first n-type field-effect transistor (NFET),

[0214] The regenerative circuit described in clause 30, wherein the sixth transistor comprises a second NFET.

[0215] Article 32.

[0216] The drain of the first NFET is coupled to the input of the first inverting circuit, and the source of the first NFET is coupled to the rail.

[0217] The regenerative circuit as described in Clause 31, wherein the drain of the second NFET is coupled to the input of the second inverting circuit and the source of the second NFET is coupled to a rail.

[0218] Clause 33. A regeneration circuit as described in any one of Clauses 30 to 32, wherein the second rail is connected to ground.

[0096]

[0219] Please understand that this disclosure is not limited to the illustrative terminology used above to describe the various aspects of this disclosure.

[0097]

[0220] Any reference in this specification to elements designated as "first," "second," etc., does not generally limit the number or order of those elements. Rather, these designations are used herein as a convenient way to distinguish two or more elements, or examples of elements. Therefore, references to first and second elements do not imply that only two elements may be employed, or that the first element must precede the second element. Furthermore, it should be understood that the designations "first," "second," etc., in this specification do not necessarily correspond to the designations "first," "second," etc., in the claims.

[0098]

[0221] Within the scope of this disclosure, the term “exemplary” is used to mean “serving as an example, illustration, or representation.” No implementation or aspect described herein as “exemplary” should necessarily be construed as being preferable or advantageous to any other aspect of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation described. The term “about” as used herein with respect to stated values ​​or properties is intended to indicate that the value or property is within 10 percent of the stated value or property.

[0099]

[0222] The above description in this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments described herein, but should be given the broadest scope that is consistent with the principles and novel features disclosed herein. The invention described in the original claims of this application is listed below. [C1] A first inverting circuit having an input and an output, A second inverting circuit having inputs and outputs, A first transistor coupled to the input of the second inverting circuit, wherein the gate of the first transistor is coupled to the first input, A second transistor coupled to the input of the first inverting circuit, wherein the gate of the second transistor is coupled to the second input, A third transistor, wherein the gate of the third transistor is coupled to the first input, A fourth transistor, wherein the gate of the fourth transistor is coupled to the second input, A first switch, wherein the first switch and the third transistor are coupled in series between the first rail and the first transistor, A regeneration circuit comprising: a second switch, wherein the second switch and the fourth transistor are coupled in series between the first rail and the second transistor. [C2] The first switch is coupled between the drain of the third transistor and the drain of the first transistor. The regeneration circuit according to [C1], wherein the second switch is coupled between the drain of the fourth transistor and the drain of the second transistor. [C3] The source of the third transistor is coupled to the first rail. The source of the fourth transistor is coupled to the first rail. The source of the first transistor is coupled to the second rail. [C2] The regenerative circuit according to claim 2, wherein the source of the second transistor is coupled to the second rail. [C4] The regeneration circuit described in [C3], wherein the second rail is connected to ground. [C5] The first transistor comprises a first n-type field-effect transistor (NFET), The aforementioned second transistor comprises a second NFET, The third transistor comprises a first p-type field-effect transistor (PFET), The regeneration circuit described in [C1], wherein the fourth transistor comprises a second PFET. [C6] The first switch has a control input coupled to the input of the first inverting circuit, The regeneration circuit according to [C1], wherein the second switch has a control input coupled to the input of the second inverting circuit. [C7] The first switch comprises a first p-type field-effect transistor (PFET) having a gate coupled to the input of the first inverting circuit, The regeneration circuit according to [C6], wherein the second switch comprises a second PFET having a gate coupled to the input of the second inverting circuit. [C8] A third switch coupled between the first transistor and the output of the first inverting circuit, The regeneration circuit according to [C1] further comprises a fourth switch coupled between the second transistor and the output of the second inverting circuit. [C9] The third switch has a control input configured to receive a timing signal, The regeneration circuit according to [C8], wherein the fourth switch has a control input configured to receive the timing signal. [C10] The regeneration circuit described in [C9], wherein the timing signal includes a clock signal. [C11] A first inverting circuit having an input and an output, A second inverting circuit having inputs and outputs, A first transistor coupled to the input of the second inverting circuit, wherein the gate of the first transistor is coupled to the first input, A second transistor coupled to the input of the first inverting circuit, wherein the gate of the second transistor is coupled to the second input, A pull-up circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit, A regeneration circuit comprising a pull-down circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit. [C12] The pull-up circuit described above, A third transistor coupled between the input and rail of the first inverting circuit, wherein the gate of the third transistor is coupled to the output of the first inverting circuit, The regeneration circuit according to [C11], further comprising: a fourth transistor coupled between the input of the second inverting circuit and the rail, wherein the gate of the fourth transistor is coupled to the output of the second inverting circuit. [C13] The third transistor comprises a first p-type field-effect transistor (PFET), The regeneration circuit described in [C12], wherein the fourth transistor comprises a second PFET. [C14] The source of the first PFET is coupled to the rail, and the drain of the first PFET is coupled to the input of the first inverting circuit. The regenerative circuit according to [C13], wherein the source of the second PFET is coupled to the rail and the drain of the second PFET is coupled to the input of the second inverting circuit. [C15] The pull-down circuit described above is A third transistor coupled between the input and rail of the first inverting circuit, wherein the gate of the third transistor is coupled to the input of the second inverting circuit or the output of the first inverting circuit, The regenerative circuit according to [C11], further comprising: a fourth transistor coupled between the input of the second inverting circuit and the rail, wherein the gate of the fourth transistor is coupled to the input of the first inverting circuit or the output of the second inverting circuit. [C16] The third transistor comprises a first n-type field-effect transistor (NFET), The regeneration circuit described in [C15], wherein the fourth transistor comprises a second NFET. [C17] The drain of the first NFET is coupled to the input of the first inverting circuit, and the source of the first NFET is coupled to the rail, The regenerative circuit according to [C16], wherein the drain of the second NFET is coupled to the input of the second inverting circuit, and the source of the second NFET is coupled to the rail. [C18] The regeneration circuit described in [C15], wherein the rail is connected to ground. [C19] A first switch coupled between the first transistor and the output of the first inverting circuit, The regeneration circuit according to [C11], further comprising: a second switch coupled between the second transistor and the output of the second inverting circuit. [C20] The first switch has a control input configured to receive a timing signal, The regeneration circuit according to [C19], wherein the second switch has a control input configured to receive the timing signal. [C21] A method for operating a sampler regeneration circuit, wherein the regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, a second transistor coupled to the input of the first inverting circuit, a third transistor, and a fourth transistor, and the method is During the reset phase, Disabling the regenerative feedback of the first inverting circuit and the second inverting circuit, During the regeneration phase, To enable the regenerative feedback of the first inverting circuit and the second inverting circuit, The gates of the first transistor and the third transistor are driven by a first voltage, The gates of the second transistor and the fourth transistor are driven by a second voltage, A method comprising coupling the third transistor to the output of the first inverting circuit, or coupling the fourth transistor to the output of the second inverting circuit. [C22] The method according to [C21], wherein during the regeneration phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate. [C23] The method according to [C22], wherein the first rate is based on a first input signal to the sampler, and the second rate is based on a second input signal to the sampler. [C24] The method according to [C23], wherein if the first input signal is greater than the second input signal, the first rate is greater than the second rate, and if the second input signal is greater than the first input signal, the second rate is greater than the first rate. [C25] The third transistor is coupled to the output of the first inverting circuit, or the fourth transistor is coupled to the output of the second inverting circuit. If the first rate is greater than the second rate, the third transistor is coupled to the output of the first inverting circuit. The method according to [C22], which includes coupling the fourth transistor to the output of the second inverting circuit when the second rate is greater than the first rate. [C26] The third transistor is coupled to the output of the first inverting circuit, or the fourth transistor is coupled to the output of the second inverting circuit. The method according to [C22], comprising coupling the third transistor to the output of the first inverting circuit based on the voltage at the input of the first inverting circuit, or coupling the fourth transistor to the output of the second inverting circuit based on the voltage at the input of the second inverting circuit. [C27] The method according to [C21], further comprising pulling up the first voltage and the second voltage to the supply voltage during the reset phase. [C28] The first transistor comprises a first n-type field-effect transistor (NFET), and the second transistor comprises a second NFET. The method according to [C21], wherein the third transistor comprises a first p-type field-effect transistor (PFET), and the fourth transistor comprises a second PFET. [C29] Disabling the regenerative feedback of the first inverting circuit and the second inverting circuit is Disconnecting the output of the first inverting circuit from the first transistor, This includes disconnecting the output of the second inverting circuit from the second transistor, Enabling the regenerative feedback of the first inverting circuit and the second inverting circuit is The output of the first inverting circuit is coupled to the first transistor, The method according to [C21], further comprising coupling the output of the second inverting circuit to the second transistor.

Claims

1. A first inverting circuit having inputs and outputs, A second inverting circuit having inputs and outputs, A first transistor coupled to the input of the second inverting circuit, wherein the gate of the first transistor is coupled to the first input, A second transistor coupled to the input of the first inverting circuit, wherein the gate of the second transistor is coupled to the second input, A pull-up circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit, The circuit comprises a pull-down circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit, The output of the first inverting circuit is electrically coupled to the input of the second inverting circuit, and the output of the second inverting circuit is electrically coupled to the input of the first inverting circuit. The aforementioned pull-up circuit A third transistor coupled between the input of the first inverting circuit and the first rail, wherein the gate of the third transistor is coupled to the output of the first inverting circuit, A fourth transistor coupled between the input of the second inverting circuit and the first rail, wherein the gate of the fourth transistor is coupled to the output of the second inverting circuit, regeneration circuit.

2. The third transistor comprises a first p-type field-effect transistor (PFET), The regeneration circuit according to claim 1, wherein the fourth transistor comprises a second PFET.

3. The source of the first PFET is coupled to the first rail, and the drain of the first PFET is coupled to the input of the first inverting circuit. The regenerative circuit according to claim 2, wherein the source of the second PFET is coupled to the first rail, and the drain of the second PFET is coupled to the input of the second inverting circuit.

4. The aforementioned pull-down circuit A fifth transistor coupled between the input of the first inverting circuit and the second rail, wherein the gate of the fifth transistor is coupled to the input of the second inverting circuit or the output of the first inverting circuit, The regenerative circuit according to claim 1, further comprising: a sixth transistor coupled between the input of the second inverting circuit and the second rail, wherein the gate of the sixth transistor is coupled to the input of the first inverting circuit or the output of the second inverting circuit.

5. The fifth transistor comprises a first n-type field-effect transistor (NFET), The regeneration circuit according to claim 4, wherein the sixth transistor comprises a second NFET.

6. The drain of the first NFET is coupled to the input of the first inverting circuit, and the source of the first NFET is coupled to the second rail. The regenerative circuit according to claim 5, wherein the drain of the second NFET is coupled to the input of the second inverting circuit, and the source of the second NFET is coupled to the second rail.

7. The regeneration circuit according to claim 4, wherein the second rail is connected to ground.

8. A first switch coupled between the first transistor and the output of the first inverting circuit, The regeneration circuit according to claim 1, further comprising: a second switch coupled between the second transistor and the output of the second inverting circuit.

9. The first switch has a control input configured to receive a timing signal, The regeneration circuit according to claim 8, wherein the second switch has a control input configured to receive the timing signal.

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