Pixel circuit, pixel control method, and display device

Abstract

The present application discloses a pixel circuit, a pixel control method, and a display device, the pixel circuit including: a first thin film transistor (T1) having a controlled terminal connected to a scan line (L1) and an input terminal connected to a data line (L2); and a first selection circuit (10) having an input terminal connected to an output terminal of the first thin film transistor (T1), a first output terminal connected to a first pixel electrode (S1), and a second output terminal connected to a second pixel electrode (S2), the first thin film transistor (T1) being used to respond to a scanning signal transmitted on the scan line (L1).

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application with the application number 202211688066.5, filed on December 28, 2022, and incorporates all of its contents herein by reference.

[0002] This application relates to the technical field of pixel control, and particularly to pixel circuits, pixel control methods, and display devices.

Background Art

[0003] Display brightness is an important parameter that affects the display quality of a liquid crystal display device. On the other hand, the aperture ratio is the main factor determining the display brightness. The aperture ratio is the ratio of the light - transmitting part to the non - transmitting part in the effective display area of the display device, that is, the ratio of the effective area through which light can pass. That is, the higher the aperture ratio, the higher the display brightness. However, conventional liquid crystal display devices have a low aperture ratio, so the display brightness is low.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The main object of this application is to provide a pixel circuit for solving the problem that the display brightness of a liquid crystal display device is low due to a low aperture ratio.

Means for Solving the Problems

[0005] The main object of this application is to provide a pixel circuit for solving the problem that the display brightness of a liquid crystal display device is low due to a low aperture ratio.

[0006] To achieve the above object, the pixel circuit proposed by this application is used in a display panel including a scanning line, a data line, a first pixel including a first pixel electrode, and a second pixel including a second pixel electrode. The pixel circuit includes a first thin - film transistor with a controlled terminal connected to the scanning line and an input terminal connected to the data line, The system includes a first selection circuit whose input terminal is connected to the output terminal of the first thin-film transistor, whose first output terminal is connected to the first pixel electrode, and whose second output terminal is connected to the second pixel electrode, The first thin-film transistor is used to sequentially charge the first and second pixels so that the first and second pixels can be sequentially charged to the pixel potential of the corresponding current frame by sequentially writing the data signal transmitted on the data line to the first and second pixels via the first selection circuit in response to the scan signal transmitted on the scan line. Pixel circuit.

[0007] This application further proposes a pixel control method applicable to the above-described pixel circuit, and the pixel control method is: In the first subphase, a high-potential scanning signal is output to the Nth scan line, and a data signal with a predetermined potential and positive polarity is output to the data line, thereby charging the first pixel to the pixel potential of the corresponding current frame. The second subphase includes the step of charging a second pixel to the pixel potential of the corresponding current frame by outputting a high-potential scanning signal to the Nth scan line and a data signal with a predetermined potential and negative polarity to the data line.

[0008] This application further proposes a display device, the display device being: Scan lines and, Data lines and, A first pixel including a first pixel electrode, A second pixel including a second pixel electrode, The system includes the scan line, the data line, the first pixel electrode, and the second pixel electrode, respectively, and the pixel circuit connected to them. The display device is used to control the pixel circuit to drive the operation of the first pixel and the second pixel according to the pixel control method described above.

[0009] (Beneficial effects) The present invention uses a first thin-film transistor and a first selection circuit to sequentially charge the first and second pixels by sequentially writing the data signal transmitted on the data line to the first and second pixels via the first selection circuit in response to the scan signal transmitted on the scan line, thereby sequentially charging the first and second pixels to the pixel potential of the corresponding current frame. Thus, the pixel circuit of the present invention can realize display control for two pixels located on either side of a scan line with only one scan line and one thin-film transistor. Therefore, in the case of a liquid crystal display device with a resolution of m × n, it is only necessary to provide 0.5n scan lines L1 and 0.5 × m × n thin-film transistors in the effective display area of ​​the liquid crystal display device. Compared to the conventional technology, the number of scan lines L1 and thin-film transistors provided in the effective display area is greatly reduced, and the aperture ratio of the effective display area of ​​the liquid crystal display device is greatly improved, thereby solving the problem of low display brightness of liquid crystal display devices due to a low aperture ratio.

[0010] To more clearly explain the embodiments of the present application and the prior art, the accompanying drawings necessary for describing the embodiments or the prior art are briefly described below. It is clear that the accompanying drawings in the following description represent only some embodiments of the present application, and a person skilled in the art can obtain other accompanying drawings based on the structures shown in these drawings without any creative work. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram of the module configuration of the pixel circuit according to Embodiment 1 of the present invention. [Figure 2] This is a schematic diagram illustrating the configuration of the newly formed aperture position in the pixel circuit according to Embodiment 1 of the present invention. [Figure 3] This is a schematic circuit diagram of the pixel circuit according to Embodiment 1 of the present invention. [Figure 4] This is another schematic circuit diagram of the pixel circuit according to Embodiment 1 of the present invention. [Figure 5] This is a schematic step flowchart of the pixel control method according to Embodiment 2 of the present invention. [Figure 6] It is a schematic diagram of the layout in the effective display area according to Embodiment 1 of the present application. [Figure 7] It is a schematic diagram of another layout in the effective display area according to Embodiment 1 of the present application. [Figure 8] It is a schematic driving timing diagram of the pixel circuit according to Embodiment 1 of the present application.

Embodiments for Carrying out the Invention

[0012] Referring to the accompanying drawings, the realization of the object of the present application, functional features and advantages will be further described in combination with the embodiments.

[0013] Hereinafter, in combination with the drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. It is obvious that the described embodiments are only a part of the embodiments of the present application, not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the scope protected by the present application.

[0014] Also, the descriptions such as "first" and "second" in the embodiments of the present application are only used for the purpose of explanation, and should not be understood as presenting or implying their relative importance, or implicitly specifying the number of the presented technical features. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of such features. Also, as long as it can be realized by those skilled in the art, the technical solutions of each embodiment can be combined with each other. If a contradiction or inability to be realized occurs in the combination of technical solutions, it should be understood that such a combination of technical solutions does not exist and is not within the scope that the present application seeks to protect.

[0015] Embodiment 1: The present application proposes a pixel circuit applicable to a liquid crystal display panel.

[0016] In the effective display area of the display panel, a plurality of scanning lines L1 and a plurality of data lines L2 may be provided to intersect so as to form a plurality of pixel intervals arranged in a matrix, and one pixel may be formed in each pixel interval. Here, the first pixel PXL1 may include a first pixel electrode S1, and the first pixel electrode S1 may form a pixel capacitor and an accumulation capacitor in the first pixel PXL1 together with a common electrode line (hereinafter, in this specification, it is represented as the first pixel capacitor Ccl1 and the first accumulation capacitor Cst1). The second pixel PXL2 may include a second pixel electrode S2, and the second pixel electrode S2 may form a pixel capacitor and an accumulation capacitor in the second pixel PXL2 together with a common electrode line (hereinafter, in this specification, it is represented as the second pixel capacitor and the second accumulation capacitor Cs).

[0017] In one exemplary technique, it is necessary to provide one pixel circuit in each pixel interval, the pixel circuits in the pixel intervals of the same row need to be connected to the same scanning line L1, and at least one thin-film transistor needs to be provided in each pixel circuit. Therefore, in the case of a liquid crystal display device with a resolution of m×n, it is necessary to provide n scanning lines L1 and at least m×n thin-film transistors in the effective display area. As a result, since the aperture ratio of the liquid crystal display device is low, the display luminance of the liquid crystal display device becomes low.

[0018] Regarding the above problem, referring to FIGS. 1 to 2, in Example 1, the pixel circuit includes a first thin-film transistor T1 having a controlled terminal connected to the scanning line L1 and an input terminal connected to the data line L2, a first selection circuit 10 having an input terminal connected to the output terminal of the first thin-film transistor T1, a first output terminal connected to the first pixel electrode S1, and a second output terminal connected to the second pixel electrode S2. The first thin-film transistor T1 is used to sequentially charge the first pixel PXL1 and the second pixel PXL2 so that they can sequentially charge to the pixel potential of the corresponding current frame by sequentially writing the data signal transmitted on the data line L2 to the first pixel PXL1 and the second pixel PXL2 via the first selection circuit 10 in response to the scanning signal transmitted on the scan line L1.

[0019] In this embodiment, the first thin-film transistor T1 may be an N-type or P-type thin-film transistor, but in the following description, the present invention will be explained using the case where the first thin-film transistor T1 is an N-type thin-film transistor as an example. The controlled terminal, input terminal, and output terminal of the first thin-film transistor T1 may be the gate, drain, and source of an N-type thin-film transistor, respectively. The first thin-film transistor T1 conducts when it receives a high-potential scanning signal, and when it conducts, it can receive the data signal transmitted on the data line L2 and output it to the first selection circuit 10.

[0020] The first selection circuit 10 may have multiple unidirectional circuits, and each unidirectional circuit may have two terminals. Each unidirectional circuit conducts when the potential of one of its two terminals is greater than the potential of the other terminal, and the direction of current during conduction is from the terminal with the higher potential to the other terminal with the lower potential, and does not conduct when the potential of the other terminal is greater than the potential of the first terminal. In other words, each unidirectional circuit has the characteristic of unidirectional conduction. The first selection circuit 10 conducts the corresponding unidirectional circuit in different subphases of the display control phase according to the potential of the data signal output from the first thin-film transistor T1, thereby sequentially inputting the data signal with the corresponding potential to the first pixel electrode S1 and the second pixel electrode S2 via the corresponding unidirectional circuit in different subphases of the display control phase. Furthermore, the first pixel capacitor Ccl1, the first storage capacitor Cst1, the second pixel capacitor, and the second storage capacitor Cs can be charged to the potential value required for screen display of the current frame, i.e., the pixel potential of the current frame, using the input data signal. As a result, the first pixel PXL1 and the second pixel PXL2 can control the degree of inversion of the liquid crystal molecules using the corresponding pixel potential of the current frame during the display phase, and furthermore, the display of the first pixel PXL1 and the second pixel PXL2 on the screen of the current frame can be realized.

[0021] Thus, the pixel circuit of this invention can achieve display control for two pixels (PXL1 and PXL2) located on either side of the scan line L1 using only one scan line L1 and one first thin-film transistor T1. Therefore, when employing the pixel circuit of this invention, in the case of a liquid crystal display device with a resolution of m × n, it is only necessary to provide 0.5n scan lines L1 and 0.5 × m × n thin-film transistors in its effective display area. Compared to the conventional technology, the number of scan lines L1 and thin-film transistors provided in the effective display area is significantly reduced, and the aperture ratio of the effective display area of ​​the liquid crystal display device is greatly improved. When the first pixel PXL1 and the second pixel PXL2 are in the same row and located on opposite sides of the same scan line L1, the newly created aperture position is specifically as shown in Figure 2, which is advantageous for improving the display brightness of the liquid crystal display device and solves the problem of low display brightness of liquid crystal display devices due to a low aperture ratio.

[0022] Referring to Figures 2 and 3, in Example 1, the first selection circuit 10 is A first unidirectional circuit 11 has a first terminal connected to the output terminal of the first thin-film transistor T1 and a second terminal connected to the first pixel electrode S1, The system includes a second unidirectional circuit 12, the first terminal of which is connected to the output terminal of the first thin-film transistor T1 and the second terminal of which is connected to the second pixel electrode S2, The first unidirectional circuit 11 and the second unidirectional circuit 12 may be realized by a PN junction, the first unidirectional circuit 11 may include a first PN junction PN1, and the second unidirectional circuit 12 may include a second PN junction PN2. Since the PN junction has a positive electrode and a negative electrode, the first selection circuit 10 can have two types of circuit configurations depending on the connection method of the positive and negative electrodes of the PN junction, specifically as follows.

[0023] In the first type of circuit configuration of the first selection circuit 10, specifically as shown in Figure 3, the first terminal of the first unidirectional circuit 11 may be the positive terminal of the first PN junction PN1 and the second terminal may be the negative terminal of the first PN junction PN1, and the first terminal of the second unidirectional circuit 12 may be the negative terminal of the second PN junction PN2 and the second terminal may be the positive terminal of the second PN junction PN2. Thus, when the first thin-film transistor T1 outputs a high-potential data signal, the first unidirectional circuit 11 conducts, and the second unidirectional circuit 12 does not conduct. The direction of the current when the first unidirectional circuit 11 conducts, i.e., the direction of the conduction current, is from the first terminal to the second terminal, thus enabling the writing of a high-potential data signal to the first pixel PXL1 and charging the first pixel PXL1. When the first thin-film transistor T1 outputs a low-potential data signal, the first unidirectional circuit 11 does not conduct, and the second unidirectional circuit 12 conducts. The direction of the current when the second unidirectional circuit 12 conducts is from the second terminal to the first terminal, thus enabling the writing of a low-potential data signal to the second pixel PXL2 and charging the second pixel PXL2.

[0024] In the second type of circuit configuration of the first selection circuit 10, specifically refer to Figure 4, where the first terminal of the first unidirectional circuit 11 may be the negative terminal of the first PN junction PN1 and the second terminal may be the positive terminal of the first PN junction PN1, and the first terminal of the second unidirectional circuit 12 may be the positive terminal of the second PN junction PN2 and the second terminal may be the negative terminal of the second PN junction PN2. Thus, when the first thin-film transistor T1 outputs a high-potential data signal, the first unidirectional circuit 11 does not conduct, and the second unidirectional circuit 12 conducts. Since the current direction when the second unidirectional circuit 12 conducts is from its first terminal to its second terminal, the high-potential data signal is written to the second pixel PXL2, charging the second pixel PXL2. When the first thin-film transistor T1 outputs a low-potential data signal, the first unidirectional circuit 11 conducts, and the second unidirectional circuit 12 does not conduct. Since the current direction when the second unidirectional circuit 12 conducts is from its second terminal to its first terminal, the low-potential data signal is written to the first pixel PXL1, charging the first pixel PXL1.

[0025] In other words, when the first thin-film transistor T1 outputs a data signal, one of the first unidirectional circuit 11 and the second unidirectional circuit 12 conducts and the other turns off, and the direction of the conduction current of the first unidirectional circuit 11 and the direction of the conduction current of the second unidirectional circuit 12 are opposite.

[0026] In actual display, there are display conditions where the pixel potential of the previous frame of a pixel is higher or lower than the pixel potential of the current frame. When this display condition occurs, it affects the conduction of the first unidirectional circuit 11 or the second unidirectional circuit 12, and thus affects the charging effect of the first pixel PXL1 or the second pixel PXL2 when the current frame is displayed on the screen. For example, if the pixel potential of the first pixel PXL1 in the previous frame is higher than the pixel potential of the current frame, the first thin-film transistor T1 outputs a high-potential data signal. If this high-potential data signal is a low-potential signal compared to the pixel potential of the previous frame, the first unidirectional circuit 11 will not conduct, and therefore the first pixel PXL1 cannot be charged to the pixel potential of the current frame.

[0027] In view of these problems, the present invention provides a reset circuit 30 in the pixel circuit, the reset circuit 30 is used such that a controlled terminal is connected to a scan line L1 of a predetermined number of previous rows, an input terminal is connected to a predetermined reset potential DC1, a first output terminal is connected to the first pixel electrode S1, and a second output terminal is connected to the second pixel electrode S2, and the reset circuit 30 is used to reset the first pixel PXL1 and the second pixel PXL2 by outputting the predetermined reset potential DC1 to the first pixel electrode S1 and the second pixel electrode S2 in response to a scan signal transmitted on the scan line L1 of a predetermined number of previous rows.

[0028] In this embodiment, the default reset potential DC1 may be an intermediate potential between the high and low potentials of both the first pixel PXL1 and the second pixel PXL2. The previous default number of scan lines L1 may be determined as required by the actual reset of the display device, and may be, for example, the previous one scan line L1 or the previous two scan lines L1, etc., but are not limited herein. The reset circuit 30 may be implemented using a switch constructed of a thin-film transistor, and the thin-film transistor may be an N-type or P-type thin-film transistor, but are not limited herein.

[0029] In the embodiments shown in Figures 3 and 4, the reset circuit 30 may include a fourth thin-film transistor T4 and a fifth thin-film transistor T5, both of which are N-type thin-film transistors. The gates of the fourth thin-film transistor T4 and the fifth thin-film transistor (T5) may be connected to the scan lines L1 of a predetermined number of previous rows, respectively, and the drains may be connected to the first potential line L3, respectively. The drain of the fourth thin-film transistor T4 is connected to the first pixel electrode S1, the drain of the fifth thin-film transistor T5 is connected to the second pixel electrode S2, and the first potential line L3 is connected to a predetermined reset potential DC1 and used to transmit the predetermined reset potential DC1. As a result, the reset circuit 30 conducts when a high-potential scanning signal is transmitted on the scan line L1 of the previous predetermined number of rows. When it conducts, it outputs the connected predetermined reset potential DC1 to the first pixel electrode S1 and the second pixel electrode S2, thereby lowering the potential of the first pixel electrode S1 and the second pixel electrode S2 to the predetermined reset potential DC1, and thus enabling the potential reset of the first pixel PXL1 and the second pixel PXL2. Furthermore, since this invention uses two thin-film transistors to achieve the potential reset of the first pixel PXL1 and the second pixel PXL2, it is possible to avoid charge sharing due to direct electrical connection between the first pixel electrode S1 and the second pixel electrode S2, compared to using one thin-film transistor to simultaneously output a predetermined reset potential to both pixels. This is advantageous in improving the display stability and display effect of the first pixel PXL1 and the second pixel PXL2.

[0030] Since the default reset potential DC1 is lower than the high potential of the data signal and higher than the low potential of the data signal, after reset, the first unidirectional circuit 11 and the second unidirectional circuit 12 can output data signals of different potentials output from the first thin-film transistor T1 to the first pixel electrode S1 and the second pixel electrode S2, respectively. This allows the potentials of the first pixel PXL1 and the second pixel PXL2 to be charged to the corresponding pixel potential of the current frame, which is advantageous for improving the display effect of the liquid crystal display device.

[0031] In actual use, the reset circuit 30 has a large off-state leakage current, which easily affects the potential of the first pixel electrode S1 and the second pixel electrode S2, and therefore easily affects the charging effect and the potential after charging of the first pixel PXL1 and the second pixel PXL2.

[0032] In view of these problems, the present invention further provides a second selection circuit 20 in the pixel circuit, wherein the second selection circuit 20 has a first input terminal connected to the first output terminal of the reset circuit 30, a second input terminal connected to the second output terminal of the reset circuit 30, a first output terminal connected to the first pixel electrode S1, and a second output terminal connected to the second pixel electrode S2. Here, the first selection circuit 10 may similarly have a plurality of unidirectional circuits, each unidirectional circuit including at least one PN junction, and the PN junction may be used to reduce the off-state leakage current of the reset circuit 30.

[0033] In one embodiment, the second selection circuit 20 is A third unidirectional circuit 21, the first terminal of which is connected to the first pixel electrode S1 and the second terminal of which is connected to the input terminal of the reset circuit 30, The system includes a fourth unidirectional circuit 22, the first of which is connected to the second pixel electrode S2 and the second of which is connected to the input terminal of the reset circuit 30, When the reset circuit 30 is conductive, the first unidirectional circuit 11 and the second unidirectional circuit 12 are both conductive, the direction of the current conduction of the third unidirectional circuit 21 is the same as the direction of the current conduction of the first unidirectional circuit 11, and the direction of the current conduction of the fourth unidirectional circuit 22 is the same as the direction of the current conduction of the second unidirectional circuit 12.

[0034] The third unidirectional circuit 21 and the fourth unidirectional circuit 22 may be implemented by PN junctions, the third unidirectional circuit 21 may include a third PN junction PN3, and the fourth unidirectional circuit 22 may include a fourth PN junction PN4. For the same reason, the second selection circuit 20 can similarly have two types of circuit configurations depending on the connection method of the positive and negative electrodes of the PN junction, specifically as follows.

[0035] In the first type of circuit configuration of the second selection circuit 20, specifically as shown in Figure 3, the first terminal of the third unidirectional circuit 21 may be the positive terminal of the third PN junction PN3 and the second terminal may be the negative terminal of the third PN junction PN3, and the first terminal of the fourth unidirectional circuit 22 may be the negative terminal of the fourth PN junction PN4 and the second terminal may be the positive terminal of the fourth PN junction PN4. In this case, the first selection circuit 10 may also have a first type of circuit configuration, that is, the direction of the current conduction in the first unidirectional circuit 11 and the third unidirectional circuit 21 in this case is from the first terminal to the second terminal, and that is, the direction of the current conduction in the second unidirectional circuit 12 and the fourth unidirectional circuit 22 in this case is from the second terminal to the first terminal. This makes it possible to prevent the writing function of the first selection circuit 10 and the reset function of the second selection circuit 20, both of which employ a first type of circuit configuration, from affecting each other.

[0036] In the second type of circuit configuration of the second selection circuit 20, specifically as shown in Figure 4, the first terminal of the third unidirectional circuit 21 may be the negative terminal of the third PN junction PN3 and the second terminal may be the positive terminal of the third PN junction PN3, and the first terminal of the fourth unidirectional circuit 22 may be the positive terminal of the fourth PN junction PN4 and the second terminal may be the negative terminal of the fourth PN junction PN4. In this case, the first selection circuit 10 may also have a type 2 circuit configuration, that is, the direction of the current conduction in the first unidirectional circuit 11 and the third unidirectional circuit 21 in this case is from the second terminal to the first terminal, and that is, the direction of the current conduction in the second unidirectional circuit 12 and the fourth unidirectional circuit 22 in this case is from the first terminal to the second terminal. This makes it possible to prevent the writing function of the first selection circuit 10 and the reset function of the second selection circuit 20, both of which employ a type 2 circuit configuration, from affecting each other.

[0037] However, when a data signal is written, the third unidirectional circuit 21, under the action of the first pixel PXL1, causes the potential at its first terminal to become greater than the potential at its second terminal, and the fourth unidirectional circuit 22, under the action of the second pixel PXL2, causes the potential at its first terminal to become less than the potential at its second terminal. This causes the third unidirectional circuit 21 and the fourth unidirectional circuit 22 to conduct, and further generates leakage current in the fourth thin-film transistor T4 and the fifth thin-film transistor T5, affecting the potentials of the first pixel PXL1 and the second pixel PXL2.

[0038] In view of these problems, the present invention provides a second thin-film transistor T2 and a third thin-film transistor T3, wherein the second thin-film transistor T2 is used to have its controlled terminal connected to the scan line L1, its input terminal connected to a first predetermined potential DC2, and its output terminal connected to the second terminal of the third unidirectional circuit 21, and the third thin-film transistor T3 is used to have its controlled terminal connected to the scan line L1, its input terminal connected to a second predetermined potential DC3, and its output terminal connected to the second terminal of the fourth unidirectional circuit 22.

[0039] Here, the input terminal of the second thin-film transistor T2 may be connected to the second potential line L4, which is connected to the first default potential DC2 and used to transmit the first default potential DC2, and the first default potential DC2 may be the maximum potential value among the data signals which are positive polarity signals (relative to the common electrode). The input terminal of the third thin-film transistor T3 may be connected to the third potential line L5, which is connected to the second default potential DC3 and used to transmit the second default potential DC3, and the second default potential DC3 may be the minimum potential value among the data signals which are negative polarity signals (relative to the common electrode). Thus, when data signals are written to the first pixel PXL1 and the second pixel PXL2, that is, when a high-potential scan signal G(N) is transmitted on the scan line L1 of this row, the second thin-film transistor T2 and the third thin-film transistor T3 conduct, raising the potential of the second terminal of the third unidirectional circuit 21 to the first predetermined potential DC2, and raising the potential of the second terminal of the fourth unidirectional circuit 22 to the second predetermined potential DC3. This allows the third unidirectional circuit 21 and the fourth unidirectional circuit 22 to be turned off by setting the potential of the first terminal of the third unidirectional circuit 21 to be below the potential of its second terminal, and the potential of the first terminal of the fourth unidirectional circuit 22 to be above the potential of its second terminal. Furthermore, this prevents the potentials of the first pixel PXL1 and the second pixel PXL2 from being affected by the leakage current of the fourth thin-film transistor T4 and the fifth thin-film transistor T5.

[0040] Furthermore, in order to avoid a decrease in aperture ratio due to being located in the effective display area and to further improve display brightness, the second to fifth thin-film transistors (T2 to T5) and the first to third potential lines (L3 to L5) may be located in the non-effective display area of ​​the liquid crystal display device.

[0041] Example 2: This application further discloses a pixel control method used to control the above-mentioned pixel circuit. The specific configuration of this pixel circuit is described by referring to the embodiments described above. Since this pixel control method adopts all the technical proposals of all the embodiments described above, it has at least all the beneficial effects of the technical proposals of the embodiments described above, and therefore, a detailed explanation is omitted here.

[0042] The display device may further include a timing controller, a source drive circuit, and a gate drive circuit, where the timing controller may be the main implementer of the pixel control method of the present invention. The source drive circuit is connected to the timing controller and a plurality of data lines L2, and can output data signals of the corresponding potential to each data line L2 under the control of the timing controller. The gate drive circuit is connected to the timing controller and a plurality of scan lines L1, and can sequentially turn on the scan lines L1 by outputting scan signals of the corresponding potential to each scan line L1 in line order under the control of the timing controller.

[0043] Referring to Figures 5 to 8, in Embodiment 2, in the frame display period in which the timing controller controls the effective display area to display one frame of the screen, the frame display period may be divided into a control phase and an uncontrol phase for the first pixel PXL1 and the second pixel PXL2, and the control phase may include a first subphase and a second subphase that are executed sequentially. The pixel control method includes the following steps.

[0044] In step S100, during the first subphase T1, a high-potential scan signal is output to the Nth scan line L1, and a data signal with a predetermined potential and positive polarity is output to the data line L2, thereby charging the first pixel PXL1 to the pixel potential of the corresponding current frame.

[0045] Specifically, the timing controller controls the gate drive circuit to turn on the Nth scan line L1 by outputting a high-potential scan signal G(n) to the Nth scan line L1, and controls the source drive circuit to output a data signal with a predetermined positive polarity to the data line L2, thereby writing the data signal with a predetermined positive polarity to the first pixel PXL1 connected to the pixel circuit connected to the Nth scan line L1 and the data line L2, and enabling the first pixel PXL1 to be charged to the pixel potential of the corresponding current frame.

[0046] In step S200, during the second subphase T2, a high-potential scan signal G(n) is output to the Nth scan line L1, and a data signal with a predetermined potential and negative polarity is output to the data line L2, thereby charging the second pixel PXL2 to the pixel potential of the corresponding current frame.

[0047] Specifically, the timing controller controls the gate drive circuit to turn on the Nth scan line L1 by outputting a high-potential scan signal G(n) to the Nth scan line L1, and controls the source drive circuit to output a data signal of a predetermined negative polarity to the data line L2, thereby writing the data signal of a predetermined negative polarity to a second pixel PXL2 connected to the pixel circuit connected to the Nth scan line L1 and data line L2, and enabling the second pixel PXL2 to be charged to the pixel potential of the corresponding current frame.

[0048] In non-controlled phases other than the control phase, the timing controller may control the Nth row scan line L1 to turn off by outputting a low-potential scan signal G(n). In the embodiment shown in Figure 8, in the pixel circuit, the controlled terminal of the reset circuit 30 is connected to the previous row scan line. Therefore, when a high-potential scan signal G(n₁) is input to the previous row scan line, the potentials of the first pixel PXL1 and the second pixel PXL2 are reset to a predetermined reset potential DC1.

[0049] Furthermore, the positive polarity default potential and negative polarity default potential described herein are relative to the default reset potential DC1, where the positive polarity default potential is higher than the default reset potential DC1, and the negative polarity default potential is lower than the default reset potential DC1. In addition, the positive polarity default potential may be determined by the pixel potential required by the first pixel PXL1 to display the current frame, and the negative polarity default potential may be determined by the pixel potential required by the second pixel PXL2 to display the current frame, but this is not limited to the foregoing.

[0050] Since both the first selection circuit 10 and the second selection circuit 20 of this application have two types of circuit configurations, the pixel circuit of the present invention can also have two types of circuit configurations, specifically as follows.

[0051] The pixel circuit of the first type of circuit configuration may specifically include a first selection circuit 10 and a second selection circuit 20, each employing the respective first type of circuit configuration, as shown in Figure 3. The pixel circuit of the second type of circuit configuration may specifically include a first selection circuit 10 and a second selection circuit 20, each employing the respective second type of circuit configuration, as shown in Figure 4.

[0052] On the other hand, based on the circuit configurations of the two types of pixel circuits described above, the effective display area of ​​the present invention may also have two types of pixel circuit arrangements, specifically as follows.

[0053] The first type of setting method is one in which the circuit configuration of any pixel circuit within the effective display area is the same. Specifically, see Figure 7, and all pixel circuits in this case may adopt the circuit configuration of the first type. In other words, in this case, the conduction current of the first unidirectional circuit 11, the second unidirectional circuit 12, the third unidirectional circuit 21, and the fourth unidirectional circuit 22 in any pixel circuit is the same as that of the first unidirectional circuit 11, the second unidirectional circuit 12, the third unidirectional circuit 21, and the fourth unidirectional circuit 22 in another adjacent pixel circuit in the same row. The timing controller can achieve row inversion control for each pixel in the effective display area by controlling the polarity of the data signals transmitted on any two adjacent data lines L2 to be reversed, thereby planning the combination of polarities of each pixel in the effective display area so that the polarities of two pixels adjacent vertically are different.

[0054] The second type of setting method can be specifically described in Figure 8, in which any two adjacent pixel circuits on the same row within the effective display area are different, but any two adjacent pixel circuits on the same column are the same. In this case, the effective display area is provided with pixel circuits of two different circuit configurations. In other words, in this case, the conduction current of the first unidirectional circuit 11, the second unidirectional circuit 12, the third unidirectional circuit 21, and the fourth unidirectional circuit 22 within any pixel circuit is the opposite of the first unidirectional circuit 11, the second unidirectional circuit 12, the third unidirectional circuit 21, and the fourth unidirectional circuit 22 within another adjacent pixel circuit in the same row. The timing controller plans the polarity combination of each pixel within the effective display area by controlling the data signals transmitted on any two adjacent data lines L2 to have the same polarity, thereby realizing dot inversion control for each pixel within the effective display area. Furthermore, due to the unidirectional conductivity of the PN junction, the polarity of the pixel electrodes can be changed simultaneously by correspondingly changing the polarity of the common electrode.

[0055] Example 3: This application further proposes a display device including scan lines L1, data lines L2, a first pixel PXL1, a second pixel PXL2, and a pixel circuit. The specific configuration of this pixel circuit can be found in the above-described embodiment. Since this display device incorporates all the technical concepts of all the above-described embodiments, it possesses at least all the beneficial effects of the technical concepts of the above embodiments, and therefore, further explanation is omitted here.

[0056] The first pixel PXL1 and the second pixel PXL2 are located on opposite sides of the scan line L1, the first pixel PXL1 includes a first pixel electrode S1, and the second pixel PXL2 includes a second pixel electrode S2, and the pixel circuit is connected to the scan line L1, the data line L2, the first pixel electrode S1, and the second pixel electrode S2, respectively. The display device may further include a timing controller, which can display the current frame by controlling the pixel circuit to drive the operation of the first pixel PXL1 and the second pixel PXL2 according to the pixel control method described above.

[0057] The foregoing describes only preferred embodiments of the present application and does not thereby limit the scope of the patent. Any equivalent structural transformations or direct / indirect applications to other related technical fields made using the contents of the specification and accompanying drawings of the present application under the inventive concept of the present application are all within the scope of the patent protection of the present application.

Claims

1. A pixel circuit used in a display panel, comprising a scan line (L1), a data line (L2), a first pixel (PXL1) including a first pixel electrode (S1), and a second pixel (PXL2) including a second pixel electrode (S2), A first thin-film transistor (T1) has a controlled terminal connected to the scan line (L1) and an input terminal connected to the data line (L2), The first selection circuit (10) includes an input terminal connected to the output terminal of the first thin-film transistor (T1), a first output terminal connected to the first pixel electrode (S1), and a second output terminal connected to the second pixel electrode (S2), The first thin-film transistor (T1) is used to sequentially charge the first pixel (PXL1) and the second pixel (PXL2) so that they can be sequentially charged to the pixel potential of the corresponding current frame by sequentially writing the data signal transmitted on the data line (L2) to the first pixel (PXL1) and the second pixel (PXL2) via the first selection circuit (10) in accordance with the scanning signal transmitted on the scan line (L1). The first selection circuit (10) includes a plurality of unidirectional circuits, each of which has unidirectional conduction characteristics. Pixel circuit.

2. One scan line (L1) and one first thin-film transistor (T1) within the pixel circuit control the display of the first pixel (PXL1) and the second pixel (PXL2) located on either side of the scan line (L1). The pixel circuit according to claim 1.

3. Multiple unidirectional circuits, A first unidirectional circuit (11) has a first terminal connected to the output terminal of the first thin-film transistor (T1) and a second terminal connected to the first pixel electrode (S1), The system includes a second unidirectional circuit (12) whose first terminal is connected to the output terminal of the first thin-film transistor (T1) and whose second terminal is connected to the second pixel electrode (S2), When the first thin-film transistor (T1) outputs a data signal, one of the first unidirectional circuit (11) and the second unidirectional circuit (12) conducts, and the other turns off, and the direction of the current conduction of the first unidirectional circuit (11) and the direction of the current conduction of the second unidirectional circuit (12) are opposite. The pixel circuit according to claim 1.

4. The aforementioned pixel circuit is The controlled terminal is connected to a predetermined number of scan lines (L1) of the previous row, the input terminal is used to connect to a predetermined reset potential (DC1), the first output terminal is connected to the first pixel electrode (S1), and the second output terminal is connected to the second pixel electrode (S2), including a reset circuit (30), The reset circuit (30) is used to reset the first pixel (PXL1) and the second pixel (PXL2) by outputting a predetermined reset potential (DC1) to the first pixel electrode (S1) and the second pixel electrode (S2) in response to a scan signal transmitted on the previous predetermined number of scan lines (L1). The pixel circuit according to claim 3.

5. The fourth thin-film transistor (T4) and the fifth thin-film transistor (T5) have gates connected to the scan lines (L1) of the predetermined number of rows, respectively, and drains connected to the first potential line (L3), the drain of the fourth thin-film transistor (T4) is connected to the first pixel electrode (S1), the drain of the fifth thin-film transistor (T5) is connected to the second pixel electrode (S2), and the first potential line (L3) is connected to and used to transmit the predetermined reset potential (DC1). The pixel circuit according to claim 4.

6. The aforementioned pixel circuit is The system further includes a second selection circuit (20) whose first input terminal is connected to the first output terminal of the reset circuit (30), whose second input terminal is connected to the second output terminal of the reset circuit (30), whose first output terminal is connected to the first pixel electrode (S1), and whose second output terminal is connected to the second pixel electrode (S2). The pixel circuit according to claim 4.

7. The second selection circuit (20) is, A third unidirectional circuit (21) has a first terminal connected to the first pixel electrode (S1) and a second terminal connected to the first output terminal of the reset circuit (30), The system includes a fourth unidirectional circuit (22) whose first terminal is connected to the second pixel electrode (S2) and whose second terminal is connected to the second output terminal of the reset circuit (30), When the reset circuit (30) is in operation, the first unidirectional circuit (11) and the second unidirectional circuit (12) are both in operation, the direction of the current flowing through the third unidirectional circuit (21) is the same as the direction of the current flowing through the first unidirectional circuit (11), and the direction of the current flowing through the fourth unidirectional circuit (22) is the same as the direction of the current flowing through the second unidirectional circuit (12). The pixel circuit according to claim 6.

8. The aforementioned pixel circuit is A second thin-film transistor (T2) is used to connect its controlled terminal to the scan line (L1), its input terminal to a first predetermined potential (DC2), and its output terminal to the second terminal of the third unidirectional circuit (21), A third thin-film transistor (T3) is used to connect its controlled terminal to the scan line (L1), its input terminal to a second predetermined potential (DC3), and its output terminal to the second terminal of the fourth unidirectional circuit (22), The pixel circuit according to claim 7, further comprising:

9. The first unidirectional circuit (11), the second unidirectional circuit (12), the third unidirectional circuit (21), and the fourth unidirectional circuit (22) include a PN junction. The pixel circuit according to claim 7.

10. The third unidirectional circuit (21) has a first terminal which is the positive terminal of the third PN junction (PN3) and a second terminal which is the negative terminal of the third PN junction (PN3), and the fourth unidirectional circuit (22) has a first terminal which is the negative terminal of the fourth PN junction (PN4) and a second terminal which is the positive terminal of the fourth PN junction (PN4). The pixel circuit according to claim 7.

11. The third unidirectional circuit (21) has a first terminal which is the negative terminal of the third PN junction (PN3) and a second terminal which is the positive terminal of the third PN junction (PN3), and the fourth unidirectional circuit (22) has a first terminal which is the positive terminal of the fourth PN junction (PN4) and a second terminal which is the negative terminal of the fourth PN junction (PN4). The pixel circuit according to claim 7.

12. A pixel control method applied to a pixel circuit used in a display panel, which includes scan lines (L1), data lines (L2), a first pixel (PXL1) including a first pixel electrode (S1), and a second pixel (PXL2) including a second pixel electrode (S2), The aforementioned pixel circuit is A first thin-film transistor (T1) has a controlled terminal connected to the scan line (L1) and an input terminal connected to the data line (L2), The first selection circuit (10) includes an input terminal connected to the output terminal of the first thin-film transistor (T1), a first output terminal connected to the first pixel electrode (S1), and a second output terminal connected to the second pixel electrode (S2), The first thin-film transistor (T1) is used to sequentially charge the first pixel (PXL1) and the second pixel (PXL2) so that they can be sequentially charged to the pixel potential of the corresponding current frame by sequentially writing the data signal transmitted on the data line (L2) to the first pixel (PXL1) and the second pixel (PXL2) via the first selection circuit (10) in accordance with the scanning signal transmitted on the scan line (L1). The aforementioned pixel control method is, In the first subphase, a high-potential scanning signal is output to the Nth scan line (L1), and a data signal with a predetermined potential and positive polarity is output to the data line (L2), thereby charging the first pixel (PXL1) to the pixel potential of the corresponding current frame (S100). In the second subphase, a high-potential scanning signal is output to the Nth scan line (L1), and a data signal with a predetermined potential and negative polarity is output to the data line (L2), thereby charging the second pixel (PXL2) to the pixel potential of the corresponding current frame (S200). A pixel control method including the following.

13. In two adjacent pixel circuits of the same row, if the direction of the current conduction of the first unidirectional circuit (11), the second unidirectional circuit (12), the third unidirectional circuit (21), and the fourth unidirectional circuit (22) is the same, the polarity of the data signals transmitted on any two adjacent data lines (L2) is controlled to be reversed. In two adjacent pixel circuits of the same row, if the direction of the current conduction of the first unidirectional circuit (11), the second unidirectional circuit (12), the third unidirectional circuit (21), and the fourth unidirectional circuit (22) is opposite, control is performed so that the polarity of the data signals transmitted on any two adjacent data lines (L2) is the same. The pixel control method according to claim 12.

14. Scan line (L1) and, Data line (L2) and, A first pixel (PXL1) including a first pixel electrode (S1), A second pixel (PXL2) including a second pixel electrode (S2), The system includes the scan line (L1), the data line (L2), the first pixel electrode (S1), and the second pixel electrode (S2), respectively, and a pixel circuit connected to each of them. A display device used in a pixel control method, which controls the pixel circuit to drive the operation of the first pixel (PXL1) and the second pixel (PXL2), The control method described above is In the first subphase, a high-potential scanning signal is output to the Nth scan line (L1), and a data signal with a predetermined potential and positive polarity is output to the data line (L2), thereby charging the first pixel (PXL1) to the pixel potential of the corresponding current frame (S100). In the second subphase, a high-potential scanning signal is output to the Nth scan line (L1), and a data signal with a predetermined potential and negative polarity is output to the data line (L2), thereby charging the second pixel (PXL2) to the pixel potential of the corresponding current frame (S200). A display device that includes a display device.

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