Superjunction semiconductor device

Abstract

To provide a super junction semiconductor device capable of mitigating an electric field near a channel stopper and preventing a decrease in breakdown voltage in an edge termination region.SOLUTION: A super junction semiconductor device 40 has an active region 30 and a termination structure portion 31. An active region 30 and the termination structure portion 31 have a first conductivity type of semiconductor substrate, a first conductivity type of a first semiconductor layer and a parallel pn structure 19 in which a striped first conductivity type of first column 4 and a striped second conductivity type of second column 3 are repeatedly arranged alternately in a direction parallel to the front surface. The termination structure portion 31 has a channel stopper on the surface layer of the parallel pn structure 19, and in the parallel pn structure 19, the second column 3 is separated from the channel stopper by 0.1 μm or more in the longitudinal direction of the second column 3.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This invention relates to a superjunction semiconductor device. [Background technology]

[0002] In a typical n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the n-type conduction layer (drift layer) is the most resistive of the multiple semiconductor layers formed within the semiconductor substrate. The electrical resistance of this n-type drift layer significantly affects the overall on-resistance of the vertical MOSFET. Reducing the overall on-resistance of the vertical MOSFET can be achieved by reducing the thickness of the n-type drift layer and shortening the current path.

[0003] However, vertical MOSFETs also have the function of maintaining their breakdown voltage by extending the depletion layer to the high-resistance n-type drift layer in the off state. Therefore, if the n-type drift layer is thinned to reduce on-resistance, the extension of the depletion layer in the off state becomes shorter, making it easier to reach the breakdown field strength at a low applied voltage, and thus reducing the breakdown voltage. On the other hand, in order to increase the breakdown voltage of a vertical MOSFET, it is necessary to increase the thickness of the n-type drift layer, which increases the on-resistance. This relationship between on-resistance and breakdown voltage is called a trade-off relationship, and it is generally difficult to improve both of them simultaneously.

[0004] A superjunction (SJ) structure is known as a semiconductor device structure that solves the problems described above. For example, a MOSFET having a superjunction structure (SJ structure) (hereinafter referred to as SJ-MOSFET) is known.

[0005] Figure 24 is a plan view showing the structure of a conventional superjunction semiconductor device. As shown in Figure 24, the SJ-MOSFET 140 comprises an active region 130 and an edge termination region 131 surrounding the active region 130. The active region 130 is the region through which current flows when the device is ON. The edge termination region 131 is the region that mitigates the electric field on the substrate surface side of the drift region and maintains the breakdown voltage.

[0006] The SJ-MOSFET140 has a parallel structure (hereinafter referred to as the parallel pn structure 119) in which p-type column regions 103 and n-type column regions 104 are alternately arranged in the active region 130 and the edge termination region 131. In the parallel pn structure 119, by making the amount of impurities contained in the p-type column region 103 and the n-type column region 104 approximately equal, a pseudo-undoped layer can be created in the off state, thereby achieving a high breakdown voltage.

[0007] Figure 25 is a cross-sectional view showing the structure of a conventional superjunction semiconductor device. Figure 25(a) is a cross-sectional view of Figure 24 along the line Y-Y'. Figure 25(b) is a cross-sectional view of Figure 24 along the line X-X'. Figure 25(c) is a cross-sectional view of Figure 24 along the line X1-X1'. Also, Figure 25(b) is a cross-sectional view of part A in Figure 25(a). Figure 25(c) is a cross-sectional view of part B in Figure 25(a).

[0008] As shown in Figures 25(a) to 25(c), the SJ-MOSFET140 has a high impurity concentration n + The material is a wafer on which an n-type drift layer 102 is grown on a type semiconductor substrate 101. The n-type drift layer 102 has a parallel pn structure 119 in which p-type column regions 103 that penetrate the n-type drift layer 102 from the wafer surface, extend in a direction perpendicular to the main surface of the substrate and have a narrow width in a plane parallel to the main surface of the substrate, and n-type column regions 104 sandwiched between the p-type column regions 103 are alternately arranged in a plane parallel to the main surface of the substrate. In Figures 25(a) and 25(b), the p-type column regions 103 are n + Although it has reached the semiconductor substrate 101, n + It is not necessary to reach the semiconductor substrate 101.

[0009] In the active region 130, a p-type base region 106 is provided on the parallel pn structure 119 of the SJ-MOSFET 140. Inside the p-type base region 106, an n + -type source region 107 is provided. A p + -type contact region may be provided inside the p-type base region 106. Also, a trench 118 is provided that penetrates the p-type base region 106 and the n + -type source region 107 and reaches the p-type column region 103. An n + -type source region 107 is arranged so as to contact the side surface of this trench 118.

[0010] Also, inside the parallel pn structure 119, a first p + -type base region 114 is selectively provided so as to cover the entire bottom surface of the trench 118. On the surface layer opposite to the n + -type semiconductor substrate 101 side of the parallel pn structure 119, a second p + -type base region 115 is selectively provided.

[0011] The inner wall surface of the trench 118 is covered with a gate insulating film 109 formed of an oxide film or the like, and the inside of the trench 118 is filled with a gate electrode 110 formed on the surface of the gate insulating film 109. In this way, a trench gate structure is configured. Also, an ohmic electrode (not shown) is electrically connected to the p-type base region 106 and the n + -type source region 107 through a contact hole formed in an interlayer insulating film (not shown).

[0012] And on the back side of the n + -type semiconductor substrate 101, a back surface electrode (not shown) electrically connected to the n + -type semiconductor substrate 101 is formed.

[0013] In the edge termination region 131, the p-type base region 106 and the second p +The p-type base region 115 is removed, and a step is formed in which the edge-terminal region 131 is lower than the active region 130 (recessed towards the drain side), exposing the parallel pn structure 119 at the bottom surface of the step. This step is intended to remove the p-type base region 106 at the edge-terminal region 131 when the p-type base region 106 is formed by epitaxial growth, but is not necessary when the p-type base region 106 is formed by ion implantation.

[0014] Furthermore, the edge termination region 131 is provided with a JTE structure in which multiple p-type regions (in this case, two, the first JTE region 120 and the second JTE region 121) are arranged adjacent to each other. In addition, an n functioning as a channel stopper is provided on the outside of the JTE structure (towards the chip end). + A mold region 122 is provided.

[0015] The first JTE region 120 and the second JTE region 121 are selectively provided in the portion of the parallel pn structure 119 that is exposed at the bottom of the step. When a high voltage is applied, the lateral high voltage outside the active region 130 is maintained at the pn junction between the first JTE region 120, the second JTE region 121 and the n-type column region 104.

[0016] It is known that SJ structures have low avalanche tolerance, especially when the amount of impurities in the p-type column region 103 and the n-type column region 104 are approximately equal, resulting in a charge balance and the highest static pressure resistance. Conversely, it is known that structures with a slight deviation from the charge balance, particularly those with a greater charge in the p-type column region 103 than in the n-type column region 104 (p-rich), exhibit high avalanche tolerance. Furthermore, it is known that by making the surface side of the SJ structure p-rich and the substrate side (drain side) with a greater charge in the n-type column region 104 than in the p-type column region 103 (n-rich), the margin for variation in charge amounts can be improved, and avalanche tolerance can be enhanced.

[0017] Furthermore, there is a known MOSFET in which the average positive charge density ρ(x) at a predetermined depth position of the SJ structure when the MOSFET is turned off and the SJ structure is depleted can be represented by an upward-convex, right-sloping curve, thereby reducing the variation in switching characteristics when the MOSFET is turned off compared to conventional MOSFETs (see, for example, Patent Document 1 below). Also, there is a known semiconductor device in which the p-type column region does not reach the channel stopper in the longitudinal direction of the p-type column region, and in which no p-type column region is provided below the channel stopper in the direction in which the n-type column region and the p-type column region are aligned (see, for example, Patent Document 2 below).

[0018] Furthermore, in the peripheral region, semiconductor devices are known that have a charge balance change region in which the amount of N-type charge in the superjunction structure gradually increases to more than the amount of P-type charge as you move toward the outer periphery of the cell region (see, for example, Patent Document 3 below). Also known are semiconductor devices that have an n-type drift layer that carries a drift current when on and depletes when off, a p-type drift layer that depletes when off, and in addition, a second n-type drift layer and a second p-type drift layer formed in at least one of two mutually orthogonal directions in the junction termination region (see, for example, Patent Document 4 below). Furthermore, semiconductor devices are known that have a final edge structure comprising a plurality of N-type superimposed semiconductor layers and two inserted columns within a plurality of superimposed semiconductor layers consisting of stacked P-type doped regions, with the column closer to the high-voltage semiconductor device being deeper than the column further away from the device (see, for example, Patent Document 5 below). Furthermore, a semiconductor device is known in which pairs of p-type epitaxial embedding layers and n-type epitaxial layers are arranged alternately in a superjunction structure, with p-type lateral resurf regions provided at the terminals, and each p-type epitaxial embedding layer at the terminals does not have a p-type lateral resurf region on at least a portion of its surface and does not overlap (see, for example, Patent Document 6 below). [Prior art documents] [Patent Documents]

[0019] [Patent Document 1] Japanese Patent Publication No. 2018-164098 [Patent Document 2] Japanese Patent Publication No. 2015-164218 [Patent Document 3] International Publication No. 2013 / 046544 [Patent Document 4] Japanese Patent Publication No. 2003-273355 [Patent Document 5] Japanese Patent Publication No. 2000-183350 [Patent Document 6] Japanese Patent Publication No. 2010-040973 [Overview of the project] [Problems that the invention aims to solve]

[0020] However, if the surface is p-rich and a JTE structure is formed in the p-type column region 103, it becomes even more p-rich, making it difficult for the p-type column region 103 to be depleted. This can lead to a concentration of the electric field between the p-type column region 103 and the channel stopper, potentially reducing the breakdown voltage.

[0021] Furthermore, a p-type column region 103 also exists on the outer periphery of the edge termination region 131. At relatively low voltages where the p-type column region 103 is not completely depleted, if a neutral region of the source potential exists in the p-type column region 103, a high electric field is applied between it and the channel stopper of the drain potential, raising concerns about a decrease in breakdown voltage.

[0022] Even in such cases, applying an even higher voltage will completely deplete the p-type column region 103, thus mitigating the electric field. However, there is a concern that an avalanche current may flow during the voltage increase process. This concern is particularly heightened when the column is p-rich to improve avalanche tolerance or when the surface is p-rich.

[0023] Figure 26 shows the extent of the depletion layer at low voltage (Vds1) in the edge termination region of a conventional superjunction semiconductor device. Figure 26(a) is a plan view, and Figure 26(b) is a cross-sectional view of Figure 26(a) along X-X'. Here, the depletion layer on the n-type column region 104 side and the channel stopper side is not shown. The same applies to Figures 27(a) to 28(b). As shown in Figures 26(a) and 26(b), at low drain-source voltage Vds1, the drain potential of the channel stopper (n + A source-drain voltage is applied to the depletion layer 132 extending from the junction between the p-type region 122 and the p-type column region 103. The breakdown voltage at this time is the channel stopper (n + This represents the bonding strength between the type region 122) and the p-type column region 103.

[0024] Figure 27 shows the extent of the depletion layer at a medium voltage (Vds2) in the edge termination region of a conventional superjunction semiconductor device. Figure 27(a) is a plan view, and Figure 27(b) is a cross-sectional view of Figure 27(a) along the line X-X'. As shown in Figures 27(a) and 27(b), at higher voltages Vds2, the depletion layer 132 extending from the junction between the p-type column region 103 and the n-type column region 104 acts as a channel stopper (n + It connects to the depletion layer 132 extending from the junction between the p-type region 122) and the p-type column region 103.

[0025] Figure 28 shows the depletion layer spread at high voltage (Vds3) in the edge termination region of a conventional superjunction semiconductor device. Figure 28(a) is a plan view, and Figure 28(b) is a cross-sectional view of Figure 28(a) along X-X'. As shown in Figures 28(a) and 28(b), the voltage Vds2 is channel stopper (n + If the voltage is below the breakdown voltage of the junction between the p-type region 122) and the p-type column region 103, increasing the drain-source voltage to Vds3 will further expand the depletion layer 132 extending from the junction between the p-type column region 103 and the n-type column region 104, and the neutral region 133 and the channel stopper (n + Because the distance between type region 122) is large, breakdown does not occur at low voltages, but the channel stopper (n +When the breakdown voltage exceeds the junction breakdown voltage between the type region 122) and the p-type column region 103, breakdown occurs at a low voltage. This problem is particularly likely to occur when the column is p-rich to increase avalanche tolerance, or when the surface is p-rich.

[0026] Figure 29 shows the breakdown location of a 1200V class SJ-SiCMOSFET at high temperature (175°C). Figures 29(a) and 29(b) are examples of different chips, and the breakdown location is identified by the emission of light from the surface when the chip is +50%p rich and heated to high temperature (175°C).

[0027] As shown by arrow A in Figure 29(a), the annular first JTE region 120 surrounds the active region 130, and the area outside the second JTE region 121 is further surrounded by n + It can be seen that light is being emitted in the p-type column region 103 in contact with the type region 122. Also, as shown by arrow B in Figure 29(b), n is outside the first JTE region 120 and the second JTE region 121. + It can be seen that light is emitted along the type region 122, and that light is emitted even outside the p-type column region 103. Furthermore, as shown in Figures 29(a) and 29(b), it can be seen that light is not emitted along the top and bottom edges of the chip, but rather in the left-right direction of the chip, i.e., at the longitudinal end of the p-type column region 103. This is because the n-type region is located at the top and bottom of the chip. + Because the p-type column region 103, which overlaps with the type region 122, is not directly connected to the source potential, the p-type column region 103 becomes floating due to depletion of the JTE regions 120 and 121 at low voltages, and even if a neutral region exists in the p-type column region 103, its potential will be between the drain potential and the source potential, so breakdown does not occur.

[0028] Thus, in the structure of the SJ-MOSFET140, the breakdown voltage decreases at high temperatures, and in the state of reduced breakdown voltage, the p-type column region 103 and the high concentration of n +A breakdown occurs when the electric field concentrates at the point where the type regions 122 meet. This is because Al is used as a p-type impurity in SiC, and Al has the shallowest acceptor level among p-type impurities. Furthermore, deep electron traps and hole traps exist in SiC, and it is known that many deep electron traps and deep hole traps are generated, especially by Al ion implantation. Therefore, it is thought that the depletion layer shrinks as the majority carriers trapped in deep traps at room temperature are detrapped at high temperatures.

[0029] The purpose of this invention is to provide a super-junction semiconductor device that can mitigate the electric field near the channel stopper and prevent a decrease in breakdown voltage in the edge termination region, in order to solve the problems of the conventional technology described above. [Means for solving the problem]

[0030] To solve the above-mentioned problems and achieve the objectives of the present invention, the superjunction semiconductor device according to this invention has the following features. The superjunction semiconductor device has an active region through which electric current flows, and a termination structure disposed outside the active region and having a breakdown structure formed thereon. The active region and the termination structure include a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the front surface of a semiconductor substrate of a first conductivity type, and a parallel pn structure provided on the surface of the first semiconductor layer, in which striped first columns of a first conductivity type and striped second columns of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface. The termination structure includes a channel stopper disposed to surround the parallel pn structure in a plan view. The second column of the parallel pn structure is provided away from the channel stopper in the longitudinal direction of the second column. At the longitudinal end of the second column of the parallel pn structure, the product of the width of the second column and the impurity concentration of the second column is equal to or greater than the product of the width of the first column and the impurity concentration of the first column, and the second column and the channel stopper are separated by 0.1 μm or more in the longitudinal direction of the second column. The second column is implanted with impurities of a second conductivity type, and the activation rate of the implanted impurities is greater than 70% and less than or equal to 90%.

[0031] To solve the above-mentioned problems and achieve the objectives of the present invention, the superjunction semiconductor device according to this invention has the following features. The superjunction semiconductor device has an active region through which electric current flows, and a termination structure disposed outside the active region and having a voltage-resistant structure formed thereon. The active region and the termination structure each include a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the front surface of a semiconductor substrate of a first conductivity type, and a parallel pn structure provided on the surface of the first semiconductor layer, in which striped first columns of a first conductivity type and striped second columns of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface. The terminal structure comprises a channel stopper arranged to surround the parallel pn structure in a plan view, the second column of the parallel pn structure is provided at a distance from the channel stopper in the longitudinal direction of the second column, and at the longitudinal end of the second column of the parallel pn structure, the product of the width of the second column and the impurity concentration of the second column is greater than the product of the width of the first column and the impurity concentration of the first column, the width of the second column is +50% or less of the width of the first column, and the distance between the second column and the channel stopper is 0.4 μm or more in the longitudinal direction of the second column.

[0032] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, the distance at which the second column of the parallel pn structure is separated from the channel stopper in the longitudinal direction of the second column, which is directly connected to the surface electrode potential, is uniform in the straight portion of the channel stopper, and at the corner portion of the channel stopper, it is the same as or longer than the distance in the straight portion.

[0033] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, each of the longitudinal ends of the second column of the parallel pn structure is inclined in accordance with the curvature of the channel stopper at the corner portion of the channel stopper.

[0034] Furthermore, the superjunction semiconductor device according to the present invention is characterized in that the active region comprises a second semiconductor layer of a second conductivity type provided on the surface side of the parallel pn structure, a first semiconductor region of a first conductivity type selectively provided on the surface layer of the second semiconductor layer, a gate insulating film provided on the surface side of the second semiconductor layer and in contact with the second semiconductor layer, and a gate electrode provided on the surface side of the gate insulating film opposite to the surface in contact with the second semiconductor layer.

[0035] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the above-described invention, the first and second columns of the parallel pn structure do not reach the semiconductor substrate.

[0036] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the above-described invention, the semiconductor substrate is composed of a wide-bandgap semiconductor.

[0037] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, the channel stopper is of the first conductivity type.

[0038] Furthermore, the superjunction semiconductor device according to this invention is characterized in that, in the invention described above, the semiconductor substrate is a silicon carbide semiconductor, the first conductivity type is n-type formed by adding nitrogen to the silicon carbide semiconductor, and the second conductivity type is p-type formed by adding aluminum to the silicon carbide semiconductor.

[0039] According to the invention described above, the p-type column region (second column of the second conductivity type) in the second parallel pn structure of the terminal region is n +Because it is separated from the type region (channel stopper), the amount of p-type impurities in the second parallel pn structure of the termination region is less than the amount of p-type impurities in the parallel pn structure of the active region and the first parallel pn structure of the termination region. This prevents the electric field from concentrating in the area where the channel stopper and the p-type column region overlap when the neutral region remains in the edge termination region at low voltages, thereby mitigating the electric field near the channel stopper and preventing a decrease in breakdown voltage in the edge termination region. [Effects of the Invention]

[0040] The super-junction semiconductor device according to the present invention has the effect of mitigating the electric field near the channel stopper and preventing a decrease in breakdown voltage in the edge termination region. [Brief explanation of the drawing]

[0041] [Figure 1] Figure 1 is a plan view showing the structure of a super-junction semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a cross-sectional view of Figure 1 showing the structure of a superjunction semiconductor device according to Embodiment 1. [Figure 3] Figure 3 is a plan view of the simulated edge termination region in the super-junction semiconductor device according to Embodiment 1. [Figure 4] Figure 4 is a plan view of the simulated edge termination region in the superbonding semiconductor device according to Embodiment 1. [Figure 5] Figure 5 is a plan view of the simulated edge termination region in the super-junction semiconductor device according to Embodiment 1. [Figure 6] Figure 6 is a cross-sectional view showing the state of a super-junction semiconductor device during the manufacturing process according to Embodiment 1. [Figure 7] Figure 7 is a plan view showing the structure of a super-junction semiconductor device according to Embodiment 2. [Figure 8] Figure 8 is a cross-sectional view of Figure 7 showing the structure of a superjunction semiconductor device according to Embodiment 2. [Figure 9]Figure 9 is a plan view of the simulated edge termination region in the super-junction semiconductor device according to Embodiment 2. [Figure 10] Figure 10 is a plan view of the simulated edge termination region in the super-junction semiconductor device according to Embodiment 2. [Figure 11] Figure 11 is a simulated diagram of the structure of the edge termination region of the superjunction semiconductor device according to Embodiment 2. [Figure 12] Figure 12 is a plan view showing the structure of a super-junction semiconductor device according to Embodiment 3. [Figure 13] Figure 13 is a cross-sectional view showing the structure of a super-junction semiconductor device according to Embodiment 3. [Figure 14] Figure 14 is a cross-sectional view showing the structure of a super-bonding semiconductor device according to Embodiment 4. [Figure 15] Figure 15 is a superjunction semiconductor device according to Embodiment 5, and is a top view showing the longitudinal end of the p-type column region set up for simulation, similar to Figures 3 to 5 and Figures 9 to 11. [Figure 16] Figure 16 is a graph showing the decrease in breakdown voltage at high temperatures when an SJ-SiCMOSFET with a breakdown voltage of 1200V class is constructed as shown in Figure 15(c). [Figure 17] Figure 17 is a graph showing the relationship between Vds and COSS for a 3300V class full SJ-SiC MOSFET. [Figure 18] Figure 18 is a graph showing the relationship between the width of the p-type column region and the depletion voltage of the p-type column region in a 3300V class SJ-SiCMOSFET. [Figure 19] Figure 19 is a graph showing the dependence of the dielectric breakdown field on doping density. [Figure 20] Figure 20 is a graph showing the relationship between the distance between the p-type column region and the n+-type region and the breakdown voltage when the Al activation rate is 70% (the lower limit when formed by ion implantation). [Figure 21]Figure 21 is a graph showing the relationship between the distance between the p-type column region and the n+-type region and the breakdown voltage when the Al activation rate is 90% (the upper limit when formed by ion implantation). [Figure 22] Figure 22 is a graph showing the relationship between the distance between the p-type and n+-type column regions and the breakdown voltage when the Al activation rate is 100%. [Figure 23] Figure 23 is a top view showing the configuration of the neighborhood between the p-type column region and the n+-type region, magnified from one of the four corners in a plan view of the superjunction semiconductor device according to Embodiment 5. [Figure 24] Figure 24 is a plan view showing the structure of a conventional super-junction semiconductor device. [Figure 25] Figure 25 is a cross-sectional view showing the structure of a conventional superjunction semiconductor device. [Figure 26] Figure 26 shows the extent of the depletion layer at low voltage (Vds1) in the edge termination region of a conventional superjunction semiconductor device. [Figure 27] Figure 27 shows the extent of the depletion layer at medium voltage (Vds2) in the edge termination region of a conventional superjunction semiconductor device. [Figure 28] Figure 28 shows the extent of the high-voltage (Vds3) depletion layer in the edge termination region of a conventional superjunction semiconductor device. [Figure 29] Figure 29 shows the breakdown location at high temperatures for a 1200V class SJ-SiCMOSFET. [Modes for carrying out the invention]

[0042] Preferred embodiments of the superjunction semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. When the notation for n and p, including + and -, is the same, it indicates similar concentrations, but does not necessarily mean that the concentrations are equivalent. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0043] (Embodiment 1) The superjunction semiconductor device 40 according to the present invention is constructed using a wide-bandgap semiconductor. In Embodiment 1, a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC) as the wide-bandgap semiconductor will be described using a superjunction MOSFET as an example.

[0044] Figure 1 is a plan view showing the structure of a superjunction semiconductor device according to Embodiment 1. As shown in Figure 1, the SJ-MOSFET 40 comprises an active region 30 and an edge termination region 31 surrounding the active region 30. In Figure 1, the region inside the dotted line C is the active region 30, and the region between dotted line C and dotted line D is the edge termination region 31.

[0045] The SJ-MOSFET40 has a parallel structure (hereinafter referred to as the parallel pn structure 19) in which p-type column regions 3 and n-type column regions 4 are alternately arranged in the active region 30 and the edge termination region 31. In the parallel pn structure 19, the amount of impurities contained in the p-type column region 3 and the n-type column region 4 is made approximately equal, and charge balancing is achieved, thereby creating a pseudo-undoped layer in the off state and enabling high breakdown voltage.

[0046] Furthermore, the parallel pn structure 19 is composed of an active region parallel pn structure 19a, a terminal region first parallel pn structure 19b, and a terminal region second parallel pn structure 19c. The terminal region first parallel pn structure 19b is the portion of the parallel pn structure 19 on the active region 30 side in the longitudinal direction (x direction) between the p-type column region 3 and the n-type column region 4, and the terminal region second parallel pn structure 19c is the portion of the parallel pn structure 19 on the outer periphery side in the longitudinal direction (x direction).

[0047] Figure 2 is a cross-sectional view of Figure 1 showing the structure of the superjunction semiconductor device according to Embodiment 1. Figure 2(a) is a cross-sectional view of Figure 1 taken along the line Y-Y'. Figure 2(b) is a cross-sectional view of Figure 1 taken along the line X-X'. Figure 2(c) is a cross-sectional view of Figure 1 taken along the line X1-X1'. Furthermore, Figure 2(b) is a cross-section of part A in Figure 2(a), and Figure 2(c) is a cross-section of part B in Figure 2(a). Points C and D in Figures 2(a) to 2(c) correspond to the positions of the dotted lines C and D in Figure 1.

[0048] Figures 2(a) to 2(c) show a superjunction semiconductor device containing two unit cells (functional units of the element), but actual superjunction semiconductor devices contain more than two unit cells. The superjunction semiconductor device 40 shown in Figures 2(a) to 2(c) is a superjunction MOSFET equipped with a MOS gate on the front side (the side facing the p-type base region 6) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide.

[0049] The silicon carbide substrate is n + The MOS gate is formed by epitaxially growing a silicon carbide layer that will become an n-type drift layer 2 on the first main surface (front surface) of a type semiconductor substrate (first conductivity type semiconductor substrate) 1. The MOS gate consists of a p-type base region (second semiconductor layer of the second conductivity type) 6 and n + It consists of a type source region (first semiconductor region of the first conductivity type) 7, a gate insulating film 9, and a gate electrode 10.

[0050] The n-type drift layer 2 is provided with a parallel pn structure 19. The parallel pn structure 19 is formed by alternately joining p-type column regions (second semiconductor regions of the second conductivity type) 3 and n-type regions (n-type column regions 4) sandwiched between the p-type column regions 3. The p-type column regions 3 are formed by the bottom surface (n) of the p-type base region 6. + From the side of the semiconductor substrate 1, through the n-type drift layer 2, + The surface of the type semiconductor substrate 1 is reached. The planar shape of the p-type column region 3 and the n-type column region 4 is striped (rectangular), as shown in Figure 1.

[0051] A p-type base region 6 is provided on the source side (ohmic electrode side) surface layer of the n-type drift layer 2. A trench structure is formed on the first main surface side (p-type base region 6 side) of the silicon carbide substrate. Specifically, the trench 18 is the n-type of the p-type base region 6. + The gate electrode penetrates the p-type base region 6 from the surface opposite to the n-type semiconductor substrate 1 (the first main surface side of the silicon carbide substrate) and reaches the p-type column region 3. Along the inner wall of the trench 18, a gate insulating film 9 is formed at the bottom and side walls of the trench 18, and the gate electrode 10 is formed inside the gate insulating film 9 within the trench 18. The gate insulating film 9 insulates the gate electrode 10 from the n-type column region 4 and the p-type base region 6. A portion of the gate electrode 10 may protrude from above the trench 18 (the first main surface side) towards the ohmic electrode side.

[0052] Under Trench 18, page 1 + A type base region 14 may be provided, and the first p + The width of the base region 14 may be wider than the width of the trench 18. The n of the parallel pn structure 19 + On the surface layer opposite to the semiconductor substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate), the second p + The type base region 15 may be selectively provided so as to be connected to the p-type base region 6. + Type base region 14 and 2p + The mold base region 15 is doped with, for example, aluminum.

[0053] 1st p. + Type base region 14 and 2p + The depth position of the drain-side end of the base region 15 is the first p + Type base region 14 and 2p + The pn junction between the type base region 15 and the n-type column region 4 only needs to be located deeper on the drain side than the bottom surface of the trench 18, and can be modified in various ways according to the design conditions. + Type base region 14 and 2p + The mold base region 15 prevents a high electric field from being applied to the gate insulating film 9 in the portion along the bottom surface of the trench 18.

[0054] Inside the p-type base region 6, on the substrate first main surface side, n + A type source region 7 is selectively provided. Also, p + A type contact region (not shown) may be selectively provided. In this case, n + Type source region 7 and p + The contact regions may be in contact with each other. + The depth of the contact region is, for example, n + The type source area 7 may be shallower or deeper. Also, in the depth direction (x-axis direction) of the trench 18, p + Type contact region and n + A type source area 7 is provided alongside it.

[0055] The interlayer insulating film (not shown) is provided over the entire surface of the first main surface side of the silicon carbide substrate, covering the gate electrode 10 embedded in the trench 18. The ohmic electrode (not shown) is connected via a contact hole opened in the interlayer insulating film, n + It is adjacent to the p-type source region 7 and the p-type base region 6. + If a type contact area is provided, n + Type source region 7 and p +It contacts the type contact region. The ohmic electrode is electrically insulated from the gate electrode 10 by an interlayer insulating film. A source electrode pad (not shown) is provided on the ohmic electrode. A barrier metal (not shown) may be provided between the ohmic electrode and the interlayer insulating film to prevent the diffusion of metal atoms from the ohmic electrode to the gate electrode 10 side.

[0056] n + A back electrode (not shown) is provided on the second main surface (back surface, i.e., the back surface of the semiconductor substrate) of the semiconductor substrate 1. The back electrode constitutes the drain electrode.

[0057] Furthermore, as shown in Figures 2(a) to 2(c), the edge termination region 31 is provided with a junction termination extension (JTE) structure. In the edge termination region 31, the p-type base region 6 is removed throughout the entire region, and a step is formed on the surface of the silicon carbide substrate, making the edge termination region 31 lower than the active region 30 (recessed towards the drain side), with a parallel pn structure 19 exposed at the bottom of the step. In addition, the edge termination region 31 has multiple p-type structures, with the impurity concentration decreasing as they are positioned towards the outside (tip end side). - Type low concentration region (here there are two, from the inside out p - type, p -- A first JTE region 20 and a second JTE region 21 are provided as a JTE structure in which two adjacent JTE regions (designated as type 20 and 21) are arranged. In addition, outside the second JTE region 21 (towards the chip end), a channel stopper is provided. + A type region 22 is provided. A guard ring may be provided instead of the JTE structure. Note that in Figure 2(b), the p-type column region 3 terminates in the region that overlaps with the second JTE region 21, but as shown by the dotted line at the end of the arrow in Figure 2(b), the second JTE region 21 and n + The type region 22 may be terminated within that region.

[0058] In Embodiment 1, the amount of p-type impurities in the second parallel pn structure 19c of the terminal region is less than the amount of p-type impurities in the parallel pn structure 19a of the active region and the first parallel pn structure 19b of the terminal region. The amount of p-type impurities in the second parallel pn structure 19c of the terminal region is the product of the width w, length l, depth d, and p-type impurity concentration of the p-type column region 3 present in the second parallel pn structure 19c of the terminal region (see Figures 1 and 2(a)). The amount of p-type impurities in the parallel pn structure 19a of the active region and the first parallel pn structure 19b of the terminal region is similar.

[0059] In Figure 1, in the longitudinal direction (x direction) of the p-type column region 3, which is perpendicular to the direction in which the p-type column region 3 and the n-type column region 4 are aligned, the p-type column region 3 in the second parallel pn structure 19c of the terminal region functions as a channel stopper. + It is separated from the type region 22 (see Figures 2(a) to 2(c)). The amount of p-type impurities in the second parallel pn structure 19c of the terminal region is less than the amount of p-type impurities in the parallel pn structure 19a of the active region and the first parallel pn structure 19b of the terminal region. Note that in Figure 1, the n is located outside the dotted line D on the outer periphery of the edge terminal region 31. + Type region 22 is located there.

[0060] For example, the end of the p-type column region 3 in the second parallel pn structure 19c of the terminal region may be on the active region 30 side of the outer edge of the second JTE region 21 (see Figure 2(a)). Also, the end of the p-type column region 3 in the second parallel pn structure 19c of the terminal region may be n + If the type region 22 side has not been reached, then from the second JTE region 21, n + It may also be located on the type region 22 side.

[0061] Figure 3 is a plan view of the simulated edge termination region in the superjunction semiconductor device according to Embodiment 1. Figure 3(a) is a plan view showing the depletion layer extent in the simulation of a low voltage (Vds1) in the edge termination region. Figure 3(b) is a cross-sectional view of Figure 3(a) along X-X'. As shown in Figures 3(a) and 3(b), at a low voltage Vds1, the drain potential channel stopper (n +A source-drain voltage is applied to the depletion layer 32 extending from the junction between the n-type region (n-type column region 4) adjacent to the p-type region 22) and the p-type column region 3. Because the n-type column region 4 is located between the p-type column region 3 and the channel stopper, the breakdown voltage between the channel stopper and the p-type column region 3 increases.

[0062] Figure 4 is a plan view showing a simulated edge termination region in a superjunction semiconductor device according to Embodiment 1. Figure 4(a) is a plan view showing the expansion of the depletion layer in a simulation of a medium voltage (Vds2) in the edge termination region. Figure 4(b) is a cross-sectional view taken along X-X' in Figure 4(a). As shown in Figures 4(a) and 4(b), increasing Vds expands the depletion layer 32 on the p-type column region 3 side, increasing the distance between the neutral region 33 of the p-type column region 3 and the channel stopper, thus easing the electric field.

[0063] Figure 5 is a plan view showing a simulated edge termination region in a superjunction semiconductor device according to Embodiment 1. Figure 5(a) is a plan view showing the depletion layer expansion in a simulation of a high voltage (Vds3) in the edge termination region. Figure 5(b) is a cross-sectional view taken along X-X' in Figure 5(a). As shown in Figures 5(a) and 5(b), as the voltage increases from Vds2 to Vds3, the neutral region 33 recedes rapidly due to the effect of the SJ structure.

[0064] In this way, the amount of impurities (charge amount) in the p-type column region 3 of the edge-terminating region 31 is reduced on the drain potential side (channel stopper side), resulting in an n-rich state in the edge-terminating region 31. Therefore, in low voltage conditions (Vds1) where a neutral region (source potential region) remains in the edge-terminating region 31, it is possible to prevent the electric field from concentrating in the area where the channel stopper and the p-type column region 3 overlap, thereby mitigating the electric field near the channel stopper and preventing a decrease in breakdown voltage in the edge-terminating region 31.

[0065] (Method for manufacturing a super-junction semiconductor device according to Embodiment 1) Next, a method for manufacturing the super-junction semiconductor device 40 according to Embodiment 1 will be described. Figure 6 is a cross-sectional view showing the state of the super-junction semiconductor device during the manufacturing process according to Embodiment 1.

[0066] First, n made of n-type single crystal 4H-SiC + Prepare a semiconductor substrate 1. Then, n + A lower n-type drift layer 2a made of silicon carbide is epitaxially grown on the surface of a type semiconductor substrate 1 while doping it with n-type impurities. The state up to this point is shown in Figure 6(a). n made of single crystal 4H-SiC + A substrate in which an epitaxially grown layer such as a lower n-type drift layer 2a is formed on a type semiconductor substrate 1 is called a single-crystal 4H-SiC epitaxial substrate.

[0067] Next, an ion implantation mask 34 having predetermined openings is formed on the surface of the lower n-type drift layer 2a by photolithography, for example, using an oxide film. Then, p-type impurities are implanted into the openings of the oxide film to form the lower p-type column region 3a. The lower p-type column region 3a functions as an n-type channel stopper. + It is formed so as to be separate from the mold region 22 (not shown). The state up to this point is shown in Figure 6(b). Next, the ion implantation mask 34 is removed.

[0068] Next, an upper n-type drift layer 2b made of silicon carbide is epitaxially grown on the surfaces of the lower n-type drift layer 2a and the lower p-type column region 3a while doping with n-type impurities. This state is shown in Figure 6(c). Next, an ion implantation mask 34 with predetermined openings is formed on the surface of the upper n-type drift layer 2b using photolithography, for example, with an oxide film. Then, p-type impurities are injected into the openings of the oxide film to form the upper p-type column region 3b. The upper p-type column region 3b functions as a channel stopper, similar to the lower p-type column region 3a. + It is formed so as to be separate from the mold region 22 (not shown). The state up to this point is shown in Figure 6(d). Next, the ion implantation mask 34 is removed.

[0069] Next, the epitaxial growth process shown in Figure 6(c) and the ion implantation process shown in Figure 6(d) are repeated a predetermined number of times to form the p-type column region 3 and the n-type column region 4. The lower p-type column region 3a and the upper p-type column region 3b become part of the p-type column region 3, and the lower n-type drift layer 2a and the upper n-type drift layer 2b become part of the n-type column region 4. After forming the n-type column region 4, a portion of the n-type column region 4 is turned over to form the first p + Type base region 14 (not shown) and 2p + A mold base region 15 (not shown) may be formed. Although the above is a so-called multi-epitaxial method, it may also be formed by a so-called trench backfilling method, in which a trench is formed in the drift region of one conductivity type and an epitaxial layer containing impurities of the other conductivity type is grown in the trench.

[0070] Next, although the diagram showing the process in order is omitted, as shown in the cross-sectional view of Figure 2(a), a p-type base region 6 doped with p-type impurities such as aluminum is formed on the surfaces of the p-type column region 3 and the n-type column region 4. Next, a step is formed on the surface of the p-type base region 6 in the edge termination region 31 to a depth of, for example, 0.3 μm by photolithography and etching, and the p-type base region 6 is removed in the edge termination region 31 to expose the n-type drift layer 2. Next, an ion implantation mask having predetermined openings is formed on the surface of the p-type base region 6 by photolithography, for example, in a laminated structure of resist, oxide film, semiconductor film, or oxide film / semiconductor film. An n-type impurity such as phosphorus (P) is ion-implanted into these openings, and a portion of the surface of the p-type base region 6 is ion-implanted. + A type source region 7 is formed. Next, n + Remove the ion implantation mask used to form the n-type source region 7. Next, an ion implantation mask having a predetermined opening is formed in the same manner, and n-type impurities are ion-implanted into a portion of the surface of the n-type drift layer 2. + A type region 22 is formed. Next, n + Remove the ion implantation mask used to form the type region 22. + Type region 22 has the same mask n +It may be formed simultaneously with the type source region 7.

[0071] Next, an ion implantation mask having a predetermined opening is formed in the same manner, and p-type impurities such as aluminum are ion-implanted into a portion of the surface of the p-type base region 6, + A type contact region may be formed. + The impurity concentration in the p-type contact region is set to be higher than the impurity concentration in the p-type base region 6. Next, an ion implantation mask with predetermined openings is formed on the step of the edge termination region 31 and the surface of the n-type drift layer 2 by photolithography, for example, using an oxide film. P-type impurities are ion-implanted into these openings to form a first JTE region 20 and a second JTE region 21 on a portion of the step and the surface of the n-type drift layer 2. Next, the ion implantation mask used to form the first JTE region 20 and the second JTE region 21 is removed.

[0072] Next, heat treatment (annealing) is performed in an inert gas atmosphere at approximately 1700°C, and the p-type column regions 3 and n + Type source area 7, p + Activation treatment is performed on the contact region and other areas. As mentioned above, the ion implantation regions may be activated together in a single heat treatment, or they may be activated by performing heat treatment each time ion implantation is performed.

[0073] Next, a trench-forming mask having predetermined openings is formed on the surface of the p-type base region 6 by photolithography, for example, using an oxide film. Then, a trench 18 is formed by dry etching, penetrating the p-type base region 6 and reaching the n-type column region 4. The bottom of the trench 18 is the first p-type formed in the n-type column region 4. + The mold base region 14 may be reached. Next, the trench-forming mask is removed.

[0074] Before removing the trench-forming mask, isotropic etching may be performed to remove damage to the trenches 18, or heat treatment or sacrificial oxidation may be performed to round the corners of the bottom and opening of the trenches 18, while the trench-forming mask is still attached. Either isotropic etching or sacrificial oxidation may be performed alone. Alternatively, sacrificial oxidation may be performed after isotropic etching. The trench-forming mask is removed simultaneously with the oxide film formed by sacrificial oxidation.

[0075] Next, n + A gate insulating film 9 is formed along the surface of the mold source region 7 and the bottom and side walls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by deposition by a chemical reaction such as high-temperature oxidation (HTO).

[0076] If formed by thermal oxidation, the interface state density at the interface between the gate insulating film 9 and the semiconductor portion may be reduced by heat treatment (POA (Post Oxidation Anneal) treatment). If the gate insulating film 9 is formed by a deposition method such as HTO, post-deposition annealing (PDA) may be performed to reduce leakage current and improve the dielectric constant.

[0077] Next, a polycrystalline silicon layer, for example, doped with phosphorus atoms, is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed to fill the trench 18. The gate electrode 10 is formed by patterning this polycrystalline silicon layer using photolithography and leaving it inside the trench 18.

[0078] Next, for example, a ring glass is formed to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, and an interlayer insulating film (not shown) is formed. Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film. The interlayer insulating film and the gate insulating film 9 are patterned by photolithography, and n + a contact hole exposing the -type source region 7 is formed. p + When a -type contact region is formed, n + contact holes exposing the -type source region 7 and the n + -type source region 7 are formed. Thereafter, heat treatment (reflow) is performed to flatten the interlayer insulating film.

[0079] Next, a conductive film serving as an ohmic electrode (not shown) is provided in the contact hole and on the interlayer insulating film. This conductive film is selectively removed to leave only the ohmic electrode in the contact hole, and n + the -type source region 7 is brought into contact with the ohmic electrode. p + When a -type contact region is formed, n + the -type source region 7 and the p + -type contact region are brought into contact with the ohmic electrode. Next, the ohmic electrodes other than those in the contact holes are selectively removed.

[0080] Next, for example, by sputtering, an electrode pad serving as a source electrode pad (not shown) is deposited on the ohmic electrode on the front surface of the silicon carbide semiconductor substrate and on the upper portion of the interlayer insulating film.

[0081] Next, n + a back electrode (not shown) such as nickel is provided on the second main surface of the -type semiconductor substrate 1. Thereafter, heat treatment is performed in an inert gas atmosphere at about 1000 °C, and n +A back surface electrode that makes an ohmic contact with the type semiconductor substrate 1 is formed. When the trench 18 is not formed, an n-type well region is formed in a part of the surface region of the p-type base region 6, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 9, and the p-type base region 6 and each region formed on the surface of the p-type base region 6 are covered with the gate insulating film 9. On the gate insulating film 9, a polycrystalline silicon layer is formed as a gate electrode 10, the polycrystalline silicon layer is patterned and selectively removed, and the polycrystalline silicon layer is left on the part sandwiched between the n + type source region 7 and the n-type well region, and an interlayer insulating film is formed so as to cover the gate electrode 10.

[0082] In the above-described epitaxial growth and ion implantation, as the n-type impurity (n-type dopant), for example, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. that become n-type with respect to silicon carbide may be used. As the p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc. that become p-type with respect to silicon carbide may be used. In this way, the silicon carbide semiconductor device shown in FIGS. 1 to 2(c) is completed.

[0083] As described above, according to the first embodiment, since the p-type column region in the terminal region second parallel pn structure is separated from the n + type region (channel stopper), the amount of p-type impurities in the terminal region second parallel pn structure is made less than the amount of p-type impurities in the active region parallel pn structure and the terminal region first parallel pn structure. As a result, it is possible to prevent the electric field from concentrating on the portion where the channel stopper and the p-type column region overlap in the state where the neutral region remains in the p column of the edge terminal region and the voltage is low, relax the electric field near the channel stopper, and prevent the breakdown voltage from decreasing in the edge terminal region.

[0084] (Embodiment 2) Figure 7 is a plan view showing the structure of the superjunction semiconductor device according to Embodiment 2. Figure 8 is a cross-sectional view of Figure 7 showing the structure of the superjunction semiconductor device according to Embodiment 2. Figure 8(a) is a cross-sectional view taken along the line Y-Y' in Figure 7. Figure 8(b) is a cross-sectional view taken along the line X-X' in Figure 7. Figure 8(c) is a cross-sectional view taken along the line X1-X1' in Figure 7.

[0085] As shown in Figure 7, in Embodiment 2, in the longitudinal direction (x direction) of the p-type column region 3, which is perpendicular to the direction in which the p-type column region 3 and the n-type column region 4 are aligned, the width w of the p-type column region 3 narrows as it approaches the outer edge. As a result, the amount of impurities in the p-type column region 3 at the edge termination region 31 is reduced on the drain potential side (the n-type column region 3, which functions as a channel stopper). + It is reduced in the type region 22 side. Therefore, similar to Embodiment 1, when the voltage is low and a neutral region (region that is the source potential) remains in the edge termination region 31, the channel stopper (n + This prevents the electric field from concentrating in the area where the p-type region 22) and the p-type column region 3 overlap, and the channel stopper (n + This reduces the electric field near the mold region 22) and prevents a decrease in breakdown voltage in the edge termination region 31.

[0086] Figure 9 is a plan view showing a simulated edge termination region in a superjunction semiconductor device according to Embodiment 2. Figure 9(a) is a plan view showing the depletion layer spread in a simulation of a low voltage (Vds1) in the edge termination region. Figure 9(b) is a cross-sectional view taken along X-X' in Figure 9(a). As shown in Figures 9(a) and 9(b), because the amount of impurities at the end of the p-type column region 3 is small, at Vds1, the depletion layer 32 extending from the junction between the p-type column region 3 and the n-type column region 4 is already connected to the depletion layer 32 extending from the junction between the channel stopper and the p-type column region 3.

[0087] Figure 10 is a plan view of a simulated edge termination region in a superjunction semiconductor device according to Embodiment 2. Figure 10(a) is a plan view showing the depletion layer spread in a simulation of a medium voltage (Vds2) in the edge termination region. Figure 10(b) is a cross-sectional view of Figure 10(a) taken along X-X'. As shown in Figures 10(a) and 10(b), as Vds is further increased, the edge of the depletion layer 32 moves away from the channel stopper, so the electric field strength between the neutral region 33 at the source potential and the channel stopper at the drain potential does not increase, and breakdown does not occur at low voltages.

[0088] Figure 11 is a simulated diagram of the structure of the edge termination region of the superjunction semiconductor device according to Embodiment 2. Figure 11(a) is a plan view showing the spread of the depletion layer in a simulation of a high voltage (Vds3) in the edge termination region. Figure 11(b) is a cross-sectional view taken along X-X' in Figure 11(a). As shown in Figures 11(a) and 11(b), as the voltage is increased from Vds2 to Vds3, the neutral region 33 recedes rapidly due to the effect of SJ.

[0089] (Method for manufacturing a super-junction semiconductor device according to Embodiment 2) The method for manufacturing the super-junction semiconductor device 40 according to Embodiment 2 is the same as the method for manufacturing the super-junction semiconductor device 40 according to Embodiment 1, wherein the p-type column region 3 functions as a channel stopper n + The p-type column region 3 can be manufactured by forming it in the lower region of the mold region 22 and narrowing the width of the p-type column region 3 in the longitudinal direction as it approaches the outer edge.

[0090] As described above, according to Embodiment 2, in the longitudinal direction of the p-type column region, the width of the p-type column region narrows as it approaches the outer edge. As a result, the amount of p-type impurities in the second parallel pn structure of the terminal region is less than the amount of p-type impurities in the parallel pn structure of the active region and the first parallel pn structure of the terminal region. Therefore, the same effects as in Embodiment 1 can be obtained.

[0091] (Embodiment 3) Figure 12 is a plan view showing the structure of the superjunction semiconductor device according to Embodiment 3. Figure 13 is a cross-sectional view showing the structure of the superjunction semiconductor device according to Embodiment 3. Figure 13(a) is a cross-sectional view taken along Y-Y' in Figure 12. Figure 13(b) is a cross-sectional view taken along X-X' in Figure 12. Figure 13(c) is a cross-sectional view taken along X1-X1' in Figure 12.

[0092] As shown in Figure 12, in Embodiment 3, in the longitudinal direction of the p-type column region 3, the p-type column region 3 in the terminal region second parallel pn structure 19c functions as a channel stopper n + The p-type column region 3 is separated from the type region 22, and in the longitudinal direction of the p-type column region 3, the width w of the p-type column region 3 narrows as it approaches the outer edge. In other words, it possesses the features of both Embodiment 1 and Embodiment 2.

[0093] As a result, similar to Embodiments 1 and 2, when the voltage is low and a neutral region (the region that is the source potential) remains in the edge termination region 31, the channel stopper (n + This prevents the electric field from concentrating in the area where the p-type region 22) and the p-type column region 3 overlap, and the channel stopper (n + This reduces the electric field near the mold region 22) and prevents a decrease in breakdown voltage in the edge termination region 31.

[0094] (Method for manufacturing a super-junction semiconductor device according to Embodiment 3) The manufacturing method for the super-junction semiconductor device 40 according to Embodiment 3 is the same as the manufacturing method for the super-junction semiconductor device 40 according to Embodiment 1, wherein the p-type column region 3 functions as a channel stopper in the longitudinal direction of the p-type column region 3. + The p-type column region 3 can be manufactured by forming it so as to be separate from the mold region 22, and by narrowing the width of the p-type column region 3 in the longitudinal direction of the p-type column region 3 as it approaches the outer edge.

[0095] As described above, according to Embodiment 3, in the longitudinal direction of the p-type column region, the p-type column region in the second parallel pn structure of the terminal region functions as a channel stopper. +The p-type region is separated from the p-type region, and in the longitudinal direction of the p-type column region, the width of the p-type column region narrows as it approaches the outer edge. As a result, the amount of p-type impurities in the second parallel pn structure of the terminal region is less than the amount of p-type impurities in the parallel pn structure of the active region and the first parallel pn structure of the terminal region. Therefore, the same effects as in Embodiment 1 and Embodiment 2 can be obtained.

[0096] (Embodiment 4) The plan view showing the structure of the superjunction semiconductor device according to Embodiment 4 is the same as that of Figure 12, and therefore is omitted. Figure 14 is a cross-sectional view showing the structure of the superjunction semiconductor device according to Embodiment 4. Figure 14(a) is a cross-sectional view taken along Y-Y' in Figure 12. Figure 14(b) is a cross-sectional view taken along X-X' in Figure 12. Figure 14(c) is a cross-sectional view taken along X1-X1' in Figure 12.

[0097] As shown in Figures 14(a) to 14(c), in Embodiment 4, the p-type column region 3 and the n-type column region 4 are n + This is a so-called semi-SJ structure that has not yet reached the type semiconductor substrate 1. Therefore, the parallel pn structure 19 and n + An n-type drift layer 2 exists between the n-type semiconductor substrates 1. In Embodiment 4, as in Embodiment 3, in the longitudinal direction of the p-type column region 3, the p-type column region 3 in the terminal region second parallel pn structure 19c functions as an n-type drift layer 2. + The p-type column region 3 is separated from the type region 22, and in the longitudinal direction of the p-type column region 3, the width of the p-type column region 3 is narrowed as it approaches the outer edge.

[0098] As a result, similar to Embodiment 3, when the voltage is low and a neutral region (the region that is the source potential) remains in the edge termination region 31, it is possible to prevent the electric field from concentrating in the area where the channel stopper and the p-type column region 3 overlap, thereby mitigating the electric field near the channel stopper and preventing a decrease in breakdown voltage in the edge termination region 31.

[0099] (Method for manufacturing a super-junction semiconductor device according to Embodiment 4) The method for manufacturing the super-junction semiconductor device 40 according to Embodiment 4 is the method for manufacturing the super-junction semiconductor device 40 according to Embodiment 3, wherein the p-type column region 3 and the n-type column region 4 are n + It can be manufactured by forming it so as not to reach the semiconductor substrate 1.

[0100] As explained above, according to Embodiment 4, the p-type column region and the n-type column region are n + The semiconductor substrate 1 has not yet been reached. Even with this SJ structure, the same effects as in Embodiment 3 can be obtained.

[0101] Alternatively, the structure may be similar to that of conventional superjunction semiconductor devices, and the impurity concentration in the p-type column region 3 of the second parallel pn structure 19c of the termination region may be reduced as it approaches the outer edge in the longitudinal direction (x direction) of the p-type column region 3. This reduces the amount of impurities in the p-type column region 3 of the edge termination region 31 on the drain potential side (channel stopper side).

[0102] In this case as well, the same effects as in Embodiments 1 to 4 described above can be obtained. Furthermore, in Embodiments 1 to 4 described above, the impurity concentration in the p-type column region 3 may be made to decrease as it approaches the outer edge.

[0103] (Embodiment 5) Figure 15 is a superjunction semiconductor device according to Embodiment 5, and is a top view showing the longitudinal end of the p-type column region set up for simulation, similar to Figures 3 to 5 and Figures 9 to 11. In Embodiment 5, the parallel pn structure 19 is in the longitudinal direction (x direction) of the n-type column region 4 and the p-type column region 3, n + In region S adjacent to type region 22, the region is n-rich. That is, in region S, the product of the width of n-type column region 4 and the impurity concentration of n-type column region 4 is greater than the product of the width of p-type column region 3 and the impurity concentration of p-type column region 3.

[0104] For example, as shown in Figure 15(a), the impurity concentration in the n-type column region 4 and the impurity concentration in the p-type column region 3 are made the same, and the parallel pn structure 19 is n + In the vicinity of the region S adjacent to the type region 22, the width W2 of the p-type column region 3 may be made narrower than the width W1 of the n-type column region 4. Also, as shown in Figure 15(b), the impurity concentration of the n-type column region 4 and the impurity concentration of the p-type column region 3 may be made the parallel pn structure 19 n + As the p-type column region 3 approaches the region S adjacent to the p-type region 22, the width W2 of the p-type column region 3 may be monotonically decreased. Alternatively, the width W2 of the p-type column region 3 and the width W1 of the n-type column region 4 may be made the same, and the impurity concentration of the n-type column region 4 may be higher than that of the p-type column region 3. Furthermore, the p-type column region 3 near the surface and the high-concentration n-type column region may be... + Because the electric field is particularly concentrated at the point where the type region 22 touches, n + Only the area near the surface of region S that is in contact with type region 22 may be n-rich.

[0105] Furthermore, in Embodiment 5, as shown in Figure 15(c), the p-type column region 3 of the parallel pn structure 19 is arranged in the longitudinal direction of the p-type column region 3, n + It may be provided at a distance L from the type region 22. In this case, the n of the edge termination region 31 + In the vicinity of the type region 22, the n-richness increases as the distance L increases. By increasing this distance L, the longitudinal end of the p-type column region 3 of the parallel pn structure 19 can be made p-rich, just like the active region. In this case, the width and impurity concentration in the longitudinal direction of the p-type column region 3 and the longitudinal direction of the n-type column region 4 can be made the same as the active region without changing them.

[0106] Therefore, as shown in Figure 15(c), the p-type column region 3 of the parallel pn structure 19 is defined in the longitudinal direction of the p-type column region 3, n +If the p-type column region 4 is separated from the n-type column region 22 by a distance L, the impurity concentration of the n-type column region 4 and the impurity concentration of the p-type column region 3 may be made the same, and the width W2 of the p-type column region 3 may be the same as or wider than the width W1 of the n-type column region 4 along the entire longitudinal direction of the p-type column region 3. Alternatively, the width W2 of the p-type column region 3 and the width W1 of the n-type column region 4 may be made the impurity concentration of the n-type column region 4 the same as or lower than the impurity concentration of the p-type column region 3. Furthermore, the p-type column region 3 near the surface and the high-concentration n-type column region may be + Because the electric field is particularly concentrated at the point where the p-type region 22 is in contact, the p-type column region 3 is n only near the surface. + It may be provided at a distance L from the mold region 22.

[0107] Here, Figure 16 is a graph showing the voltage drop at high temperatures for a 1200V class SJ-SiCMOSFET with the structure shown in Figure 15(c). In Figure 16, the vertical axis represents the drain-source current I. DS The graph shows the unit in A. The horizontal axis represents the drain-source voltage V. DS The value shown is in V. Figure 16 shows the value of V in a semi-SJ structured SiCMOSFET with a cell pitch of 5 μm. GS The voltage drop at room temperature (RT) and high temperature (175°C) is shown when the voltage is set to 0V and the parallel pn structure 19 is made n-rich or p-rich.

[0108] Figure 16(a) shows the case of 50% p-richness, Figure 16(b) shows the case of 30% p-richness, Figure 16(c) shows the case of 10% n-richness, and Figure 16(d) shows the case of 50% n-richness. Here, 50% p-richness means that the product of the width of the p-type column region 3 and the impurity concentration of the p-type column region 3 is 50% greater than the product of the width of the n-type column region 4 and the impurity concentration of the n-type column region 4, or 1.5 times. The same applies to 30% p-richness, 10% n-richness, and 50% n-richness.

[0109] As shown in Figure 16(a), when enriched with 50% p, the withstand voltage decreases by 58% at high temperatures (175°C) compared to room temperature (RT). As shown in Figure 16(b), when enriched with 30% p, the withstand voltage decreases by 26% at high temperatures (175°C) compared to room temperature (RT). On the other hand, as shown in Figure 16(c), when enriched with 10% n, and as shown in Figure 16(d), when enriched with 50% n, there is no decrease in withstand voltage even at high temperatures (175°C).

[0110] Therefore, in Embodiment 5, the p-type column region 3 and a high concentration of n + In order to prevent the electric field from concentrating at high temperatures at the point where the n-type column region 22 is in contact, as shown in Figures 15(a) and 15(b), the n-type column region 4 and the p-type column region 3 are arranged in the longitudinal direction. + In region S adjacent to type region 22, the region is n-rich. This reduces the deep electron traps and deep hole traps generated by Al ion implantation, reduces the detrapping of majority carriers at high temperatures, and suppresses the shrinkage of the depletion layer. Therefore, n functions as a channel stopper. + By making the intersection of the p-type column region 22 and the p-type column region 3 n-rich, the pressure drop at high temperatures (175°C) can be suppressed. + The formation of the type region 22 is a separate process, involving the edges of the p-type column region 3 and a high concentration of n + Variations occur in the formation position due to mask alignment of type region 22. In the longitudinal direction of n-type column region 4 and p-type column region 3, n + In the structure in contact with the mold region 22, even if the contact position shifts due to manufacturing variations, it does not affect the suppression of pressure reduction because it is a part that is made n-rich by changing the width of the n-type column region 4 and the p-type column region 3. Furthermore, since it only involves changing the width of the n-type column region 4 and the p-type column region 3, it offers a high degree of design and manufacturing freedom.

[0111] Furthermore, as shown in Figure 15(c), the p-type column region 3 of the parallel pn structure 19 is defined in the longitudinal direction of the p-type column region 3, n + By separating the p-type region 22 from the high-concentration n-type region 3, the p-type column region 3 and the n-type region 22 are separated by a distance L.+ The contact points of the mold region 22 are eliminated, and the channel stopper n at high temperatures + This prevents breakdown near type region 22. When the active region is made p-rich to increase avalanche tolerance, the width of the p-type column region 3 and n-type column region 4 of the active region does not need to be changed all the way to the edges, thus enabling the precise formation of a parallel pn structure.

[0112] Figure 17 shows the Vds and C of a 3300V class full SJ-SiC MOSFET. OSS This graph shows the relationship. In Figure 17, the vertical axis is the output capacitance C. OSS The horizontal axis shows the drain-source voltage Vds, in units of F. Figure 17 shows the Vds and C values ​​when the temperature of the SJ-SiCMOSFET is varied. OSS The relationship is shown in Figure 17(a) for -55°C, Figure 17(b) for 25°C, and Figure 17(c) for 140°C. Figure 17 shows the case where the SJ-SiCMOSFET has operating frequencies of 1 MHz, 100 kHz, 10 kHz, and 1 kHz.

[0113] Furthermore, Figure 17 shows the impurity concentration in the p-type column region 3 as 6 × 10⁻⁶. 16 / cm 3 The impurity concentration in n-type column region 4 is 3 × 10⁻⁶. 16 / cm 3 The calculation assumes a width of 1.5 μm for the p-type column region 3, a width of 3.5 μm for the n-type column region 4, and an activation rate of 70% for the impurities injected into the p-type column region 3. Here, the activation rate is defined as the integral concentration obtained by integrating the true doping concentration over the p-type column region 3 for the electrically activated true doping concentration distribution, and dividing this integral by the injection dose. The true doping concentration can be obtained by the well-known CV (capacitance-applied voltage) measurement.

[0114] As shown in Figure 17, at low temperatures (-55°C) and room temperature (25°C), C becomes higher at high frequencies (1 MHz). OSS Although it is decreasing, at high temperatures (140°C), C is present at both high and low frequencies (1kHz).OSS The values ​​are the same. This is because, with deep energy levels, it is not possible to follow high frequencies, and the capacitance appears small. At low frequencies, it is possible to follow even deep traps (energy levels), so the capacitance appears large. Also, as the temperature increases, the carrier response improves, so the capacitance appears large at both high and low frequencies. Thus, the capacitance increases as the temperature and frequency decrease. An increase in capacitance means that the depletion layer shrinks. From these results, as shown in Figure 15, the n function as a channel stopper. + It is preferable to make the intersection of type region 22 and p-type column region 3 n-rich.

[0115] Figure 18 is a graph showing the relationship between the width of the p-type column region and the depletion voltage of the p-type column region in a 3300V class SJ-SiCMOSFET. In Figure 18, the vertical axis represents the depletion voltage in units of V. The horizontal axis represents the width of the p-type column region 3 in units of μm. Figure 18 shows the cases where the activation rate of the aluminum implanted in the p-type column region 3 is 70%, 90%, and 100%. The case with an activation rate of 100% is when formed by epitaxial growth, while the activation rates of 70% and 90% represent the lower and upper limits when formed by ion implantation. The configuration of the SJ-SiCMOSFET in Figure 18 is the same as the configuration of the SJ-SiCMOSFET in Figure 17.

[0116] As shown in Figure 18, the depletion voltage increases as the width of the p-type column region 3 increases, i.e., as it becomes p-rich, and the depletion voltage increases as the activation rate increases. For this reason, the channel stopper n at high temperatures + p-type column region 3 and n to prevent breakdown in the vicinity of type region 22 + The distance L from type region 22 must be determined considering the activation rate.

[0117] Figure 19 is a graph showing the dependence of the dielectric breakdown field on doping density. In Figure 19, the vertical axis represents the dielectric breakdown field in units of V / cm, and the horizontal axis represents the doping density in units of / cm. 3Figure 19 shows how long it takes for breakdown to occur for Si, as well as 3C-SiC, 4H-SiC, and 6H-SiC. From Figure 19, it can be seen that for 4H-SiC, the impurity concentration (doping density) in p-type column region 3 is 6 × 10⁻⁶. 16 / cm 3 In this case, the dielectric breakdown field is 3 × 10 6 The value is V / cm.

[0118] Figure 20 shows the p-type column region and n-type column region when the Al activation rate is 70% (lower limit when formed by ion implantation). + This graph shows the relationship between the distance to the p-type region and the breakdown voltage. In Figure 20, the vertical axis represents the breakdown voltage in V. The horizontal axis represents the distance between the p-type column region 3 and n + This shows the distance L to the type region 22, in units of μm. Figure 20 shows the results calculated using the same configuration as in Figure 18 for the SJ-SiCMOSFET. In Figure 20, the dielectric breakdown field Emax is 3 × 10⁻⁶. 6 In addition to the case of V / cm, the dielectric breakdown field Emax is calculated for cases where the lateral Emax is 0.8 times the vertical Emax, and also for cases where the dielectric breakdown field Emax × 0.9 and Emax × 0.8. Here, the lateral and vertical directions refer to the directions with respect to the C axis of the silicon carbide semiconductor substrate. In typical MOSFETs or IGBTs, such as planar type with Si or C planes, or trench type with m or a planes, the depth direction is approximately in the C axis direction, and the longitudinal direction of the p-type column region 3 is perpendicular to the C axis. Therefore, the dielectric breakdown field Emax is calculated using the lateral Emax to determine the magnitude of the distance L. Figure 20 also shows the depletion voltage of the p-type column region 3 by a straight line when the width of the p-type column region 3 is increased from 1.5 μm to +30% and +50% to make it p-rich.

[0119] As shown in Figure 20, the impurity concentration in the p-type column region 3 is 6 × 10 16 / cm 3 Even with an Al activation rate of 70% and an Emax × 0.8, the p-type column region 3 and n + Even at a distance L from the type region 22 of 0 μm, the p-type column region 3 becomes depleted, so n +No breakdown occurs in type region 22. Therefore, when the Al activation rate exceeds 70%, the p-type column region 3 and n + The distance L from the mold region 22 is set to be greater than 0 μm.

[0120] Figure 21 shows the p-type column region and n-type column region when the Al activation rate is 90% (the upper limit when formed by ion implantation). + This graph shows the relationship between the distance to the p-type region and the breakdown voltage. In Figure 21, the vertical axis represents the breakdown voltage in V. The horizontal axis represents the distance between the p-type column region 3 and n + This shows the distance L to the type region 22, in units of μm. Figure 21 shows the results calculated using the same configuration as in Figure 20.

[0121] As shown in Figure 21, the impurity concentration in the p-type column region 3 is 6 × 10⁻⁶ 16 / cm 3 When the Al activation rate is 90%, and the dielectric breakdown field is Emax, the width of the p-type column region 3 is +30% and the p-type column region 3 and n + If the distance L from type region 22 is 0.1 μm or less, then n + Breakdown occurs near type region 22. Therefore, p-type column region 3 and n + It is preferable that the distance L from the mold region 22 is greater than 0.1 μm.

[0122] Furthermore, in the case of dielectric breakdown field Emax, the width of the p-type column region 3 is +50% of the width of the p-type column region 3 and n + If the distance L from type region 22 is 0.4 μm or less, then n + Breakdown occurs near type region 22. Furthermore, if the horizontal Emax is smaller than the vertical Emax, i.e., Emax × 0.8, the required distance increases even further.

[0123] Figure 22 shows the p-type column region and n-type column region when Al activation rate is 100%. +This graph shows the relationship between the distance to the p-type region and the breakdown voltage. 100% Al activation rate is, for example, when p-type column region 3 is formed by epitaxial growth. In Figure 22, the vertical axis shows the breakdown voltage in V. The horizontal axis shows the distance between p-type column region 3 and n + This shows the distance L to the type region 22, in units of μm. Figure 22 shows the results calculated using the same configuration as Figure 20.

[0124] As shown in Figure 22, the impurity concentration in the p-type column region 3 is 6 × 10⁻⁶ 16 / cm 3 When the Al activation rate is 100%, and the dielectric breakdown field is Emax, the width of the p-type column region 3 is +30% and the p-type column region 3 and n + If the distance L from type region 22 is 0.4 μm or less, then n + Breakdown occurs near type region 22. Therefore, p-type column region 3 and n + It is preferable that the distance L from the mold region 22 is greater than 0.4 μm.

[0125] Furthermore, in the case of dielectric breakdown field Emax, the width of the p-type column region 3 is +50% of the width of the p-type column region 3 and n + If the distance L from type region 22 is 1.0 μm or less, then n + Breakdown occurs near type region 22. Therefore, p-type column region 3 and n + It is preferable that the distance L from the mold region 22 is greater than 1.0 μm. Furthermore, if the lateral Emax is smaller than the vertical Emax, i.e., Emax × 0.8, the required distance increases further.

[0126] Figure 23 shows a magnified view of one of the four corners of the plan view structure of the superjunction semiconductor device according to Embodiment 5, showing the p-type column region and n + This is a top view showing the configuration of the neighborhood with the type region. + The type region 22 is provided so as to surround the active region 30 and consists of a straight portion and a curved portion at the corner. As shown in the area indicated by the dotted line S1 in Figure 23, in the longitudinal direction of the p-type column region 3, the p-type column region 3 and n + The distance L1 at which type region 22 separates from the other is n+ It is preferable that the linear portion of the type region 22 is uniform. Also, n + p-type column region 3 and n at the corner of type region 22 + The distance L2 at which the mold region 22 separates from the straight section is preferably the same as or longer than the distance L1 in the straight section.

[0127] Furthermore, as shown within the dotted line area indicated by S2 in Figure 23, the longitudinal end of the p-type column region 3 is n + At the corner of the type region 22, n + It is tilted to match the curvature of the type region 22. As a result, even at the corners, the p-type column region 3 and n + The distance between the type region 22 and the other region is uniform.

[0128] (Method for manufacturing a superjunction semiconductor device according to Embodiment 5) The method for manufacturing the super-junction semiconductor device 40 according to Embodiment 5 is the method for manufacturing the super-junction semiconductor device 40 according to Embodiment 1, wherein the width of the p-type column region 3 is narrowed in the longitudinal direction of the p-type column region 3, or the p-type column region 3 is n + It can be manufactured by forming it so as not to reach the mold region 22.

[0129] As described above, according to Embodiment 5, in the longitudinal direction of the n-type column region and the p-type column region, + In the region adjacent to the type region, it is n-rich. This reduces the deep electron traps and deep hole traps generated by Al ion implantation, reduces the detrapping of majority carriers at high temperatures, and suppresses the shrinkage of the depletion layer. Therefore, n functions as a channel stopper. + By making the intersection of the p-type region and the p-type column region n-rich, the pressure drop at high temperatures (175°C) can be suppressed. In addition, the p-type column region of the parallel pn structure is n-rich in the longitudinal direction of the p-type column region. + By separating the p-type region from the high-concentration n-type region by a distance L, the p-type column region and the high-concentration n-type region are separated. + By eliminating the points where the mold regions touch, the channel stopper n at high temperatures +This prevents breakdown in the vicinity of the type domain.

[0130] In the above-described embodiment, the present invention was explained using the example of a MOS gate structure constructed on the first main surface of a silicon carbide substrate made of silicon carbide. However, the present invention is not limited to this, and the surface orientation of the main surface of the substrate can be changed in various ways. Furthermore, in the embodiments of the present invention, the first conductivity type was set to n type and the second conductivity type to p type. However, the present invention also holds true if the first conductivity type is p type and the second conductivity type is n type. Moreover, the present invention is applicable not only to semiconductor devices with a trench structure in which the channel is formed perpendicular to the substrate surface, but also to planar structures in which the channel is formed parallel to the substrate surface. Furthermore, in the embodiments described above, the case in which silicon carbide is used as the wide-bandgap semiconductor was explained as an example. However, similar effects can be obtained when using wide-bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN), or silicon other than wide-bandgap semiconductors. Furthermore, although the present invention has been described in an embodiment in which the trench 18 is parallel to the longitudinal direction of the p-type column region 3 and the n-type column region 4, the same effect can be obtained even if the trench 18 is perpendicular to the longitudinal direction of the p-type column region 3 and the n-type column region 4. [Industrial applicability]

[0131] As described above, the superjunction semiconductor device according to the present invention is useful as a high-voltage semiconductor device used in power supply devices for power conversion devices and various industrial machines. [Explanation of symbols]

[0132] 1, 101 n + Semiconductor substrate 2. 10² n-type drift layer 2a Lower n-type drift layer 2b Upper n-type drift layer 3, 103 p-type column region 3a Lower p-type column region 3b Upper p-type column region 4, 104 n-type column region 6, 106 p-type base region 7, 107 n + Type source area 9, 109 Gate Insulator 10, 110 TT 14, 114 1st p. + Type-based domain 15, 115 2nd p. + Type-based domain 18, 118 Trench 19, 119 parallel pn structure 19a Active region parallel pn structure 19b Termination region first parallel pn structure 19c Termination region second parallel pn structure 20, 120 1st JTE area 21, 121 2nd JTE area 22, 122 n + type area 30, 130 active area 31, 131 Edge Termination Region 32, 132 Depletion layer 33, 133 neutral region 34 Ion Infusion Mask 40, 140 SJ-MOSFET

Claims

1. A superjunction semiconductor device having an active region through which electric current flows, and a terminal structure disposed outside the active region and having a voltage-resistant structure formed thereon, The active region and the terminal structure are, A first semiconductor layer of the first conductivity type, having a lower impurity concentration than the semiconductor substrate, is provided on the front surface of the first conductivity type semiconductor substrate. A parallel pn structure is provided on the surface of the first semiconductor layer, in which a striped first column of a first conductivity type and a striped second column of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface, Equipped with, The terminal structure includes a channel stopper arranged to surround the parallel pn structure in a plan view. The second column of the parallel pn structure is provided in the longitudinal direction of the second column, separated from the channel stopper. At the longitudinal end of the second column of the parallel pn structure, the product of the width of the second column and the impurity concentration of the second column is greater than the product of the width of the first column and the impurity concentration of the first column. The width of the second column is 50% or less of the width of the first column. A super-junction semiconductor device characterized in that the second column and the channel stopper are separated by 0.4 μm or more in the longitudinal direction of the second column.

2. The superjunction semiconductor device according to Claim 1, characterized in that the distance at which the second column of the parallel pn structure is separated from the channel stopper in the longitudinal direction of the second column directly connected to the surface electrode potential is uniform in the straight portion of the channel stopper, and at the corner portion of the channel stopper is the same as or longer than the distance in the straight portion.

3. Each of the longitudinal ends of the second column of the parallel pn structure is inclined in accordance with the curvature of the channel stopper at the corner portion of the channel stopper. A superjunction semiconductor device according to claim 1 or 2.

4. The active region is A second semiconductor layer of the second conductivity type is provided on the surface side of the parallel pn structure, A first semiconductor region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer, A gate insulating film provided on the surface side of the second semiconductor layer and in contact with the second semiconductor layer, A gate electrode is provided on the surface side of the gate insulating film opposite to the surface that contacts the second semiconductor layer, A super-bonding semiconductor device according to any one of claims 1 to 3, characterized by comprising the above.

5. The superjunction semiconductor device according to any one of claims 1 to 4, characterized in that the first column and the second column of the parallel pn structure do not reach the semiconductor substrate.

6. The superjunction semiconductor device according to any one of claims 1 to 5, characterized in that the semiconductor substrate is made of a wide bandgap semiconductor.

7. The superjunction semiconductor device according to any one of claims 1 to 6, characterized in that the channel stopper is of the first conductivity type.

8. The semiconductor substrate is a silicon carbide semiconductor, The first conductivity type is an n-type formed by adding nitrogen to the silicon carbide semiconductor, The superjunction semiconductor device according to any one of claims 1 to 7, characterized in that the second conductivity type is p-type, formed by adding aluminum to the silicon carbide semiconductor.

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