Semiconductor equipment
By strategically inducing avalanche breakdown in the intermediate region without gate trenches, the semiconductor device addresses reliability issues caused by localized heating, ensuring effective current flow and improved device longevity.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2022-11-16
- Publication Date
- 2026-05-29
Smart Images
Figure 0007867421000001 
Figure 0007867421000002 
Figure 0007867421000003
Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to a semiconductor device.
Background Art
[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate having a central region and a terminal region. The central region is a region where the upper surface of the semiconductor substrate is covered by an upper electrode, and the terminal region is located around the central region and is a region where the upper surface of the semiconductor substrate is covered by an insulating film. In this semiconductor device, a superjunction region in which p-type pillar regions and n-type pillar regions are alternately arranged in the lateral direction is provided in a depth range below the body region.
[0003] When the semiconductor device of Patent Document 1 is turned off, a depletion layer extends laterally from the pn junction at the boundary between the p-type pillar region and the n-type pillar region. As a result, substantially the entire n-type pillar region is depleted. In this semiconductor device, breakdown voltage is ensured by the depletion layer that extends from the boundary to the n-type pillar region. Further, in this semiconductor device, since the n-type pillar region is easily depleted, the impurity concentration of the n-type pillar region serving as a current path can be increased, and the on-resistance can be reduced.
[0004] When a high reverse bias voltage is applied to the pn junction (for example, the pn junction at the boundary between the p-type pillar region and the n-type pillar region) inside the semiconductor substrate while the semiconductor device of Patent Document 1 is off, avalanche breakdown occurs and an avalanche current flows. The avalanche current flows to the upper electrode through the body region. When avalanche breakdown occurs in the terminal region, the avalanche current flows to the upper electrode through the end portion of the body region (the portion of the body region near the terminal region) in the central region. That is, the avalanche current concentrates and flows at the end portion of the body region, and a high load is applied to the end portion.
[0005] Patent Document 1 describes how the breakdown voltage in the central region is lower than that of the terminal region by creating an imbalance between the amount of p-type impurities and n-type impurities in the superjunction region within the central region. This allows avalanche breakdown to occur within the central region, reducing the load on the semiconductor device. [Prior art documents] [Patent Documents]
[0006] [Patent Document 1] Japanese Patent Publication No. 2020-161559 [Overview of the project] [Problems that the invention aims to solve]
[0007] In the semiconductor device described in Patent Document 1, avalanche breakdown occurs within the central region. The avalanche current flows to the upper electrode through the p-type pillar region and body region within the central region. At this time, the avalanche current causes the p-type pillar region and body region to heat up. A gate trench is provided in the central region, and the body region is in contact with the gate insulating film, so the heat generated in the body region is transferred to the gate insulating film. Therefore, repeated flow of avalanche current can adversely affect the gate insulating film. As a result, the reliability of the semiconductor device is reduced in the technology described in Patent Document 1. This specification provides a technology to suppress the reduction in reliability of a semiconductor device due to avalanche current. [Means for solving the problem]
[0008] The semiconductor device (10) disclosed herein comprises a semiconductor substrate (12), a gate insulating film (24), and a gate electrode (26). The semiconductor substrate has a central region (14) whose upper surface (12a) is covered by an upper electrode (70), and a terminal region (16) located around the central region and whose upper surface is covered by an insulating film (29). The central region has an element region (14a) in which a plurality of gate trenches (22) are provided on its upper surface, and an intermediate region (14b) located between the element region and the terminal region and in which the gate trenches are not provided on its upper surface. The gate insulating film covers the inner surface of the gate trenches. The gate electrode is disposed within the gate trenches and is insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate comprises an n-type source region (30) located within the element region, in contact with the upper electrode, and in contact with the gate insulating film; a p-type body region (32) distributed across the element region and the intermediate region, in contact with the upper electrode in the element region and the intermediate region, and in contact with the gate insulating film below the source region; and a superjunction region (40) distributed across the element region and the intermediate region in a depth range below the body region, wherein the superjunction region consists of a plurality of p-type pillar regions (42) and a plurality of n-type pillar regions (44) arranged alternately in the lateral direction. The plurality of p-type pillar regions include a plurality of first p-type pillar regions (42a) located within the element region and connected to the body region, and a plurality of second p-type pillar regions (42b) located within the intermediate region and connected to the body region. The absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers (L2) of two adjacent n-type pillar regions via the second p-type pillar region is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers (L1) of two adjacent n-type pillar regions via the first p-type pillar region.
[0009] In the semiconductor device described above, the semiconductor substrate has an intermediate region between the termination region and the element region where a gate trench is provided, which is covered by the upper electrode and does not have a gate trench. The absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers of two adjacent n-type pillar regions via a p-type pillar region (second p-type pillar region) within the intermediate region is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers of two adjacent n-type pillar regions via a p-type pillar region (first p-type pillar region) within the element region. In other words, the breakdown voltage of the intermediate region is lower than that of the element region. For this reason, in the semiconductor device described above, avalanche breakdown occurs in the intermediate region before that of the element region. The intermediate region has a body region, which is in contact with the upper electrode. Therefore, when avalanche breakdown occurs in the intermediate region, an avalanche current flows to the upper electrode via the second p-type pillar region and the body region within the intermediate region. Since gate trenches are provided within the element region but not in the intermediate region, even if the body region in the intermediate region heats up due to the flow of avalanche current, it has almost no effect on the gate insulating film provided within the element region. In this way, the above semiconductor device can suppress the deterioration of the reliability of the semiconductor device due to avalanche current by selectively inducing avalanche breakdown in the region where gate trenches do not exist. [Brief explanation of the drawing]
[0010] [Figure 1] Plan view of the semiconductor device of Example 1. [Figure 2] A partially enlarged plan view of the semiconductor device of Example 1. [Figure 3] Cross-sectional view along line III-III in Figure 2. [Figure 4] A partially enlarged plan view of the semiconductor device of Example 2. [Figure 5] A partially enlarged plan view of the semiconductor device of Example 3. [Modes for carrying out the invention]
[0011] In one example semiconductor device disclosed herein, the superjunction region may be distributed across the element region, the intermediate region, and the termination region. A plurality of the p-type pillar regions may have a third p-type pillar region located within the termination region and in contact with the insulating film. The absolute difference between the amount of p-type impurity and the amount of n-type impurity measured between the centers of two adjacent n-type pillar regions via the second p-type pillar region may be greater than the absolute difference between the amount of p-type impurity and the amount of n-type impurity measured between the centers of two adjacent n-type pillar regions via the third p-type pillar region.
[0012] In this configuration, the breakdown voltage in the intermediate region is lower than that in the terminal region. Therefore, avalanche breakdown occurs in the intermediate region before the terminal region. Consequently, it is possible to suppress the localized concentration of avalanche current.
[0013] In one example semiconductor device disclosed herein, the width of the second p-type pillar region may be wider than the width of the first p-type pillar region.
[0014] In this configuration, the difference in the balance between the amount of p-type impurities and n-type impurities in the intermediate region and the element region can be easily adjusted.
[0015] An example semiconductor device disclosed herein may further include a plurality of p-type connection regions that connect two adjacent second p-type pillar regions and are connected to the body region.
[0016] In this configuration, not only the second p-type pillar region but also the connection region can function as a path for the avalanche current. In other words, a wider current path for the avalanche current can be secured, which reduces the resistance of the avalanche current path and improves the avalanche withstand capability.
[0017] In a semiconductor device according to an example disclosed in this specification, the two connection regions arranged via the second p-type pillar region may be arranged at different positions in a direction orthogonal to the arrangement direction of the second p-type pillar region and the n-type pillar region.
[0018] For example, when two connection regions arranged via a second p-type pillar region are arranged at the same position in a direction orthogonal to the arrangement direction of the second p-type pillar region and the n-type pillar region, the p-type impurity concentration at the connection portion between the connection region and the second p-type pillar region may become excessively large, and the breakdown voltage of the semiconductor device may decrease. In contrast, in the above configuration, it is possible to suppress the p-type impurity concentration from becoming excessively large locally (that is, at the above connection portion), and to suppress a decrease in the breakdown voltage of the semiconductor device.
[0019] In a semiconductor device according to an example disclosed in this specification, within the central region, when the semiconductor substrate is viewed from above, the p-type pillar region and the n-type pillar region may extend long along a first direction and be alternately arranged along a second direction orthogonal to the first direction. In this case, the dimension in the second direction is the width of the p-type pillar region and the n-type pillar region.
[0020] In a semiconductor device according to an example disclosed in this specification, within the terminal region, they may be alternately arranged along a direction from the central region toward the outer peripheral edge of the semiconductor substrate. In this case, within the terminal region, the p-type pillar region and the n-type pillar region may extend annularly so as to surround the central region multiple times. In this case, the dimension in the direction from the central region toward the outer peripheral edge of the semiconductor substrate is the width of the p-type pillar region and the n-type pillar region.
[0021] (Example) FIG. 1 shows a semiconductor device 10 of an embodiment. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and has a semiconductor substrate 12, electrodes, insulating films, and the like. The semiconductor substrate 12 is made of SiC (silicon carbide). However, the material constituting the semiconductor substrate 12 is not particularly limited, and other semiconductor materials such as Si (silicon) and GaN (gallium nitride) may be used. As shown in FIG. 1, the semiconductor substrate 12 has a central region 14 and a termination region 16. The central region 14 is disposed on the central side of the semiconductor substrate 12, and is a region where the upper surface 12a of the semiconductor substrate 12 (see FIGS. 2, 3, etc.) is covered by the upper electrode 70. The termination region 16 is disposed around the central region 14, and is a region where the upper surface 12a of the semiconductor substrate 12 is covered by the insulating film 29. Further, a gate pad 18 for inputting a gate signal is provided on the upper surface 12a of the semiconductor substrate 12 in the central region 14. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction.
[0022] FIG. 2 is an enlarged view of the region A shown by a broken line in FIG. 1 as viewed from above. As shown in FIG. 2, the central region 14 has an element region 14a and an intermediate region 14b. The element region 14a is a region located on the central side of the central region 14, and is a region where a plurality of gate trenches 22 are formed on the upper surface 12a of the semiconductor substrate 12. The intermediate region 14b is a region located between the element region 14a and the termination region 16, and is a region where no gate trench 22 is provided on the upper surface 12a of the semiconductor substrate 12.
[0023] Each gate trench 22 extends long along the x-direction. Each gate trench 22 extends parallel to one another. Each gate trench 22 is arranged with spacing in the y-direction. Note that in Figure 2, the configuration on the upper surface 12a of the semiconductor substrate 12 (electrodes, insulating film, etc.) is omitted. As shown in the figure, a gate insulating film 24 and a gate electrode 26 are arranged inside each gate trench 22. The gate insulating film 24 covers the inner surface of each gate trench 22. The gate electrode 26 is located inside each gate trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. Each gate electrode 26 is connected to the gate pad 18 shown in Figure 1 at a location not shown.
[0024] The upper surface of each gate electrode 26 is covered by an interlayer insulating film 28. An upper electrode 70 is positioned on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 in the central region 14 (i.e., the element region 14a and the intermediate region 14b) in the portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. The upper surface 12a of the semiconductor substrate 12 in the terminal region 16 is covered by an insulating film 29. A lower electrode 72 is positioned on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with substantially the entire area of the lower surface 12b of the semiconductor substrate 12.
[0025] As shown in the figure, the semiconductor substrate 12 is provided with multiple source regions 30, body regions 32, superjunction regions 40, bottom drift regions 34, and drain regions 35 inside.
[0026] Each source region 30 is n-type and is located within the element region 14a. Each source region 30 is positioned to be exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24 on the side surface of the gate trench 22.
[0027] The body region 32 is p-type and is distributed across the element region 14a and the intermediate region 14b. The body region 32 has a contact region 32a and a main body region 32b. The p-type impurity concentration in the contact region 32a is higher than that in the main body region 32b.
[0028] Within the element region 14a, the contact region 32a is located in the area between the two source regions 30 and is in ohmic contact with the upper electrode 70. The main body region 32b is located below each source region 30 and the contact region 32a. The main body region 32b is in contact with each source region 30 and the contact region 32a from below. The main body region 32b is in contact with the gate insulating film 24 on the side surface of the gate trench 22 below the source region 30.
[0029] Within the intermediate region 14b, the source region 30 is not provided, and the main body region 32b extends to a position where it is exposed on the upper surface 12a of the semiconductor substrate 12. The main body region 32b is in contact with the upper electrode 70. That is, the main body region 32b is positioned around the contact region 32a.
[0030] The superjunction region 40 is a region distributed across the element region 14a, the intermediate region 14b, and the termination region 16 in a depth range below the body region 32. The superjunction region 40 is a region in which a plurality of p-type pillar regions 42 and a plurality of n-type pillar regions 44 are alternately and repeatedly arranged along the lateral direction (i.e., the direction parallel to the upper surface 12a of the semiconductor substrate 12 (y-direction in the cross-section of the figure)). The p-type pillar region 42 has a plurality of first p-type pillar regions 42a, a plurality of second p-type pillar regions 42b, and a plurality of third p-type pillar regions 42c. The first p-type pillar region 42a is located within the element region 14a. The second p-type pillar region 42b is located within the intermediate region 14b. The third p-type pillar region 42c is located within the termination region 16.
[0031] Each first p-type pillar region 42a is connected to the main body region 32b and extends downward from the main body region 32b. That is, each first p-type pillar region 42a is connected to the upper electrode 70 via the main body region 32b and the contact region 32a. Therefore, the potential of each first p-type pillar region 42a is approximately equal to the potential of the upper electrode 70. The first p-type pillar regions 42a are located in each of the areas sandwiched between the two gate trenches 22. Each first p-type pillar region 42a extends in a direction parallel to the gate trenches 22 (x-direction). The first p-type pillar regions 42a are spaced apart in the y-direction. Each first p-type pillar region 42a is located below the contact region 32a and is not in contact with the gate insulating film 24. The p-type impurity concentration of each first p-type pillar region 42a is lower than the p-type impurity concentration of each contact region 32a. Within the element region 14a, each n-type pillar region 44 is located below the gate trench 22. Each n-type pillar region 44 is in contact with the gate insulating film 24 below the main body region 32b. Each n-type pillar region 44 extends in a direction parallel to the gate trench 22 (x-direction). The n-type pillar regions 44 are spaced apart in the y-direction. Each n-type pillar region 44 is separated from the source region 30 by the body region 32. The n-type impurity concentration in each n-type pillar region 44 is lower than the n-type impurity concentration in each source region 30.
[0032] Each second p-type pillar region 42b is connected to the main body region 32b and extends downward from the main body region 32b. That is, each second p-type pillar region 42b is connected to the upper electrode 70 via the main body region 32b and the contact region 32a. Therefore, the potential of each second p-type pillar region 42b is approximately equal to the potential of the upper electrode 70. Each second p-type pillar region 42b extends in a circular fashion around the element region 14a. The second p-type pillar regions 42b are arranged at intervals along the direction from the central region 14 to the terminal region 16. The p-type impurity concentration of each second p-type pillar region 42b is approximately equal to the p-type impurity concentration of each first p-type pillar region 42a. Within the intermediate region 14b, each n-type pillar region 44 is connected to the main body region 32b and extends downward from the main body region 32b. Each n-type pillar region 44 extends around the element region 14a. The n-type pillar regions 44 are spaced apart along the direction from the central region 14 to the terminal region 16. That is, in the intermediate region 14b, the second p-type pillar region 42b and the n-type pillar region 44 are arranged alternately along the direction from the central region 14 to the terminal region 16.
[0033] Each third p-type pillar region 42c is exposed to the upper surface 12a of the semiconductor substrate 12 and is in contact with the insulating film 29. Each third p-type pillar region 42c extends downward from the upper surface 12a of the semiconductor substrate 12. That is, each third p-type pillar region 42c is insulated from the upper electrode 70. For this reason, each third p-type pillar region 42c is electrically floating. Each third p-type pillar region 42c extends around the perimeter of the intermediate region 14b. The third p-type pillar regions 42c are arranged with spacing along the direction from the central region 14 toward the terminal region 16. The p-type impurity concentration of each third p-type pillar region 42c is approximately equal to the p-type impurity concentration of each first p-type pillar region 42a. Within the terminal region 16, each n-type pillar region 44 is exposed to the upper surface 12a of the semiconductor substrate 12 and is in contact with the insulating film 29. Each n-type pillar region 44 extends downward from the upper surface 12a of the semiconductor substrate 12. Each n-type pillar region 44 extends in a circular fashion around the intermediate region 14b. The n-type pillar regions 44 are arranged at intervals along the direction from the central region 14 toward the terminal region 16. That is, in the terminal region 16, the third p-type pillar region 42c and the n-type pillar region 44 are arranged alternately along the direction from the central region 14 toward the terminal region 16.
[0034] In the cross-section shown in Figure 3, the distances between the centers of each p-type pillar region 42 (for example, the distance between the centers of two adjacent first p-type pillar regions 42a, the distance between the centers of adjacent first p-type pillar region 42a and second p-type pillar region 42b, etc.) are approximately equal. Also, the width (length in the shorter direction) w2 of the second p-type pillar region 42b is greater than the width w1 of the first p-type pillar region 42a and the width w3 of the third p-type pillar region 42c. As described above, the p-type impurity concentrations in the first p-type pillar region 42a, the second p-type pillar region 42b, and the third p-type pillar region 42c are approximately equal to each other. However, since the width w2 of the second p-type pillar region 42b is wider than the width w1 of the first p-type pillar region 42a and the width w3 of the third p-type pillar region 42c, the amount of p-type impurities contained in the second p-type pillar region 42b is greater than the amount of p-type impurities contained in the first p-type pillar region 42a and the amount of p-type impurities contained in the third p-type pillar region 42c.
[0035] In the superjunction region 40, the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured at the distance L2 between the centers of two adjacent n-type pillar regions 44 connected via the second p-type pillar region 42b is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured at the distance L1 between the centers of two adjacent n-type pillar regions 44 connected via the first p-type pillar region 42a. Furthermore, the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured at the distance L2 is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured at the distance L3 between the centers of two adjacent n-type pillar regions 44 connected via the third p-type pillar region 42c. In other words, the balance between the amount of p-type impurities and the amount of n-type impurities in the intermediate region 14b is worse than the balance between the amount of p-type impurities and the amount of n-type impurities in the element region 14a and the terminal region 16. Specifically, when measured at the distances L1 and L3, the amounts of p-type impurities and n-type impurities are approximately equal. On the other hand, when measured at the center L2, the amount of p-type impurities contained in the second p-type pillar region 42b is relatively large, so the amount of p-type impurities is greater than the amount of n-type impurities.
[0036] The bottom drift region 34 is n-type and is distributed below the superjunction region 40, spanning the element region 14a, the intermediate region 14b, and the termination region 16. The bottom drift region 34 is in contact with each p-type pillar region 42 and each n-type pillar region 44 from below.
[0037] The drain region 35 is n-type and is located below the bottom drift region 34. The drain region 35 is distributed across the device region 14a, the intermediate region 14b, and the termination region 16. The n-type impurity concentration in the drain region 35 is higher than that in the bottom drift region 34. The drain region 35 is exposed on the bottom surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72 on the bottom surface 12b of the semiconductor substrate 12.
[0038] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 72 than to the upper electrode 70. When a voltage above the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in contact with the gate insulating film 24, and the semiconductor device 10 is turned on. When the voltage applied to the gate electrode 26 is reduced to below the gate threshold, the channel disappears, and the semiconductor device 10 is turned off.
[0039] When the semiconductor device 10 is turned off, the potential of the lower electrode 72 is much higher than the potential of the upper electrode 70. In this state, the n-type pillar region 44 and the bottom drift region 34 have a potential close to that of the lower electrode 72. Also, as described above, the first p-type pillar region 42a and the second p-type pillar region 42b have a potential approximately equal to that of the upper electrode 70. Therefore, in the central region 14, a high reverse voltage is applied to the pn junction at the interface between the body region 32, the first p-type pillar region 42a, and the second p-type pillar region 42b and each n-type pillar region 44. Consequently, a depletion layer spreads from the body region 32, the first p-type pillar region 42a, and the second p-type pillar region 42b into each n-type pillar region 44. This depletion layer maintains the voltage applied between the lower electrode 72 and the upper electrode 70. Furthermore, this depletion layer spreads from the central region 14 toward the terminal region 16. When the depletion layer extending from the body region 32 and the second p-type pillar region 42b reaches the innermost (i.e., closest to the central region 14) third p-type pillar region 42c, the depletion layer extends further outward from the third p-type pillar region 42c. In this way, in the terminal region 16, the depletion layer extends outward through each third p-type pillar region 42c. This ensures the breakdown voltage of the terminal region 16. As described above, in the superjunction region 40, the depletion layer spreads not only from the body region 32 but also from the first p-type pillar region 42a and the second p-type pillar region 42b to each n-type pillar region 44, making each n-type pillar region 44 easily depleted. Therefore, in the semiconductor device 10 having the superjunction region 40, the n-type impurity concentration in the current path (i.e., the n-type pillar region 44) can be increased. As a result, the on-resistance of the semiconductor device 10 can be reduced.
[0040] When the semiconductor device 10 is turned off, the depletion layer extending from each p-type region 32, 42 depletes almost the entire area of each n-type pillar region 44 and the bottom drift region 34. When a high voltage is applied to the lower electrode 72 while the semiconductor device 10 is turned off, avalanche breakdown occurs within the semiconductor substrate 12, and an avalanche current flows from the bottom drift region 34 and each n-type pillar region 44 to the upper electrode 70 via each p-type pillar region 42 and the body region 32 in the central region 14. When an avalanche current flows, the region through which the avalanche current flows generates heat. In this embodiment, in the superjunction region 40, the impurity concentrations of each region are set such that the balance between the amount of p-type impurities and n-type impurities in the intermediate region 14b is worse than the balance between the amount of p-type impurities and n-type impurities in the element region 14a and the termination region 16. That is, the breakdown voltage of the intermediate region 14b is lower than the breakdown voltage of either the element region 14a or the termination region 16. Therefore, in the semiconductor device 10 of this embodiment, avalanche breakdown occurs in the intermediate region 14b before the element region 14a and the termination region 16.
[0041] As described above, a body region 32 is provided in the intermediate region 14b, and this body region 32 is in contact with the upper electrode 70. Therefore, when avalanche breakdown occurs in the intermediate region 14b, the avalanche current flows to the upper electrode 70 via the second p-type pillar region 42b and the body region 32 within the intermediate region 14b. Since there is no gate trench 22 in the intermediate region 14b, even if the body region 32 within the intermediate region 14b generates heat due to the flow of avalanche current, it has almost no effect on the gate insulating film 24 provided in the element region 14a. In this way, in the semiconductor device 10 of this embodiment, by selectively inducing avalanche breakdown in a region where there is no gate trench 22 (i.e., the intermediate region 14b), the deterioration of the reliability of the semiconductor device 10 due to avalanche current can be suppressed.
[0042] Furthermore, as described above, in this embodiment, avalanche breakdown occurs in the intermediate region 14b before the terminal region 16. If avalanche breakdown were to occur in the terminal region 16, the avalanche current would flow to the upper electrode 70 through the end of the body region 32 in the central region 14 (i.e., the portion of the body region 32 in the intermediate region 14b that is near the terminal region 16). In other words, the avalanche current would concentrate at the end of the body region 32, and a high load would be applied to that end. However, in this embodiment, since avalanche breakdown occurs in the intermediate region 14b before the terminal region 16, it is possible to suppress the localized concentration of the avalanche current.
[0043] (Example 2) In the semiconductor device of Embodiment 2, compared to the configuration of Embodiment 1, an additional connection region 60 is provided inside the semiconductor substrate 12. As shown in Figure 4, the connection region 60 connects two adjacent second p-type pillar regions 42b. Although not shown, each connection region 60 extends downward from the main body region 32b. Each connection region 60 extends from the main body region 32b to approximately the same depth range as each second p-type pillar region 42b. As shown in Figure 4, in Embodiment 2, when the semiconductor substrate 12 is viewed from above, each connection region 60 is arranged such that a grid shape is formed by each second p-type pillar region 42b and each connection region 60.
[0044] In the semiconductor device of Example 2, not only the second p-type pillar region 42b but also the connection region 60 can function as a path for the avalanche current. That is, in the semiconductor device of Example 2, a wide current path for the avalanche current can be secured, so the resistance of the avalanche current path is reduced and the avalanche withstand capability is improved.
[0045] (Example 3) In the semiconductor device of Example 3, the configuration of the connection region 60 differs from that of Example 2. In Example 3, as shown in Figure 5, the two connection regions 60 arranged via the second p-type pillar region 42b are positioned at different locations in a direction perpendicular to the arrangement direction of the second p-type pillar region 42b and the n-type pillar region 44. In other words, each connection region 60 is arranged such that the connection portion between the second p-type pillar region 42b and the connection region 60 forms a T-shape. Other aspects are the same as in Example 2.
[0046] When two connection regions 60 arranged via a second p-type pillar region 42b are positioned at the same location in a direction perpendicular to the arrangement direction of the second p-type pillar region 42b and the n-type pillar region 44 (i.e., the configuration of Embodiment 2), the concentration of p-type impurities at the connection portion between the connection region 60 and the second p-type pillar region 42b may become excessively high during the semiconductor device manufacturing process, potentially reducing the breakdown voltage of the semiconductor device. In contrast, the configuration of Embodiment 3 suppresses the localized excessive p-type impurity concentration (i.e., at the connection portion) and prevents a decrease in the breakdown voltage of the semiconductor device.
[0047] In each of the embodiments described above, the width w2 of the second p-type pillar region 42b does not have to be wider than the width w1 of the first p-type pillar region 42a and the width w3 of the third p-type pillar region 42c. For example, the width w2 may be approximately equal to the widths w1 and w3. Also, in each of the embodiments described above, when measured at the distance L2 between centers, the amount of p-type impurities was greater than the amount of n-type impurities, but it is also possible to have a configuration where the amount of n-type impurities is greater than the amount of p-type impurities. That is, the absolute value of the difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers of two adjacent n-type pillar regions 44 connected by the p-type pillar region 42 should be largest in the intermediate region 14b.
[0048] Furthermore, in the above-described embodiment, the second p-type pillar region 42b and the third p-type pillar region 42c were formed in an annular shape. However, the shape of the second p-type pillar region 42b and the third p-type pillar region 42c is not limited to this, and for example, they may extend in a straight line, similar to the first p-type pillar region 42a.
[0049] Furthermore, in Embodiment 2, when viewed along the direction from the central region 14 to the terminal region 16, the width of the connection region 60 may be narrower at both ends (i.e., the parts adjacent to the element region 14a and the terminal region 16) than at the central part of the intermediate region 14b. In this configuration, the breakdown voltage of the central part of the intermediate region 14b is lower than the breakdown voltage of the ends of the intermediate region 14b. That is, the breakdown voltage is lowest at the central part of the intermediate region 14b. Therefore, avalanche breakdown can be more reliably induced in the intermediate region 14b.
[0050] The components disclosed herein are listed below. (Composition 1) A semiconductor device, It comprises a semiconductor substrate, a gate insulating film, and a gate electrode. The semiconductor substrate has a central region in which the upper surface of the semiconductor substrate is covered by an upper electrode, and an end region located around the central region in which the upper surface is covered by an insulating film. The central region comprises an element region having a plurality of gate trenches on its upper surface, and an intermediate region located between the element region and the terminal region, where the gate trenches are not provided on the upper surface. The gate insulating film covers the inner surface of the gate trench. The gate electrode is disposed within the gate trench and is insulated from the semiconductor substrate by the gate insulating film. The aforementioned semiconductor substrate An n-type source region is located within the element region, is in contact with the upper electrode, and is in contact with the gate insulating film, A p-type body region is distributed across the element region and the intermediate region, is in contact with the upper electrode in the element region and the intermediate region, and is in contact with the gate insulating film on the lower side of the source region, A superjunction region distributed across the element region and the intermediate region in a depth range below the body region, wherein a plurality of p-type pillar regions and a plurality of n-type pillar regions are alternately arranged in the lateral direction. It is equipped with, The plurality of p-type pillar regions include a plurality of first p-type pillar regions arranged within the element region and connected to the body region, and a plurality of second p-type pillar regions arranged within the intermediate region and connected to the body region. The absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers of two adjacent n-type pillar regions via the second p-type pillar region is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers of two adjacent n-type pillar regions via the first p-type pillar region. Semiconductor equipment. (Configuration 2) The superjunction region is distributed across the element region, the intermediate region, and the termination region. Each of the p-type pillar regions has a third p-type pillar region that is located within the terminal region and is in contact with the insulating film. The semiconductor device according to configuration 1, wherein the absolute value of the difference between the amount of p-type impurity and the amount of n-type impurity measured between the centers of two adjacent n-type pillar regions via the second p-type pillar region is greater than the absolute value of the difference between the amount of p-type impurity and the amount of n-type impurity measured between the centers of two adjacent n-type pillar regions via the third p-type pillar region. (Composition 3) The semiconductor device according to configuration 1 or 2, wherein the width of the second p-type pillar region is wider than the width of the first p-type pillar region. (Composition 4) A semiconductor device according to any one of configurations 1 to 3, further comprising a plurality of p-type connection regions that connect two adjacent second p-type pillar regions and are connected to the body region. (Composition 5) The semiconductor device according to configuration 4, wherein the two connection regions arranged via the second p-type pillar region are positioned at different locations in a direction orthogonal to the arrangement direction of the second p-type pillar region and the n-type pillar region.
[0051] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]
[0052] 10: Semiconductor device, 12: Semiconductor substrate, 14: Central region, 14a: Element region, 14b: Intermediate region, 16: Termination region, 22: Gate trench, 24: Gate insulating film, 26: Gate electrode, 29: Insulating film, 30: Source region, 32: Body region, 40: Superjunction region, 42a: 1st p-type pillar region, 42b: 2nd p-type pillar region, 42c: 3rd p-type pillar region, 44: n-type pillar region, 60: Connection region, 70: Upper electrode, 72: Lower electrode, 80: Insulating film
Claims
1. Semiconductor device (10), It comprises a semiconductor substrate (12), a gate insulating film (24), and a gate electrode (26). The semiconductor substrate has a central region (14) in which the upper surface (12a) of the semiconductor substrate is covered by an upper electrode (70), and an end region (16) located around the central region, in which the upper surface is covered by an insulating film (29). The central region comprises an element region (14a) having a plurality of gate trenches (22) on its upper surface, and an intermediate region (14b) located between the element region and the terminal region, where the gate trenches are not provided on the upper surface. The gate insulating film covers the inner surface of the gate trench. The gate electrode is disposed within the gate trench and is insulated from the semiconductor substrate by the gate insulating film. The aforementioned semiconductor substrate An n-type source region (30) is located within the element region, is in contact with the upper electrode, and is in contact with the gate insulating film, A p-type body region (32) is distributed across the element region and the intermediate region, is in contact with the upper electrode in the element region and the intermediate region, and is in contact with the gate insulating film on the lower side of the source region, A superjunction region (40) distributed across the element region, the intermediate region and the terminal region in a depth range below the body region, wherein a plurality of p-type pillar regions (42) and a plurality of n-type pillar regions (44) are arranged alternately in the lateral direction. It is equipped with, The plurality of p-type pillar regions include a plurality of first p-type pillar regions (42a) arranged within the element region and connected to the body region, a plurality of second p-type pillar regions (42b) arranged within the intermediate region and connected to the body region, and a third p-type pillar region (42c) arranged within the terminal region and in contact with the insulating film. The absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers (L2) of two adjacent n-type pillar regions via the second p-type pillar region is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers (L1) of two adjacent n-type pillar regions via the first p-type pillar region. The absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers of two adjacent n-type pillar regions via the second p-type pillar region is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers of two adjacent n-type pillar regions via the third p-type pillar region (L3). Semiconductor equipment.
2. The semiconductor device according to claim 1, wherein the width (w2) of the second p-type pillar region is wider than the width (w1) of the first p-type pillar region.
3. The semiconductor device according to claim 1, further comprising a plurality of p-type connection regions (60) that connect two adjacent second p-type pillar regions and are connected to the body region.
4. The semiconductor device according to claim 3, wherein the two connection regions arranged via the second p-type pillar region are each positioned at different locations in a direction perpendicular to the arrangement direction of the second p-type pillar region and the n-type pillar region.
5. Semiconductor device (10), It comprises a semiconductor substrate (12), a gate insulating film (24), and a gate electrode (26). The semiconductor substrate has a central region (14) in which the upper surface (12a) of the semiconductor substrate is covered by an upper electrode (70), and an end region (16) located around the central region, in which the upper surface is covered by an insulating film (29). The central region comprises an element region (14a) having a plurality of gate trenches (22) on its upper surface, and an intermediate region (14b) located between the element region and the terminal region, where the gate trenches are not provided on the upper surface. The gate insulating film covers the inner surface of the gate trench. The gate electrode is disposed within the gate trench and is insulated from the semiconductor substrate by the gate insulating film. The aforementioned semiconductor substrate An n-type source region (30) is located within the element region, is in contact with the upper electrode, and is in contact with the gate insulating film, A p-type body region (32) is distributed across the element region and the intermediate region, is in contact with the upper electrode in the element region and the intermediate region, and is in contact with the gate insulating film on the lower side of the source region, A superjunction region (40) distributed across the element region and the intermediate region in a depth range below the body region, wherein a plurality of p-type pillar regions (42) and a plurality of n-type pillar regions (44) are arranged alternately in the lateral direction. It is equipped with, The plurality of p-type pillar regions have a plurality of first p-type pillar regions (42a) arranged within the element region and connected to the body region, and a plurality of second p-type pillar regions (42b) arranged within the intermediate region and connected to the body region. The semiconductor substrate further comprises a plurality of p-type connection regions (60) that connect two adjacent second p-type pillar regions and are connected to the body region, The absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers (L2) of two adjacent n-type pillar regions via the second p-type pillar region is greater than the absolute difference between the amount of p-type impurities and the amount of n-type impurities measured between the centers (L1) of two adjacent n-type pillar regions via the first p-type pillar region. Semiconductor equipment.