Semiconductor device manufacturing methods

Abstract

The purpose of the present disclosure is to improve productivity and suppress cracking of wafers in manufacturing a semiconductor device in which wafers are re-used. A semiconductor device manufacturing method according to the present disclosure comprises: (a) a step for obtaining, from a plurality of SiC wafers (13, 17) by dividing the SiC wafers (13, 17) in the thickness direction, at least each one of divided wafers (20, 23) not including device structures (12, 16); (b) a step for obtaining a bonded wafer (24) by bonding the divided wafers (20, 23) obtained from the different SiC wafers (13, 17); and (c) a step for forming a device structure (26) on the surface of the bonded wafer (24).

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a bonded wafer.

Background Art

[0002] Conventionally, in order to reduce the cost of semiconductor devices, techniques for effectively using expensive single crystal wafers have been proposed. For example, Patent Document 1 proposes a method of slicing a wafer during a thinning process of a device process and reusing the divided wafer on which no device is formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method disclosed in Patent Document 1, in order to reduce cracking of the reused divided wafer, an epitaxial film serving as a buffer layer unrelated to device operation is thickly formed on the divided wafer, and the divided wafer needs to be made to have the same thickness as the original wafer. The formation of a thick epitaxial film is disadvantageous from the viewpoint of productivity. On the other hand, when the epitaxial film is thinly formed, there is a problem that the risk of cracking when the divided wafer is reused increases.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to improve productivity and suppress cracking of a wafer in the manufacture of a semiconductor device that reuses a wafer.

Means for Solving the Problems

[0006] The method for manufacturing a semiconductor device according to the present disclosure comprises: (a) obtaining at least one first divided wafer that does not contain a device structure from each of a plurality of first wafers by dividing each of the first wafers in the thickness direction; (b) obtaining a first bonded wafer, which is a bonded wafer, by joining a plurality of first divided wafers obtained from different first wafers; and (c) forming a device structure on the surface of the first bonded wafer. [Effects of the Invention]

[0007] According to the semiconductor device manufacturing method of this disclosure, a device structure is formed on a bonded wafer obtained by joining together divided wafers. Therefore, it is possible to form a bonded wafer with sufficient thickness to account for cracking at a lower cost than forming an epitaxial film on divided wafers, and to reuse the wafer. The objectives, features, embodiments, and advantages of this disclosure will become clearer from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows the basic process for manufacturing a semiconductor device according to Embodiment 1. [Figure 2] This is a flowchart showing the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 3] This figure shows a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 500 μm. [Figure 4] This figure shows a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 500 μm. [Figure 5] This figure shows a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 350 μm. [Figure 6] This figure shows a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 350 μm. [Figure 7] This figure shows the depth of the bonding surface in a bonded wafer consisting of two split wafers. [Figure 8]It is a diagram showing the depth of the bonding surface in a bonded wafer composed of three divided wafers. [Figure 9] It is a diagram showing the pattern of the wafer division timing in the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 10] It is a diagram showing the basic process when dividing a SiC wafer before forming an epitaxial film in the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 11] It is a diagram showing the basic process of the method for manufacturing a semiconductor device according to Embodiment 2. [Figure 12] It is a diagram showing the basic process of the method for manufacturing a semiconductor device according to a modified example of Embodiment 2. [Figure 13] It is a diagram showing the basic process of the method for manufacturing a semiconductor device according to Embodiment 3. [Figure 14] It is a diagram showing the basic process of the method for manufacturing a semiconductor device according to a modified example of Embodiment 3.

BEST MODE FOR CARRYING OUT THE INVENTION

[0009] <A. Embodiment 1> <A-1. Basic Process> FIG. 1 is a schematic diagram showing the basic process of the method for manufacturing a semiconductor device in the present embodiment. FIG. 2 is a flowchart of the method for manufacturing a semiconductor device in the present embodiment. Hereinafter, the method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS. 1 and 2.

[0010] First, in step S101, an epitaxial film 11 is formed on a single-crystal SiC wafer 10, and a surface structure of a device (hereinafter referred to as a device structure) 12 is formed on the epitaxial film 11. The formation of the device structure 12 includes ion implantation and the formation of a surface electrode. The device structure 12 is, for example, a SiC power device structure. When a GaN wafer or a gallium oxide wafer is used instead of the SiC wafer, the device structure 12 is, for example, a GaN high-frequency device structure, a GaN power device structure, or a gallium oxide power device structure. A GaN high-frequency device structure, a GaN power device structure, or a gallium oxide power device structure may be formed on the SiC wafer. The SiC wafer 10 on which the epitaxial film 11 and the device structure 12 are formed is referred to as a SiC wafer 13.

[0011] In step S101, a SiC wafer 17 similar to the SiC wafer 13 is further formed. That is, an epitaxial film 15 is formed on a single-crystal SiC wafer 14, and a device structure 16 is formed on the epitaxial film 15. The SiC wafer 14 on which the epitaxial film 15 and the device structure 16 are formed is referred to as a SiC wafer 17. The SiC wafers 13 and 17 are also referred to as the first wafers. Here, the SiC wafers 10 and 14 may be bonded wafers formed by bonding a plurality of SiC wafers. The SiC wafers 10 and 14 have an N-type or P-type conductivity type, or are semi-insulating.

[0012] Next, in step S102, the SiC wafer 13 is divided into a device-attached wafer 19 including the device structure 12 and a divided wafer 20 not including the device structure 12. The device-attached wafer 19 includes a SiC wafer 18 divided from the SiC wafer 10, an epitaxial film 11 on the SiC wafer 18, and a device structure 12 on the epitaxial film 11.

[0013] In step S102, the SiC wafer 17 is divided in the same way as the SiC wafer 13. That is, the SiC wafer 17 is divided into a device-attached wafer 22 that includes the device structure 16, and a divided wafer 23 that does not include the device structure 16. The device-attached wafer 22 comprises a SiC wafer 21 separated from the SiC wafer 14, an epitaxial film 15 on the SiC wafer 21, and a device structure 16 on the epitaxial film 15. The device-attached wafers 19 and 22 are also referred to as first device-attached wafers, and the divided wafers 20 and 23 are also referred to as first divided wafers. Laser slicing technology or the like is used to divide the SiC wafers 13 and 17 in this step.

[0014] Subsequently, in step S103, the back surface of the device-equipped wafers 19 and 22, which is the side opposite to the device structures 12 and 16, is processed. First, the damaged layer on the back surface of the device-equipped wafers 19 and 22, which was damaged by laser slicing, is removed by grinding or polishing, and the device-equipped wafers 19 and 22 are adjusted to the desired thickness. After that, normal back surface processes, such as the formation of back surface electrodes (not shown), are performed on the back surface of the device-equipped wafers 19 and 22.

[0015] Next, in step S104, the front surface processing of the divided wafers 20 and 23 is performed. Since the divided wafers 20 and 23 also include a damaged layer damaged by laser slicing, this damaged layer is removed by grinding or polishing, etc., and the divided wafers 20 and 23 are further adjusted to a desired thickness. Considering the depth of the bonding surface in the bonding wafer described later, the thickness of the divided wafers 20 and 23 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. When adjusting the thickness of the divided wafers 20 and 23, processing on the back surface side of the divided wafers 20 and 23, such as grinding or polishing, may be performed as necessary. By performing processing on the back surface side, in addition to adjusting the thickness, it is possible to remove scratches and the like that occurred during the device process. As a result, a high-quality bonding wafer can be obtained in the subsequent step S105. Here, a high-quality bonding wafer refers to one in which damage suppression, warpage suppression, or flatness improvement has been achieved. The processing on the back surface side of the divided wafers 20 and 23 can also be said to be a process having a certain effect in manufacturing a wafer with a device by division and bonding.

[0016] Thereafter, in step S105, the divided wafers 20 and 23 are bonded. The wafer formed by bonding the divided wafers 20 and 23 is referred to as a bonding wafer 24. The bonding wafer 24 is also referred to as a first bonding wafer. At this time, surface processing may be performed on the bonding surfaces of the divided wafers 20 and 23 by grinding, polishing, or CMP, etc. In order to reduce the warpage of the bonding wafer 24, the warpage or surface state of the divided wafers 20 and 23 is inspected, and the combination of the divided wafers 20 and 23 to be bonded may be determined according to the result. By doing so, a high-quality bonding wafer can be obtained. Here, the two divided wafers 20 and 23 may be manufactured simultaneously or separately. That is, the two divided wafers 20 and 23 may be manufactured simultaneously or sequentially using, for example, different processing facilities, or may be manufactured sequentially using the same processing facility. By doing so, flexible production becomes possible, and the productivity of the divided wafers can be improved. Although the bonding of two divided wafers 20 and 23 is described here, a bonding wafer 24 may be formed by bonding any number of three or more divided wafers.

[0017] The divided wafers 20 and 23 are joined, for example, by room-temperature bonding. Room-temperature bonding does not include a metal layer or the like at the bonding interface, resulting in a clean interface. Furthermore, room-temperature bonding creates an amorphous layer at the bonding interface. After joining the divided wafers 20 and 23, the bonded wafer 24 may be processed to a desired thickness by grinding, polishing, or CMP. In this process, the bonded wafer 24 becomes about the same thickness as a commonly used SiC wafer, making it possible to reuse the divided wafers 20 and 23 at a lower cost and without the risk of breakage compared to forming a thick epitaxial film on a thin SiC wafer to maintain overall strength.

[0018] Before bonding, the divided wafers 20 and 23 may be beveled to remove the sharp points at the intersections of the outer surface and the cut surface, in other words, the corners of the divided wafers 20 and 23. In this case, the shape of the edges of the bonded wafer 24 will be a shape like the letter "3" in cross-section, or a bent shape with 5 to 7 deformation points. If the edges of the divided wafers 20 and 23 are curved, the shape of the edges of the bonded wafer 24 will be a shape like "3" after bonding. If the edges of the divided wafers 20 and 23 are triangular, one deformation point will be duplicated after bonding, and the shape of the edges of the bonded wafer 24 will be a bent shape with 5 deformation points. If the edges of the divided wafers 20 and 23 are trapezoidal, one deformation point will be duplicated after bonding, and the shape of the edges of the bonded wafer 24 will be a bent shape with 7 deformation points. In this case, beveling after bonding is unnecessary, and the amount of material to be removed is small, so the area of ​​the bonded wafer 24 can be increased.

[0019] Alternatively, the beveling may not be performed on the segmented wafers 20 and 23 before bonding, but only on the bonded wafer 24. In this case, the bevel shape of the bonded wafer will be a curved shape like ")" or a trapezoidal shape in cross-section, similar to a normal wafer that is not a bonded wafer. In this case, the chipping prevention effect on the bonded wafer 24 is enhanced compared to a shape like "3". Furthermore, both the segmented wafers 20 and 23 before bonding and the bonded wafer 24 after bonding may be beveled. In this case, both the prevention of chipping during processing and the chipping prevention of the bonded wafer 24 can be obtained.

[0020] Next, in step S106, an epitaxial film 25 is formed on the bonded wafer 24, and then a device structure 26 is formed on the epitaxial film 25. The wafer thus formed is referred to as the bonded wafer 27.

[0021] Subsequently, in step S107, the bonded wafer 27 is divided in the thickness direction to obtain a device-attached wafer 29 including the device structure 26 and a divided wafer 30 not including the device structure 26. The device-attached wafer 29 is also referred to as the second device-attached wafer, and the divided wafer 30 is also referred to as the second divided wafer. The device-attached wafer 29 has a structure in which an epitaxial film 25 is formed on the SiC wafer 10, and the device structure 26 is formed on the epitaxial film 25. This process is the same as in step S102.

[0022] Although the bonded wafer 27 includes the bonding surface of the two divided wafers 20 and 23, it is desirable that this bonding surface is not included in the device-attached wafer 29. This makes it possible to avoid variations in device characteristics due to the bonding surface in the device-attached wafer 29. Here, if the bonded wafer 27 was formed by room-temperature bonding, an amorphous layer will be formed at the bonding interface, so it can also be said that it is desirable that the SiC wafer 28 of the device-attached wafer 29 does not include an amorphous layer. However, even if the device-attached wafer 29 includes the bonding surface of the two divided wafers 20 and 23, this may not be a problem depending on the type of device structure or the characteristics required of the device. In this case, it is not necessary to exclude the bonding surface when obtaining the device-attached wafer 29, and the degree of freedom in process adjustment or thickness adjustment of the wafer division process can be improved.

[0023] The device-equipped wafer 29 obtained in step S107 undergoes the back surface processing (not shown) of step S103 again. The divided wafer 30 obtained in step S107 may also undergo the processing from step S104 onwards again. After that, the divided wafer 30 can be joined with other divided wafers and used to create further device-equipped wafers. That is, the processing from steps S105 to S107 is repeated at least once with the divided wafer 30, which is the second divided wafer, as a new first divided wafer.

[0024] In this way, three device-attached wafers 19, 22, and 29 were obtained from two SiC wafers 13 and 17. By repeating the above process, it is possible to obtain more device-attached wafers than the original SiC wafers. Furthermore, multiple device-attached wafers can be fabricated from SiC wafers with a low amount of various defects, so-called high-quality wafers, enabling the efficient production of a large number of high-quality devices.

[0025] In the case of a bonded wafer formed by bonding a plurality of divided wafers, depending on the state of each divided wafer, the amount of various defects such as crystal defects, for example, through dislocations, may differ across the bonding surface. In this case, the crystal defect density existing in the surface layer may be different between the device structure formation surface side and the opposite side of the bonded wafer, or the crystal defect density existing in the vicinity of the bonding interface may be different. Furthermore, in a normal wafer, through dislocations that are continuous from the front surface to the back surface become discontinuous at the bonding interface in a bonded wafer. However, even when the amount of various defects differs between a plurality of divided wafers, the influence thereof on the device process or device characteristics can be ignored. Here, by appropriately selecting the device structure or divided wafers, the influence of the discontinuity of the above-mentioned defects on the device process or device characteristics can be further suppressed. Furthermore, if the bonded surface is not included in the wafer with devices, the influence of the discontinuity of the above-mentioned defects on the device characteristics can be eliminated.

[0026] <A-2. Practical operation> Figures 3 to 6 are diagrams showing the flow when the basic process shown in FIG. 1 is applied to actual operation. FIGS. 3 and 4 show examples of the flow in a SiC wafer with a thickness of 500 μm, and FIGS. 5 and 6 show examples of the flow in a SiC wafer with a thickness of 350 μm.

[0027] FIGS. 3 and 5 show the process from SiC wafers A3 and B3 until the bonded wafer E1 is formed. FIGS. 4 and 6 show the process from the bonded wafer E1 and the SiC wafer F3 until the bonded wafer G1 is formed. In FIGS. 3 to 6, the numbers shown inside the wafers indicate the thickness (μm) of the wafers. Also, the numbers written in parentheses above or below the wafers indicate the thickness (μm) of the removed wafers. The dashed lines inside the wafers indicate the bonding surfaces, and the numbers written in parentheses next to the bonding surfaces indicate the depth (μm) of the bonding surfaces, that is, the depth (μm) from the front surface of the bonded wafer to the bonding surface. However, the thicknesses and depths of each layer shown in these figures are examples and can be appropriately changed.

[0028] As shown in Figure 3, SiC wafers A3 and B3 are prepared. The thickness of SiC wafers A3 and B3, including the epitaxial film, is 510 μm. SiC wafer A3 is formed by forming device structure A2 on the front surface of SiC wafer A1. Similarly, SiC wafer B3 is formed by forming device structure B2 on the front surface of SiC wafer B1. In the explanation of Figures 3 to 6, the device structure is assumed to include the epitaxial film. For example, device structure A2 more specifically includes the epitaxial film formed on SiC wafer A1 and the device structure formed on that epitaxial film. This is also true for other device structures that appear in the explanation of Figures 3 to 6.

[0029] SiC wafer A3 is divided into a device-attached wafer A4 having device structure A2 and a divided wafer A12 without device structure A2. Device-attached wafer A4 consists of SiC wafer A11 and device structure A2 on it. 50 μm is removed from the back surface of SiC wafer A11, making the thickness of SiC wafer A11 100 μm. Divided wafer A12 has 50 μm removed from the front surface and 10 μm removed from the back surface, making its thickness 300 μm.

[0030] The split wafer A12 has an additional 25 μm removed from its back surface, resulting in a thickness of 275 μm.

[0031] SiC wafer B3 is divided into a device-attached wafer B4 having a device structure B2 and a divided wafer B12 without the device structure B2. Device-attached wafer B4 consists of a SiC wafer B11 and the device structure B2 on it. 50 μm is removed from the back surface of SiC wafer B11, resulting in a thickness of 100 μm. 50 μm is removed from the front surface and 10 μm from the back surface of divided wafer B12, resulting in a thickness of 300 μm.

[0032] The split wafer B12 has an additional 25 μm removed from its top surface, resulting in a thickness of 275 μm.

[0033] Next, the segmented wafers A12 and B12 are joined together to obtain a bonded wafer C1 with a thickness of 550 μm. Here, the depth of the bonded surface of bonded wafer C1 is 275 μm.

[0034] Subsequently, a thickness of 50 μm is removed from the top surface of bonded wafer C1, resulting in a thickness of 500 μm for bonded wafer C1. At this point, the depth of the bonded surface of bonded wafer C1 is 225 μm.

[0035] Next, a device structure C2 is formed on the bonded wafer C1. The wafer consisting of the bonded wafer C1 and the device structure C2 is called the bonded wafer C3. The thickness of the bonded wafer C3 is 510 μm, and the depth of the bonded surface on the bonded wafer C3 is 235 μm.

[0036] Subsequently, the bonded wafer C3 is divided into a device-attached wafer C4 having a device structure C2 and a divided wafer C5 not having a device structure C2. The device-attached wafer C4 consists of a SiC wafer A121, which is part of the divided wafer A12, and the device structure C2 on the SiC wafer A121. The bonding surface in bonded wafer C3 is not included in the device-attached wafer C4. By removing 50 μm from the back surface of SiC wafer A121, the thickness of the device-attached wafer C4 becomes 100 μm. The divided wafer C5 consists of a SiC wafer A122, which is part of the divided wafer A12, and divided wafer B12. 50 μm is removed from the front surface and 10 μm from the back surface of the divided wafer C5, resulting in a thickness of 300 μm. Here, the depth of the bonding surface in the divided wafer C5 is 35 μm.

[0037] The split wafer C5 has an additional 25 μm removed from its back surface, resulting in a thickness of 275 μm.

[0038] A SiC wafer D3 is prepared. SiC wafer D3 is formed by forming a device structure D2 on the front surface of SiC wafer D1.

[0039] SiC wafer D3 is divided into a device-attached wafer D4 having a device structure D2 and a divided wafer D12 without the device structure D2. Device-attached wafer D4 consists of a SiC wafer D11 and the device structure D2 on it. By removing 50 μm from the back surface of SiC wafer D11, the thickness of SiC wafer D11 becomes 100 μm. Divided wafer D12 has 50 μm removed from the front surface and 10 μm removed from the back surface, resulting in a thickness of 300 μm.

[0040] The split wafer D12 has an additional 25 μm removed from its top surface, resulting in a thickness of 275 μm.

[0041] Next, the segmented wafers C5 and D12 are joined together to obtain a bonded wafer E1 with a thickness of 550 μm. At this point, the bonded wafer E1 includes a first bonding surface, which is the bonding surface between SiC wafer A122 and segmented wafer B12, and a second bonding surface, which is the bonding surface between segmented wafer B12 and segmented wafer D12. The depth of the first bonding surface is 35 μm, and the depth of the second bonding surface is 275 μm.

[0042] Subsequently, as shown in Figure 4, 50 μm of the top surface of bonded wafer E1 is removed. This removes SiC wafer A122 from bonded wafer E1, and the thickness of bonded wafer E1 becomes 500 μm. Here, the depth of the bonded surface in bonded wafer E1 is 225 μm.

[0043] Next, a device structure E2 is formed on the front surface of the bonded wafer E1. The SiC wafer consisting of the bonded wafer E1 and the device structure E2 on it is called the bonded wafer E3. The thickness of the bonded wafer E3 is 510 μm, and the depth of the bonded surface on the bonded wafer E3 is 235 μm.

[0044] Subsequently, the bonded wafer E3 is divided into a device-attached wafer E4 having the device structure E2 and a divided wafer E5 without the device structure E2. The device-attached wafer E4 consists of a SiC wafer B121, which is part of the divided wafer B12, and the device structure E2 on it. The divided wafer E5 consists of a divided wafer D12 and a SiC wafer B122, which is part of the divided wafer B12. 50 μm is removed from the front surface and 10 μm from the back surface of the divided wafer E5, resulting in a thickness of 300 μm.

[0045] The split wafer D12 has an additional 25 μm removed from its back surface, resulting in a thickness of 275 μm.

[0046] A SiC wafer F3 is prepared. SiC wafer F3 is formed by forming a device structure F2 on the front surface of SiC wafer F1.

[0047] SiC wafer F3 is divided into a device-attached wafer F4 having a device structure F2 and a divided wafer F12 without the device structure F2. Device-attached wafer F4 consists of a SiC wafer F11 and the device structure F2 on it. By removing 50 μm from the back surface of SiC wafer F11, the thickness of SiC wafer F11 becomes 100 μm. Divided wafer F12 has 50 μm removed from the front surface and 10 μm removed from the back surface, resulting in a thickness of 300 μm.

[0048] The split wafer F12 has an additional 25 μm removed from its top surface, resulting in a thickness of 275 μm.

[0049] Next, the segmented wafers E5 and F12 are joined together to obtain a bonded wafer G1 with a thickness of 550 μm. At this point, the bonded wafer G1 includes a first bonding surface, which is the bonding surface between the SiC wafer B122 and the segmented wafer D12, and a second bonding surface, which is the bonding surface between the segmented wafer D12 and the segmented wafer F12. The depth of the first bonding surface is 35 μm, and the depth of the second bonding surface is 275 μm.

[0050] Subsequently, 50 μm of the top surface of bonded wafer G1 is removed. This removes SiC wafer B122 from bonded wafer G1, leaving a thickness of 500 μm for bonded wafer G1. The depth of the bonded surface on bonded wafer G1 is 225 μm.

[0051] Figures 3 and 4 illustrate the process up to the formation of the bonded wafer G1. However, it is also possible to form a device structure on the bonded wafer G1 and then extract further divided wafers from it. In this way, by repeatedly joining divided wafers to form a bonded wafer, forming a device structure on the bonded wafer, and dividing the bonded wafer, it is possible to repeatedly create wafers with devices using divided wafers.

[0052] Three device-attached wafers A4, B4, and C4 were obtained from two SiC wafers A3 and B3. Furthermore, five device-attached wafers A4, B4, C4, D4, and E4 were obtained from three SiC wafers A3, B3, and D3. In other words, (2n-1) device-attached wafers can be obtained from n SiC wafers 10. This allows for the production of device-attached wafers with a reduced quantity of SiC wafers, resulting in cost reduction.

[0053] In the examples in Figures 3 and 4, SiC wafers A3, B3, D3, and F3 are described as having a 10 μm epitaxial film formed on a 500 μm thick SiC wafer. However, the thickness of each layer constituting SiC wafers A3, B3, D3, and F3 is not limited to this and can be appropriately changed depending on the desired device characteristics or wafer thickness. For example, Figures 5 and 6 show the case where the wafer thickness is 350 μm and the epitaxial film thickness is 10 μm.

[0054] In the examples in Figures 3 and 4, the thickness of the device-attached wafers A4, C4, and E4 is 100 μm, but this is not limited to this, and can be appropriately selected according to the device characteristics. Also, the back surface of SiC wafers A11, A121, and B121 is shown to have 50 μm removed, but this is not limited to this. In order to remove the damaged layer during splitting and make the device-attached wafers A4, C4, and E4 the desired thickness, the amount of material removed from the back surface of SiC wafers A11, A121, and B121 can be appropriately selected, for example, between 10 μm and 100 μm.

[0055] In the examples in Figures 3 and 4, the thickness of the segmented wafers A12, C5, and E5 is 275 μm, but this is not required. The thickness of the segmented wafers A12, C5, and E5 should be 50 μm or more, preferably 80 μm or more, and most preferably 100 μm or more. This prevents cracking of the segmented wafers and allows for operation without a bonding surface in the device-attached wafers C4 and E4. By eliminating the bonding surface, the device-attached wafer can avoid the influence of the bonding surface on device characteristics, and can obtain characteristics equivalent to those of a device using a normal wafer without bonding means.

[0056] Although 50 μm of the top surface of the divided wafers A12, C5, and E5 is removed, this is not limited to this. To remove the damaged layer during division, or to make the divided wafers A12, C5, and E5 the desired thickness, the amount of material removed from the top surface of the divided wafers A12, C5, and E5 may be appropriately selected between, for example, 10 μm and 100 μm.

[0057] In the examples in Figures 3 and 4, the back surfaces of the segmented wafers A12, C5, and E5 are processed in two separate steps. However, this is not limited to this method; the processing can be done in a single step or in two or more separate steps. Performing the processing in a single step reduces the number of steps. Dividing the processing into multiple steps can improve the quality after removal.

[0058] In the examples shown in Figures 3 and 4, the back surfaces of each of the segmented wafers A12, C5, and E5 are removed by a total of 35 μm in two processes. However, the amount of material removed from the back surfaces of segmented wafers A12, C5, and E5 is not limited to this amount, and can be appropriately selected to achieve the desired thickness of segmented wafers A12, C5, and E5. Furthermore, if the desired thickness of segmented wafers A12, C5, and E5 can be achieved by surface processing, back surface processing may not be necessary. By removing the back surfaces of segmented wafers A12, C5, and E5, the laser markings normally applied to the wafers can be removed, thus eliminating the effects of laser markings during bonding, i.e., damage or unevenness on the bonding surface, and improving the quality of the bonded wafer. This effect appears when the total amount of material removed from the back surfaces of the segmented wafers is 1 μm or more, and is particularly noticeable when it is 30 μm or more.

[0059] In the examples in Figures 3 and 4, the total material removal amounts on the surfaces of segmented wafers A12, C5, E5 and B12, D12, F12 are different, but they may be the same. If they are the same, the processing process for these segmented wafers can be standardized, which is advantageous from a productivity standpoint. Similarly, in the examples in Figures 3 and 4, the total material removal amounts on the back surfaces of segmented wafers A12, C5, E5 and B12, D12, F12 are different, but they may be the same. If they are the same, the processing process for these segmented wafers can be standardized, which is advantageous from a productivity standpoint.

[0060] In the examples shown in Figures 3 and 4, two 275 μm thick segmented wafers are joined to create 550 μm thick joined wafers C1, E1, and G1. However, the thickness of the segmented wafers is not limited to this and can be changed as appropriate. Furthermore, segmented wafers of different thicknesses may be joined; for example, segmented wafers A12 and B12 may have different thicknesses.

[0061] In the examples shown in Figures 3 and 4, 50 μm is removed from the top surface of bonded wafers C1, E1, and G1. However, the amount of removal from the top surface of bonded wafers C1, E1, and G1 is not limited to this and can be adjusted as appropriate to achieve the desired thickness of bonded wafers C1, E1, and G1. Furthermore, if the desired thickness is achieved during bonding, this removal is unnecessary. Note that the film thickness of the bonded wafer does not need to be the same as that of the original wafer; it may be different. If the bonded wafer is thicker, cracking and warping can be further reduced during the device manufacturing process. If they are the same, the same process as for a normal wafer is possible. Even if it is thin, if the thickness of the bonded wafer is 100 μm or more, more preferably 250 μm, and most preferably 300 μm or more, the device process can be easily carried out.

[0062] Furthermore, after each film thickness removal step, finishing processes such as grinding, polishing, or CMP may be performed. In particular, for the finishing of the bonding surface of the segmented wafer, precise processing may be required to reduce surface roughness, and it is desirable to perform mirror finishing by polishing or CMP. This makes it possible to obtain a high-quality bonded wafer.

[0063] Note that the device structures A2, B2, C2, D2, E2, and F2 exemplified in Figures 3 and 4 may be the same or different. In other words, the device structure on a normal wafer may be different from the device structure on a bonded wafer. For example, device structure A2 and device structure C2 may be different. If the thickness of the bonded wafer is thin and therefore more sensitive to warping or cracking than a normal wafer, warping or cracking can be avoided by manufacturing a device with a low process load on that bonded wafer. Alternatively, the effects of warping or cracking of the bonded wafer can also be reduced by manufacturing a device that requires a thick epitaxial film. The device structures referred to here may be semiconductor elements such as diodes, transistors, thyristors, or combinations thereof.

[0064] Further, the device structure on the bonded wafer may be determined by the manufacturing yield of the device fabricated on the normal wafer. That is, when the quality of the normal wafer is low and the manufacturing yield of the device fabricated using it is low, a device structure insensitive to the wafer quality may be formed on the bonded wafer obtained by dividing and bonding the wafer. Also, when the quality of the normal wafer is high and the manufacturing yield of the device fabricated using it is high, a device structure sensitive to the wafer quality may be formed on the bonded wafer obtained by dividing and bonding the wafer. Here, the quality of the wafer may be determined by the amount or type of defects that affect device characteristics. Therefore, not only the manufacturing yield of the device, but also at least one of the amount and type of these defects is measured in advance before fabricating the device structure, and after obtaining information to determine that desired characteristics can be obtained, the device structure on the bonded wafer may be determined. Thus, by changing the device structure to be formed between wafers with high yield and high quality and wafers with low yield and low quality, the manufacturing yield of the entire factory can be improved.

[0065] In addition, even when the processes illustrated in FIGS. 3 and 4 are appropriately changed, (2n - 1) device-attached wafers can be obtained from n SiC wafers 10. Thus, the usage amount of the SiC wafers is reduced, and the cost reduction effect can be obtained. That is, the effects of the technology of the present disclosure can be sufficiently obtained.

[0066] Since only the thickness of the wafer is different from that in FIGS. 3 and 4 in FIGS. 5 and 6, the description of these figures is omitted. Similar to FIGS. 3 and 4, the numerical values illustrated in FIGS. 5 and 6 can also be appropriately changed.

[0067] <A-3. Thickness of Wafer and Depth of Bonding Surface> Taking the example of FIG. 1, when the bonding surface is included in the wafer 29 with devices, the bonding surface may affect the characteristics of the devices. In particular, when a bonding defect occurs at the bonding surface, the characteristics of the devices are adversely affected. To avoid such risks, it is desirable that the wafer 29 with devices be formed avoiding the bonding surface of the bonding wafer. Therefore, it is desirable that the depth of the bonding surface in the bonding wafer 24 be greater than the thickness of the wafer 29 with devices. Considering this, the depth of the bonding surface in the bonding wafer 24 is desirably 50 μm or more, more desirably 80 μm or more, and most desirably 100 μm or more. Thereby, even when a device structure is formed using the bonding wafer, the bonding surface does not affect the device characteristics, and characteristics equivalent to those obtained when using a normal wafer without bonding can be obtained.

[0068] In addition, in the bonding wafers C1, E1, and G1 before forming the device structures shown in FIGS. 3 and 4, the depth of the bonding surface is 225 μm in each case. Also, in the bonding wafers C1, E1, and G1 before forming the device structures shown in FIGS. 5 and 6, the depth of the bonding surface is 160 μm in each case.

[0069] As shown in FIG. 7, when the bonding wafer is formed by bonding two split wafers, it is desirable that the depth of the bonding surface be 50 μm or more from the surface of the bonding wafer. Also, as shown in FIG. 8, when the bonding wafer is formed by bonding three split wafers, it is desirable that the depth of the shallowest bonding surface be 50 μm or more from the surface of the bonding wafer.

[0070] In FIGS. 3 and 4, the thickness of the bonding wafers C1, E1, and G1 is 500 μm, and in FIGS. 5 and 6, the thickness of the bonding wafers C1, E1, and G1 was 350 μm. The thicknesses of these bonding wafers are determined in consideration of no warpage occurring when a device structure is formed on the bonding wafer. That is, the thickness of the bonding wafer is desirably 100 μm or more, more desirably 250 μm, and most desirably 300 μm or more.

[0071] <A-4. Timing of Wafer Splitting> Figures 1 to 6 show that a divided wafer was separated from a SiC wafer having a device structure. That is, the separation was performed after the device structure was formed on the SiC wafer. However, the timing of the separation of the divided wafer constituting the bonded wafer from the original SiC wafer is not limited to after the device structure has been formed on the original SiC wafer. Figure 9 shows the different wafer separation timings indicated by "+". Both the divided wafer that will become the front side of the bonded wafer after subsequent bonding and the divided wafer that will become the back side may be separated before the epitaxial film is formed on the original SiC wafer (pre-epitaxial), after the epitaxial film has been formed on the original SiC wafer but before the device structure is formed (post-epitaxial), or after the device structure has been formed on the original SiC wafer. Furthermore, the separation timing from the original SiC wafer may differ between the divided wafer that will become the front side of the bonded wafer and the divided wafer that will become the back side after subsequent bonding. In other words, the separation process may be performed before epitaxial film formation, before device formation, or after device formation.

[0072] Figure 10 shows the basic process for splitting a SiC wafer before epitaxial film formation. The basic process will be explained below in accordance with Figure 10.

[0073] First, a high-quality SiC wafer 40 and a low-quality SiC wafer 43 are prepared. The difference in quality between the two SiC wafers 40 and 43 is expressed, for example, in the number of defects or the flatness. The high-quality SiC wafer 40 has a smaller surface defect or dislocation density in the crystal compared to the low-quality SiC wafer 43. To determine the quality of the SiC wafer, for example, optical microscopy observation, photoluminescence imaging observation, or X-ray diffraction analysis are used.

[0074] The SiC wafer 40 is divided into two high-quality divided wafers 41 and 42, and similarly, the SiC wafer 43 is divided into two low-quality divided wafers 44 and 45. Subsequently, the damaged layer formed on the cut surfaces of the divided wafers 41, 42, 44, and 45 is removed by grinding or polishing.

[0075] Next, a high-quality segmented wafer 41 and a low-quality segmented wafer 44 are joined together to form a bonded wafer 46. Furthermore, a high-quality segmented wafer 42 and a low-quality segmented wafer 45 are joined together to form a bonded wafer 47.

[0076] Subsequently, an epitaxial film 48 and a device structure 49 are formed on the bonded wafer 46. The wafer consisting of the bonded wafer 46, the epitaxial film 48, and the device structure 49 is referred to as the bonded wafer 50. Similarly, an epitaxial film 51 and a device structure 52 are formed on the bonded wafer 47. The wafer consisting of the bonded wafer 47, the epitaxial film 51, and the device structure 52 is referred to as the bonded wafer 53.

[0077] Next, the bonded wafer 50 is divided into a device-attached wafer 54 having a device structure 49 and a divided wafer 44. The device-attached wafer 54 is composed of a high-quality divided wafer 41, an epitaxial film 48, and a device structure 49. Similarly, the bonded wafer 53 is divided into a device-attached wafer 55 having a device structure 52 and a divided wafer 45. The device-attached wafer 55 is composed of a high-quality divided wafer 42, an epitaxial film 51, and a device structure 52.

[0078] This method allows for the creation of multiple device-attached wafers from a high-quality SiC wafer by using a low-quality SiC wafer as the back-side wafer, i.e., the support substrate, in the bonded wafer. Furthermore, by dividing the initial SiC wafer into multiple wafers before the formation of the epitaxial film, all of the divided wafers can be reused. It should be noted that using a high-quality divided wafer as the front-side wafer and a low-quality wafer as the back-side wafer is also applicable when the wafer is divided after device formation, as explained in Figures 1 to 6. By determining the quality of the wafer and utilizing a high-quality divided wafer as the surface of the bonded wafer, as in this method, high-quality wafers can be utilized more efficiently, improving the overall device yield of the manufacturing plant and thus increasing productivity.

[0079] <A-5. Modified Example> In the above description, the original wafer to be divided is a single-crystal SiC wafer. In this case, since SiC is easy to process, there is an advantage that it is easy to bond the divided wafers together. However, the original wafer to be divided, for example, the first wafer, the first divided wafer, or the first bonded wafer, etc., is not limited to SiC, and may be made of other single-crystal materials such as diamond, gallium nitride (GaN), gallium oxide (Ga2O3), aluminum nitride (AlN), etc. Even in such a case, since there is no difference in the coefficient of thermal expansion between the divided wafers, stable bonding can be performed.

[0080] In the examples of FIGS. 3 to 6, the thicknesses of the divided wafers constituting the bonded wafer were the same. For example, in FIG. 3, the thicknesses of the divided wafers A12 and B12 constituting the bonded wafer C1 were both 275 μm. Also, in FIG. 5, the thicknesses of the divided wafers A12 and B12 constituting the bonded wafer C1 were both 190 μm. However, the thicknesses of the divided wafers constituting the bonded wafer do not have to be the same.

[0081] In the examples of FIGS. 3 to 6, one bonded wafer was divided into one wafer with devices and one divided wafer having no device structure. However, one bonded wafer may be divided into one wafer with devices and a plurality of divided wafers having no device structure.

[0082] Also, in the example of FIG. 10, one SiC wafer 40 was divided into two divided wafers 41 and 42. However, one SiC wafer 40 may be divided into a plurality of divided wafers. This is also the same for the SiC wafer 43 in the example of FIG. 10.

[0083] <A-6. Effect> In the example of FIG. 1, the method for manufacturing a semiconductor device according to Embodiment 1 includes: (a) obtaining at least one divided wafer 20, 23 that does not include a device structure from the SiC wafers 13, 17 by dividing each of the plurality of SiC wafers 13, 17 in the thickness direction; (b) joining the plurality of divided wafers 20, 23 obtained from different SiC wafers 13, 17 to obtain a joined wafer 24; and (c) forming a device structure 26 on the surface of the joined wafer 24. Thus, by reusing the remaining divided wafer 20 obtained from the SiC wafer 13 to obtain the device-attached wafer 19 together with another divided wafer 23, a further device-attached wafer 29 can be obtained.

[0084] As a method of reusing wafers, the method described in Patent Document 1 of forming a thick epitaxial layer on a divided wafer has problems such as poor economic efficiency and the wafers being prone to warping and cracking. In contrast, in the method of this embodiment, since the divided wafers are joined to each other, the wafers can be reused at low cost while suppressing warping.

[0085] Also, in the example of FIG. 1, the joined wafer 24 is a joined wafer formed by joining a plurality of divided wafers 20, 23 that do not include a device structure divided from different SiC wafers 13, 17. And at a position 50 μm or more deep from the surface of the joined wafer 24, the joining surfaces of the plurality of divided wafers 20, 23 exist. Thereby, a device-attached wafer 29 that does not include a joining surface can be manufactured using the joined wafer 24. Therefore, the influence of the joining surface on the characteristics of the device can be avoided.

[0086] <B. Embodiment 2> In Embodiment 1, a joined wafer is formed by joining a plurality of divided wafers. In contrast, in Embodiment 2, a joined wafer is formed by joining one divided wafer to a single crystal wafer that is not a divided wafer.

[0087] <B-1. Basic Process> Figure 11 is a schematic diagram showing the basic process in the semiconductor device manufacturing method of Embodiment 2. The semiconductor device manufacturing method of Embodiment 2 will be described below with reference to Figure 11.

[0088] First, a SiC wafer 63 and a single-crystal SiC wafer 67 are prepared. The SiC wafer 63 has an epitaxial film 61 formed on a SiC wafer 60, and a device structure 62 is further formed on the epitaxial film 61.

[0089] Next, the SiC wafer 63 is divided into a device-attached wafer 65 having a device structure 62 and a divided wafer 66 not having a device structure 62. The device-attached wafer 65 is composed of a SiC wafer 64 divided from the SiC wafer 60, an epitaxial film 61 on the SiC wafer 64, and a device structure 62 on the epitaxial film 61.

[0090] Damage layers due to the splitting occur on the back surface of the device-attached wafer 65 and the front surface of the split wafer 66. These damage layers are removed by grinding or polishing.

[0091] Next, the segmented wafer 66 is bonded to the single-crystal SiC wafer 67, thus forming a bonded wafer 68. The segmented wafer 66 is the front side of the bonded wafer 68, and the single-crystal SiC wafer 67 is the back side of the bonded wafer 68. In this way, the single-crystal SiC wafer 67 is used as a support substrate for the segmented wafer 66.

[0092] Subsequently, an epitaxial film 69 is formed on the bonded wafer 68, and then a device structure 70 is formed on the epitaxial film 69. The wafer consisting of the bonded wafer 68, the epitaxial film 69, and the device structure 70 is referred to as the bonded wafer 71.

[0093] Next, the bonded wafer 71 is divided into a device-attached wafer 72 having a device structure 70 and a single-crystal SiC wafer 67. Here, it is desirable that the device-attached wafer 72 does not include the bonding surface between the divided wafer 66 and the single-crystal SiC wafer 67. Therefore, considering the thickness of the device structure 70, it is desirable that the bonding surface between the divided wafer 66 and the single-crystal SiC wafer 67 in the bonded wafer 68 be located at a depth of 50 μm or more from the surface of the bonded wafer 68, more preferably at a depth of 80 μm, and most preferably at a depth of 100 μm or more. In other words, it is desirable that the thickness of the divided wafer 66 be 50 μm or more, more preferably at 80 μm or more, and most preferably at 100 μm or more. As a result, the device-attached wafer 72 does not include the bonding surface, and the influence of the bonding surface on the device can be eliminated.

[0094] Thus, the single-crystal SiC wafer 67 is used as a support substrate when forming a device structure 70 on the divided wafer 66. After being separated from the bonded wafer 71, the single-crystal SiC wafer 67 can be reused as a support substrate for another divided wafer. However, the support substrate may not have a structure such as warp, surface roughness, or surface irregularities suitable for bonding with the SiC wafer. Therefore, before bonding the SiC wafer and the support substrate, the surface of the SiC wafer that will be bonded to the support substrate may be treated by grinding, polishing, or CMP, or the SiC wafer may be treated by pressurizing or heating, to form a structure such as warp, surface roughness, or surface irregularities suitable for bonding with the support substrate on the SiC wafer, the support substrate, or both. This makes it possible to achieve good bonding between the SiC wafer and the support substrate.

[0095] Furthermore, the thickness of the single-crystal SiC wafer 67 separated from the bonded wafer 71 may differ from the original thickness of the single-crystal SiC wafer 67. In other words, when separating the single-crystal SiC wafer 67 from the bonded wafer 71, it is not necessary for the separation to occur at the bonding surface between the separated wafer 66 and the single-crystal SiC wafer 67. Alternatively, the bonding surface may be removed by removing the damaged layer from the separated single-crystal SiC wafer 67. Alternatively, the bonding surface may remain on the separated single-crystal SiC wafer 67.

[0096] In the example shown in Figure 11, one SiC wafer 63 is divided into one device-equipped wafer 65 and one segmented wafer 66 without a device structure. However, one SiC wafer 63 may also be divided into one device-equipped wafer 65 and multiple segmented wafers without a device structure.

[0097] A single-crystal GaN wafer or a single-crystal gallium oxide wafer may be used instead of the single-crystal SiC wafer 67. Such alternative wafers may be used from the standpoint of thermal management in the device manufacturing process, such as heat dissipation from the wafer or heat storage in the wafer.

[0098] A wafer made of another material as mentioned in Embodiment 1 may be used instead of the SiC wafer 63. In that case, if the wafer used as the support substrate and the divided wafer are made of the same material, it is easier to ensure bonding strength.

[0099] In a bonded wafer obtained by bonding a divided wafer and a support substrate, depending on the state of each wafer, the amount of various defects such as crystal defects, for example, through dislocations, may differ across the bonding surface. In this case, the crystal defect density present in the surface layer may differ between the device structure formation surface side and the opposite side of the bonded wafer, or the crystal defect density present in the vicinity of the bonding interface may differ. Furthermore, a through dislocation that is continuous from the front surface to the back surface in a normal wafer becomes discontinuous at the bonding interface in the bonded wafer. However, even when the amount of various defects differs among multiple wafers, the impact on the device process or device characteristics can be ignored. Here, by appropriately selecting the device structure, divided wafer, or support substrate, the impact on the device process or device characteristics caused by the discontinuity of the above-mentioned defects can be further suppressed. Furthermore, if the bonding surface is not included in the wafer with devices, the impact on device characteristics caused by the discontinuity of the above-mentioned defects can be eliminated.

[0100] <B-2. Modified Example> FIG. 12 is a schematic diagram showing the basic process in the method for manufacturing a semiconductor device in a modified example of Embodiment 2. In this modified example, the SiC wafer is divided before the epitaxial film is formed. Hereinafter, the method for manufacturing a semiconductor device in the modified example of Embodiment 2 will be described with reference to FIG. 12.

[0101] First, a SiC wafer 80 and two single crystal SiC wafers 83 and 84 are prepared.

[0102] Next, the SiC wafer 80 is divided into two divided wafers 81 and 82.

[0103] Damage layers are generated on the back surface of the divided wafer 81 and the front surface of the divided wafer 82 due to the division. These damage layers are removed by grinding or polishing or the like.

[0104] Subsequently, the segmented wafer 81 and the single-crystal SiC wafer 83 are joined to form a bonded wafer 85, and the segmented wafer 82 and the single-crystal SiC wafer 84 are joined to form a bonded wafer 86. In this way, the single-crystal SiC wafers 83 and 84 are used as support substrates for the segmented wafers 81 and 82.

[0105] Next, an epitaxial film 87 is formed on the bonded wafer 85, and a device structure 88 is formed on the epitaxial film 87. The wafer consisting of the bonded wafer 85, the epitaxial film 87, and the device structure 88 is referred to as the bonded wafer 89. Similarly, an epitaxial film 90 is formed on the bonded wafer 86, and a device structure 91 is formed on the epitaxial film 90. The wafer consisting of the bonded wafer 86, the epitaxial film 90, and the device structure 91 is referred to as the bonded wafer 92.

[0106] Subsequently, the bonded wafer 89 is divided into a device-attached wafer 93 having a device structure 88 and a single-crystal SiC wafer 83. The device-attached wafer 93 comprises a divided wafer 81, an epitaxial film 87, and a device structure 88. Similarly, the bonded wafer 92 is divided into a device-attached wafer 94 having a device structure 91 and a single-crystal SiC wafer 84. The device-attached wafer 94 comprises a divided wafer 82, an epitaxial film 90, and a device structure 91.

[0107] Here, it is desirable that the device-attached wafers 93 and 94 do not include the bonding surface between the divided wafers 81 and 82 and the single-crystal SiC wafers 83 and 84. Therefore, considering the thickness of the device structures 88 and 91, it is desirable that the bonding surface between the divided wafers 81 and 82 and the single-crystal SiC wafers 83 and 84 in the bonded wafers 85 and 86 be located at a depth of 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more from the surface of the bonded wafers 85 and 86. In other words, it is desirable that the thickness of the divided wafers 81 and 82 be 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. As a result, the device-attached wafers 93 and 94 do not include the bonding surface, and the influence of the bonding surface on the device can be eliminated.

[0108] According to the above method, by using the single-crystal SiC wafers 83 and 84 as a support substrate, it becomes possible to form device structures 88 and 91 on a plurality of divided wafers 81 and 82 divided from the SiC wafer. In addition, the single-crystal SiC wafers 83 and 84 divided from the bonded wafers 89 and 92 can be reused as a support substrate for other divided wafers.

[0109] Note that the thickness of the single-crystal SiC wafers 83 and 84 divided from the bonded wafers 89 and 92 may change from the thickness of the original single-crystal SiC wafers 83 and 84. That is, when dividing the single-crystal SiC wafers 83 and 84 from the bonded wafers 89 and 92, it is not necessary to divide at the bonding surface between the divided wafers 81 and 82 and the single-crystal SiC wafers 83 and 84. Further, the bonding surface may be removed by removing the damaged layer of the single-crystal SiC wafers 83 and 84 after division. Also, the bonding surface may remain on the single-crystal SiC wafers 83 and 84 after division.

[0110] In the example of FIG. 12, one SiC wafer 80 is divided into two divided wafers 81 and 82. However, one SiC wafer 80 may be divided into three or more divided wafers.

[0111] Instead of the SiC wafer 80, wafers of other materials mentioned in Embodiment 1 may be used. In that case, it is desirable that the wafer used as the support substrate and the divided wafer are made of the same material in order to ensure the bonding strength.

[0112] <B-3. Effect> The method for manufacturing a semiconductor device according to Embodiment 2 includes: (a) a step of obtaining divided wafers by dividing a wafer in the thickness direction; (b) a step of bonding the divided wafers to a single-crystal support substrate to obtain a bonded wafer; and (c) a step of forming a device structure on the bonded wafer. Thereby, while suppressing cracking of the wafer, it is possible to manufacture a semiconductor device by reusing the wafer with high productivity.

[0113] Moreover, the bonded wafer according to Embodiment 2 is a bonded wafer formed by bonding a split wafer that does not include a device structure divided from a wafer to a support substrate, and it is desirable that a bonding surface between the split wafer and the support substrate exists at a position 50 μm or more deep from the surface. In this case, when a device structure is formed on the bonded wafer and then the wafer with the device structure including the device structure is divided from the bonded wafer, since the bonding surface is not included in the wafer with the device structure, the influence on the device due to the bonding surface can be removed.

[0114] When using the split wafer shown in Embodiment 1 as a support substrate (for example, the process shown in FIG. 10), since the wafer serving as the support substrate is manufactured by dividing it from a normal wafer, there may be a limitation on the thickness of the support substrate, or there may be waste when removing the support substrate or the split wafer to obtain a bonded wafer with a desired film thickness. In this embodiment, the support substrate is manufactured by directly dividing it from an ingot. Therefore, there is no limitation on the plate thickness, and a single crystal wafer with the plate thickness required as a support substrate can be directly manufactured, reducing waste. As a result, a high cost reduction effect can be obtained. Also, by using a low-quality crystal with many crystal defects that is not suitable for device manufacturing as a support substrate, it is possible to reduce the material loss throughout the manufacturing process.

[0115] <C. Embodiment 3> In Embodiment 2, a bonded wafer is formed by bonding one split wafer to a single crystal wafer that is not a split wafer. In contrast, in Embodiment 3, a bonded wafer is formed by bonding one split wafer to a polycrystalline wafer that is not a split wafer.

[0116] <C-1. Basic Process> FIG. 13 is a schematic diagram showing the basic process in the method for manufacturing a semiconductor device according to Embodiment 3. Hereinafter, the method for manufacturing a semiconductor device according to Embodiment 3 will be described with reference to FIG. 13.

[0117] First, a SiC wafer 103 and a polycrystalline SiC wafer 107 are prepared. The SiC wafer 103 is formed by creating an epitaxial film 101 on a SiC wafer 100, and then creating a device structure 102 on top of the epitaxial film 101.

[0118] Next, the SiC wafer 103 is divided into a device-attached wafer 105 having a device structure 102 and a divided wafer 106 not having a device structure 102. The device-attached wafer 105 is composed of a SiC wafer 104 separated from the SiC wafer 100, an epitaxial film 101 on the SiC wafer 104, and a device structure 102 on the epitaxial film 101.

[0119] Damage layers due to the splitting occur on the back surface of the device-attached wafer 105 and the front surface of the split wafer 106. These damage layers are removed by grinding or polishing.

[0120] Next, the segmented wafer 106 is bonded to the polycrystalline SiC wafer 107, thus forming the bonded wafer 108. The segmented wafer 106 is the front side of the bonded wafer 108, and the polycrystalline SiC wafer 107 is the back side of the bonded wafer 108. In this way, the polycrystalline SiC wafer 107 is used as a support substrate for the segmented wafer 106.

[0121] Subsequently, an epitaxial film 109 is formed on the bonded wafer 108, and then a device structure 110 is formed on the epitaxial film 109. The wafer consisting of the bonded wafer 108, the epitaxial film 109, and the device structure 110 is referred to as the bonded wafer 111.

[0122] Next, the bonded wafer 111 is divided into a device-attached wafer 112 having a device structure 110 and a polycrystalline SiC wafer 107. In this way, the polycrystalline SiC wafer 107 is used as a support substrate when forming the device structure 110 on the divided wafer 106. After being divided from the bonded wafer 111, the polycrystalline SiC wafer 107 can be reused as a support substrate for another divided wafer. Here, the support substrate may not have a structure such as warp, surface roughness, or surface irregularities that are suitable for bonding with the SiC wafer. Therefore, before bonding the SiC wafer and the support substrate, the surface of the SiC wafer that will be bonded to the support substrate may be ground, polished, or treated with CMP, or the SiC wafer may be treated with pressure or heat to form a structure such as warp, surface roughness, or surface irregularities that are suitable for bonding with the support substrate on the SiC wafer, the support substrate, or both. This makes it possible to achieve good bonding between the SiC wafer and the support substrate.

[0123] The thickness of the polycrystalline SiC wafer 107 separated from the bonded wafer 111 may differ from the original thickness of the polycrystalline SiC wafer 107. That is, when separating the polycrystalline SiC wafer 107 from the bonded wafer 111, the separation may be done at the bonding surface between the separated wafer 106 and the polycrystalline SiC wafer 107, but this is not required. Alternatively, the bonding surface may be removed by removing the damaged layer of the separated polycrystalline SiC wafer 107. Alternatively, the bonding surface may remain on the separated polycrystalline SiC wafer 107.

[0124] The bonded wafer 108 includes a bonding surface between the divided wafer 106 and the polycrystalline SiC wafer 107. It is desirable that the device-attached wafer 112 does not include this bonding surface. Therefore, the depth of the bonding surface between the divided wafer 106 and the polycrystalline SiC wafer 107 in the bonded wafer 108 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. In other words, the thickness of the divided wafer 106 separated from the SiC wafer 103 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. This ensures that the device-attached wafer 112 does not include a bonding surface, eliminating any influence of the bonding surface on the device.

[0125] In the example shown in Figure 13, one SiC wafer 103 is divided into one device-equipped wafer 105 and one segmented wafer without a device structure. However, one SiC wafer 103 may also be divided into one device-equipped wafer 105 and multiple segmented wafers without a device structure.

[0126] Instead of the SiC wafer 63, wafers made of other materials, as mentioned in Embodiment 1, may be used. In that case, it is desirable that the wafer used as the support substrate and the divided wafer be made of the same material in order to ensure bonding strength.

[0127] In the bonded wafer obtained by bonding a divided wafer and a support substrate, depending on the state of each wafer, the amount of various defects such as crystal defects, for example, through dislocations, may differ across the bonding surface. In this case, the crystal defect density present in the surface layer may differ between the device structure formation surface side and the opposite surface side of the bonded wafer, or the crystal defect density present in the vicinity of the bonding interface may differ. Furthermore, in a normal wafer, through dislocations that are continuous from the front surface to the back surface become discontinuous at the bonding interface in the bonded wafer. However, even when the amount of various defects differs among multiple wafers, the influence thereof on the device process or device characteristics can be ignored. Here, by appropriately selecting the device structure, divided wafer, or support substrate, the influence of the discontinuity of the above-mentioned defects, etc., on the device process or device characteristics can be further suppressed. Furthermore, if the bonded surface is not included in the wafer with devices, the influence of the discontinuity of the above-mentioned defects, etc., on the device characteristics can be eliminated.

[0128] <C-2. Modified Example> FIG. 14 is a schematic diagram showing a basic process in a method for manufacturing a semiconductor device in a modified example of Embodiment 3. In this modified example, the SiC wafer is divided before the epitaxial film is formed. Alternatively, the SiC wafer may be divided after the formation of the epitaxial film and before the formation of the device structure. Hereinafter, referring to FIG. 14, a method for manufacturing a semiconductor device in a modified example of Embodiment 3 will be described.

[0129] First, a SiC wafer 120 and two polycrystalline SiC wafers 123 and 124 are prepared.

[0130] Next, the SiC wafer 120 is divided into two divided wafers 121 and 122.

[0131] Damage layers are generated on the back surface of the divided wafer 121 and the front surface of the divided wafer 122 due to the division. These damage layers are removed by grinding or polishing, etc.

[0132] Subsequently, the segmented wafer 121 and the polycrystalline SiC wafer 123 are joined to form a bonded wafer 125, and the segmented wafer 122 and the polycrystalline SiC wafer 124 are joined to form a bonded wafer 126. In this way, the polycrystalline SiC wafer 123 is used as a support substrate for the segmented wafer 121, and the polycrystalline SiC wafer 124 is used as a support substrate for the segmented wafer 122.

[0133] Next, an epitaxial film 127 is formed on the bonded wafer 125, and a device structure 128 is formed on the epitaxial film 127. The wafer consisting of the bonded wafer 125, the epitaxial film 127, and the device structure 128 is referred to as the bonded wafer 129. Similarly, an epitaxial film 130 is formed on the bonded wafer 126, and a device structure 131 is formed on the epitaxial film 130. The wafer consisting of the bonded wafer 126, the epitaxial film 130, and the device structure 131 is referred to as the bonded wafer 132.

[0134] The bonded wafers 125 and 126 include the bonding surface between the divided wafers 121 and 122 and the polycrystalline SiC wafers 123 and 124. It is desirable that the device-attached wafers 133 and 134 do not include this bonding surface. Therefore, the depth of the bonding surface between the divided wafers 121 and 122 and the polycrystalline SiC wafers 123 and 124 in the bonded wafers 125 and 126 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. In other words, the thickness of the divided wafers 121 and 122 separated from the SiC wafer 120 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. This ensures that the device-attached wafers 133 and 134 do not include the bonding surface, eliminating any influence of the bonding surface on the device.

[0135] Thereafter, the bonded wafer 129 is divided into a wafer with devices 133 having the device structure 128 and a polycrystalline SiC wafer 123. The wafer with devices 133 includes a divided wafer 121, an epitaxial film 127, and a device structure 128. Similarly, the bonded wafer 132 is divided into a wafer with devices 134 having the device structure 131 and a polycrystalline SiC wafer 124. The wafer with devices 134 includes a divided wafer 122, an epitaxial film 130, and a device structure 131.

[0136] According to the above method, by using the polycrystalline SiC wafers 123 and 124 as support substrates, it becomes possible to form the device structures 128 and 131 on the plurality of divided wafers 121 and 122 divided from the SiC wafer. Also, the polycrystalline SiC wafers 123 and 124 divided from the bonded wafers 129 and 132 can be reused as support substrates for other divided wafers.

[0137] Note that the thicknesses of the polycrystalline SiC wafers 123 and 124 divided from the bonded wafers 129 and 132 may be changed from the thicknesses of the original polycrystalline SiC wafers 123 and 124. That is, when dividing the polycrystalline SiC wafers 123 and 124 from the bonded wafers 129 and 132, it is not necessary to divide at the bonding surfaces between the divided wafers 121 and 122 and the polycrystalline SiC wafers 123 and 124. Also, the bonding surfaces may be removed by removing the damaged layers of the polycrystalline SiC wafers 123 and 124 after division. Also, the bonding surfaces may remain on the polycrystalline SiC wafers 123 and 124 after division.

[0138] In the example of FIG. 14, one SiC wafer 120 is divided into two divided wafers. However, one SiC wafer 120 may be divided into three or more divided wafers.

[0139] <C-3. Effect> In the example shown in Figure 14, the semiconductor device manufacturing method according to Embodiment 3 comprises the steps of (a) obtaining divided wafers 121 and 122 with a thickness of 50 μm or more by dividing a SiC wafer 120 in the thickness direction; (b) obtaining bonded wafers 125 and 126 by bonding the divided wafers 121 and 122 to polycrystalline SiC wafers 123 and 124 which are support substrates; and (c) forming device structures 128 and 131 on the bonded wafers 125 and 126. This makes it possible to manufacture semiconductor devices by reusing wafers with high productivity while suppressing wafer cracking.

[0140] Furthermore, in the example shown in Figure 14, the bonded wafer according to Embodiment 3 is a bonded wafer formed by bonding divided wafers 121 and 122, which do not contain a device structure and are separated from a SiC wafer 120, to a polycrystalline SiC wafer 123 and 124 that serve as a support substrate, with the bonding surface between the divided wafers 121 and 122 and the polycrystalline SiC wafer 123 and 124 located at a depth of 50 μm or more from the surface. This makes it possible to manufacture semiconductor devices by reusing wafers with high productivity while suppressing wafer cracking.

[0141] In the case where the segmented wafer shown in Embodiment 1 is used as a support substrate (for example, the process shown in Figure 10), the wafer that will serve as the support substrate is manufactured by segmenting a regular wafer. This can lead to limitations on the thickness of the support substrate, or waste may occur when removing the support substrate or segmented wafer to obtain a bonded wafer with the desired film thickness. In this embodiment, the support substrate is manufactured by segmenting directly from an ingot. Therefore, there are no limitations on the thickness of the wafer, and a single-crystal wafer of the required thickness for the support substrate can be manufactured directly, thus reducing waste. This makes it possible to achieve a high cost reduction effect. Furthermore, by using a low-quality crystal with many crystal defects unsuitable for device manufacturing as the support substrate, it is also possible to reduce material loss throughout the entire manufacturing process.

[0142] Furthermore, compared to the case where a single-crystal wafer is used as the support substrate as shown in Embodiment 2, a polycrystalline substrate can be manufactured at a lower cost, thus achieving cost reduction.

[0143] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate. The above description is illustrative in all embodiments. It is understood that countless variations not illustrated can be conceivable. For example, the processes of splitting, joining, and related wafer front and back processing shown in Embodiment 1, or the features of the split wafer, joined wafer, and device-attached wafer, can be combined, modified, or omitted as appropriate in the forms using the support substrate shown in Embodiments 2 and 3. [Explanation of Symbols]

[0144] 10,13 SiC wafers, 11,15,25 epitaxial films, 12,16,26 device structures, 19,22,29 wafers with devices, 20,23,30,66,106 segmented wafers, 67 single-crystal SiC substrates, 107 polycrystalline SiC substrates.

Claims

1. (a) A step of obtaining at least one first divided wafer that does not contain a device structure from each of the multiple first wafers by dividing each of the first wafers in the thickness direction, (b) A step of joining a plurality of first divided wafers obtained from different first wafers to obtain a first bonded wafer, (c) A step of forming a device structure on the surface of the first bonding wafer, A method for manufacturing semiconductor devices.

2. Step (a) is a step of dividing each of the first wafers having a device structure formed on its surface into a first device-attached wafer which is a device-attached wafer including the device structure, and at least one of the first divided wafers. A method for manufacturing a semiconductor device according to claim 1.

3. (d) The first bonded wafer on which the device structure is formed is further divided into a second device-attached wafer which is a device-attached wafer including the device structure and at least one second divided wafer which does not include the device structure. A method for manufacturing a semiconductor device according to claim 1 or claim 2.

4. (e) After step (d), the process further comprises repeating steps (b) through (d) at least once, using the second divided wafer as a new first divided wafer. A method for manufacturing a semiconductor device according to claim 3.

5. At least one of the first wafers is a bonded wafer formed by joining multiple wafers. A method for manufacturing a semiconductor device according to claim 1.

6. If the wafer from which the device-attached wafer is divided is a bonded wafer formed by joining multiple wafers, the device-attached wafer does not include the bonding surface included in the original bonded wafer. A method for manufacturing a semiconductor device according to claim 3.

7. The material of the first wafer is SiC. A method for manufacturing a semiconductor device according to claim 1.

8. The material of the first wafer is single-crystal SiC. A method for manufacturing a semiconductor device according to claim 7.

9. The thickness of the first divided wafer is 50 μm or more. A method for manufacturing a semiconductor device according to claim 1.

10. The structure of the aforementioned device is a SiC power device structure. A method for manufacturing a semiconductor device according to claim 1.

11. (a) A step of obtaining a divided wafer by dividing a wafer that is not a bonded wafer in the thickness direction, (b) A step after step (a) of bonding the divided wafer to a support substrate to obtain a bonded wafer, (c) A step of forming a device structure on the bonded wafer after step (b), A method for manufacturing semiconductor devices.

12. The bonding surface between the divided wafer and the support substrate in the bonded wafer is located at a depth of 50 μm or more from the surface of the bonded wafer. A method for manufacturing a semiconductor device according to claim 11.

13. The support substrate is made of single-crystal SiC or single-crystal GaN. A method for manufacturing a semiconductor device according to claim 11 or claim 12.

14. The support substrate is a polycrystalline substrate. A method for manufacturing a semiconductor device according to claim 11 or claim 12.

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