Semiconductor devices and power converters
A multi-layer insulating film structure in semiconductor devices with a silicon-free layer between gallium oxide and silicon dioxide layers suppresses silicon diffusion, stabilizing electrical properties and maintaining high insulating performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2024-09-27
- Publication Date
- 2026-05-29
Smart Images
Figure 0007867639000001 
Figure 0007867639000002 
Figure 0007867639000003
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device having a gallium oxide layer and an insulating film mainly containing SiO2.
Background Art
[0002] In semiconductor devices, various insulating films such as gate insulating films, interlayer insulating films, and passivation films are provided on semiconductor layers. Silicon dioxide (SiO2) or a material mainly containing SiO2 has a large bandgap and a large breakdown electric field, so it is widely used as an insulating film in semiconductor devices. For example, Patent Document 1 describes a Schottky barrier diode including an n-type semiconductor layer and an insulating film made of SiO2 that covers a part of the upper surface of the n-type semiconductor layer.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] However, according to the study by the inventors of the present disclosure, when a film having SiO2 is formed as an insulating film on a semiconductor layer made of gallium oxide (Ga2O3), when heat is applied, silicon (Si) diffuses into Ga2O3 at the Ga2O3 / SiO2 interface, and the donor concentration on the Ga2O3 surface changes, resulting in problems such as fluctuations in the electrical characteristics of the semiconductor device.
[0005] The present disclosure has been made to solve the above problems, and an object thereof is to suppress the diffusion of Si from a film having SiO2 into a gallium oxide layer in a gallium oxide semiconductor device.
Means for Solving the Problems
[0006] The semiconductor device of this disclosure comprises a gallium oxide layer and an insulating film formed above the gallium oxide layer. The insulating film includes a first insulating film that does not contain silicon as a material, a second insulating film having silicon dioxide, and a third insulating film that is thicker than the second insulating film. The first insulating film is provided between the second insulating film and the gallium oxide layer, and the third insulating film is provided on the side of the second insulating film opposite to the first insulating film. The semiconductor device of this disclosure is divided in a plan view into an active region and a terminal region surrounding the active region, and further comprises a heterogeneous semiconductor layer made of a semiconductor different from gallium oxide, provided on a gallium oxide layer in the terminal region. A first insulating film is provided on the heterogeneous semiconductor layer, and a second insulating film is provided on the heterogeneous semiconductor layer via the first insulating film. [Effects of the Invention]
[0007] The semiconductor device of this disclosure includes a lower insulating film that does not contain Si between an upper insulating film having high insulating performance SiO2 and a gallium oxide layer, thereby suppressing the diffusion of Si from the upper insulating film to the gallium oxide layer. As a result, the electrical properties of the semiconductor device can be kept stable while maintaining high insulating performance due to the upper insulating film. [Brief explanation of the drawing]
[0008] [Figure 1] This is a cross-sectional view showing the configuration of the active region of the semiconductor device according to Embodiment 1. [Figure 2] This figure shows the energy bands for SiO2, Al2O3, and Ga2O3. [Figure 3] This is a cross-sectional view showing the configuration of the termination region of a semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view showing another configuration of the termination region of the semiconductor device according to Embodiment 1. [Figure 5] This is a cross-sectional view showing the configuration of the active region of the semiconductor device according to Embodiment 2. [Figure 6] This is a block diagram showing the configuration of the power conversion system according to Embodiment 3. [Modes for carrying out the invention]
[0009] In the following description, n-type and p-type indicate the conductivity types of semiconductors. In the present disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. n+ type means that the impurity concentration is higher than that of n-type, and n- type means that the impurity concentration is lower than that of n-type. p+ type means that the impurity concentration is higher than that of p-type, and p- type means that the impurity concentration is lower than that of p-type. Also, the height of the impurity concentration in each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak concentration of impurities.
[0010] The drawings are shown schematically, and the mutual relationships of the sizes and positions of the images shown in different drawings are not necessarily accurately described and may be changed as appropriate. Also, in the following description, the same reference numerals are used to illustrate the same components, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.
[0011] In the following description, terms such as "upper", "lower", "side", "front", and "back" that mean specific positions and directions may be used, but these terms are used for convenience to facilitate understanding of the content of the embodiments and have nothing to do with the directions in actual implementation.
[0012] <A. Embodiment 1> <A-1. Active Region> FIG. 1 is a cross-sectional view showing the configuration of the active region of the semiconductor device 101 according to Embodiment 1. The semiconductor device 101 is a vertical planar MOSFET. As shown in FIG. 1, the semiconductor device 101 includes a gallium oxide layer 20, a gate insulating film 5, a gate electrode 6, an interlayer insulating film 7, a source electrode 8, and a drain electrode 9 in the active region. Here, the transistor is described as an example of the semiconductor device 101, but the semiconductor device 101 may be other devices such as a diode.
[0013] The gallium oxide layer 20 comprises a first main surface S1 and a second main surface S2. The gallium oxide layer 20 is a semiconductor layer made of gallium oxide (Ga2O3), but may contain impurities such as In or Al. The gallium oxide layer 20 comprises an n+ type first gallium oxide layer 1, an n- type second gallium oxide layer 2, a p-type well layer 3, and an n+ type source region 4. The second gallium oxide layer 2 is provided on the first main surface S1 side of the first gallium oxide layer 1. The lower surface of the first gallium oxide layer 1 corresponds to the second main surface S2, and a drain electrode 9 is provided on the second main surface S2. Here, for example, a gallium oxide single crystal substrate can be used for the first gallium oxide layer 1. However, if the semiconductor device 101 is manufactured using a process such as so-called back surface polishing or dissimilar substrate delamination, the gallium oxide layer 20 may not include the first gallium oxide layer 1.
[0014] A p-type well layer 3 is formed on a portion of the surface of the second gallium oxide layer 2 on the first main surface S1 side. The well layer 3 is not limited to a p-type layer; it may also be a layer in which elements such as nitrogen are added to form a somewhat deep or deep acceptor level. An n+-type source region 4 is formed on the surface of the well layer 3 on the first main surface S1 side. The surface of the well layer 3 between the source region 4 and the second gallium oxide layer 2 becomes a channel region. A gate insulating film 5 is formed on the first main surface that is in contact with the second gallium oxide layer 2, the channel region, and a portion of the source region 4 between adjacent well layers 3.
[0015] The gate insulating film 5 has a two-layer structure consisting of a first gate insulating film 51 in contact with the gallium oxide layer 20 and a second gate insulating film 52 on the first gate insulating film 51. The first gate insulating film 51 is made of a material that does not contain Si, for example, aluminum oxide (Al2O3). The second gate insulating film 52 is made of SiO2 only, for example. The second gate insulating film 52 is not made of SiO2 only, but may also be made of SiO2 in combination with other insulating materials.
[0016] A gate electrode 6 is formed on the gate insulating film 5. An interlayer insulating film 7 is formed on the gate electrode 6. A source electrode 8 is formed on the interlayer insulating film 7. The gate electrode 6 and the source electrode 8 are insulated by the interlayer insulating film 7. Here, the thickness of the interlayer insulating film 7 is greater than the thickness of the second gate insulating film 52 or the gate insulating film 5. Note that the interlayer insulating film 7 is in contact with the gate insulating film 5 at both ends of the gate electrode 6. The interlayer insulating film 7 may or may not contain Si.
[0017] In the semiconductor device 101, the second gate insulating film 52 is an insulating film made of SiO2 and is also referred to as the second insulating film. The first gate insulating film 51 is an insulating film that does not contain Si as a material and is provided between the second insulating film and the gallium oxide layer, and is also referred to as the first insulating film. The interlayer insulating film 7 is an insulating film provided on the opposite side of the first insulating film of the second insulating film, and is also referred to as the third insulating film.
[0018] The source electrode 8 contacts the source region 4 at a portion of the first main surface S1 where the gate insulating film 5 is not formed.
[0019] The semiconductor device 101 has a configuration in which a first gate insulating film 51 that does not contain Si is inserted between the gallium oxide layer 20 and the second gate insulating film 52 made of SiO2. Thereby, the diffusion of Si from the second gate insulating film 52 to the gallium oxide layer 20 is suppressed. As a result, the donor concentration of the gallium oxide layer 20 is stabilized and the conductivity is stabilized.
[0020] The material of the first gate insulating film 51 does not need to contain Si from the viewpoint of suppressing the diffusion of Si, but it is desirable to further satisfy the following conditions. Here, the first gate insulating film 51 is not limited to Al2O3 or HfO2, and may be an insulating film composed of three or more elements and satisfying the following conditions.
[0021] Figure 2 shows the energy bands of SiO2 used for the second gate insulating film 52, Al2O3 used for the first gate insulating film 51 as an example, and β-Ga2O3 used for the gallium oxide layer 20 as an example.
[0022] (1) If the band gap of the material of the first gate insulating film 51 is Eg_1, the band gap of Ga2O3 is (Eg_Ga2O3) = 4.6 eV, and the band gap of SiO2 is (Eg_SiO2) = 8.7 eV, then it is desirable that (Eg_SiO2) > (Eg_1) > (Eg_Ga2O3). Materials that satisfy this condition include Al2O3 with a band gap of 6.8 eV, hafnium oxide (HfO2) with a band gap of approximately 6 eV, or ZrO2 with a band gap of 5.5 eV.
[0023] (2) Let (ΔEc_1) be the absolute value of the energy difference between the lower end of the conduction band of the material of the first gate insulating film 51 and the lower end of the conduction band of Ga2O3, and let (ΔEc_SiO2) be the absolute value of the energy difference between the lower end of the conduction band of SiO2 and the lower end of the conduction band of Ga2O3. It is desirable that (ΔEc_SiO2) > (ΔEc_1) > 0. This condition is also satisfied when the material of the first gate insulating film 51 is Al2O3, HfO2, or ZrO2.
[0024] (3) Let (ΔEv_1) be the absolute value of the energy difference between the upper end of the valence band of the material of the first gate insulating film 51 and the upper end of the valence band of Ga2O3, and let (ΔEv_S) be the absolute value of the energy difference between the upper end of the valence band of SiO2 and the upper end of the valence band of Ga2O3. i If O2 is used, it is desirable that (ΔEv_SiO2)>(ΔEv_1)>0. This condition is also satisfied when the material of the first gate insulating film 51 is Al2O3. Due to conditions (1), (2), and (3), the band gap changes stepwise from the gallium oxide layer 20 to the first gate insulating film 51 and then to the second gate insulating film 52, so that electrons or holes are not trapped in the first gate insulating film 51 or the interface.
[0025] (4) Let the thickness of the first gate insulating film 51 be (t_1), and the thickness of the SiO2 used for the second gate insulating film 52 be (t_SiO2). Then, it is desirable that (t_SiO2) > (t_1). The thicker the first gate insulating film 51, the higher the Si diffusion suppression effect. However, due to design limitations, there is an upper limit to the thickness of the gate insulating film 5. Therefore, as the first gate insulating film 51 becomes thicker, the second gate insulating film 52 may become thinner. From the perspective of ensuring a high reliability SiO2 thickness, this condition is obtained.
[0026] <A-2. Termination Region> FIG. 3 is a cross-sectional view showing the configuration of the termination region of the semiconductor device 101 according to Embodiment 1. In FIG. 3, A indicates the chip edge. As shown in FIG. 3, the semiconductor device 101 includes a second gallium oxide layer 2, a well layer 3, a termination well layer 11, a first termination insulating film 21, a second termination insulating film 22, an interlayer insulating film 23, a surface protection film 24, and a source electrode 8 in the termination region. Note that in FIG. 3, the drain electrode 9, the first gallium oxide layer 1, and various electric field relaxation structures are not shown.
[0027] The termination well layer 11 is a p-type semiconductor layer formed of an oxide semiconductor in the surface layer portion on the first main surface S1 side of the second gallium oxide layer 2, or a high-resistance layer formed by nitrogen ion implantation or the like, and is adjacent to the well layer 3. The well layer 3 is also a p-type semiconductor layer formed of an oxide semiconductor in the surface layer portion on the first main surface S1 side of the second gallium oxide layer 2, or a high-resistance layer formed by nitrogen ion implantation or the like. The depth or impurity concentration of the well layer 3 and the termination well layer 11 may be different or may be the same.
[0028] The first termination insulating film 21 is formed on the termination well layer 11. The second termination insulating film 22 is formed on the first termination insulating film 21. The interlayer insulating film 23 is formed on the second termination insulating film 22. The source electrode 8 is formed on the well layer 3. The surface protection film 24 is formed on the second gallium oxide layer 2 covering the first termination insulating film 21, the second termination insulating film 22, and the interlayer insulating film 23.
[0029] The first terminal insulating film 21, the second terminal insulating film 22, and the interlayer insulating film 23 may be formed in the same process as the first gate insulating film 51, the second gate insulating film 52, and the interlayer insulating film 7, and may be composed of the same materials. That is, the second terminal insulating film 22 contains SiO2, and the first terminal insulating film 21 does not contain Si.
[0030] According to the configuration of the terminal region of the semiconductor device 101 shown in Figure 3, the diffusion of Si from the second terminal insulating film 22 to the well layer 3 or the terminal well layer 11 can be suppressed by the first terminal insulating film 21. As a result, the electric field of the gallium oxide layer can be stabilized, and the electrical properties can be kept stable. In particular, fluctuations in the electrical properties of the semiconductor device or a decrease in breakdown voltage caused by impurity species or amounts of impurities in the p-type semiconductor in the terminal region can be suppressed.
[0031] Figure 3 illustrates the case where a terminal well layer 11 is formed on the surface of the second gallium oxide layer 2. However, as shown in Figure 4, instead of the terminal well layer 11, a heteromaterial layer 12 made of a material different from gallium oxide may be formed on the first main surface S1 of the second gallium oxide layer 2. In this case, a first terminal insulating film 21 is formed on the heteromaterial layer 12, and a second terminal insulating film 22 is formed on the first terminal insulating film 21. The heteromaterial layer 12 is, for example, a p-type semiconductor layer, and can be NiO, Cu2O, etc. In Figure 4, the first terminal insulating film 21 and the second terminal insulating film 22 are also formed on the second gallium oxide layer 20, but they may also be formed only on the heteromaterial layer 12.
[0032] In Figures 3 and 4, the first and second terminal insulating films 21 and 22 are not formed up to the chip edge. In this case, there is a risk that Si may diffuse from the second terminal insulating film 22 to the second gallium oxide layer 2 through the region of the first main surface S1 where the first terminal insulating film 21 is not formed. To prevent this, the first and second terminal insulating films 21 and 22 may be formed up to the chip edge. Alternatively, the first and second terminal insulating films 21 and 22 may be formed up to a region outside of various electric field relaxation structures (not shown) that does not overlap with the chip's dicing line.
[0033] <A-3. Effect> As described above, the semiconductor device 101 according to Embodiment 1 includes a gallium oxide layer 20 and a gate insulating film 5 formed on the gallium oxide layer 20. The gate insulating film 5 includes a first gate insulating film 51 that does not contain silicon as a material, a second gate insulating film 52 having silicon dioxide, and an interlayer insulating film 7. The first gate insulating film 51 is provided between the second gate insulating film 52 and the gallium oxide layer 20. The interlayer insulating film 7 is provided on the side opposite to the first gate insulating film 51 of the second gate insulating film 52. With such a configuration, the diffusion of Si from the interlayer insulating film 7 to the gallium oxide layer 20 when the second gate insulating film 52 or SiO2 is present is suppressed. As a result, the donor concentration of the gallium oxide layer 20 is stabilized, and the electrical characteristics of the semiconductor device are stabilized.
[0034] <B. Embodiment 2> <B-1. Active Region> FIG. 5 is a cross-sectional view showing the configuration of the active region of the semiconductor device 102 according to Embodiment 2. The semiconductor device 102 is a vertical trench-type MOSFET. As shown in FIG. 5, a trench 10 is formed in the gallium oxide layer 20 that penetrates the source region 4 and the well layer 3 from the first main surface S1 and reaches the second gallium oxide layer 2. A gate insulating film 5 is formed on the side surface and the bottom surface of the trench 10, and a gate electrode 6 is embedded in the trench 10 through the gate insulating insulating film insulating film 5.
[0035] The gate insulating film 5 has a two-layer structure of a first gate insulating film 51 and a second gate insulating film 52. The second gate insulating film 52 is formed in contact with the gate electrode 6, and the first gate insulating film 51 is formed between the second gate insulating film 52 and the gallium oxide layer 20.
[0036] An interlayer insulating film 7 is formed on the gate electrode 6. The interlayer insulating film 7 insulates the gate electrode 6 and the source electrode 8. The interlayer insulating film 7 is in contact with the second gate insulating film 52 on both sides of the trench 10. The configuration of the other active regions of the semiconductor device 102 is the same as the configuration of the active regions of the semiconductor device 101 described in Embodiment 1.
[0037] <B-2. Terminal Region> The configuration of the terminal region of the semiconductor device 102 may be the same as the configuration of the terminal region of the semiconductor device 101 shown in FIGS. 3 and 4. As another configuration, a trench reaching the second gallium oxide layer 2 may be formed in the terminal region, and a hetero material layer 12 may be formed in the trench. That is, as long as the formation of the first terminal insulating film 21 and the second terminal insulating film 22 suppresses the diffusion of Si and stabilizes the function of the terminal region, the terminal region of the semiconductor device 102 is not limited to a specific structure.
[0038] <B-3. Effects> In the semiconductor device 102, the first gate insulating film 51 is provided on the bottom surface and the side wall of the trench 10 formed in the gallium oxide layer 20. The second gate insulating film 52 is provided on the bottom surface and the side wall of the trench 10 via the first gate insulating film 51. The semiconductor device 102 includes a gate electrode 6 embedded in the trench 10 via the first gate insulating film 51 and the second gate insulating film 52. Further, in the semiconductor device 102, the third insulating film is the interlayer insulating film 7. Even in the above configuration, similar to the semiconductor device 101 according to the first embodiment, the first gate insulating film 51 suppresses the diffusion of Si from the second gate insulating film 52 to the gallium oxide layer 20. As a result, the donor concentration of the gallium oxide layer 20 is stabilized, the electric field of the gallium oxide layer is stabilized, and the electrical characteristics of the semiconductor device are stabilized. In the case of the trench type, since the gate insulating film 5 contacts both the side surface and the bottom surface of the trench 10, it is not easy to select the plane orientation of the gallium oxide layer 20 so as to reduce the influence of Si diffusion on both surfaces. Therefore, it can be said that the configuration of the present disclosure that suppresses the diffusion of Si into the gallium oxide layer 20 by the first gate insulating film 51 is particularly effective in the trench type.
[0039] <C. Embodiment 3> This embodiment applies the semiconductor devices 101 and 102 according to Embodiments 1 and 2 described above to a power converter. The application of the semiconductor devices 101 and 102 according to Embodiments 1 and 2 is not limited to a specific power converter, but below, as Embodiment 3, we will describe the case in which the semiconductor devices 101 and 102 according to Embodiments 1 and 2 are applied to a three-phase inverter.
[0040] Figure 6 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.
[0041] The power conversion system shown in Figure 6 consists of a power supply 100, a power converter 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power converter 200. The power supply 100 can be composed of various components, for example, a DC grid, a solar cell, or a battery, or it may be composed of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 100 may be composed of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.
[0042] The power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300. It converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As shown in Figure 6, the power converter 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202 to control the drive circuit 202.
[0043] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Note that Load 300 is not limited to a specific application; it is a motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.
[0044] The details of the power converter 200 are described below. The main conversion circuit 201 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 100 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. At least one of the switching elements and each freewheeling diode of the main conversion circuit 201 is fitted with the semiconductor devices 101 and 102 according to the above embodiments 1 and 2. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.
[0045] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203, which will be described later, it outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element. When the switching elements are kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching elements, and when the switching elements are kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching elements.
[0046] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state based on the power to be supplied to the load 300. For example, the main converter circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
[0047] In the power conversion device according to this embodiment, semiconductor devices 101 and 102 according to embodiments 1 and 2 are used as switching elements of the main conversion circuit 201, thereby improving the reliability of the power conversion device.
[0048] In this embodiment, an example of applying the semiconductor devices 101 and 102 according to Embodiments 1 and 2 to a two-level three-phase inverter has been described. However, the application of the semiconductor devices 101 and 102 according to Embodiments 1 and 2 is not limited to this, and they can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. Furthermore, when supplying power to a single-phase load, the semiconductor devices 101 and 102 according to Embodiments 1 and 2 may be applied to a single-phase inverter. In addition, when supplying power to a DC load, it is also possible to apply the semiconductor devices 101 and 102 according to Embodiments 1 and 2 to a DC / DC converter or an AC / DC converter.
[0049] Furthermore, the power conversion device to which the semiconductor devices 101 and 102 according to Embodiments 1 and 2 are applied is not limited to the case where the load is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, laser processing machine, induction heating cooker, or contactless power supply system, and can even be used as a power conditioner for a solar power generation system or energy storage system.
[0050] Furthermore, the second terminal insulating film 22 and the second gate insulating film 52 in embodiments 1 and 2 contain Si. Therefore, Si may diffuse into the vicinity outside each of them, for example, the first terminal insulating film 21 or the first gate insulating film 51, forming a first terminal insulating film 21 or first gate insulating film 51 containing Si. If we refer to this insulating film containing Si as a Si-containing insulating film, the Si-containing insulating film is interposed between the first terminal insulating film 21 and the second terminal insulating film 22, or between the first gate insulating film 51 and the second gate insulating film 52, for example. The Si-containing insulating film can be composed of a Si-containing composition or an oxygen-rich composition based on the composition of the first terminal insulating film 21 or the first gate insulating film 51, for example. Thus, strictly speaking, the gate insulating film 5 or terminal insulating film has at least a three-layer structure, but this has been omitted in the above explanation. Furthermore, it is conceivable that Si diffuses and reaches the interface of the gallium oxide layer 20, that is, that Si is present throughout or almost throughout the first terminal insulating film 21 or the first gate insulating film 51. In this case, the gate insulating film 5 or the terminal insulating film can be said to have at least a two-layer structure, or partially a three-layer structure.
[0051] Furthermore, the first termination insulating film 21 and the first gate insulating film 51 according to Embodiments 1 and 2 can also be described as layers that stop or suppress Si diffusion, and it is preferable that they have a trap structure that can easily capture Si. The trap structure may have molecular structures such as defects that easily form bonds with Si, either partially or entirely, and it is sufficient that it has some function of stopping or suppressing Si diffusion.
[0052] Although preferred embodiments have been described in detail above, the invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims. Furthermore, this disclosure can be applied not only to power semiconductor devices but also to high-frequency semiconductor devices. [Explanation of Symbols]
[0053] 1 First gallium oxide layer, 2 Second gallium oxide layer, 3 Well layer, 4 Source region, 5 Gate insulating film, 6 Gate electrode, 7, 23 Interlayer insulating film, 8 Source electrode, 9 Drain electrode, 10 Trench, 11 Termination well layer, 12 Heteromaterial layer, 20 Gallium oxide layer, 21 First termination insulating film, 22 Second termination insulating film, 24 Surface protective film, 51 First gate insulating film, 52 Second gate insulating film, 100 Power supply, 101, 102 Semiconductor device, 200 Power converter, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 300 Load, S1 First main surface, S2 Second main surface.
Claims
1. Gallium oxide layer, Formed above the gallium oxide layer, The insulating film comprises a first insulating film that does not contain silicon as a material, a second insulating film having silicon dioxide, and a third insulating film having a thickness greater than the thickness of the second insulating film. The first insulating film is provided between the second insulating film and the gallium oxide layer. The third insulating film is provided on the side of the second insulating film opposite to the first insulating film, In a plan view, it is divided into an active region and a terminal region surrounding the active region. The terminal region further comprises a heterogeneous semiconductor layer made of a semiconductor different from gallium oxide, provided on the gallium oxide layer. The first insulating film is provided on the dissimilar semiconductor layer, The second insulating film is provided on the heterogeneous semiconductor layer via the first insulating film. Semiconductor equipment.
2. The band gap of the material constituting the first insulating film is larger than the band gap of the gallium oxide semiconductor and smaller than the band gap of silicon dioxide. The semiconductor device according to claim 1.
3. The thickness of the first insulating film is less than the thickness of the second insulating film. The semiconductor device according to claim 1 or claim 2.
4. The absolute value of the energy difference between the lower end of the conduction band of the material constituting the first insulating film and the lower end of the conduction band of the gallium oxide semiconductor is less than the absolute value of the energy difference between the lower end of the conduction band of silicon dioxide and the lower end of the conduction band of the gallium oxide semiconductor, and greater than 0. The semiconductor device according to claim 1.
5. The absolute value of the energy difference between the upper end of the valence band of the material constituting the first insulating film and the upper end of the valence band of the gallium oxide semiconductor is less than the absolute value of the energy difference between the upper end of the valence band of silicon dioxide and the upper end of the valence band of the gallium oxide semiconductor, and greater than 0. The semiconductor device according to claim 1.
6. The first insulating film is provided on the bottom surface and side walls of the trench formed in the gallium oxide layer. The second insulating film is provided on the bottom surface and side walls of the trench via the first insulating film. The gate electrode is further embedded in the trench via the first insulating film and the second insulating film, The third insulating film is an interlayer insulating film formed on the gate electrode. The semiconductor device according to claim 1.
7. A semiconductor device according to claim 1, comprising a main conversion circuit that converts and outputs input power, The system includes a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit, Power converter.