Image sensor and imaging device

Abstract

To improve circuit layout efficiency in a logic chip of an imaging device in which pixel chips and logic chips are alternately laminated, and to effectively utilize duplicated function circuits.SOLUTION: An imaging device comprises a first signal processing circuit, a second signal processing circuit, and wiring. The first signal processing circuit comprises a first ramp signal generation circuit and a first AD conversion circuit. The second signal processing circuit comprises a second ramp signal generation circuit and a second AD conversion circuit. The wiring is used for connecting the first ramp signal generation circuit to the first and second AD conversion circuits and connecting the second ramp signal generation circuit to the first and second AD conversion circuits in such a manner that: the first ramp signal output from the first ramp signal generation circuit is supplied to the first and second AD conversion circuits; and the second ramp signal output from the second ramp signal generation circuit is supplied to the second and first AD conversion circuits.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0002] There is a technology of a stacked image sensor that forms a pixel chip of a CMOS image sensor by a backside process to improve the layout freedom of a pixel readout circuit, and by bonding it to a separately formed logic chip, the readout processing speed is improved. In recent years, in the logic chip of a stacked image sensor, the digital signal processing circuit has been made into multiple paths or a large-capacity memory has been mounted, and the processing performance of the stacked image sensor has greatly improved.

[0003] Also, in an imaging apparatus such as a digital camera, in order to pursue higher image quality imaging ability, the aperture of the photographing lens has been increased, and the development of a stacked image sensor in a so-called 35mm full-size CMOS image sensor has also become active as a CMOS image sensor.

[0004] On the other hand, in a semiconductor exposure apparatus responsible for manufacturing a stacked image sensor, due to the resolution range and resolution constraints of the mask pattern, in a large-area chip such as a full-size CMOS image sensor, the mask pattern cannot be exposed in a single exposure. And split exposure in two steps is essential. In particular, in the case of the logic chip of a full-size stacked CMOS image sensor, manufacturing using split exposure that prioritizes the resolution of exposure is required for high speed and low power consumption. Therefore, digital circuits and memories with the same specifications are formed on the left and right of the chip.

[0005] As a result, some functional circuits that could otherwise be used in common are formed redundantly on both the left and right sides of the chip, sometimes resulting in a redundant circuit configuration. Operating redundant circuits together is a waste of power. In light of these circumstances, Patent Document 1 provides control means for setting the functional circuits of the left and right chips formed by split exposure to either an enabled or disabled function. This eliminates power waste by enabling one and disabling the other for functions where it is sufficient for one to operate.

[0006] Furthermore, even if the left and right channels have identical functional circuits, differences in the characteristics of these circuits can cause mismatches in the analog signals processed between the left and right channels. For example, differences in the linearity characteristics of the left and right AD conversion circuits can cause shifts in the gradation of the digital image signals generated by these circuits, potentially leading to image noise. Therefore, it is desirable to share some of the functional circuits that can be used in common between the left and right digital circuits to avoid mismatches in the analog signals that occur between the left and right channels. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 6245474 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, while Patent Document 1 mentions enabling one side of an identical functional circuit and disabling the other, it does not mention any specific usage methods to avoid inconsistencies that arise when identical functional circuits are not shared between the left and right sides.

[0009] Furthermore, in chips created by segmented exposure, adding new circuit functions doubles the size of the circuitry within the chip. Therefore, redundant circuits can impair the efficiency of circuit placement within the chip and hinder the addition of new circuits, but the aforementioned prior art cannot solve this problem.

[0010] Furthermore, enabling one of the overlapping functional circuits in each segmented exposure area of ​​a stacked image sensor while disabling the other results in different functional operation on the left and right sides, making it difficult to equalize power consumption. In other words, differences in heat generation may occur in each segmented exposure area, potentially causing differences in the temperature-dependent characteristics (dark current noise) of the stacked pixel chips.

[0011] Therefore, the objective of the present invention is to improve the circuit layout efficiency within the logic chip and effectively utilize redundant functional circuits while maintaining the consistency of analog signals for each segmented exposure region of an image sensor in which pixel chips and logic chips are stacked on top of each other. Furthermore, the objective is to provide an image sensor that reduces power consumption and suppresses differences in heat generation for each segmented exposure region within the logic chip. [Means for solving the problem]

[0012] To achieve the above objective, the present invention provides an image sensor in which a pixel chip in which a plurality of unit pixels are arranged in a matrix and a logic chip in which a first signal processing circuit and a second signal processing circuit formed by segmented exposure are arranged are stacked on top of each other, wherein the first signal processing circuit comprises a first lamp signal generation circuit and a first AD conversion circuit, the second signal processing circuit comprises a second lamp signal generation circuit and a second AD conversion circuit, and the first lamp signal output from the first lamp signal generation circuit is supplied to the first AD conversion circuit and the second AD conversion circuit, and the wiring is connected so that the second lamp signal output from the second lamp signal generation circuit is supplied to the second AD conversion circuit and the first AD conversion circuit. [Effects of the Invention]

[0013] According to the present invention, while maintaining consistency of analog signals for each exposure area of ​​an image sensor in which pixel chips and logic chips are stacked on top of each other, it is possible to improve the circuit layout efficiency within the logic chip and effectively utilize overlapping functional circuits. [Brief explanation of the drawing]

[0014] [Figure 1] Block diagram of an imaging recording device. [Figure 2] Plan view of a pixel chip of a stacked image sensor. [Figure 3] Plan view of a logic chip of a stacked image sensor. [Figure 4] Overall configuration diagram of the inside of a stacked image sensor. [Figure 5] Circuit configuration diagram of a stacked image sensor in pixel units [Figure 6] ADC circuit configuration diagram in column units of a column signal processing section of a stacked image sensor [Figure 7] Shooting timing diagram of a stacked image sensor [Figure 8] Readout timing diagram of pixel signals of a stacked image sensor [Figure 9] Configuration block diagram of a column circuit in Example 1. [Figure 10] Operation explanatory diagram in Example 1. [Figure 11] Configuration block diagram of a column circuit in Example 2. [Figure 12] Operation explanatory diagram in Example 2. [Figure 13] Configuration block diagram of a column circuit in Example 3. [Figure 14] Configuration block diagram of a column circuit in Example 3. [Figure 15] Diagram showing temperature change when only one RAMP circuit is used in Example 3. [Figure 16] Diagram showing in-plane temperature distribution of an imaging device when only one RAMP circuit is used in Example 3. [Figure 17] Diagram showing temperature changes of two RAMP circuits when the two RAMP circuits are switched and used in an example. [Figure 18] Diagram showing temperature changes of two RAMP circuits when the two RAMP circuits are switched and used in an example.

Modes for Carrying Out the Invention

[0015] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0016] Below, we will first describe the general outline of the imaging device in the embodiment of the present invention with reference to Figures 1 to 7.

[0017] Figure 1 is a block diagram showing the configuration of the imaging device according to this embodiment. First, the configuration shown in Figure 1 will be described.

[0018] The photographic lens 110 is composed of multiple lens groups, such as a focus lens and a zoom lens, and an aperture mechanism. The lens control unit 111 controls the focus, zoom, and aperture of the photographic lens 110 based on the control by the system control circuit 180.

[0019] The stacked image sensor 120 is a CMOS sensor that generates an electric charge corresponding to the amount of incident light by photoelectric conversion, performs AD conversion, and then outputs a digital signal. In addition to reading out the signals from all pixels, it can also read out the charge by adding up the charges from specific pixels and by downsampling every other row or column.

[0020] The image signal output from the stacked image sensor 120 is taken up by an image processing circuit 130 that includes a dynamic range expansion circuit 131. The dynamic range expansion circuit 131 has the function of generating a dynamic range expanded image using high-exposure and low-exposure images that have been previously stored in the memory 140.

[0021] The image processing circuit 130 performs various signal processing, including gamma processing, color signal processing, and exposure compensation processing. It also performs image scaling processing, such as enlargement and reduction, associated with zoom operations, also known as electronic zoom processing. During this process, it writes and reads image signals to and from the memory 140. The output of the image processing circuit 130 can also be displayed on the LCD display 150.

[0022] Image data processed by the image processing circuit 130 is compressed via the image conversion circuit 160 and written to the memory card 170 for recording. The image conversion circuit 160 has the function of compressing the image data from the image processing circuit 130 and outputting it to the memory card 170, and the function of decompressing the image data read from the memory card 170 and outputting it to the image processing circuit 130. As a result, the data file of the captured still image is recorded on the memory card 170.

[0023] Furthermore, when recording moving images, the image signals processed sequentially by the signal processing unit 130 are compressed via the image conversion circuit 160, and the data files of the captured moving images are sequentially recorded on the memory card 170.

[0024] The system control circuit 180 uses the signals processed by the image processing circuit 130 to perform TTL (through-the-lens) autofocus (AF), automatic exposure (AE), and flash pre-flash (EF) processing. Regarding exposure conditions during image capture, the system control circuit 180 can calculate arbitrary conditions based on the results of the automatic exposure (AE) processing and conditions necessary for dynamic range expansion, and then issue control instructions to the lens control unit 111 and the image sensor drive circuit 121.

[0025] Furthermore, the control unit 190 is an operation unit for the photographer to input instructions to the imaging device, such as a shutter release button, a mode switching dial for still images and videos, and zoom operation, and the input content is notified to the system control circuit 180.

[0026] Figure 2 is a plan view of the substrate on which the pixel chips of the stacked image sensor 120 in an embodiment of the present invention are provided, and Figure 3 is a plan view of the substrate on which the logic chips of the stacked image sensor 120 are provided, mainly representing the image of the mounting layout. In the stacked image sensor 120, the pixel chips and logic chips are stacked on top of each other.

[0027] In Figure 2, the pixel chip body 200 consists of unit pixels 201 arranged in a matrix, a pixel signal transmission unit 202 that transmits pixel output signals to a logic chip described later, and a vertical drive signal transmission unit 203 that receives vertical drive signals from the logic chip described later. The pixel signal transmission unit 202 and the vertical drive signal transmission unit 203 are divided into a left pixel signal transmission unit 202-a and a right pixel signal transmission unit 202-b, and a left vertical drive signal transmission unit 203-a and a right vertical drive signal transmission unit 203-b.

[0028] In Figure 3, the logic chip body 300 consists of a column circuit section 301, a digital signal processing circuit 302, a repeater circuit 303, an output interface circuit 304, an ADC output data line 305, a RAMP signal generation circuit 306, and a RAMP signal supply line 307.

[0029] The silicon layer and most of the wiring layers of the logic chip body 300 are manufactured in a semiconductor exposure apparatus by split exposure in two stages, left half and right half. Therefore, using the same mask pattern, the left digital signal processing circuit 302-a and the right digital signal processing circuit 302-b are formed, separated by the dashed line in the center of the figure. Furthermore, the left RAMP signal generation circuit 306-a (first ramp signal generation circuit) and the right RAMP signal generation circuit 306-b (second ramp signal generation circuit) are formed.

[0030] Similarly, the column circuit section 301 is positioned above and below the digital signal processing circuit 302, but the left pixel signal transmission section 202-a and the right pixel signal transmission section 202-b are positioned symmetrically on the upper and lower edges of the pixel chip body 200 and the logic chip body 300. Therefore, the left column circuit sections 301-a1 and 301-a2, and the right column circuit sections 301-b1 and 301-b2 are grouped together.

[0031] Similarly, the repeater circuit 303 is responsible for repeating logic signal transmission between the digital signal processing circuit 302 and the output interface circuit 304, and is formed as the left repeater circuits 303-a1 and 303-a2, and the right repeater circuits 303-b1 and 303-b2. The output interface circuit 304 is also formed as the left first and second output interface circuits 304-a1 and 304-a2, and the right first and second output interface circuits 304-b1 and 304-b2, and is input through the repeater circuit 303. The output interface circuit 304 outputs the video output of the digital signal processing circuit 302 as, for example, a clock-embedded differential high-speed serial signal, as the first to fourth stacked sensor RAW output signals S100 to S103. The pixel signal transmission unit 202 is positioned on the same plane along the stacking direction of the pixel chip body 200 and the logic chip body 300, and supplies the pixel signal from the pixel chip body 200 to the column circuit unit 301.

[0032] In the column circuit section 301, the pixel signals are converted using AD conversion and supplied to the digital signal processing circuit 302, where the signal processing described later is performed. The digital signal processing circuit 302 also generates pixel control signals related to the vertical drive of the pixel chip body 200 and supplies them to the pixel chip body 200 from the left vertical drive signal transmission section 203-a and the right vertical drive signal transmission section 203-b.

[0033] A portion of the wiring layer of the logic chip body 300 is exposed in a single exposure (hereinafter referred to as "batch exposure") by reducing the exposure resolution in the semiconductor exposure apparatus. The ADC output data line 305 and the RAMP signal supply line 307 are formed by batch exposure.

[0034] When the pixel signals transmitted via the left and right pixel signal transmission units 202-a and 202-b are converted into digital signals by the left and right column circuit units 301-a and 301-b, it is necessary to supply RAMP signals output from both the left and right RAMP signal generation circuits 306-a and 306-b. For this reason, the RAMP signal supply line 307 is configured to supply RAMP signals to the left and right column circuit units 301-a and 301-b from the left and right RAMP signal generation circuits 306-a and 306-b, respectively.

[0035] The stacked image sensor 120 can be made to perform more effectively by using the left and right RAMP signals separately with the above configuration, thereby expanding the signal dynamic range and speeding up AD conversion, as described later.

[0036] Figure 4 shows the overall circuit configuration and connection relationships of the stacked image sensor 120 according to this embodiment, and is a diagram for further explanation.

[0037] The stacked image sensor 120 shown in Figure 4 comprises a pixel chip 200 consisting of pixels 201, a horizontal column scanning circuit 401, a vertical row scanning circuit 402, a timing control circuit 403, and a column circuit section 301 formed from multiple column circuits 404 as shown in Figure 3, and a digital chip 300 consisting of left and right logic circuits 400-a and 400-b, including a RAMP signal generation circuit 306 and a repeater circuit 303.

[0038] Logic circuit 400-a (first signal processing circuit) is the circuit block located in the left region of the split exposure shown in Figure 3, and logic circuit 400-b (second signal processing circuit) is the circuit block located in the right region of the split exposure shown in Figure 3.

[0039] The pixels 201 that make up the pixel chip body 200 are arranged in a matrix in the horizontal and vertical directions. Multiple pixels 201 are assumed to have a 2x2 array of color filters, where odd-numbered rows are a repetition of R (red) filter and G (green) filter, and even-numbered rows are a repetition of G (green) filter and B (blue) filter.

[0040] The vertical row scanning circuit 402 selects one row at a time from the pixel array of the pixel chip 200 and drives and controls the reset and read operations of the selected pixel row. The vertical drive signal transmission unit 203 is connected in common to each pixel row and transmits the row-by-row drive control signal group 405 from the vertical row scanning circuit 402, which will be described later. The vertical drive signal transmission unit 203 is connected in common to each pixel column, and the pixel signals of the row selected by the vertical drive signal line are read out to the pixel signal transmission unit 202 as corresponding vertical signal lines 406.

[0041] Each column circuit 404 is provided for each corresponding vertical signal line 406, and performs the signal processing described below on each pixel signal in a row that is transmitted through the vertical signal line. The horizontal column scanning circuit 401 selects each column of column circuits 404 via the column selection lines 406 to which it is connected. The pixel signals 407 digitized by the column circuits 404 are then subjected to predetermined signal processing by the digital signal processing circuits 302-a1, 302-a2, 302-b1, and 302-b2, respectively.

[0042] These signals are then output as the first to fourth stacked sensor RAW output signals S100 to S103, respectively, via the repeater circuit 303 and the output interface circuit 304. The RAW output signals S100 to S103 output from the stacked image sensor 120 are output to the image processing circuit 130 in the form of digitized row-by-row pixel signals as shown in Figure 1.

[0043] The timing control circuit 403 outputs various clock signals and control signals necessary for the operation of each part of the stacked image sensor 120, based on control signals from the system control circuit 180. Here, control lines 410 to 413 transmit clock signals and control signals from the timing control circuit 403 to the horizontal column signal processing circuit 401, the vertical row scanning circuit 402 and column circuit 404, and the RAMP signal generation circuit 306, respectively. Control line 414 transmits control signals such as column selection from the horizontal column scanning circuit 401 to the column circuit 404.

[0044] Figure 5 shows the circuit configuration of pixel 201 in the pixel chip 200. The pixel 201 enclosed by the dotted line represents one of the pixels that make up the pixel chip 200. Pixel 201 is connected to other circuits by a drive control signal group 405 and a vertical signal line 406.

[0045] The vertical signal line 406 is connected to the load circuit and the column circuit 404, and is also connected to the vertical pixel column in common, outputting the pixel signal.

[0046] The drive control signal group 405 is connected to the vertical row scanning circuit 402 via the vertical drive signal transmission unit 203, and is also connected to all pixels in a horizontal row, allowing for simultaneous control of pixels in a horizontal row, thereby enabling reset and signal readout. Furthermore, the drive control signal group 405 shown in Figure 4 consists of a transfer control line pTX, a reset control line pRS, and a vertical selection line pSEL, which will be described later.

[0047] The photoelectric conversion element PD is a photodiode that converts light into electric charge and stores the converted charge. The P side of the PN junction is grounded, and the N side is connected to the source of the transfer transistor (transfer switch) TX. The gate of the transfer transistor (transfer switch) TX is connected to the transfer control line pTX, and the drain is connected to the FD capacitor CFD, controlling the transfer of charge from the photoelectric conversion element PD to the FD capacitor CFD.

[0048] Here, FD stands for floating diffusion layer, which has a capacitor capacitance capable of injecting a certain amount of charge. This capacitance is called the FD capacitance. The FD capacitance CFD is grounded on one end and accumulates charge when converting the charge transferred from the photoelectric conversion element PD into a voltage. At this time, the connection point between the drain of the transfer transistor (transfer switch) TX and the other end of the FD capacitance CFD will be called the FD node in the FD section.

[0049] The reset transistor (reset switch) RS has its gate connected to the reset control line pRS, its drain connected to the power supply voltage Vdd, and its source connected to the FD capacitance CFD. By turning the reset transistor (reset switch) RS ON, the potential of the FD node can be reset to the power supply voltage Vdd. When the reset transistor (reset switch) RS is OFF, the charge transferred from the photoelectric conversion element PD in the FD capacitance CFD is converted into a voltage.

[0050] The drive transistor (amplifier) ​​Tdrv is a transistor that constitutes the in-pixel amplifier. Its gate is connected to the FD capacitance CFD, its drain is connected to the power supply voltage Vdd, and its source is connected to the drain of the selector transistor (selector switch) SEL. It outputs a voltage corresponding to the voltage of the FD capacitance CFD. The selector transistor (selector switch) SEL has its gate connected to the vertical selector line pSEL and its source connected to the vertical signal line 406. It outputs the output of the drive transistor Tdrv to the vertical signal line 406 as the output signal of the pixel 201.

[0051] The load transistor Tlod in the load circuit provided for each vertical signal line has its source and gate grounded, and its drain connected to the vertical signal line 406. Together with the drive transistor Tdrv of the pixel 201 in the column connected by the vertical signal line 406, it forms a source follower circuit that acts as an in-pixel amplifier. Normally, when outputting the signal from pixel 201, the load transistor Tlod is operated as a gate-grounded constant current source. In this embodiment, transistors other than the drive transistor Tdrv and the load transistor Tlod act as switches, conducting (ON) when the control line connected to the gate is High and disconnecting (OFF) when it is Low.

[0052] Figure 6 shows the circuit configuration of the AD conversion circuit 600 in the column circuit 404 of the stacked image sensor 120 according to this embodiment. The AD conversion circuit 600 shown in Figure 6 includes a comparator 601, a counter circuit 602, a latch circuit 603, and an arithmetic circuit 604.

[0053] Comparator 601 is a comparator that connects the ramp wave signal line Vrmp and the pixel signal (Vsig) output from the vertical signal line 406 as two inputs and outputs the comparison result. For example, when the relative magnitudes of the two input signals are reversed, the output signal changes from High to Low level, thereby outputting the comparison result.

[0054] Here, the ramp wave output by the timing control circuit 403 to the ramp wave signal line Vrmp is a triangular wave that gradually changes from an initial voltage. Furthermore, its amplitude should have sufficient margin over the signal amplitude of the pixel signal (Vsig) input to the comparator 601. When the gradually changing ramp wave intersects with the pixel signal, the comparator 601 outputs the comparison result.

[0055] The counter circuit 602 is connected to the counter control line pCNT and operates the counter based on the clock supplied from the counter control line pCNT. At this time, the counter circuit 602 starts counting in accordance with the start of the ramp wave, receives the comparison result signal from the comparator 601 and outputs the count value at that time. This count value is a digitized signal of the pixel signal received via the vertical signal line 406.

[0056] The latch circuit 603 is connected to the latch control line pLTC and temporarily holds the count value output by the counter circuit 602, and outputs the held count value through control via the latch control line pLTC. The arithmetic circuit 604 is connected to the arithmetic control line pCAL and stores the count value output by the latch circuit 603 as a digital signal of the pixel through control via the arithmetic control line pCAL.

[0057] Furthermore, the arithmetic circuit 604 incorporates the functionality of a CDS circuit and removes reset noise generated during reset from the digital signal of the pixel signal by subtracting the reset signal from the latched pixel signal. The arithmetic circuit 604 also outputs the stored digital signal of the pixel to the digital output line DSig via control through the corresponding selection line pH.

[0058] As described above, the AD conversion circuit 600 shown in Figure 6 is configured using a comparator 601, a counter circuit 602, a latch circuit 603, and a ramp wave signal line Vrmp.

[0059] Here, the control lines 412 from the timing control circuit 403 are indicated by the counter control line pCNT, the latch control line pLTC, and the calculation control line pCAL. The output signal from the RAMP signal generation circuit 306 is indicated by the ramp wave signal line Vrmp. The column selection line 414 from the horizontal column scanning circuit 401 is indicated by the selection line pH. The output line 407 connected to and supplied to the digital signal processing circuit 302 is indicated by the digital output line DSig. The above constitutes the basic configuration of the imaging device in this embodiment.

[0060] Next, we will explain the basic operation of the imaging device described above. Figure 7 is a timing chart showing the imaging operation of the imaging device.

[0061] In Figure 7, the frame synchronization signal FSync is a synchronization signal for driving the stacked image sensor 120, which becomes active on the falling edge and performs a predetermined operation for each frame. In this embodiment, the equally spaced signals indicated by timings s01, s04, s08, s12, and s16 are the frame synchronization signals.

[0062] Furthermore, the vertical direction simplifies the operation timing from the first row to the last row when controlling the pixel chips 200 of the stacked image sensor 120 row by row. For example, timings s01 to s03 indicate the operation of reading out the pixel signals row by row.

[0063] Next, at timings s02 to s05, the exposure is initiated by resetting the charge of the photoelectric conversion element PD for each row. The lines shown in thick lines represent the reset timing for each row. Then, at timings s04 to s07, the exposure ends and the pixel signal is read out by reading the charge of the photoelectric conversion element PD for each row. This completes the acquisition of the signal of the subject image.

[0064] Similarly, in the operations starting at timings s06 and s10, exposure is initiated by resetting the charge of the photoelectric conversion element PD. Then, in the operations starting at the corresponding timings s08 and s12, exposure is terminated and the pixel signal is read out by reading the charge of the photoelectric conversion element PD. In this way, continuous shooting is possible by controlling the exposure and reading out the pixel signal for each frame.

[0065] Next, the readout operation of the image sensor's pixel 201 will be explained with reference to Figure 8. Figure 8 is a timing chart showing the pixel operation of the stacked image sensor 120, and shows the operation timing of the transfer control line pTX, reset control line pRS, and vertical selection line pSEL, which are the drive control signal group 405 that control the pixels.

[0066] In Figure 8, the line synchronization signal LSync is a synchronization signal for driving the stacked image sensor 120. It becomes active on the falling edge and executes a predetermined pixel operation for each line. That is, within the frame synchronization signal period, the line synchronization signal LSync controls the pixel operation timing of the pixels 201 from the first row to the last row, row by row.

[0067] Figure 8(a) shows a representative timing for one line in the line-by-line reset operation starting from timings s02, s06, and s10 in Figure 5, where the charge of the photoelectric conversion element PD is reset. Following the line synchronization signal LSync, all of the drive control signals in the group 405 except the vertical selection line pSEL are turned ON, resetting the photoelectric conversion element PD, FD capacitance CFD, and power supply voltage Vdd.

[0068] Next, exposure is started by turning OFF the transfer transistor (transfer switch) TX. Subsequently, the reset of the FD capacitance CFD is ended by turning OFF the reset transistor RS. Figures 8(b) to (d) show representative timings for one line in which the charge readout operation of the photoelectric conversion element PD is performed during the row-by-row pixel signal readout operation starting from timings s04, s08, and s12 in Figure 5.

[0069] In Figure 8(b) and subsequent steps, the read operation begins. First, the FD capacitance reset operation is performed. Initially, with the column gain switching control line pGAIN remaining at a low level, the selection transistor SEL is turned ON following the line synchronization signal LSync, setting the pixel signal to be output to the vertical signal line 231. Simultaneously, the reset transistor RS is turned ON to reset the FD capacitance CFD. At this time, the transfer transistor TX remains OFF, so the photoelectric conversion element PD maintains its charge. Then, the reset transistor RS is turned OFF, ending the reset of the FD capacitance CFD.

[0070] Next, in Figure 8(c), the operation to transfer the charge from the photoelectric conversion element PD to the FD section is performed. That is, by turning on the transfer transistor TX, the signal charge is transferred from the photoelectric conversion element PD to the FD summation capacitor CFDadd in the FD section. After the transfer of the signal charge is complete, the transfer transistor TX is turned off.

[0071] Next, in Figure 8(d), the reset operation of the photoelectric conversion element PD and FD capacitance CFD is performed. That is, the transfer transistor TX and reset transistor RS are turned ON to reset the photoelectric conversion element PD and FD capacitance CFD. Then, the reset of the photoelectric conversion element PD and FD capacitance CFD is completed by turning OFF the transfer transistor TX and reset transistor RS in that order. Subsequently, the selection transistor SEL is turned OFF to disconnect the readable pixel and vertical signal line 406.

[0072] The above describes the readout operation of one line of pixel signals, initiated by the line synchronization signal LSync shown in Figure 8(b). Subsequently, the readout of the next row of pixel signals begins, synchronized with the next line synchronization signal LSync shown in Figure 8(d).

[0073] At this time, in parallel with the readout operation of the pixel signal of the next row, the horizontal column scanning circuit 401 selects the column circuits 404 column by column via the column selection lines 412 to which they are connected. Then, the pixel signals digitized by the column circuits 404 are controlled to be output to the outside of the stacked image sensor via the digital signal processing circuit 302, the repeater circuit 303, and the output interface circuit 304.

[0074] Subsequently, the timing operations shown in Figures 8(b) to (d) are repeated a predetermined number of times to control the exposure and read out the image signal for one frame.

[0075] (Example 1) Next, with reference to Figures 9 and 10, the signal dynamic range expansion method and operation in Example 1 will be described. Figure 9 is a circuit diagram illustrating the connection configuration between pixel 201 and column circuit 404.

[0076] The pixel signals of odd-numbered rows output from a single pixel 201 in the pixel chip 200 via the vertical signal line 406 are supplied to logic circuit 400-a, and similarly, the pixel signals of even-numbered rows are supplied to logic circuit 400-b.

[0077] Furthermore, in logic circuit 400-a, the dashed box shows the circuit configuration of one column of column circuit 404, and it is equipped with two AD conversion circuits 600-a and 600-b. The internal configuration of each AD conversion circuit is equivalent to that of the aforementioned AD conversion circuit 600 shown in Figure 6. The AD conversion circuits 600-a and 600-b are supplied with pixel signals of odd-numbered columns as analog signals. In addition, the AD conversion circuit 600-a is supplied with the ramp wave signal Vrmp-a output from the RAMP signal generation circuit 306-a as a reference signal. Similarly, the AD conversion circuit 600-b is supplied with the ramp wave signal Vrmp-b output from the RAMP signal generation circuit 306-b.

[0078] Then, the AD conversion circuits 600-a and 600-b output the pixel signals, which have been AD converted by referring to the ramp wave signals Vrmp-a and Vrmp-b, as digital signals 407-a and 407-b.

[0079] Furthermore, in logic circuit 400-b, the dashed box shows the circuit configuration of one column of column circuit 404, which is composed of two AD conversion circuits 600-a and 600-b. The AD conversion circuits 600-a and 600-b are supplied with the pixel signals of even-numbered columns as analog signals. In addition, AD conversion circuit 600-a is supplied with the ramp wave signal Vrmp-a output from RAMP signal generation circuit 306-a as a reference signal. Similarly, AD conversion circuit 600-b is supplied with the ramp wave signal Vrmp-b output from RAMP signal generation circuit 306-b.

[0080] Then, the AD conversion circuits 600-a and 600-b output the pixel signals, which have been AD converted by referring to the ramp wave signals Vrmp-a and Vrmp-b, as digital signals 407-a and 407-b.

[0081] Based on the above configuration, the signal dynamic range expansion operation will now be explained. Figure 10 is a timing chart showing the readout operation of pixel signals in the column circuit 404 of the stacked image sensor 120. The V direction represents the potential of each signal, and the t direction represents the passage of time.

[0082] First, during the tr1 period, an operation is performed to initialize the column circuit 404. As part of the initial setup, for example, the input signals of the AD conversion circuits 600-a and 600-b are clamped.

[0083] Next, during the tt1 period, the FD capacitance CFD is reset. The timing of the pixel operation during the reset is explained in Figure 8(b). At this time, the tt1 period is the readout period of the reset signal after the FD capacitance CFD has been reset and the reset transistor RS has been turned OFF, and the signal stabilization period. Then, the reset signal Vn is input to the AD conversion circuits 600-a and 600-b in the column circuit 404 via the vertical signal line 406.

[0084] The reset signal Vn is compared with the ramp wave signal Vrmp-nL generated by the RAMP signal generation circuit 306-a during the tr2 period. Then, the comparator 601 in the AD conversion circuit 600 inverts, and the data is confirmed by the latch circuit 603, storing the count value cnL for the tnL period in the arithmetic circuit 604. This count value cnL becomes the low-gain digital reset signal.

[0085] Furthermore, the reset signal Vn is compared with the ramp wave signal Vrmp-nH generated by the RAMP signal generation circuit 306-b during the tr3 period. Then, the comparator 601 in the AD conversion circuit 600 inverts, and the data is confirmed by the latch circuit 603, storing the count value cnH for the tnL period in the arithmetic circuit 604. This count value cnH becomes the high-gain digital reset signal.

[0086] Next, the readout operation of the pixel signals of the stacked image sensor 120 is moved to the tt2 period. During the tt2 period, charge-voltage conversion is performed by the FD capacitance CFD. The charge of the photoelectric conversion element PD is transferred to the FD capacitance CFD of the FD section. At this time, the tt2 period is the charge transfer period from the photoelectric conversion element PD to the FD addition capacitance CFD of the FD section and the signal stabilization period.

[0087] Then, the pixel signal Vsig, input to the AD conversion circuit 600-a in the column circuit 404 via the vertical signal line 406, is compared with the ramp wave signal Vrmp-sL generated by the RAMP signal generation circuit 306-a during the tt4 period. The comparator 601 in the AD conversion circuit 600 then inverts, and the data is finalized by the latch circuit 603, storing the count value csL for the tsL period in the arithmetic circuit 604. This count value csL becomes the low-gain digital pixel signal.

[0088] Furthermore, the pixel signal Vsig input to the AD conversion circuit 600-b in the column circuit 404 is compared with the ramp wave signal Vrmp-sH generated by the RAMP signal generation circuit 306-b during the tr5 period. Then, the comparator 601 in the AD conversion circuit 600 inverts, and the data is finalized by the latch circuit 603, storing the count value csH for the tsL period in the arithmetic circuit 604. This count value csH becomes the high-gain digital pixel signal.

[0089] Then, in the arithmetic circuit 604 within the AD conversion circuit 600, reset noise generated during reset is removed from the pixel signal csH by subtracting the reset signal cnH from the latched pixel signal csH.

[0090] Furthermore, the slopes of the ramp wave signals Vrmp-nL and Vrmp-sL generated by the RAMP signal generation circuit 306-a are set to four times the slope of the ramp wave signals Vrmp-nH and Vrmp-sH generated by the RAMP signal generation circuit 306-b. As a result, the period during which comparator 601 inverts in the low-gain pixel signal after noise reduction is shortened to one-quarter, and the gain becomes one-quarter compared to the high-gain pixel signal after noise reduction.

[0091] Therefore, in the arithmetic circuit 604 within the AD conversion circuit 600, the pixel signal at low gain after noise removal is multiplied by four through digital calculation. The low-gain pixel signal is then converted to a digital signal value equivalent to a high-gain pixel signal, that is, a low-gain signal value equivalent to a high-gain signal, and this value is stored in the arithmetic circuit 604.

[0092] Furthermore, in the arithmetic circuit 604 within the AD conversion circuit 600, reset noise generated during reset is removed from the pixel signal csH by subtracting the reset signal cnH from the latched pixel signal csH. Then, in the arithmetic circuit 604 within the AD conversion circuit 600, the high-gain pixel signal after noise removal is stored directly in the arithmetic circuit 604.

[0093] The above operations complete the AD conversion of both the low-gain and high-gain pixel signals.

[0094] Next, during the tt3 period, the photoelectric conversion element PD and FD capacitance CFD are reset, ending the operation of one line that performs pixel signal readout. At this time, in parallel with the readout operation of the next row of pixel signals, the horizontal column scanning circuit 401 selects the column circuits 404 column by column via the column selection lines 412. Then, the stored digitized low-gain and high-gain pixel signals are controlled to be output to the outside of the stacked image sensor via the digital signal processing circuit 302, the repeater circuit 303, and the output interface circuit 304.

[0095] Through the above operations, both the digital signal value of the high-gain pixel signal and the digital signal value of the low-gain pixel signal equivalent to the high-gain signal are stored in the arithmetic circuit 604 of the column circuit 404 as signal values ​​for each pixel. Then, the dynamic range expansion circuit 131 in the image processing circuit 130 located downstream of the stacked image sensor 120 performs the following HDR processing.

[0096] In other words, if the digital signal value of the high-gain pixel signal is smaller than the digital signal value corresponding to the amplitude of the high-gain ramp wave, the high-gain digital signal value is stored in the arithmetic circuit (not shown) as the signal value of the corresponding pixel.

[0097] If the digital signal value of a high-gain pixel signal corresponds to the digital signal value of a high-gain ramp wave, the digital signal value of a low-gain pixel signal equivalent to the high-gain signal is stored in the calculation circuit (not shown) as the signal value of the corresponding pixel.

[0098] Furthermore, depending on the shooting conditions, for example, if the entire image signal is overexposed, the high-gain pixel signal will reach a saturation level and will not be necessary for image formation. For this reason, the operation of the AD conversion circuit 600-b, which outputs the high-gain pixel signal, and the RAMP signal generation circuit 306-b, which outputs a high-gain ramp wave, may be stopped by a power suppression means (not shown). Doing so can also suppress the power consumption of the stacked image sensor.

[0099] As explained above, by using two RAMP circuits and outputting both low-gain and high-gain pixel signals obtained by AD conversion using two types of ramp waves with different slopes, the dynamic range of the image signal can be expanded by subsequent HDR processing.

[0100] (Example 2) Next, with reference to Figures 11 and 12, the AD conversion method and conversion operation of the pixel signal in Embodiment 2 will be explained. Figure 11 is a circuit diagram illustrating the connection configuration between pixel 201 and column circuit 404.

[0101] The pixel signals of odd-numbered rows output from a single pixel 201 in the pixel chip 200 via the vertical signal line 406 are supplied to logic circuit 400-a, and similarly, the pixel signals of even-numbered rows are supplied to logic circuit 400-b.

[0102] Furthermore, in logic circuit 400-a, the dashed box shows the circuit configuration of one column of column circuit 404, which consists of a comparator 701, an analog signal switch 703, and one AD conversion circuit 600. The internal configuration of the AD conversion circuit is equivalent to that of the aforementioned AD conversion circuit 600 shown in Figure 6. Pixel signals of odd-numbered columns are supplied as analog signals to one input of the AD conversion circuit 600 and comparator 701, while a comparison voltage Vcp is input to the other input of comparator 701. The output of comparator 701 is connected to the switching control terminal of analog signal switch 703.

[0103] One input of the analog signal switch 703 is supplied with the ramp wave signal Vrmp-a output from the RAMP signal generation circuit 306-a, and the other input is supplied with the ramp wave signal Vrmp-b output from the RAMP signal generation circuit 306-b.

[0104] The output of the selectively switchable analog signal switch 703 is then supplied to the AD conversion circuit 600 as a reference signal. The pixel signals of the odd-numbered rows, which are input as analog signals, are compared with one of the reference signals selected from ramp wave signals Vrmp-a and Vrmp-b, and the AD-converted pixel signals are output from the AD conversion circuit 600 as a digital signal 407.

[0105] Furthermore, in logic circuit 400-b, the dashed box shows the circuit configuration of one column circuit 404, which consists of a comparator 701, an analog signal switch 703, and one AD conversion circuit 600. The internal configuration of the AD conversion circuit is the same as that of the AD conversion circuit 600 shown in Figure 6. Pixel signals from even-numbered columns are supplied as analog signals to one input of the AD conversion circuit 600 and comparator 701, while a comparison voltage Vcp is input to the other input of comparator 701. The output of comparator 701 is connected to the switching control terminal of the analog signal switch 703.

[0106] One input of the analog signal switch 703 is supplied with the ramp wave signal Vrmp-a output from the RAMP signal generation circuit 306-a, and the other input is supplied with the ramp wave signal Vrmp-b output from the RAMP signal generation circuit 306-b.

[0107] The output of the selectively switchable analog signal switch 703 is then supplied as a reference signal to the AD conversion circuit 600. The pixel signals of the even-numbered rows, which are input as analog signals, are compared with one of the reference signals selected from ramp wave signal lines Vrmp-a and Vrmp-b, and the AD-converted pixel signals are output as digital signals 407 from the AD conversion circuit 600.

[0108] Based on the above configuration, the AD conversion operation will now be explained. Figure 12 is a timing chart showing the readout operation of pixel signals in the column circuit 404 of the stacked image sensor 120. The V direction represents the potential of each signal, and the t direction represents the passage of time.

[0109] First, during the tr1 period, an operation is performed to initialize the column circuit 404. As part of the initial setup, for example, the input signal of the AD conversion circuit 600 is clamped.

[0110] Next, during the tt1 period, the FD capacitance CFD is reset. The timing of the pixel operation during the reset is as explained in Figure 8(b). At this time, the tt1 period is the readout period of the reset signal after the FD capacitance CFD has been reset and the reset transistor RS has been turned OFF, and the signal stabilization period. Then, the reset signal Vn is input to the AD conversion circuit 600 in the column circuit 404 via the vertical signal line 406.

[0111] The reset signal Vn is masked during the period when the ramp wave signal Vrmp-nH, generated by the RAMP signal generation circuit 306-b during the tr2 period, is generated, and the switching control of the analog signal switch 703 is then fixed to the ramp wave signal Vrmp-nH generated by the RAMP signal generation circuit 306-b.

[0112] The reset signal Vn is compared with the ramp wave signal Vrmp-nH generated by the RAMP signal generation circuit 306-b during the tr2 period. Then, the comparator 601 in the AD conversion circuit 600 inverts, and the data is confirmed by the latch circuit 603, and the count value cnH for the tnL period is stored in the arithmetic circuit 604. This count value cnH becomes the high-gain digital reset signal. At the same time, a value cnL, which corresponds to the count value of the digital reset signal at low gain, is calculated by digitally dividing the count value cnH of the digital reset signal by 1 / 4 and stored in the arithmetic circuit 604.

[0113] Next, the readout operation of the pixel signals of the stacked image sensor 120 is moved to the tt2 period. During the tt2 period, charge-voltage conversion is performed by the FD capacitance CFD. The charge of the photoelectric conversion element PD is transferred to the FD capacitance CFD of the FD section. At this time, the tt2 period is the charge transfer period from the photoelectric conversion element PD to the FD addition capacitance CFD of the FD section and the signal stabilization period.

[0114] Then, during the tt3 period, the pixel signal Vs input to the comparator 701 in the column amplifier 404 via the vertical signal line 406 is compared with the comparison voltage Vcp. Based on the comparison result, if the brightness of the pixel signal is high, i.e., Vs ≥ Vcp, the analog signal switch 703 selects the ramp wave signal Vrmp-sL generated by the RAMP signal generation circuit 306-a.

[0115] In this case, the pixel signal Vs, which is also input to the AD conversion circuit 600 within the column amplifier 404, is compared with the ramp wave signal Vrmp-sL generated by the RAMP signal generation circuit 306-a. Then, the comparator 601 within the AD conversion circuit 600 inverts, and the data is finalized by the latch circuit 603, storing the count value csL for the tsL period in the arithmetic circuit 604. This count value csL becomes the low-gain digital pixel signal.

[0116] Then, in the arithmetic circuit 604 within the AD conversion circuit 600, the reset noise generated at the time of reset is removed from the pixel signal csL by subtracting the reset signal cnL from the latched pixel signal csL.

[0117] On the other hand, when the brightness of the pixel signal is low, that is, when Vs < Vcp, according to the comparison result, in the analog signal switch 703, the ramp wave signal Vrmp-sH generated by the RAMP signal generation circuit 306-b is selected.

[0118] In this case, the pixel signal Vs input to the AD conversion circuit 600 within the column amplifier 404 is also compared with the ramp wave signal Vrmp-sH generated by the RAMP signal generation circuit 306-b. Then, when the comparator 601 within the AD conversion circuit 600 is inverted, the data is determined by the latch circuit 603, and the count value csH during the tsH period is stored in the arithmetic circuit 604. This count value csH becomes a high-gain digital pixel signal.

[0119] Then, in the arithmetic circuit 604 within the AD conversion circuit 600, the reset noise generated at the time of reset is removed from the pixel signal csH by subtracting the reset signal cnH from the latched pixel signal csH.

[0120] Note that the slopes of the ramp wave signals Vrmp-nL and Vrmp-sL generated by the RAMP signal generation circuit 306-a are set to four times the slopes of the ramp wave signals Vrmp-nH and Vrmp-sH generated by the RAMP signal generation circuit 306-b. And in this case, the comparison voltage Vcp is usually set to the full-range voltage of the ramp wave signal Vrmp-sL. Thereby, the pixel signal at the time of low gain after noise removal has a gain that is one-fourth that of the pixel signal at the time of high gain after noise removal as well, because the period during which the comparator 601 is inverted is shortened to one-fourth.

[0121] Therefore, in the arithmetic circuit 604 within the AD conversion circuit 600, the pixel signal at low gain after noise removal is multiplied by four through digital calculation. The low-gain pixel signal is then converted to a digital signal value equivalent to a high-gain pixel signal, that is, a low-gain signal value equivalent to a high-gain signal, and this value is stored in the arithmetic circuit 604.

[0122] Furthermore, in the arithmetic circuit 604 within the AD conversion circuit 600, reset noise generated during reset is removed from the pixel signal csH by subtracting the reset signal cnH from the latched pixel signal csH. Then, in the arithmetic circuit 604 within the AD conversion circuit 600, the high-gain pixel signal after noise removal is stored directly in the arithmetic circuit 604.

[0123] Through the above operations, AD conversion using either the low-gain pixel signal or the high-gain pixel signal is completed.

[0124] Next, during the tt4 period, the photoelectric conversion element PD and FD capacitance CFD are reset, ending the operation of one line that performs pixel signal readout. At this time, in parallel with the readout operation of the next row of pixel signals, the horizontal column scanning circuit 401 selects the column circuits 404 column by column via the column selection lines 412. The stored digitized low-gain and high-gain pixel signals are controlled to be output to the outside of the stacked image sensor via the digital signal processing circuit 302, repeater circuit 303, and output interface circuit 304.

[0125] Through the above operations, either the digital signal value of the high-gain pixel signal or the digital signal value of the low-gain pixel signal equivalent to the high-gain signal is stored in the arithmetic circuit 604 of the column circuit 404 as the signal value for each pixel.

[0126] As explained above, during the AD conversion of the pixel signal, two RAMP circuits are used to prepare two types of ramp waves with different slopes. Then, when the brightness of the pixel signal Vs is high, switching to the ramp wave signal Vrmp-sH with a larger slope reduces the AD conversion time to one-quarter compared to the ramp wave signal Vrmp-sL with a smaller slope.

[0127] (Example 3) Next, with reference to Figures 13 to 17, the AD conversion method and conversion operation of the pixel signal in Embodiment 3 will be explained. Figures 13 and 14 are circuit diagrams illustrating the connection configuration between the pixel 201 and the logic circuit 400.

[0128] In Figure 13, either ramp wave signal line Vrmp-a or ramp wave signal line Vrmp-b is selected by analog signal switchers 703-a and 703-b, while in Figure 14, it is selected by analog signal switcher 703-x.

[0129] Furthermore, the ramp wave signal Vrmp-a from the RAMP signal generation circuit 306-a can be used in both the logic circuit 400-a and the logic circuit 400-b. Similarly, the ramp wave signal Vrmp-b from the RAMP signal generation circuit 306-b can be used in both the logic circuit 400-a and the logic circuit 400-b.

[0130] Furthermore, the time variation (slope) of the voltages of ramp wave signals Vrmp-a and Vrmp-b are approximately equal. Then, the RAMP signal generation circuit 306-a or RAMP signal generation circuit 306-b that is not selected is controlled to either cut off the power supply or switch to power-saving mode.

[0131] First, in Figure 13, the ramp wave signal Vrmp-a is supplied to both logic circuits 400-a and 400-b. The pixel signal 406 is then supplied to the AD conversion circuit 600, which is input to the AD conversion circuit 600, via analog signal switches 703-a and 703-b, which are provided for each AD conversion circuit 600.

[0132] Similarly, the ramp wave signal Vrmp-b is also supplied to both logic circuits 400-a and 400-b. The pixel signal 406 is then supplied to the AD conversion circuit 600, which is input to the AD conversion circuit 600, via analog signal switches 703-a and 703-b, which are provided for each AD conversion circuit 600.

[0133] As described above, the analog signal switches 703-a and 703-b, provided for each AD conversion circuit 600, are capable of exclusively supplying ramp wave signals Vrmp-a and Vrmp-b. In Figure 13, the analog signal switches 703-a and 703-b are linked as shown by the dashed lines, and are configured to simultaneously select either ramp wave signal Vrmp-a or ramp wave signal Vrmp-b.

[0134] Next, in Figure 14, all connections to which the ramp wave signal lines Vrmp-a or Vrmp-b of all ADC circuits 600 should be input are connected are common to both "logic circuit 400-a and logic circuit 400-b". Furthermore, they are connected to the analog signal switch 703-x.

[0135] In Figure 14, the analog signal switch 703-x is capable of exclusively supplying ramp wave signals Vrmp-a and Vrmp-b. The analog signal switch 703-x is configured to select either ramp wave signal Vrmp-a or ramp wave signal Vrmp-b.

[0136] Next, we will explain the temperature changes when driving the RAMP signal generation circuit 306-b. Figure 15 shows the time change in temperature of the RAMP signal generation circuit 306-b when it is used continuously for video recording, etc. The specific temperature values ​​below are merely examples.

[0137] In Figure 15, the temperature is ambient (e.g., 25°C) at the start time T-0, and the temperature rises as imaging progresses. It reaches approximately 70°C at time T-1 and approximately 90°C at time T-2. Then, at time T-2, the power supply to the RAMP signal generation circuit 306-b is stopped. After time T-2, the temperature drops rapidly.

[0138] Here, within temperature range 1 up to 70°C, no effects of temperature rise are observed in the captured images, but within temperature range 2 exceeding 70°C, effects of temperature rise are observed in the captured images. Specifically, due to localized heat generation by the RAMP signal generation circuit 306-b, a phenomenon occurs where the part of the image corresponding to where the RAMP signal generation circuit 306-b is located appears as a white background.

[0139] Furthermore, if the temperature exceeds 90°C, the image sensor 120 itself may exceed its operating temperature range, so power supply to the RAMP signal generation circuit 306-b is stopped when the temperature reaches 90°C. Therefore, at time T-2, the shooting operation must be temporarily suspended. In addition, in order to prevent the image from being affected by the temperature rise, it is necessary to drive the RAMP signal generation circuit 306-b within the temperature range of 70°C or less.

[0140] Next, the in-plane temperature distribution of the logic chip 300 will be described. Note that both the RAMP signal generation circuit 306-a and the RAMP signal generation circuit 306-b have temperature measurement means (not shown) installed immediately next to them.

[0141] Figure 16 shows the temperature distribution in the plane of the logic chip 300 at time T-1 when video recording, etc., is performed using only the RAMP signal generation circuit 306-b continuously. Figure 16 shows the temperature distribution in the plane of the logic chip 300, more specifically, in the xy cross-section of the logic chip 300, at time T-1 in Figure 15. The specific temperature values ​​below are merely examples of locations.

[0142] In Figure 15, at time T-1, the RAMP signal generation circuit 306-b reaches approximately 70°C. Therefore, the temperature at the location of the RAMP signal generation circuit 306-b in the xy cross-section of the logic chip 300 is approximately 70°C. Here, the logic chip 300 dissipates heat as it is transferred within its plane, and the temperature decreases as it moves away from the location of the RAMP signal generation circuit 306-b.

[0143] Therefore, as shown in Figure 16, a temperature gradient is generated in the xy cross-section of the logic chip 300, with the temperature at the location of the RAMP signal generation circuit 306-a being approximately 60°C. Furthermore, when only the RAMP signal generation circuit 306-a is used, when the temperature at RAMP signal generation circuit 306-a reaches approximately 70°C, the temperature at the location of RAMP signal generation circuit 306-b is approximately 60°C.

[0144] Furthermore, the logic chip 300 and the pixel chip 200 are bonded together, and their temperature distributions within their plane are almost identical. Therefore, a localized temperature increase within the plane of the logic chip 300 directly translates to a localized temperature increase within the plane of the pixel chip 200, resulting in the image being affected by this temperature rise.

[0145] Next, we will describe the temperature changes of RAMP signal generation circuits 306-a and 306-b when they are used in a switched manner. Figure 17 shows the temperature changes of RAMP signal generation circuits 306-a and 306-b when they are used in a switched manner.

[0146] The specific temperature values ​​below are merely examples. Although not shown in the diagram, each of the RAMP signal generation circuits 306-a and 306-b has a temperature measurement device located near itself. Figure 17 shows the case where the RAMP signal generation circuits 306-a and 306-b are switched over when their respective temperatures reach approximately 70°C.

[0147] Figure 17 shows the temperature changes of RAMP signal generation circuits 306-a and 306-b, respectively. A solid line indicates the state when power is supplied, and a dashed line indicates the state when power is not supplied (or in power-saving mode).

[0148] Between times T-10 and T-11, power is supplied to the RAMP signal generation circuit 306-b, but not to the RAMP signal generation circuit 306-a. At time T-11, the RAMP signal generation circuit 306-b reaches approximately 70°C, while the RAMP signal generation circuit 306-a reaches approximately 60°C (as shown in Figure 16) due to heat transfer from the RAMP signal generation circuit 306-b.

[0149] At time T-11, the power supply to RAMP signal generation circuit 306-a and RAMP signal generation circuit 306-b is switched. In other words, from time T-11 to time T-12, power is not supplied to RAMP signal generation circuit 306-b, while power is supplied to RAMP signal generation circuit 306-a.

[0150] Therefore, between time T-11 and time T-12, the RAMP signal generation circuit 306-b rapidly decreases from 70°C, and then reaches 60°C due to heat transfer from RAMP signal generation circuit 306-a. Then, RAMP signal generation circuit 306-a rises from 60°C to 70°C due to its own heat generation.

[0151] Next, at time T-12, the power supply to RAMP signal generation circuit 306-a and RAMP signal generation circuit 306-b is switched. Note that the actual switching operation between RAMP signal generation circuit 306-a and RAMP signal generation circuit 306-b is performed during a period other than when A / D conversion is in operation, in order to avoid affecting A / D conversion.

[0152] In this way, by repeating the above switching operation when the temperature of each RAMP signal generation circuit 306-a and 306-b reaches 70°C, as shown in Figure 17, neither RAMP signal generation circuit 306-a nor 306-b will exceed 70°C in temperature range 1. This makes it possible to continue capturing images continuously without affecting the image quality due to temperature rise.

[0153] Next, Figure 18 shows the temperature changes of RAMP signal generation circuits 306-a and 306-b when they are switched between being used.

[0154] In the example in Figure 17, the RAMP signal generation circuit 306-a and RAMP signal generation circuit 306-b switched when their respective temperatures reached 70°C. However, in Figure 18, the switch is simply performed after a certain period of time has elapsed. The certain period is calculated in advance to determine the time interval during which the temperature will not reach 70°C, and the switch is performed when the temperature is predicted to be lower than 70°C with a margin of safety.

[0155] By repeating the above switching operation, as shown in Figure 18, neither the RAMP signal generation circuit 306-a nor the RAMP signal generation circuit 306-b will exceed 70°C in temperature range 1. This makes it possible to continue the shooting operation without affecting the captured image due to temperature rise.

[0156] Alternatively, the RAMP signal generation circuit 306-a and the RAMP signal generation circuit 306-b may be switched simply on a frame-by-frame basis (at least one frame at a time). The number of frames to switch is calculated in advance to determine the number of frames that will not reach 70°C, and the switch is made when the temperature is predicted to be lower than 70°C with a margin of safety. [Explanation of symbols]

[0157] 120 Stacked Image Sensors 200 pixel chip 300 logic chips 201 pixels 306 RAMP signal generation circuit 600 AD conversion circuit

Claims

1. In an image sensor in which a pixel chip in which multiple unit pixels are arranged in a matrix and a logic chip in which a first signal processing circuit and a second signal processing circuit formed by segmented exposure are arranged are stacked on top of each other, The first signal processing circuit comprises a first lamp signal generation circuit and a first AD conversion circuit. The second signal processing circuit comprises a second lamp signal generation circuit and a second AD conversion circuit. An image sensor characterized by having wiring connected such that a first lamp signal output from the first lamp signal generation circuit is supplied to the first AD conversion circuit and the second AD conversion circuit, and a second lamp signal output from the second lamp signal generation circuit is supplied to the second AD conversion circuit and the first AD conversion circuit.

2. The image sensor according to claim 1, further characterized by having a switching means for selectively switching between the first lamp signal and the second lamp signal and supplying them to the first AD conversion circuit and the second AD conversion circuit.

3. The image sensor according to claim 1, characterized in that the slope of the first lamp signal is different from the slope of the second lamp signal.

4. The image sensor according to claim 1, further comprising power suppression means for suppressing the power supplied to the first lamp signal generation circuit or the second lamp signal generation circuit.

5. The image sensor according to claim 2, further comprising a temperature measuring means, wherein the switching means switches between the first lamp signal and the second lamp signal when the temperature measured by the temperature measuring means rises to a predetermined temperature.

6. The image sensor according to claim 2, characterized in that the switching means switches between the first lamp signal and the second lamp signal at regular intervals.

7. The image sensor according to claim 2, characterized in that the switching means switches between the first lamp signal and the second lamp signal on a frame-by-frame basis.

8. An imaging apparatus comprising an image sensor as described in claim 1 and control means for controlling the image sensor.

Images