Photoelectric converter

Abstract

A photoelectric conversion device which has an APD provided to a semiconductor layer having a first surface and a second surface opposite the first surface, and also has a first wiring structure which contacts the second surface, said photoelectric conversion device being characterized in that: the APD has a first semiconductor region of a first conductive type which is provided to a first depth, and a second semiconductor region of a second conductive type which is provided to a second depth which is deeper relative to the second surface than is the first depth; a first pad for imparting a first voltage to the photoelectric conversion device is provided to the first wiring structure; an oxide film and a protective film layered on the oxide film are provided to the second surface of the semiconductor layer; and there is a section which satisfies dsio>(εsio / εprot)×dprot / 2, if the thickness of the oxide film is dsio, the thickness of the protective film is dprot, the dielectric constant of the oxide film is εsio, and the dielectric constant of the protective film is εprot.

Description

[Technical Field]

[0001] This invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] Patent Document 1 describes a single-photon avalanche photodiode (SPAD) having a protective film on the surface of a silicon substrate consisting of an oxide film, a nitride film, or a combination thereof. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0152807 [Overview of the project] [Problems that the invention aims to solve]

[0004] In SPADs, avalanche multiplication is induced by applying a strong electric field to a PN junction diode provided on a semiconductor substrate, and photon detection is performed. However, when the electric field applied to the PN junction diode becomes strong, hot carriers accelerated by the electric field are generated. In the structure described in Patent Document 1, there was a problem in that the potential changes due to the trapping of hot carriers near the cathode region, and the breakdown voltage changes over time.

[0005] This invention has been made in view of the above problems, and aims to reduce the change in breakdown voltage over time caused by the increase in hot carriers trapped near the cathode region over time. [Means for solving the problem]

[0006] One aspect of the present invention is a photoelectric conversion device having an avalanche diode disposed in a semiconductor layer having a first surface and a second surface facing the first surface, and a first wiring structure in contact with the second surface, wherein the avalanche diode includes a first semiconductor region of a first conductivity type disposed at a first depth, and a second semiconductor region of a second conductivity type disposed at a second depth deeper than the first depth with respect to the second surface. A third semiconductor region is provided between the first semiconductor region and the second semiconductor region, in contact with the first semiconductor region, It has The photoelectric conversion device further comprises a first wiring section electrically connected to the first semiconductor region and a second wiring section electrically connected to the second semiconductor region. A first pad for applying a first voltage to the photoelectric conversion device is provided in the first wiring structure, and an oxide film and a protective film laminated on the first wiring structure side of the oxide film are disposed on the second surface of the semiconductor layer. When the thickness of the oxide film is d sio , the thickness of the protective film is d prot , the relative permittivity of the oxide film is ε sio , and the relative permittivity of the protective film is ε prot , there is a portion that satisfies d sio >(ε sio / ε prot )×d prot / 2. Furthermore, in a plan view, the second wiring portion overlaps with at least a part of the third semiconductor region, but does not overlap with the first semiconductor region. This is a feature.

[0007] Another aspect of the present invention is a photoelectric conversion device having an avalanche diode disposed in a semiconductor layer having a first surface and a second surface facing the first surface, and a first wiring structure in contact with the second surface, wherein the avalanche diode includes a first semiconductor region of a first conductivity type disposed at a first depth, and a second semiconductor region of a second conductivity type disposed at a second depth deeper than the first depth with respect to the second surface. A third semiconductor region is provided between the first semiconductor region and the second semiconductor region, in contact with the first semiconductor region, It has The photoelectric conversion device further comprises a first wiring section electrically connected to the first semiconductor region and a second wiring section electrically connected to the second semiconductor region. A first pad for applying a first voltage to the photoelectric conversion device is provided in the first wiring structure, and an oxide film and a protective film laminated on the first wiring structure side of the oxide film are disposed on the second surface of the semiconductor layer. The oxide film is a silicon oxide film, the protective film is a silicon nitride film, and when the thickness of the oxide film is d sio , the thickness of the protective film is d prot , the relative permittivity of the oxide film is ε sio , and the relative permittivity of the protective film is ε prot , d sioSatisfying > 15 nm Furthermore, in a plan view, the second wiring portion overlaps with at least a part of the third semiconductor region, but does not overlap with the first semiconductor region. Characterized by this.

Effect of the Invention

[0008] According to the present invention, it is possible to reduce the change over time of the breakdown voltage due to the increase over time of hot carriers trapped in the vicinity of the cathode region.

Brief Description of the Drawings

[0009] [Figure 1] It is a schematic diagram of a photoelectric conversion device according to an embodiment. [Figure 2] It is a schematic diagram of a PD substrate of a photoelectric conversion device according to an embodiment. [Figure 3] It is a schematic diagram of a circuit board of a photoelectric conversion device according to an embodiment. [Figure 4] It is a configuration example of a pixel circuit of a photoelectric conversion device according to an embodiment. [Figure 5] It is a schematic diagram showing the driving of a pixel circuit of a photoelectric conversion device according to an embodiment. [Figure 6] It is a cross-sectional view of a photoelectric conversion element according to the first embodiment. [Figure 7A] It is a plan view of a photoelectric conversion element according to the first embodiment. [Figure 7B] It is a plan view of a photoelectric conversion element according to the first embodiment. [Figure 8] It is a potential diagram of a photoelectric conversion element according to the first embodiment. [Figure 9A] It is a comparative example of a photoelectric conversion element according to the first embodiment. [Figure 9B] It is a comparative example of a photoelectric conversion element according to the first embodiment. [Figure 10] It is an enlarged view of a protective film according to the first embodiment. [Figure 11] It is a cross-sectional view of a photoelectric conversion element according to the second embodiment. [Figure 12] It is a cross-sectional view of a photoelectric conversion element according to the third embodiment. [Figure 13A]This is a plan view of a photoelectric conversion element according to the third embodiment. [Figure 13B] This is a plan view of a photoelectric conversion element according to the third embodiment. [Figure 14] This is a plan view of a photoelectric conversion element according to the fourth embodiment. [Figure 15] This is a plan view of a photoelectric conversion element according to the fifth embodiment. [Figure 16] This is a plan view of a photoelectric conversion element according to the sixth embodiment. [Figure 17] This is a plan view of a photoelectric conversion element according to the seventh embodiment. [Figure 18] This is a plan view of a photoelectric conversion element according to the eighth embodiment. [Figure 19] This is a functional block diagram of the photoelectric conversion system according to the ninth embodiment. [Figure 20A] This is a functional block diagram of a photoelectric conversion system according to the tenth embodiment. [Figure 20B] This is a functional block diagram of a photoelectric conversion system according to the tenth embodiment. [Figure 21] This is a functional block diagram of the photoelectric conversion system according to the 11th embodiment. [Figure 22] This is a functional block diagram of a photoelectric conversion system according to the twelfth embodiment. [Figure 23A] This is a functional block diagram of the photoelectric conversion system according to the 13th embodiment. [Figure 23B] This is a functional block diagram of the photoelectric conversion system according to the 13th embodiment. [Modes for carrying out the invention]

[0010] The embodiments shown below are intended to embody the technical concept of the present invention and do not limit it. The size and positional relationships of the components shown in each drawing may be exaggerated for clarity of explanation. In the following description, identical components may be given the same number and their explanation may be omitted.

[0011] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, terms indicating specific directions or positions (e.g., "up," "down," "right," "left," and other terms including these terms) will be used as needed. The use of these terms is for the purpose of facilitating the understanding of embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0012] In this specification, a plan view refers to viewing a semiconductor layer from a direction perpendicular to the light incident surface. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. If the light incident surface of the semiconductor layer is rough when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer as viewed macroscopically.

[0013] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and the signal is taken from the cathode side. Therefore, the semiconductor region of the first conductivity type, which has majority carriers of the same polarity as the signal charge, is an N-type semiconductor region, and the semiconductor region of the second conductivity type, which has majority carriers of charges with a different polarity than the signal charge, is a P-type semiconductor region. Note that the present invention also applies when the cathode of the APD is set to a fixed potential and the signal is taken from the anode side. In this case, the semiconductor region of the first conductivity type, which has majority carriers of the same polarity as the signal charge, is a P-type semiconductor region, and the semiconductor region of the second conductivity type, which has majority carriers of charges with a different polarity than the signal charge, is an N-type semiconductor region. The following description will focus on the case where one node of the APD is set to a fixed potential, but the potentials of both nodes may fluctuate.

[0014] In this specification, when the term "impurity concentration" is used, it refers to the net impurity concentration after subtracting the amount compensated by reverse-conductivity impurities. In other words, "impurity concentration" refers to the NET doping concentration. The region where the doping concentration of P-type impurities is higher than that of N-type impurities is a P-type semiconductor region. Conversely, the region where the doping concentration of N-type impurities is higher than that of P-type impurities is an N-type semiconductor region.

[0015] The configuration common to each embodiment of the photoelectric conversion device and its driving method according to the present invention will be explained with reference to Figures 1 to 5.

[0016] Figure 1 shows the configuration of a stacked photoelectric converter 100 according to an embodiment of the present invention. The photoelectric converter 100 is constructed by stacking two substrates, a sensor substrate 11 and a circuit substrate 21, and electrically connecting them. The sensor substrate 11 has a first semiconductor layer having a photoelectric conversion element 102 (described later) and a first wiring structure. The circuit substrate 21 has a second semiconductor layer having a circuit such as a signal processing unit 103 (described later) and a second wiring structure. The photoelectric converter 100 is constructed by stacking the second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer in that order. The photoelectric converter described in each embodiment is a back-illuminated type photoelectric converter in which light is incident from a first surface and a circuit substrate is arranged on a second surface.

[0017] In the following description, the sensor substrate 11 and the circuit board 21 are explained using diced chips, but they are not limited to chips. For example, each substrate may be a wafer. Furthermore, each substrate may be stacked in wafer form and then diced, or it may be made into chips and then stacked and bonded together.

[0018] The sensor board 11 is provided with a pixel region 12, and the circuit board 21 is provided with a circuit region 22 for processing signals detected in the pixel region 12.

[0019] Figure 2 shows an example of the arrangement of the sensor substrate 11. Pixels 101, each having a photoelectric conversion element 102 including an avalanche photodiode (hereinafter referred to as APD), are arranged in a two-dimensional array in a planar view, forming a pixel region 12.

[0020] Pixel 101 is typically a pixel used to form an image, but when used in TOF (Time of Flight), it does not necessarily have to form an image. In other words, pixel 101 may be a pixel used to measure the time and amount of light that arrives.

[0021] Figure 3 is a diagram of the circuit board 21. It includes a signal processing unit 103 for processing the charge photoelectrically converted by the photoelectric conversion element 102 in Figure 2, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110.

[0022] The photoelectric conversion element 102 in Figure 2 and the signal processing unit 103 in Figure 3 are electrically connected via connection wiring provided for each pixel.

[0023] The vertical scanning circuit section 110 receives control pulses supplied from the control pulse generation section 115 and supplies control pulses to each pixel. Logic circuits such as a shift register and an address decoder are used in the vertical scanning circuit section 110.

[0024] The signal output from the photoelectric conversion element 102 of the pixel is processed by the signal processing unit 103. The signal processing unit 103 is equipped with a counter and memory, and digital values ​​are stored in the memory.

[0025] The horizontal scanning circuit unit 111 inputs control pulses to the signal processing unit 103 to sequentially select each column in order to read the signal from the memory of each pixel in which the digital signal is held.

[0026] For the selected column, a signal is output from the signal processing unit 103 of the pixel selected by the vertical scanning circuit unit 110 to the signal line 113.

[0027] The signal output to signal line 113 is output via output circuit 114 to an external recording unit or signal processing unit of the photoelectric converter 100.

[0028] In Figure 2, the arrangement of photoelectric conversion elements in the pixel region may be one-dimensional. Furthermore, it is possible to obtain the effects of the present invention even with just one pixel, and the case with one pixel is also included in the present invention. The function of the signal processing unit does not necessarily need to be provided for each photoelectric conversion element; for example, one signal processing unit may be shared by multiple photoelectric conversion elements, and signal processing may be performed sequentially.

[0029] As shown in Figures 2 and 3, multiple signal processing units 103 are arranged in the region that overlaps with the pixel region 12 in a plan view. The vertical scanning circuit unit 110, horizontal scanning circuit unit 111, column circuit 112, output circuit 114, and control pulse generation unit 115 are arranged so as to overlap between the edge of the sensor substrate 11 and the edge of the pixel region 12 in a plan view. In other words, the sensor substrate 11 has a pixel region 12 and a non-pixel region arranged around the pixel region 12, and the vertical scanning circuit unit 110, horizontal scanning circuit unit 111, column circuit 112, output circuit 114, and control pulse generation unit 115 are arranged in the region that overlaps with the non-pixel region in a plan view.

[0030] Figure 4 is an example of a block diagram including the equivalent circuits of Figures 2 and 3.

[0031] In Figure 2, the photoelectric conversion element 102 having the APD201 is provided on the sensor substrate 11, and the other components are provided on the circuit board 21.

[0032] The APD201 generates charge pairs corresponding to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD201. In addition, a voltage VH (second voltage), which is higher than the voltage VL supplied to the anode, is supplied to the cathode of the APD201. A reverse bias voltage is supplied to the anode and cathode such that the APD201 performs avalanche multiplication. By supplying these voltages, the charge generated by the incident light undergoes avalanche multiplication, and an avalanche current is generated.

[0033] Furthermore, when a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the anode and cathode operate with a potential difference greater than the breakdown voltage, and linear mode, in which the anode and cathode operate with a potential difference near or below the breakdown voltage.

[0034] An APD operating in Geiger mode is called a SPAD. For example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1V. The APD201 may operate in linear mode or Geiger mode. In the case of a SPAD, the potential difference is larger compared to a linear mode APD, and the voltage withstand effect is more pronounced, so it is preferable to use a SPAD.

[0035] The quench element 202 is connected to the power supply that provides voltage VH and to the APD201. When the signal is amplified by avalanche multiplication, the quench element 202 functions as a load circuit (quench circuit), suppressing the voltage supplied to the APD201 and thereby suppressing avalanche multiplication (quench operation). In addition, the quench element 202 also works to restore the voltage supplied to the APD201 to voltage VH by flowing the current that compensates for the voltage drop caused by the quench operation (recharge operation).

[0036] The signal processing unit 103 includes a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. In this specification, the signal processing unit 103 may include any one of the waveform shaping unit 210, the counter circuit 211, or the selection circuit 212.

[0037] The waveform shaping unit 210 shapes the cathode potential change of the APD201 obtained during photon detection and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping unit 210. Figure 4 shows an example in which one inverter is used as the waveform shaping unit 210, but a circuit in which multiple inverters are connected in series may be used, or other circuits that have a waveform shaping effect may be used.

[0038] The counter circuit 211 counts the pulse signal output from the waveform shaping unit 210 and holds the count value. When the control pulse pRES is supplied via the drive line 213, the signal held by the counter circuit 211 is reset.

[0039] The selection circuit 212 receives a control pulse pSEL from the vertical scanning circuit section 110 in Figure 3 via the drive line 214 (not shown in Figure 3) in Figure 4, which switches the electrical connection between the counter circuit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0040] A switch such as a transistor may be placed between the quench element 202 and the APD201, or between the photoelectric conversion element 102 and the signal processing unit 103, to switch the electrical connection. Similarly, the supply of voltage VH or voltage VL to the photoelectric conversion element 102 may be electrically switched using a switch such as a transistor.

[0041] In this embodiment, a configuration using a counter circuit 211 is shown. However, instead of the counter circuit 211, a photoelectric converter 100 may be used that acquires pulse detection timing using a Time to Digital Converter (TDC) and memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 210 is converted into a digital signal by the TDC. A control pulse pREF (reference signal) is supplied to the TDC via a drive line from the vertical scanning circuit unit 110 in Figure 1 to measure the timing of the pulse signal. The TDC acquires the signal as a digital signal when the input timing of the signal output from each pixel via the waveform shaping unit 210 is relative to the control pulse pREF.

[0042] Figure 5 schematically illustrates the relationship between the operation of the APD and the output signal.

[0043] Figure 5(a) is an excerpt of the APD201, quench element 202, and waveform shaping unit 210 from Figure 4. Here, the input side of the waveform shaping unit 210 is denoted as nodeA and the output side as nodeB. Figure 5(b) shows the waveform change at nodeA in Figure 5(a), and Figure 5(c) shows the waveform change at nodeB in Figure 5(a).

[0044] Between time t0 and time t1, a potential difference of VH-VL is applied to APD201 in Figure 5(a). When a photon is incident on APD201 at time t1, avalanche multiplication occurs in APD201, an avalanche multiplication current flows through the quench element 202, and the voltage at nodeA drops. As the voltage drop increases further and the potential difference applied to APD201 decreases, the avalanche multiplication of APD201 stops as at time t2, and the voltage level at nodeA stops dropping below a certain value. Subsequently, between time t2 and time t3, a current flows through nodeA to compensate for the voltage drop from voltage VL, and at time t3, nodeA settles to its original potential level. At this time, any portion of the output waveform at nodeA that exceeds a certain threshold is waveform-shaped by the waveform shaping unit 210 and output as a signal at nodeB.

[0045] Note that the arrangement of the signal line 113, the column circuit 112, and the output circuit 114 is not limited to Figure 3. For example, the signal line 113 may be arranged extending in the row direction, and the column circuit 112 may be located at the end of the signal line 113.

[0046] The following describes the photoelectric conversion device for each embodiment.

[0047] (First Embodiment) A photoelectric conversion device according to the first embodiment will be described using Figures 6 to 10.

[0048] Figure 6 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to the first embodiment, in a direction perpendicular to the plane direction of the substrate, and corresponds to the A-A' cross-section in Figure 7A.

[0049] The structure and function of the photoelectric conversion element 102 will now be described. The photoelectric conversion element 102 has an N-type first semiconductor region 311, a third semiconductor region 313, a fifth semiconductor region 315, and a sixth semiconductor region 316. Furthermore, it includes a P-type second semiconductor region 312, a fourth semiconductor region 314, a seventh semiconductor region 317, and a ninth semiconductor region 319.

[0050] In this embodiment, in the cross-section shown in Figure 6, a first N-type semiconductor region 311 is formed near the surface facing the incident light surface, and a third N-type semiconductor region 313 is formed around it. A second P-type semiconductor region 312 is formed at a position that overlaps the first and second semiconductor regions in a plan view. A fifth N-type semiconductor region 315 is further arranged at a position that overlaps the second semiconductor region 312 in a plan view, and a sixth N-type semiconductor region 316 is formed around it.

[0051] The first semiconductor region 311 has a higher N-type impurity concentration than the third semiconductor region 313 and the fifth semiconductor region 315. A PN junction is formed between the P-type second semiconductor region 312 and the N-type first semiconductor region 311. By making the impurity concentration of the second semiconductor region 312 lower than that of the first semiconductor region 311, all regions of the second semiconductor region 312 that overlap the center of the first semiconductor region in a plan view become a depletion layer region. At this time, the potential difference between the first semiconductor region 311 and the second semiconductor region 312 becomes larger than the potential difference between the second semiconductor region 312 and the fifth semiconductor region 315. Furthermore, this depletion layer region extends to a portion of the first semiconductor region 311, and a strong electric field is induced in the extended depletion layer region. Due to this strong electric field, avalanche multiplication occurs in the depletion layer region that extends to a portion of the first semiconductor region 311, and a current based on the amplified charge is output as a signal charge. When light incident on the photoelectric converter 102 is converted into electricity, and avalanche multiplication occurs in this depletion layer region (avalanche multiplication region), the generated charge of the first conductivity type is collected in the first semiconductor region 311.

[0052] In Figure 6, the third semiconductor region 313 and the fifth semiconductor region 315 are formed to be of roughly the same size, but the size of each semiconductor region is not limited to this. For example, the fifth semiconductor region 315 may be formed to be larger than the third semiconductor region 313, thereby collecting charge from a wider area to the first semiconductor region 311.

[0053] Furthermore, the third semiconductor region 313 may be a P-type semiconductor region instead of an N-type. In this case, the impurity concentration of the third semiconductor region 313 is set lower than that of the second semiconductor region 312. This is because if the impurity concentration of the third semiconductor region 313 is too high, an avalanche multiplication region will form between the third semiconductor region 313 and the first semiconductor region 311, causing the DCR (Dark Count Rate) to increase.

[0054] A trench-like uneven structure 325 is formed on the surface of the semiconductor layer on the light incident side. The uneven structure 325 is surrounded by a P-type fourth semiconductor region 314, scattering the light incident on the photoelectric conversion element 102. Since the incident light travels diagonally through the photoelectric conversion element, an optical path length greater than the thickness of the semiconductor layer 301 can be secured, making it possible to photoelectrically convert longer wavelength light compared to the case without the uneven structure 325. In addition, the uneven structure 325 prevents reflection of incident light within the substrate, thus improving the photoelectric conversion efficiency of the incident light. Furthermore, by combining it with the extended anode wiring, which is a feature of the present invention, the anode wiring efficiently reflects the light diffracted diagonally by the uneven structure 325, further improving near-infrared sensitivity. Note that the uneven structure 325 is not an essential component of the present invention, and the effects of the present invention can be obtained even in a photoelectric conversion element without the uneven structure 325.

[0055] The fifth semiconductor region 315 and the uneven structure 325 are formed to overlap in a plan view. The area where the fifth semiconductor region 315 and the uneven structure 325 overlap in a plan view is larger than the area of ​​the portion of the fifth semiconductor region 315 that does not overlap with the uneven structure 325. Charges generated at a position far from the avalanche multiplication region formed between the first semiconductor region 311 and the fifth semiconductor region 315 will have a longer travel time to reach the avalanche multiplication region compared to charges generated at a position close to the avalanche multiplication region. Therefore, timing jitter may increase. By positioning the fifth semiconductor region 315 and the uneven structure 325 to overlap in a plan view, the electric field deep within the photodiode can be increased, and the collection time of charges generated at a position far from the avalanche multiplication region can be shortened, thus reducing timing jitter.

[0056] Furthermore, the fourth semiconductor region 314 covers the uneven structure three-dimensionally, thereby suppressing the generation of thermally excited charges at the interface of the uneven structure. This suppresses the DCR of the photoelectric conversion element.

[0057] Pixels are separated from each other by a trench-structured pixel isolation section 324, and a P-type seventh semiconductor region 317 formed around it separates adjacent photoelectric conversion elements by a potential barrier. Since photoelectric conversion elements are also separated by the potential of the seventh semiconductor region 317, a trench structure like the pixel isolation section 324 is not essential as a pixel isolation section, and even when a trench-structured pixel isolation section 324 is provided, its depth and position are not limited to the configuration shown in Figure 6. The pixel isolation section 324 may be a DTI (deep trench isolation) that penetrates the semiconductor layer, or it may be a DTI that does not penetrate the semiconductor layer. Metal may be embedded in the DTI to improve light shielding performance. The pixel isolation section 324 may consist of SiO, a fixed charge film, a metal member, Poly-Si, or a combination of several of these. The pixel isolation section 324 may be configured to surround the entire periphery of the photoelectric conversion element in a plan view, or it may be configured only on opposite sides of the photoelectric conversion element, for example. A voltage may be applied to the embedded component to induce a charge at the trench interface, thereby suppressing the DCR.

[0058] It is also possible to regard the distance from the pixel separation part to the pixel separation part of an adjacent pixel or a pixel provided at the nearest position as the size of one photoelectric conversion element 102. For example, assume that there is a second avalanche diode between the first avalanche diode and the third avalanche diode. Assume that there is a first pixel separation part between the first avalanche diode and the second avalanche diode, and a second pixel separation part between the second avalanche diode and the third avalanche diode. It can also be said that the distance between the first pixel separation part and the second pixel separation part is the size of one photoelectric conversion element 102.

[0059] When the size of one photoelectric conversion element 102 is L, the distance d from the light incident surface to the avalanche multiplication region satisfies L√2 / 4 < d < L×√2. When the size and depth of the photoelectric conversion element satisfy this relational expression, the electric field strength in the depth direction and the electric field strength in the plane direction in the vicinity of the first semiconductor region 311 become approximately the same. Since the variation in the time required for charge collection can be suppressed, the timing jitter can be improved.

[0060] On the light incident surface side of the semiconductor layer, a pinning film 321, a planarization film 322, and a microlens 323 are further formed. A filter layer (not shown) or the like may be further disposed on the light incident surface side. Various optical filters such as a color filter, an infrared cut filter, and a monochrome filter can be used for the filter layer. For the color filter, an RGB color filter, an RGBW color filter, or the like can be used.

[0061] On the surface of the semiconductor layer facing the light incident surface, a wiring structure including a conductor and an insulating film is provided. The photoelectric conversion element 102 shown in FIG. 6 has an oxide film 341 and a protective film 342 on the side closer to the semiconductor layer, and a wiring layer made of a conductor is further laminated. An interlayer film 343, which is an insulating film, is provided between the wiring and the semiconductor layer and between the wiring layers.

[0062] The oxide film 341 is, for example, silicon oxide (SiO), but silicon oxide (SiON) or the like may also be used. The protective film 342 is a film that protects the avalanche diode from plasma damage and metal contamination during etching. Silicon nitride (SiN), which is a nitride film, is commonly used, but silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), etc. may also be used. If both the oxide film 341 and the protective film 342 contain nitrogen, the film with the higher nitrogen content is considered the protective film.

[0063] In this embodiment, silicon nitride refers to a compound of nitrogen (N) and silicon (Si), wherein the elements other than the light elements that make up the top two in the composition ratio of the constituent elements of the compound are nitrogen (N) and silicon (Si). Silicon nitride can contain light elements such as hydrogen (H) and helium (He), and their amount (atomic %) may be more or less than that of nitrogen (N) and silicon (Si). Silicon nitride can contain elements other than nitrogen (N), silicon (Si), and light elements at lower concentrations than those of nitrogen (N) and silicon (Si). Typical elements that can be contained in silicon nitride are boron (B), carbon (C), oxygen (O), fluorine (F), phosphorus (P), chlorine (Cl), and argon (Ar). When the third most abundant element among the constituent elements of silicon nitride is oxygen, this silicon nitride can be called silicon oxidative nitride or oxygen-containing silicon nitride.

[0064] Similarly, silicon oxide is a compound of oxygen (O) and silicon (Si), where the elements other than the two lightest elements in the composition ratio of the compound are oxygen (O) and silicon (Si). Typical elements that can be contained in silicon oxide include hydrogen (H), helium (He), boron (B), carbon (C), nitrogen (N), fluorine (F), phosphorus (P), chlorine (Cl), and argon (Ar). When nitrogen is the third most abundant element among the constituent elements of silicon oxide, this silicon oxide can be called silicon nitride or nitrogen-containing silicon oxide. The elements contained in the components of photoelectric converters can be analyzed using energy dispersive X-ray spectrometry (EDX). Furthermore, the hydrogen content can be analyzed using methods such as Elastic Recoil Detection Analysis (ERDA).

[0065] The cathode wiring 331A is connected to the first semiconductor region 311, and the anode wiring 331B supplies voltage to the seventh semiconductor region 317 via the ninth semiconductor region 319, which is the anode contact. In this embodiment, the cathode wiring 331A and the anode wiring 331B are formed on the same wiring layer. The wiring is made of a conductor containing a metal such as Cu or Al. In this cross-section, the outer circumference of the cathode wiring is denoted as 332A, and the inner circumference of the anode wiring opposite 332A is denoted as 332B. The dotted line 332C is a virtual line that divides the space between the outer circumference of the cathode wiring 332A and the inner circumference of the anode wiring 332B at an equal distance. In order to enhance the effect of suppressing the change in breakdown voltage over time, it is desirable that the depth distance between the semiconductor layer and the anode wiring 331B be as short as possible. Specifically, the wiring layer on which the anode wiring 331B is provided is the layer as close as possible to the semiconductor layer among a plurality of wiring layers stacked on the semiconductor layer, preferably the closest layer. The wiring layer on which the anode wiring 331B is provided is located further from the second surface of the semiconductor layer than the contacts connecting the anode wiring 331A and the first semiconductor region.

[0066] Figures 7A and 7B are pixel plan views of two pixels of a photoelectric converter according to the first embodiment. Figure 7A is a plan view from a plane opposite to the light incident surface, and Figure 7B is a plan view from the light incident surface side.

[0067] In Figure 7A, the first semiconductor region 311, the third semiconductor region 313, and the fifth semiconductor region 315 are circular and arranged concentrically. This structure suppresses localized electric field concentration at the edge of the strong electric field region between the first semiconductor region 311 and the second semiconductor region 312, thereby reducing the DCR. The shape of each semiconductor region is not limited to a circle; for example, it may be a polygon with aligned centroids.

[0068] The dotted lines on the first semiconductor region 311 and the third semiconductor region 313 indicate the areas where the cathode wiring 331A and anode wiring 331B are provided, respectively, in a plan view. The cathode wiring 331A is circular in a plan view, and its outer periphery, 332A, overlaps the first semiconductor region 311 in a plan view. The anode wiring 331B is a surface with a circular hole in its inner periphery, and 332B completely overlaps the third semiconductor region in a plan view. In other words, the boundary between the insulating film facing the cathode wiring 331A and the anode wiring 331B overlaps the third semiconductor region. At this time, the imaginary line 332C that equally divides the space between the outer periphery 332A of the cathode wiring and the inner periphery 332B of the anode wiring overlaps the third semiconductor region 313 and does not overlap the first semiconductor region 311. By arranging the anode wiring 331B in this manner, the trapping of hot electrons can be suppressed due to the effect of the Coulomb repulsion of the anode wiring 331B.

[0069] An avalanche multiplication region is formed in the depth direction between the first semiconductor region 311 and the second semiconductor region 312, and an electric field relaxation region is provided so as to surround this avalanche multiplication region. Here, the electric field relaxation region does not need to cover the entire circumference of the avalanche multiplication region, but only needs to cover a part of the periphery of the avalanche multiplication region. In a plan view, the boundary between the insulating film facing the cathode wiring 331A and the anode wiring 331B overlaps with this electric field relaxation region. Alternatively, it can be said that a virtual line 332C that equally divides the space between the outer circumference 332A of the cathode wiring and the inner circumference 332B of the anode wiring overlaps with the electric field relaxation region.

[0070] In Figure 7B, the uneven structure 325 is formed in a grid pattern in plan view. The uneven structure 325 is formed overlapping the first semiconductor region 311 and the fifth semiconductor region 315, and the centroid of the uneven structure 325 is contained within the avalanche multiplication region in plan view. In a grid-like trench structure as shown in Figure 7B, the trench depth at the intersection of trenches is deeper than the trench depth at the portion where the trench extends independently. However, the bottom of the trench at the intersection of trenches is located closer to the light incident surface than half the thickness of the semiconductor layer. Here, the trench depth is the depth from the first surface to the bottom, and can also be called the depth of the recess of the uneven structure 325.

[0071] Figure 8 is the potential diagram of the photoelectric conversion element 102 shown in Figure 6.

[0072] The dotted line 70 in Figure 8 shows the potential distribution of the line segment FF' in Figure 6, and the solid line 71 in Figure 8 shows the potential distribution of the line segment EE' in Figure 6. Figure 8 shows the potential as seen from the electron, which is the main carrier charge in the N-type semiconductor region. When the main carrier charge is a hole, the relationship between the high and low potentials is reversed. Also, depth A (first depth) in Figure 8 corresponds to height A in Figure 6. Similarly, depth B (third depth) corresponds to height B, depth C corresponds to height C, and depth D (second depth) corresponds to height D.

[0073] In Figure 8, let A1 be the potential height of the solid line 71 at depth A, and A2 be the potential height of the dotted line 70. At depth B, let B1 be the potential height of the solid line 71 and B2 be the potential height of the dotted line 70. At depth C, let C1 be the potential height of the solid line 71 and C2 be the potential height of the dotted line 70. At depth D, let D1 be the potential height of the solid line 71 and D2 be the potential height of the dotted line 70.

[0074] From Figures 6 and 8, the potential height of the first semiconductor region 311 corresponds to A1, and the potential height near the center of the second semiconductor region 312 corresponds to B1. Furthermore, the potential height of the fifth semiconductor region 315 corresponds to A2, and the potential height at the outer edge of the second semiconductor region 312 corresponds to B2.

[0075] Regarding the dotted line 70 in Figure 8, the potential gradually decreases from depth D to depth C. Then, the potential gradually increases from depth C to depth B, reaching level B2 at depth B. Furthermore, the potential decreases from depth B to depth A, reaching level A2 at depth A.

[0076] On the other hand, with respect to the solid line 71, the potential gradually decreases from depth D to depth C, and from depth C to depth B, reaching level B1 at depth B. Then, the potential decreases sharply from depth B to depth A, reaching level A1 at depth A. At depth D, the potentials of the dotted line 70 and the solid line 71 are at almost the same height, and in the regions indicated by line segments EE' and FF', there is a potential gradient that gradually decreases toward the second surface side of the semiconductor layer 301. Therefore, the charge generated in the photodetector moves toward the second surface side due to the gradual potential gradient.

[0077] In this embodiment, the avalanche diode has a lower impurity concentration in the second P-type semiconductor region 312 than in the first N-type semiconductor region 311, and the first and second semiconductor regions 311 are supplied with potentials that are in opposite biases to each other. As a result, a depletion layer is formed on the side of the second semiconductor region 312. With this structure, the second semiconductor region 312 acts as a potential barrier for the charge photoelectrically converted in the fourth semiconductor region 314, making it easier for the charge to be collected in the first semiconductor region 311.

[0078] In Figure 6, the second semiconductor region 312 is formed across the entire surface of the photoelectric conversion element. However, for example, the portion overlapping the first semiconductor region 311 in a plan view may be left as an N-type semiconductor region instead of being a P-type semiconductor region. The impurity concentration of this N-type semiconductor region is set lower than that of the first semiconductor region 311. When using an N-type semiconductor layer, the second semiconductor region 312 may be left untouched in the portion overlapping the first semiconductor region 311 in a plan view. In this case, it is possible to recognize that a fourth semiconductor region 314 with a slit is formed. In this case, due to the potential difference between the second semiconductor region 312 and the slit, the potential decreases in the direction from line segment FF' to line segment EE' at depth C in Figure 6. This makes it easier for charges converted photoelectrically in the fourth semiconductor region 314 to move towards the first semiconductor region 311. On the other hand, when a second semiconductor region 312 is formed across the entire surface as shown in Figure 6, the applied voltage required to obtain the strong electric field necessary for avalanche multiplication can be lowered compared to when a slit is formed, and noise caused by the formation of localized strong electric field regions can be suppressed.

[0079] The charge that has moved to the vicinity of the second semiconductor region 312 is accelerated by the steep potential gradient from depth B to depth A, indicated by the solid line 71 in Figure 8, i.e., by the strong electric field, and is avalanche multiplied.

[0080] In contrast, the potential distribution between the fifth semiconductor region 315 in Figure 6 and the second P-type semiconductor region 312, that is, from depth B to depth A of the dotted line 70 in Figure 8, is such that avalanche multiplication does not occur. Therefore, the charge generated in the fourth semiconductor region 314 can be counted as a signal charge without increasing the area of ​​the strong electric field region (avalanche multiplication region) relative to the size of the photodiode. Up to this point, the conductivity type of the fifth semiconductor region 315 has been explained as N-type, but it may also be a P-type semiconductor region as long as the concentration satisfies the potential relationship described above.

[0081] Furthermore, the charge photoelectrically converted in the second semiconductor region 312 flows into the fourth semiconductor region 314 due to the potential gradient from depth B to depth C of the dotted line 70 in Figure 8. For the reasons mentioned above, the charge in the fourth semiconductor region 314 is structured to easily move to the second semiconductor region 312. Therefore, the charge photoelectrically converted in the second semiconductor region 312 moves to the first semiconductor region 311 and is detected as a signal charge by avalanche multiplication. Thus, it has sensitivity to the charge photoelectrically converted in the second semiconductor region 312.

[0082] Furthermore, the dotted line 70 in Figure 8 indicates the cross-sectional potential of the line segment FF' in Figure 3. In the dotted line 70, the point where height A in Figure 6 intersects with the line segment FF' is A2, the point where height B intersects with the line segment FF' is B2, the point where height C intersects with the line segment FF' is C2, and the point where height D intersects with the line segment FF' is D2. Electrons photoelectrically converted in the fourth semiconductor region 314 in Figure 6 move along the potential from D2 to C2 in Figure 8, but the area from C2 to B2 is a potential barrier for the electrons and they cannot overcome it. Therefore, the electrons move to the vicinity of the center of the fourth semiconductor region 314 in Figure 6, indicated by the line segment EE'. The moved electrons then move along the potential gradient from C1 to B1 in Figure 8, undergo avalanche multiplication due to the steep potential gradient from B1 to A1, pass through the first semiconductor region 311, and are detected as signal charges.

[0083] Furthermore, the charge generated near the boundary between the third semiconductor region 313 and the sixth semiconductor region 316 in Figure 6 moves along the potential gradient from potential B2 to C2 in Figure 8. Subsequently, as described above, it moves to the vicinity of the center indicated by the line segment EE' of the fourth semiconductor region 314 in Figure 6. Then, it is avalanche multiplied by the steep potential gradient from B1 to A1. The avalanche multiplied charge passes through the first semiconductor region 311 and is detected as a signal charge.

[0084] Here, a strong electric field is applied around the first semiconductor region, causing an imbalance in the thermal state between the sensor substrate and the carriers, resulting in the generation of hot carriers. These hot carriers are trapped at trap sites around the cathode region, which is close to the wiring layer. As the number of trapped hot carriers increases over time, the potential near the cathode region and the electric field strength in the strong electric field region also change over time, raising concerns about changes in the breakdown voltage over time.

[0085] The problems and effects of the present invention will be explained using the schematic cross-sectional view of the photoelectric conversion element 102 shown in Figure 9A, the schematic diagram of the electric field strength distribution shown in Figure 9B, and the enlarged cross-sectional views of the oxide film 341 and protective film 342 shown in Figure 10. Figure 9A(I) is a schematic cross-section of a pixel when the oxide film 341 is thin, and Figure 9A(II) is a schematic cross-section of a pixel when the oxide film 341 is thick. As shown in Figure 9B, in Figure 9A(I), where the oxide film 341 is thin between XX', it can be seen that when electrons (hot carriers) are trapped in the protective film 342, the electric field concentrates near the edge and directly above the center of the first semiconductor region 311. Since the breakdown voltage is roughly inversely proportional to the maximum electric field strength, the breakdown voltage changes when the electric field concentrates directly above the center of the first semiconductor region 311 where the electric field is strong. Therefore, as shown in Figure 9A(II), if the oxide film is thick and the change in maximum electric field strength is small, changes in the breakdown voltage before and after hot carrier trapping are less likely to occur.

[0086] The relationship between the thickness of the oxide film and the likelihood of hot carrier trapping and electric field concentration is explained below. Consider the hot carriers trapped at the trapping sites of the protective film 342. As shown in Figure 10, the capacity of the oxide film 341 is C sioThe capacity of the protective film 342 is C prot In this case, the combined capacity C of the trap site all This is shown in equation 1 below.

[0087]

number

[0088]

number

[0089]

number

[0090] The effect of hot carriers being trapped at trap sites on the potential of the semiconductor layer surface is the combined capacitance C. all It is proportional to C. Therefore, in order to suppress the change in breakdown voltage over time, all Reduction is important. As shown in Equation 1, C all This is the series capacitance of two capacitances. The value of a series capacitance is strongly governed by the smaller of the two capacitances. In other words, capacitance C all To reduce this, it is necessary to increase the thickness of the oxide film so that the capacitance C2 on the oxide film side becomes the dominant factor over the capacitance C1 on the protective film side (C1 > C2), thereby satisfying Equation 4. Note that the relative permittivity ε is given when the oxide film is SiO. sio It is approximately 3.6 to 4.0, and the relative permittivity ε when the protective film is SiN sin It is approximately 7.0 to 9.0. In the following formula, the relative permittivity ε of the oxide film is... sio 3.8, relative permittivity of the protective film εsin We will estimate it as 8.0.

[0091]

number

[0092] When trap sites are uniformly distributed within the protective film, a typical trap site depth d trap d sin It can be set to / 2. That is, the above capacity relationship can be set to satisfy more than 50% of the trap positions out of all trap positions present in the protective film. In this case, the oxide film thickness d sin The condition that must be satisfied is given by equation 5.

[0093]

number

[0094] Furthermore, a more preferable condition is that the above-mentioned capacity relationship is satisfied for all trap locations in the protective film. In this case, the trap site depth d at which C1 is smallest is... trap =d sin Under these conditions, it is necessary to satisfy C1 > C2. Trap site depth d trap =d sin In that case, the oxide film thickness d sin The condition that must be satisfied is given by equation 6.

[0095]

number

[0096] For example, the protective film 342 is a silicon nitride film, and the relative permittivity ε of the oxide film 341 sio The relative permittivity of the protective film 342 is ε, which is 3.8. sin If the value is 8.0 and the thickness is 60 nm, then if the thickness of oxide film 341 is greater than 15 nm, (d sio >15nm) The conditions of equation 5 above are satisfied. Also, if the thickness of oxide film 341 is greater than 30nm (dsio >30nm) The conditions of equation 6 above are satisfied.

[0097] Furthermore, while the above examples described cumulative values ​​of 50% and 100% in the trap probability density function, the values ​​are not limited to these two numbers; for example, it is possible to set it to 80%. In this case, if the thickness of the oxide film 341 is greater than 24 nm, the above capacitance relationship can be satisfied for more than 80% of the trap locations present in the protective film.

[0098] In this way, by increasing the thickness of the oxide film relative to the protective film so that the thickness of the oxide film satisfies certain conditions, the potential change on the semiconductor layer surface caused by hot carriers being trapped in the protective film can be reduced, and the change in breakdown voltage over time can be prevented.

[0099] (Second embodiment) A photoelectric conversion device according to the second embodiment will be described with reference to Figure 11.

[0100] Parts that are common to the description of the first embodiment will be omitted, and the parts that differ mainly from the first embodiment will be described. In this embodiment, the oxide film 341 is formed such that the thickness of the oxide film 341 is increased near areas where hot carrier injection into the protective film 342 is likely to occur.

[0101] Figure 11 is a cross-sectional view of two pixels of the photoelectric conversion element 102 of the photoelectric conversion device according to the second embodiment, taken perpendicular to the plane direction of the substrate.

[0102] Hot carriers are generated when carriers are accelerated by an electric field. Therefore, hot carrier injection is likely to occur in the region that overlaps with the third semiconductor region 313 in a plan view, and hot carriers are particularly likely to occur near the edge of the first semiconductor region 311. In this embodiment, the oxide film 341 in the region that overlaps with the third semiconductor region 313 in a plan view is formed to be thicker than the oxide film 341 in the region that does not overlap with the third semiconductor region 313. Since there is no need to thicken the oxide film 341 in the region connected to the cathode wiring 331A and the anode wiring 331B, the oxide film 341 does not interfere with the manufacturing of the contact plug. In this way, by locally changing the oxide film thickness, it is possible to suppress the change in breakdown voltage over time while ensuring the manufacturing stability of the contact plug.

[0103] (Third embodiment) A photoelectric conversion device according to the third embodiment will be described with reference to Figure 12.

[0104] Parts that are common to the description of the first or second embodiment will be omitted, and the parts that differ mainly from the first embodiment will be described.

[0105] Figure 12 is a cross-sectional view of the photoelectric conversion element 102 of the photoelectric conversion device according to the third embodiment, in a direction perpendicular to the plane direction of the semiconductor layer, and corresponds to the A-A' cross-section in Figure 13A. In the photoelectric conversion device according to this embodiment, compared to the photoelectric conversion device according to the first embodiment, the proportion of the N-type first semiconductor region 311 that occupies the light-receiving surface of the pixel is large, and the area of ​​the P-type second semiconductor region 312 relative to the light-receiving surface of the pixel is small.

[0106] The incident light is avalanche multiplied between the first semiconductor region 311 and the second semiconductor region 312. Therefore, when the pixel aperture is designed so that both the first semiconductor region 311 and the second semiconductor region 312 are exposed, the aperture ratio of the photoelectric converter according to this embodiment is smaller than that of the photoelectric converters according to the first to ninth embodiments. By reducing the aperture ratio, the volume of the signal-detectable photoelectric conversion region can be suppressed, thereby reducing crosstalk.

[0107] Furthermore, the uneven structure 325 has a square pyramidal shape, such that its cross-section is a triangle with the light incident surface as its base. Since such an uneven structure 325 can be formed by etching along the crystal plane, it has high manufacturing stability.

[0108] In this embodiment, the oxide film 341 is formed including oxide film 341A and oxide film 341B from the side closest to the semiconductor layer. Since oxide film 341A is in contact with the semiconductor layer, it is desirable that it be a highly homogeneous oxide film considering its effect on DCR. On the other hand, oxide film 341B is a layer that ensures sufficient thickness for the oxide film 341 as a whole, and it is desirable that it has a fast deposition rate from the viewpoint of mass production. The multiple layers constituting the oxide film 341 may include, for example, a layer made of an oxynitride film. By thus producing the oxide film 341 using multiple different deposition methods, and by having multiple layers that differ in at least one of the deposition methods, physical properties, or chemical compositions, it is possible to suppress the change in breakdown voltage over time while suppressing the manufacturing time.

[0109] Figures 13A and 13B are two-pixel pixel plan views of a photoelectric converter according to a third embodiment. Figure 13A is a plan view from a plane opposite to the light incident surface, and Figure 13B is a plan view from the light incident surface side. In the photoelectric converter shown in Figures 13A and 13B, the region of the first semiconductor region 311 that does not overlap with the second semiconductor region 312 in a plan view surrounds the avalanche multiplication region as an electric field relaxation region. The virtual line 332B that divides the space between the outer periphery 332A of the cathode wiring and the inner periphery 332B of the anode wiring at an equal distance all overlap with the first semiconductor region 311 in a plan view, and the uneven structure 325 is formed overlapping the first semiconductor region 311.

[0110] (Fourth embodiment) A photoelectric conversion device according to the fourth embodiment will be described with reference to Figure 14.

[0111] Parts that are common to the descriptions of the first to seventh embodiments will be omitted, and the parts that differ mainly from the first embodiment will be described.

[0112] Figure 14 is a cross-sectional view of the photoelectric converter 100, with light incident from the upper side of Figure 14. The first substrate 301 and the second substrate 401 are stacked from the light incident surface side.

[0113] The first substrate 301 is composed of a semiconductor layer 302 (first semiconductor layer) and a wiring structure 303 (first wiring structure). The second substrate 401 is composed of a semiconductor layer 402 (second semiconductor layer) and a wiring structure 403 (second wiring structure). The semiconductor layer 302 has a first surface P1 and a second surface P2 opposite to the first surface P1. For example, the first surface P1 is the front surface and the second surface P2 is the back surface. The semiconductor layer 402 has a third surface P3 and a fourth surface P4 opposite to the third surface P3. For example, the third surface P3 is the front surface and the fourth surface P4 is the back surface. The first substrate 301 and the second substrate 401 are joined so that the first wiring structure 303 and the second wiring structure 403 are in contact with each other. The joining surface is designated as the fifth surface P5. The fifth surface P5 is the top surface of wiring structure 303, and may be the top surface of wiring structure 403.

[0114] The first semiconductor layer 302 contains a first semiconductor region 311 of the first conductivity type, a second semiconductor region 312 of the second conductivity type, a third semiconductor region 313 of the first conductivity type, and a fourth semiconductor region 314 of the second conductivity type. The first semiconductor layer 302 also contains a fifth semiconductor region 315 of the second conductivity type, a sixth semiconductor region 316 of the first conductivity type, and a seventh semiconductor region 317 of the first conductivity type.

[0115] The first semiconductor region 311 and the second semiconductor region 312 form a PN junction, constituting an APD.

[0116] A third semiconductor region 313 is formed on the light incident surface side of the second semiconductor region 312. The impurity concentration in the third semiconductor region 313 is lower than the impurity concentration in the second semiconductor region 312. Here, "impurity concentration" refers to the net impurity concentration compensated for by reverse-conductivity impurities. In other words, "impurity concentration" refers to the NET concentration. For example, a region where the concentration of P-type added impurities is higher than the concentration of N-type added impurities is a P-type semiconductor region. Conversely, a region where the concentration of N-type added impurities is higher than the concentration of P-type added impurities is an N-type semiconductor region.

[0117] Each pixel is separated by a fourth semiconductor region 314. Furthermore, a fifth semiconductor region 315 is provided on the light incident side of the fourth semiconductor region 314. The fifth semiconductor region 315 is common to all pixels.

[0118] A voltage VPDL (first voltage) is supplied to the fourth semiconductor region 314, and a voltage VDD (second voltage) is supplied to the first semiconductor region 311. The voltage supplied to the fourth semiconductor region 314 and the voltage supplied to the first semiconductor region 311 supply a reverse bias voltage to the second semiconductor region 312 and the first semiconductor region 311. This supplies a reverse bias voltage that causes the APD to perform avalanche multiplication operation.

[0119] A pinning layer 321 is provided on the light incident side of the fifth semiconductor region 315. The pinning layer 321 is a layer provided to suppress dark current. The pinning layer 321 is formed using, for example, hafnium oxide (HfO2). The pinning layer 321 may also be formed using zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), or the like.

[0120] A planarization layer 322 and a microlens 323 are provided on the pinning layer 321. The planarization layer 322 may include any configuration such as an insulating film, a light-shielding film, or a color filter. A grid-shaped light-shielding film for optically separating each pixel may be provided between the microlens 323 and the pinning layer 321. The material of the light-shielding film can be any material that can block light, such as tungsten (W), aluminum (Al), or copper (Cu).

[0121] The second semiconductor layer 402 is provided with an active region 411 and an isolation region 412, both of which are semiconductor regions. The isolation region 412 is a field region made of an insulator.

[0122] The first wiring structure 303 has multiple insulating layers and multiple wiring layers 380. The multiple wiring layers 380 are composed of a first wiring layer (M1), a second wiring layer (M2), and a third wiring layer (M3) from the side of the first semiconductor layer 302. The uppermost layer of the first wiring structure 303 is provided so as to expose a first junction 385. The first wiring structure 303 also has a first pad opening 353 and a second pad opening 355 formed therein, and a first pad electrode 352 and a second pad electrode 354 are provided at the bottom of the first pad opening 353 and the second pad opening 355, respectively. Voltage is supplied to the first pad electrode 352 and the second pad electrode 354 from outside the photoelectric converter 100. The outside of the photoelectric converter 100 and the pad electrodes are electrically connected by wire bonding, soldering, TSV (Through Silicon Via), etc., as shown in Figure 14. The first pad electrode 352 is an electrode for supplying voltage to the circuit of the first substrate. For example, a voltage VPDL (first voltage) is supplied from the first pad electrode 352 to the fourth semiconductor region 314 via via wiring (not shown) or contact wiring (not shown).

[0123] The second wiring structure 403 has multiple insulating layers and multiple wiring layers 390. The multiple wiring layers 390 are composed of a first wiring layer (M1) to a fifth wiring layer (M5), starting from the second semiconductor layer 402 side. The uppermost layer of the second wiring structure 403 is provided so as to expose a second junction 395. The junction 385 of the first substrate is in contact with the junction 395 of the second substrate and is electrically connected. This type of bonding, where the first junction 385 exposed on the junction surface of the first substrate and the second junction 395 exposed on the junction surface of the second substrate are connected, is sometimes called a metal bonding (MB) structure or a metal junction. Since this type of bonding is often performed between copper (Cu) materials, it is sometimes called a Cu-Cu junction (Cu-Cu bonding). Furthermore, the joining of the first joint 385 and the second joint 395, and the joining of the insulating layer of the first wiring structure 303 and the insulating layer of the second wiring structure 403 are sometimes referred to as hybrid bonding.

[0124] The second pad electrode 354, provided in the first wiring structure 303, is electrically connected to one of the multiple wirings provided in the multiple wiring layers 390 via the first junction 385 and the second junction 395. For example, the second pad electrode 354 supplies a voltage VSS (third voltage) to a circuit provided in the pixel circuit 3000. The pad electrode 354 also supplies a voltage VDD (second voltage) to a circuit provided in the pixel circuit 3000. Furthermore, the second pad electrode 354 supplies voltage to the wirings of the multiple wiring layers 390 via the first junction 385 and the second junction 395, and supplies voltage to the wirings of the multiple wiring layers 380 via the second junction 395 and the first junction 385. For example, in such a path, the voltage VDD (second voltage) electrically connected to the quench element 3010 is supplied from the second pad electrode 354. Specifically, the second pad electrode 354 supplies VDD (second voltage) to the first junction 385, the second junction 395, and the wiring of the multiple wiring layers 390. Then, from the wiring of the multiple wiring layers 390, VDD (second voltage) is supplied to the first semiconductor region 311 via the quench element 3010 provided on the second substrate, the wiring of the multiple wiring layers 390, the second junction 395, and the first junction 385. In Figure 14, only one pad electrode is shown as the second pad electrode 354, but multiple second pad electrodes 354 can be provided to supply voltages with different values.

[0125] In Figure 14, the first pad electrode 352 and the second pad electrode 354 are located between the second surface P2 and the fifth surface P5, more specifically, between the first surface P1 and the fifth surface P2. The first pad electrode 352 and the second pad electrode 354 can be arranged between the second surface P2 and the fourth surface P4.

[0126] (Fifth embodiment) A photoelectric conversion device according to the fifth embodiment will be described with reference to Figure 15.

[0127] Parts that are common to the descriptions of the first to thirteenth embodiments will be omitted, and the parts that differ mainly from the first embodiment will be described.

[0128] Figure 15 shows a modified example of the photoelectric converter 100. Figure 15 corresponds to the cross-sectional view shown in Figure 6. In this embodiment, the positions of the first pad electrode 352 and the second pad electrode 354 are changed compared to the configuration of Embodiment 1.

[0129] In Figure 14, the wiring layer of the wiring structure 303, for example, the third wiring layer, includes the first pad electrode 352 and the second pad electrode 354. However, in Figure 15, the wiring layer of the wiring structure 403, for example, the fifth wiring layer, includes the first pad electrode 352 and the second pad electrode 354. The depths of the first pad opening 353 and the second pad opening 355 are greater than the depths of the first pad opening 353 and the second pad opening 355 shown in Figure 14. Here, depth means, for example, the distance from the back surface of the semiconductor layer 302. The first pad electrode 352 and the second pad electrode 354 can be located between the fifth surface P5 and the fourth surface P4, for example, between the fifth surface P5 and the third surface P3. The back surface of the semiconductor layer 302 is, for example, the interface with the pinning layer 321. The first pad opening 353 and the second pad opening 355 penetrate the bonding surface and extend from the semiconductor layer 302. The optical conversion device 100 of the present invention can also have such a configuration. Here, a configuration in which the wiring layer includes the first pad electrode 352 and the second pad electrode 354 has been described, but the pad electrodes may be formed separately from the wiring layer.

[0130] (Sixth embodiment) A photoelectric conversion device according to the sixth embodiment will be described with reference to Figure 16.

[0131] Parts that are common to the descriptions of the first to fourteenth embodiments will be omitted, and the parts that differ mainly from the first embodiment will be described.

[0132] Figure 16 shows a modified example of the photoelectric converter 100. Figure 16 corresponds to the cross-sectional view shown in Figure 6. In this embodiment, the position of the second pad electrode 354 is changed compared to the configuration of Embodiment 8.

[0133] In Figure 14, the wiring layer of the wiring structure 303, for example, the third wiring layer, includes the second pad electrode 354. However, in Figure 16, the wiring layer of the wiring structure 403, for example, the fifth wiring layer, includes the second pad electrode 354. That is, the second pad electrode 354 can be located between the fifth surface P5 and the fourth surface P4, for example, between the fifth surface P5 and the third surface P3. The second pad electrode 352 can be located between the second surface P2 and the fifth surface P5, for example, between the first surface P1 and the fifth surface P1. Alternatively, the wiring layer of the wiring structure 403 may include the first pad electrode 352, and the wiring layer of the wiring structure 303 may include the second pad electrode 354. The optical conversion device 100 of the present invention can also have such a configuration.

[0134] Here, a configuration in which the wiring layer includes a first pad electrode 352 and a second pad electrode 354 has been described, but the pad electrodes may be formed separately from the wiring layer.

[0135] (Seventh Embodiment) A photoelectric conversion device according to the seventh embodiment will be described with reference to Figure 17.

[0136] Parts that are common to the descriptions of the first to sixth embodiments will be omitted, and the parts that differ mainly from the fourth embodiment will be described.

[0137] Figure 17 shows a modified example of the photoelectric converter 100. Figure 17 corresponds to the cross-sectional view shown in Figure 6. In this embodiment, the structures of the first pad electrode 352 and the second pad electrode 354 are modified compared to the configuration of Embodiment 8.

[0138] The wiring structure 303 includes the first to third wiring layers M1 to M3 and the connection part 385. The wiring structure 403 includes the first to fifth wiring layers M1 to M5 and the connection part 395. Each wiring layer is a so-called copper wiring.

[0139] In wiring structures 303 and 403, the first wiring layer includes a conductor pattern mainly composed of copper. The conductor pattern of wiring layer 1 is a single damascene structure. Contacts are provided for electrical connection between the first wiring layer and the semiconductor layer 302. The contacts are conductor patterns mainly composed of tungsten. The second and third wiring layers include conductor patterns mainly composed of copper. The conductor patterns of the second and third wiring layers are dual damascene structures, including parts that function as wiring and parts that function as vias. The fourth and fifth wiring layers are similar to the second and third wiring layers.

[0140] The first pad electrode 352 and the second pad electrode 354 are conductive patterns mainly composed of aluminum. The first pad electrode 352 and the second pad electrode 354 are provided across the second and third wiring layers of the wiring structure 303. For example, they include portions that function as vias connecting the first and second wiring layers and portions that function as wiring for the third wiring layer. The first pad electrode 352 and the second pad electrode 354 are located, for example, between the second surface P1 and the fifth surface P5. The first pad electrode 352 and the second pad electrode 354 can be provided between the second surface P2 and the fourth surface P4, or between the second surface P2 and the fifth surface P5.

[0141] The first pad electrode 352 and the second pad electrode 354 each have a first surface and a second surface that is opposite to the first surface. The first surface is partially exposed by an opening in the semiconductor layer.

[0142] The exposed portions of the first pad electrode 352 and the second pad electrode 354 can function as connection points to external terminals, or so-called pad portions. The first pad electrode 352 and the second pad electrode 354 are connected to multiple copper-based conductors on their second surfaces.

[0143] In a configuration different from this embodiment, the first pad electrode 352 and the second pad electrode 354 may have electrical connections in the unexposed portions on the first surface side. For example, the first pad electrode 352 and the second pad electrode 354 may have vias made of a conductor mainly composed of aluminum, and may be electrically connected through these vias to a conductor mainly composed of copper located on the first surface side. Alternatively, the first pad electrode 352 and the second pad electrode 354 may be connected to the first wiring layer of the wiring structure 303 by a conductor mainly composed of tungsten on their first surfaces.

[0144] The first pad electrode 352 and the second pad electrode 354 can be formed, for example, by the following procedure. After forming the insulator covering the third wiring layer, a portion of the insulator is removed, and a film mainly composed of aluminum, which will become the first pad electrode 352 and the second pad electrode 354, is formed by patterning. By forming the first pad electrode 352 and the second pad electrode 354 after forming the copper wiring, it is possible to form the first pad electrode 352 and the second pad electrode 354 with a thick film thickness while maintaining the flatness of the fine copper wiring.

[0145] In this embodiment, the first pad electrode 352 and the second pad electrode 354 are shown as being included in the wiring structure 303, but they may also be included in the wiring structure 403. Furthermore, the position where the pad electrodes are provided may be in either the wiring structure 303 or 403, and is not limited to these. The materials and structures of each wiring layer in the wiring structures 303 and 403 are not limited to those exemplified; for example, there may be an additional conductor layer between the wiring layer 1 and the semiconductor layer. Also, there may be a stacked contact structure in which two contact layers are stacked.

[0146] (Eighth embodiment) A photoelectric conversion device according to the eighth embodiment will be described with reference to Figure 18.

[0147] Parts that are common to the descriptions of the first to seventh embodiments will be omitted, and the parts that differ mainly from the fourth embodiment will be described.

[0148] Figure 18 shows a modified example of the photoelectric converter 100. Figure 18 is an enlarged cross-sectional view of the vicinity of the pad electrode 354 in the cross-sectional view shown in Figure 6. In this embodiment, the structure of the second pad electrode 354 is mainly changed compared to the configuration of Embodiment 1.

[0149] The wiring structure 303 includes first and second wiring layers M1 and M2 and a connection part 385. The wiring structure 403 includes first to fourth wiring layers M1 to M4 and a connection part 395. Each wiring layer is a so-called copper wiring.

[0150] In wiring structures 303 and 403, the first wiring layer includes a conductor pattern mainly composed of copper. The conductor pattern of wiring layer 1 is a single damascene structure. Contacts are provided for electrical connection between the first wiring layer and the semiconductor layer 302. The contacts are conductor patterns mainly composed of tungsten. The second and third wiring layers include conductor patterns mainly composed of copper. The conductor patterns of the second and third wiring layers are dual damascene structures and include parts that function as wiring and parts that function as vias. The fourth wiring layer is similar to the second and third wiring layers.

[0151] The second pad electrode 354 is a conductive pattern mainly composed of aluminum. The second pad electrode 354 is not a wiring structure, but is positioned in an opening in the semiconductor layer 302. Here, the second pad electrode 354 is shown having an exposed surface on the second surface P2 and the first surface P1, but the exposed surface of the pad electrode may be located on the second surface P2.

[0152] A brief explanation of how to form this structure is given. An opening 353 is formed in the semiconductor layer 302 so that a portion of the wiring layer M1 of the wiring structure 303 is exposed. Then, an insulator 18-101 is formed to cover the second surface P2 of the semiconductor layer 302 and the first pad opening 353. An opening that will become a via for the second pad electrode 354 is formed in the insulator 18-101. After forming the conductive film that will become the second pad electrode 354, unnecessary parts of the conductive film are removed to achieve the desired pattern. Furthermore, an opening 18-105 is formed where the second pad electrode 354 is exposed, even though the insulator 18-102 has been formed. This structure can be formed in this manner.

[0153] Furthermore, through electrodes 18-104 may be provided from the second surface P2 side. The through electrodes 18-104 are made of a conductor mainly composed of copper and may have a barrier metal between the semiconductor layer 302 and the conductor.

[0154] A conductor 18-103 is placed on the through electrode 18-104. The conductor 18-103 may be provided in common with other through electrodes and may have the function of reducing the diffusion of the conductor of the through electrode 18-104.

[0155] The first pad electrode 352 (not shown) may have the same configuration as the second pad electrode 354. The materials and structures of each wiring layer in the wiring structures 303 and 403 are not limited to those exemplified; for example, there may be an additional conductor layer between the wiring layer 1 and the semiconductor layer. Furthermore, the contacts may have a stacked contact structure with two layers stacked.

[0156] Although the first pad electrode 352 and the second pad electrode 354 are positioned between the second surface P2 and the fourth surface P4, they may also be positioned on the second surface P2.

[0157] Furthermore, the first pad opening 353 and the second pad opening 355 may be provided on the second substrate 12. If the openings are located on the second substrate 12, through electrodes may be formed within the openings. The electrical connection between the through electrodes and the external device can be provided on the fourth surface P4.

[0158] Furthermore, the pad electrodes, which are the electrical connection points with external devices, may be provided on both the fourth surface P4 side of the second substrate 12 and the second surface P2 side of the first substrate 301.

[0159] (Ninth embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Figure 19. Figure 19 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0160] The photoelectric conversion devices described in the first to third embodiments above are applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in photoelectric conversion systems. Figure 19 shows a block diagram of a digital still camera as an example of these.

[0161] The photoelectric conversion system illustrated in Figure 19 includes an imaging device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject onto the imaging device 1004. Furthermore, it has an aperture 1003 for varying the amount of light passing through the lens 1002, and a barrier 1001 for protecting the lens 1002. The lens 1002 and aperture 1003 are an optical system that focuses light onto the imaging device 1004. The imaging device 1004 is a photoelectric conversion device of any of the above embodiments, which converts the optical image formed by the lens 1002 into an electrical signal.

[0162] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing the output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as needed and outputs the image data. The signal processing unit 1007 may be formed on the semiconductor substrate on which the imaging device 1004 is mounted, or it may be formed on a semiconductor substrate separate from the imaging device 1004.

[0163] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system includes a recording medium 1012 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0164] Furthermore, the photoelectric conversion system includes an overall control / calculation unit 1009 that controls various calculations and the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the imaging device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system only needs to have at least the imaging device 1004 and the signal processing unit 1007 that processes the output signals output from the imaging device 1004.

[0165] The imaging device 1004 outputs the imaging signal to the signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0166] Thus, according to this embodiment, a photoelectric conversion system can be realized by applying a photoelectric conversion device (imaging device) of any of the above embodiments.

[0167] (Tenth embodiment) The photoelectric conversion system and mobile unit of this embodiment will be described using Figures 20A and 20B. Figures 20A and 20B show the configuration of the photoelectric conversion system and mobile unit of this embodiment.

[0168] Figure 20A shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 1300 has an imaging device 1310. The imaging device 1310 is a photoelectric conversion device as described in any of the embodiments above. The photoelectric conversion system 1300 has an image processing unit 1312 that performs image processing on a plurality of image data acquired by the imaging device 1310, and a parallax acquisition unit 1314 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric conversion system 1300. The photoelectric conversion system 1300 also has a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 1318 may use any of this distance information to determine the possibility of a collision. The distance information acquisition means may be implemented by specially designed hardware or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0169] The photoelectric conversion system 1300 is connected to the vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1300 is also connected to the control ECU 1330, which is a control unit that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 1318. The photoelectric conversion system 1300 is also connected to the warning device 1340, which issues a warning to the driver based on the judgment result of the collision judgment unit 1318. For example, if the collision judgment result of the collision judgment unit 1318 indicates a high probability of collision, the control ECU 1330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 1340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0170] In this embodiment, the photoelectric conversion system 1300 images the area around the vehicle, for example, the front or rear. Figure 20B shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 1350). The vehicle information acquisition device 1320 sends instructions to the photoelectric conversion system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0171] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0172] (11th embodiment) The photoelectric conversion system of this embodiment will be described with reference to Figure 21. Figure 21 is a block diagram showing an example configuration of a distance image sensor, which is the photoelectric conversion system of this embodiment.

[0173] As shown in Figure 21, the distance image sensor 401 is configured to include an optical system 407, a photoelectric converter 408, an image processing circuit 404, a monitor 405, and a memory 406. The distance image sensor 401 receives light (modulated light or pulsed light) that is projected from a light source device 409 toward the subject and reflected from the surface of the subject, thereby acquiring a distance image corresponding to the distance to the subject.

[0174] The optical system 407 is composed of one or more lenses and guides the image light (incident light) from the subject to the photoelectric converter 408, where it forms an image on the light-receiving surface (sensor part) of the photoelectric converter 408.

[0175] The photoelectric converter 408 is one of the photoelectric converters from each of the embodiments described above, and a distance signal indicating the distance obtained from the light received signal output from the photoelectric converter 408 is supplied to the image processing circuit 404.

[0176] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric converter 408. The distance image (image data) obtained through this image processing is then supplied to the monitor 405 for display or supplied to the memory 406 for storage (recording).

[0177] With the distance image sensor 401 configured in this way, by applying the photoelectric conversion device described above, the characteristics of the pixels are improved, and for example, more accurate distance images can be acquired.

[0178] (12th embodiment) The photoelectric conversion system of this embodiment will be described with reference to Figure 22. Figure 22 is a diagram showing an example of a schematic configuration of an endoscopic surgical system, which is the photoelectric conversion system of this embodiment.

[0179] Figure 22 illustrates a surgeon (physician) 1131 performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgical system 1150. As shown in the figure, the endoscopic surgical system 1150 consists of an endoscope 1100, surgical instruments 1110, and a cart 1134 equipped with various devices for endoscopic surgery.

[0180] The endoscope 1100 consists of a barrel 1101, the tip of which is inserted into the body cavity of the patient 1132 for a predetermined length, and a camera head 1102 connected to the base end of the barrel 1101. In the illustrated example, the endoscope 1100 is shown as a so-called rigid endoscope having a rigid barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0181] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 1101. A light source device 1203 is connected to the endoscope 1100, and the light generated by the light source device 1203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 1101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 1132. The endoscope 1100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0182] The camera head 1102 contains an optical system and a photoelectric converter. Reflected light from the object being observed (observation light) is focused by the optical system into the photoelectric converter. The photoelectric converter converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The photoelectric converter can be any of the photoelectric converters described in the embodiments described above. The image signal is transmitted as RAW data to the camera control unit (CCU) 1135.

[0183] The CCU1135 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 1100 and the display device 1136. Furthermore, the CCU1135 receives an image signal from the camera head 1102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0184] The display device 1136 displays an image based on an image signal that has been processed by the CCU 1135, under control from the CCU 1135.

[0185] The light source device 1203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 1100 when photographing the surgical area, etc.

[0186] The input device 1137 is an input interface for the endoscopic surgical system 1150. The user can input various types of information and instructions to the endoscopic surgical system 1150 via the input device 1137.

[0187] The treatment instrument control device 1138 controls the driving of the energy treatment instrument 1112 for purposes such as tissue cauterization, incision, or blood vessel sealing.

[0188] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical area, can be composed of, for example, an LED, a laser light source, or a combination thereof. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 1203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0189] Furthermore, the light source device 1203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 1102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0190] Furthermore, the light source device 1203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissue is utilized. Specifically, by irradiating with narrowband light compared to the irradiation light used during normal observation (i.e., white light), predetermined tissues such as blood vessels on the surface of mucosa can be imaged with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light can be irradiated onto body tissue and fluorescence from the body tissue can be observed, or a reagent such as indocyanine green (ICG) can be injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be irradiated onto the body tissue to obtain a fluorescence image. The light source device 1203 may be configured to supply narrowband light and / or excitation light corresponding to such special light observation.

[0191] (13th embodiment) The photoelectric conversion system of this embodiment will be described with reference to Figures 23A and 23B. Figure 23A illustrates the eyeglasses 1600 (smart glasses), which are the photoelectric conversion system of this embodiment. The eyeglasses 1600 have a photoelectric conversion device 1602. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the embodiments described above. In addition, a display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric conversion devices 1602. In addition, multiple types of photoelectric conversion devices may be used in combination. The arrangement position of the photoelectric conversion device 1602 is not limited to Figure 23A.

[0192] The eyeglasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric converter 1602 and the display device. The control device 1603 also controls the operation of the photoelectric converter 1602 and the display device. The lens 1601 has an optical system formed therein for focusing light onto the photoelectric converter 1602.

[0193] Figure 23B illustrates a pair of glasses 1610 (smart glasses) relating to one application example. The glasses 1610 have a control device 1612, which is equipped with a photoelectric converter equivalent to a photoelectric converter 1602 and a display device. The lens 1611 has an optical system formed therein for projecting light emitted from the photoelectric converter in the control device 1612 and from the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power supply that provides power to the photoelectric converter and the display device, and also controls the operation of the photoelectric converter and the display device. The control device may have a gaze detection unit that detects the wearer's gaze. Gaze detection may use infrared light. The infrared light emitter emits infrared light towards the eyeball of the user who is fixating on the displayed image. An imaging unit having a light-receiving element detects the reflected light from the eyeball of the emitted infrared light, thereby obtaining an image of the eyeball. By having a reduction means that reduces the light from the infrared light emitter to the display unit in planar view, the deterioration of image quality is reduced.

[0194] The user's gaze towards the displayed image is detected from an image of the eyeball obtained by imaging with infrared light. Any known method can be applied to gaze detection using an image of the eyeball. For example, a gaze detection method based on the Purkinje image obtained by the reflection of the irradiated light from the cornea can be used.

[0195] More specifically, gaze detection processing is performed based on the pupil-corneal reflection method. Using the pupil-corneal reflection method, a gaze vector representing the orientation (rotation angle) of the eyeball is calculated based on the pupil image and Purkinje image contained in the captured image of the eyeball, thereby detecting the user's gaze.

[0196] The display device of this embodiment includes a photoelectric converter having a light-receiving element, and may control the display image of the display device based on the user's gaze information from the photoelectric converter.

[0197] Specifically, the display device determines a first field of view that the user is fixated on, and a second field of view other than the first field of view, based on gaze information. The first and second field of view may be determined by the control device of the display device, or they may be determined by an external control device and received. Within the display area of ​​the display device, the display resolution of the first field of view may be controlled to be higher than that of the second field of view. In other words, the resolution of the second field of view may be lower than that of the first field of view.

[0198] Furthermore, the display area may have a first display area and a second display area different from the first display area, and a higher priority area may be determined from the first and second display areas based on line-of-sight information. The first and second field-of-sight areas may be determined by the control device of the display device, or they may be determined by an external control device and received. The resolution of the higher priority area may be controlled to be higher than the resolution of the areas other than the higher priority area. In other words, the resolution of areas with relatively lower priority may be set lower.

[0199] AI may be used to determine the first field of view area and the areas with higher priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to the target object at the end of the line of sight from the image of the eye, using the image of the eye and the direction the eye was actually looking in that image as training data. The AI ​​program may be installed in the display device, the photoelectric converter, or an external device. If installed in an external device, it will be transmitted to the display device via communication.

[0200] When display control is based on visual detection, this method is preferably applicable to smart glasses that further include a photoelectric converter for capturing images of the surrounding environment. The smart glasses can display the captured external information in real time.

[0201] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways.

[0202] For example, examples in which some configurations of one embodiment are added to other embodiments, or in which some configurations of other embodiments are replaced, are also included as embodiments of the present invention.

[0203] Furthermore, the photoelectric conversion systems shown in the 9th and 10th embodiments above are merely examples of photoelectric conversion systems to which the photoelectric conversion device can be applied, and the photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 19 to 20B. The same applies to the ToF system shown in the 11th embodiment, the endoscope shown in the 12th embodiment, and the smart glasses shown in the 8th embodiment.

[0204] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0205] The present invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are attached to make the scope of the invention public.

Claims

1. An avalanche diode disposed in a semiconductor layer having a first surface and a second surface facing the first surface, A photoelectric conversion device having a first wiring structure in contact with the second surface, The avalanche diode is A first semiconductor region of a first conductivity type located at a first depth, A second semiconductor region of a second conductivity type is disposed at a second depth that is deeper with respect to the second surface than the first depth, The first semiconductor region and the second semiconductor region are provided with a third semiconductor region adjacent to the first semiconductor region, The photoelectric conversion device is A first wiring section electrically connected to the first semiconductor region, It further comprises a second wiring section electrically connected to the second semiconductor region, A first pad for applying a first voltage to the photoelectric converter is provided in the first wiring structure. An oxide film and a protective film laminated on the first wiring structure side of the oxide film are disposed on the second surface of the semiconductor layer. The thickness of the oxide film is d ｓｉｏ , the thickness of the protective film is d ｐｒｏｔ The relative permittivity of the oxide film is ε ｓｉｏ , the relative permittivity of the protective film is ε ｐｒｏｔ When that happens, d ｓｉｏ > (ε ｓｉｏ / ε ｐｒｏｔ ) × d ｐｒｏｔ There is a place that satisfies / 2, A photoelectric conversion device characterized in that, in a plan view, the second wiring portion overlaps with at least a part of the third semiconductor region and does not overlap with the first semiconductor region.

2. The photoelectric conversion device according to claim 1, characterized in that the oxide film is a silicon oxide film and the protective film is a nitride film.

3. The photoelectric conversion device according to claim 2, characterized in that the nitride film is a silicon oxynitride film or a silicon nitride film.

4. An avalanche diode disposed in a semiconductor layer having a first surface and a second surface facing the first surface, A photoelectric conversion device having a first wiring structure in contact with the second surface, The avalanche diode comprises a first semiconductor region of a first conductivity type arranged to a first depth, and a second semiconductor region of a second conductivity type arranged to a second depth that is deeper than the first depth relative to the second surface, The first semiconductor region and the second semiconductor region are provided with a third semiconductor region adjacent to the first semiconductor region, The photoelectric conversion device is A first wiring section electrically connected to the first semiconductor region, It further comprises a second wiring section electrically connected to the second semiconductor region, A first pad for applying a first voltage to the photoelectric converter is provided in the first wiring structure. An oxide film and a protective film laminated on the first wiring structure side of the oxide film are disposed on the second surface of the semiconductor layer. The oxide film is a silicon oxide film, the protective film is a silicon nitride film, and the thickness of the oxide film is d ｓｉｏ , the thickness of the protective film is d ｐｒｏｔ , the relative permittivity of the oxide film is ε ｓｉｏ , the relative permittivity of the protective film is ε ｐｒｏｔ . When set as such, d ｓｉｏ satisfies d > 15 nm, A photoelectric conversion device characterized in that, in a plan view, the second wiring portion overlaps with at least a part of the third semiconductor region and does not overlap with the first semiconductor region.

5. The photoelectric conversion apparatus according to any one of claims 1 to 4, characterized in that the protective film has a higher nitrogen content than the oxide film.

6. The photoelectric conversion device according to any one of claims 1 to 5, characterized in that the first surface is a light incident surface.

7. The photoelectric conversion device according to any one of claims 1 to 6, characterized in that it has a third semiconductor region provided between the first semiconductor region and the second semiconductor region, in contact with the second semiconductor region.

8. The photoelectric conversion device according to claim 7, characterized in that, in a plan view from the second surface, the area of ​​the first semiconductor region is smaller than the area of ​​the third semiconductor region.

9. The photoelectric conversion apparatus according to claim 7 or 8, characterized in that the impurity concentration in the third semiconductor region is lower than the impurity concentration in the first semiconductor region.

10. In a plan view from the second surface, in the region overlapping with the third semiconductor region, the oxide film and the protective film are d ｓｉｏ > (ε ｓｉｏ / ε ｐｒｏｔ ) × d ｐｒｏｔ The photoelectric conversion device according to any one of claims 7 to 9, characterized in that there is a portion that satisfies / 2.

11. An avalanche diode disposed in a semiconductor layer having a first surface and a second surface facing the first surface, A photoelectric conversion device having a first wiring structure in contact with the second surface, The avalanche diode comprises a first semiconductor region of a first conductivity type arranged to a first depth, A second semiconductor region of a second conductivity type is disposed at a second depth that is deeper with respect to the second surface than the first depth, The first semiconductor region and the second semiconductor region are provided with a third semiconductor region adjacent to the second semiconductor region, A first pad for applying a first voltage to the photoelectric converter is provided in the first wiring structure. An oxide film and a protective film laminated on the first wiring structure side of the oxide film are disposed on the second surface of the semiconductor layer. The thickness of the oxide film is d ｓｉｏ , the thickness of the protective film is d ｐｒｏｔ The relative permittivity of the oxide film is ε ｓｉｏ , the relative permittivity of the protective film is ε ｐｒｏｔ When that happens, d ｓｉｏ > (ε ｓｉｏ / ε ｐｒｏｔ ) × d ｐｒｏｔ There is a region that satisfies / 2, and in a plan view from the second surface, the region of the oxide film that overlaps with the third semiconductor region is d ｓｉｏ This is the region of the oxide film that does not overlap with the third semiconductor region, d ｓｉｏ A photoelectric converter characterized by being larger in size.

12. The oxide film and the protective film are d ｓｉｏ > (ε ｓｉｏ / ε ｐｒｏｔ ) × d ｐｒｏｔ A photoelectric conversion device according to any one of claims 1 to 11, characterized in that it has a portion that satisfies the requirements.

13. The thickness d of the protective film ｓｉｏ ga d ｓｉｏ A photoelectric conversion device according to any one of claims 1 to 10, characterized in that it satisfies >30 nm.

14. The photoelectric conversion device according to any one of claims 1 to 13, characterized in that, in a plan view from the second surface, the first semiconductor region is contained within the second semiconductor region.

15. The first wiring connected to the first semiconductor region, The second wiring connected to the second semiconductor region, The photoelectric conversion device according to any one of claims 1 to 14, characterized in that, in a plan view from the second surface, the area of ​​the first wiring is smaller than the area of ​​the second wiring.

16. In a plan view from the second surface, in the region overlapping with the edge of the first semiconductor region, the oxide film and the protective film are d ｓｉｏ > (ε ｓｉｏ / ε ｐｒｏｔ ) × d ｐｒｏｔ The photoelectric conversion device according to any one of claims 1 to 15, characterized in that there is a portion that satisfies / 2.

17. The photoelectric conversion device according to any one of claims 1 to 15, characterized in that it has a fourth semiconductor region of the second conductivity type, which is disposed at a third depth that is deeper with respect to the second surface than the second depth.

18. A fifth semiconductor region of the first conductivity type is provided between the second semiconductor region and the fourth semiconductor region. The photoelectric conversion apparatus according to claim 17, characterized in that the impurity concentration of the first conductivity type in the fifth semiconductor region is lower than the impurity concentration of the first conductivity type in the first semiconductor region.

19. The photoelectric conversion device according to claim 18, characterized in that the potential difference between the first semiconductor region and the second semiconductor region is greater than the potential difference between the second semiconductor region and the fifth semiconductor region.

20. The avalanche diode includes a first avalanche diode and a second avalanche diode adjacent to the first avalanche diode. The photoelectric conversion device according to any one of claims 1 to 19, characterized in that it has a pixel separation section between the first avalanche diode and the second avalanche diode.

21. The avalanche diode includes a third avalanche diode adjacent to the second avalanche diode. A first pixel separation section is provided between the first avalanche diode and the second avalanche diode. A second pixel separation section is provided between the second avalanche diode and the third avalanche diode. The photoelectric conversion device according to claim 20, characterized in that the second semiconductor region in the second avalanche diode extends from the first pixel separation portion to the second pixel separation portion in a cross section perpendicular to the first plane.

22. The photoelectric conversion apparatus according to any one of claims 1 to 19, characterized in that the oxide film comprises a plurality of layers having at least one different physical properties or chemical composition.

23. The photoelectric conversion device according to claim 22, characterized in that, among the plurality of layers, the layer closer to the second surface is thinner than the layer further away from the second surface.

24. The photoelectric conversion apparatus according to claim 22 or 23, characterized in that the plurality of layers include layers of oxynitride film.

25. A photoelectric conversion device having a second wiring structure in contact with the first wiring structure, The photoelectric converter according to any one of claims 1 to 24, characterized in that a second pad for applying a second voltage to the photoelectric converter is provided in the first wiring structure.

26. The photoelectric conversion device according to claim 25, characterized in that the second wiring structure includes a plurality of wiring layers, and the second pad is provided on one of the plurality of wiring layers.

27. An avalanche diode disposed in a semiconductor layer having a first surface and a second surface facing the first surface, A photoelectric conversion device having a first wiring structure in contact with the second surface and a second wiring structure in contact with the first wiring structure, The avalanche diode is A first semiconductor region of a first conductivity type located at a first depth, A second semiconductor region of a second conductivity type is disposed at a second depth that is deeper with respect to the second surface than the first depth, The first semiconductor region and the second semiconductor region are provided with a third semiconductor region adjacent to the first semiconductor region, The photoelectric conversion device is A first wiring section electrically connected to the first semiconductor region, It further comprises a second wiring section electrically connected to the second semiconductor region, A first pad for applying a first voltage to the photoelectric converter is provided in the second wiring structure. An oxide film and a protective film laminated on the first wiring structure side of the oxide film are disposed on the second surface of the semiconductor layer. When the thickness of the oxide film is dsio, the thickness of the protective film is dprot, the relative permittivity of the oxide film is εsio, and the relative permittivity of the protective film is εprot, there is a region where dsio > (εsio / εprot) × dprot / 2. A photoelectric conversion device characterized in that, in a plan view, the second wiring portion overlaps with at least a part of the third semiconductor region and does not overlap with the first semiconductor region.

28. An avalanche diode disposed in a semiconductor layer having a first surface and a second surface facing the first surface, A photoelectric conversion device having a first wiring structure in contact with the second surface and a second wiring structure in contact with the first wiring structure, The avalanche diode is A first semiconductor region of a first conductivity type located at a first depth, A second semiconductor region of a second conductivity type is disposed at a second depth that is deeper with respect to the second surface than the first depth, The first semiconductor region and the second semiconductor region are provided with a third semiconductor region adjacent to the first semiconductor region, The photoelectric conversion device is A first wiring section electrically connected to the first semiconductor region, It further comprises a second wiring section electrically connected to the second semiconductor region, A first pad for applying a first voltage to the photoelectric converter is provided in the second wiring structure. An oxide film and a protective film laminated on the first wiring structure side of the oxide film are disposed on the second surface of the semiconductor layer. The oxide film is a silicon oxide film, the protective film is a silicon nitride film, and when the thickness of the oxide film is dSiO, the thickness of the protective film is dProt, the relative permittivity of the oxide film is εSiO, and the relative permittivity of the protective film is εProt, the condition dSiO > 15 nm is satisfied. A photoelectric conversion device characterized in that, in a plan view, the second wiring portion overlaps with at least a part of the third semiconductor region and does not overlap with the first semiconductor region.

29. The photoelectric conversion device according to claim 26 or 27, characterized in that a second pad for applying a second voltage is provided in the second wiring structure.

30. The photoelectric conversion device according to any one of claims 1 to 29, characterized in that the first wiring structure includes a plurality of wiring layers, and the first pad is provided on one of the plurality of wiring layers.

31. The plurality of wiring layers included in the first wiring structure include wiring mainly composed of copper, The photoelectric conversion device according to claim 30, characterized in that the main component of the first pad is aluminum.

32. A first wiring section electrically connected to the first semiconductor region, It has a second wiring section electrically connected to the second semiconductor region, The photoelectric conversion device according to any one of claims 1 to 31, characterized in that, in a plan view, the second wiring portion overlaps with at least a part of the second semiconductor region and does not overlap with the first semiconductor region.

33. A photoelectric conversion device according to any one of claims 1 to 32, A photoelectric conversion system characterized by having a signal processing unit that generates an image using the signal output by the aforementioned photoelectric conversion device.

34. A mobile body comprising a photoelectric converter according to any one of claims 1 to 32, A mobile body characterized by having a control unit that controls the movement of the mobile body using a signal output by the photoelectric converter.

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