Semiconductor equipment

Abstract

To make it easier to extract carriers near an end part of a trench part.SOLUTION: A semiconductor device includes: a plurality of mesa regions that are regions between longitudinal parts of adjacent trench parts and include a first mesa region and a second mesa region; a well region of a first conductivity type provided at an end part of the mesa region in a first direction to a deeper position than the trench part from a surface of a semiconductor substrate; and a first opening, a second opening, a third opening, and a fourth opening provided in the insulating film. The first opening electrically connects the well region and a metal electrode in the first mesa region. The second opening and the third opening electrically connect the base region and the metal electrode in the first mesa region. The fourth opening is provided continuously from a position of the second opening beyond a position of the third opening that is closest to the second opening in the first direction and connects between the second mesa region and the metal electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a semiconductor device.

[0002] Conventionally, in semiconductor devices having an insulated-gate bipolar transistor (IGBT), an opening was provided in the interlayer insulating film provided on the floating region, and the floating region and the emitter electrode provided on the interlayer insulating film were connected through this opening (see, for example, Patent Documents 1 and 2). [Prior art document] [Patent] [Patent Document 1] Japanese Unexamined Patent Publication No. 2005-175425 [Patent Document 2] Japanese Unexamined Patent Publication No. 2007-324539 [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] In a top view of the semiconductor substrate, the floating region is a rectangular region with its longer side in the longitudinal direction of the gate trench, for example, because it is surrounded by the gate trench. Since the shorter side located at the longitudinal end of the gate trench does not have an N+ type emitter region or a P+ type contact region, carriers generated during IGBT switching tend to accumulate there. It is desirable to make it easier to extract carriers near the ends of the trench. [Means for solving the problem]

[0004] A first embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a metal electrode provided on the insulating film. In the above semiconductor device, the semiconductor substrate may include a base region of a first conductivity type, a trench portion provided from the surface of the semiconductor substrate to a position deeper than the base region and having a longitudinal portion in a first direction, and a plurality of mesa regions between adjacent longitudinal portions, including a first mesa region and a second mesa region. In any of the above semiconductor devices, the semiconductor substrate may include a well region of a first conductivity type provided at the first direction end of the mesa region to a position deeper from the surface of the semiconductor substrate to a position deeper than the trench portion, and a first opening, a second opening, a third opening, and a fourth opening provided in the insulating film. In any of the above semiconductor devices, the first opening may electrically connect the well region and the metal electrode in the first mesa region. In any of the above semiconductor devices, the second and third openings may electrically connect the base region and the metal electrode in the first mesa region. In any of the semiconductor devices described above, the fourth aperture may be provided continuously in the first direction from the position of the second aperture to the position of the third aperture that is closest to the second aperture, and may connect the second mesa region and the metal electrode.

[0005] In any of the semiconductor devices described above, the distance between the first aperture and the second aperture may be shorter than the distance between the second aperture and the third aperture that is closest to the second aperture.

[0006] In any of the above-described semiconductor devices, the semiconductor substrate may include a second conductivity type emitter region provided in the second mesa region and in contact with a metal electrode through the fourth aperture.

[0007] In any of the semiconductor devices described above, the first aperture, the second aperture, and the third aperture may be aligned in a straight line in the first direction.

[0008] In any of the semiconductor devices described above, plugs made of a stack of a barrier metal and tungsten may be provided in the first opening, the second opening, the third opening, and the fourth opening.

[0009] In any of the semiconductor devices described above, the semiconductor substrate may include a contact region of the second conductivity type having a doping concentration higher than that of the base region directly below the first opening, the second opening, or the third opening. In any of the semiconductor devices described above, the contact region may also be provided directly below the fourth opening.

[0010] In any of the semiconductor devices described above, the first opening may be provided outside the emitter region that is located most outward in the second mesa region in the first direction.

[0011] In any of the semiconductor devices described above, the base region of the first mesa region may be a floating semiconductor region.

[0012] In any of the semiconductor devices described above, the trench portion may have a short side portion in the second direction. In any of the semiconductor devices described above, the first mesa region may be surrounded by the longitudinal portion and the short side portion.

[0013] In any of the semiconductor devices described above, the mesa widths of the first mesa region and the second mesa region may be different.

[0014] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0015] [Figure 1A] It is a top view of the semiconductor device 100 in the first embodiment. [Figure 1B] It is a top view of a modified example of the semiconductor device 100 in the first embodiment. [Figure 2]This is an enlarged view of area A in Figures 1A and 1B. [Figure 3] This is a diagram showing the B-B section in Figure 2. [Figure 4] This is a diagram showing the C-C cross-section in Figure 2. [Figure 5] This is a diagram showing the section D-D in Figure 2. [Figure 6] Figure 5 shows the n-type net doping concentration distribution at E-E. [Figure 7] This is the simulation result of the time evolution of hole concentration. [Figure 8] These are the simulation results for VGE, VCE, and IC during low-current turn-off. [Figure 9] These are the simulation results for VGE, VCE, and IC during high-current turn-off. [Figure 10] This is a simulation result showing the relationship between Ic and the surge voltage at VCE at each distance L2. [Figure 11] This is a simulation result showing the relationship between Ic and Eoff at each distance L2. [Figure 12] This is a top view showing the vicinity of the outer end of the trench portion 40 in the second embodiment. [Figure 13] This is a top view showing the vicinity of the outer end of the trench portion 40 in the third embodiment. [Figure 14] This is a top view showing the vicinity of the outer end of the trench portion 40 in the fourth embodiment. [Figure 15] This is a modified example of area B in Figures 1A and 1B. [Figure 16] This figure shows a part of the circuit 200 of a welding machine equipped with a semiconductor device 100. [Modes for carrying out the invention]

[0016] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0017] In this specification, one side of the semiconductor substrate 10 in the direction parallel to the depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity. In each embodiment, an example is shown in which the first conductivity type is P-type and the second conductivity type is N-type, but in other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. Note that P+ type means that the doping concentration is higher than that of P-type, and P-type means that the doping concentration is higher than that of P-type. Similarly, N+ type means that the doping concentration is higher than that of N-type, and N-type means that the doping concentration is higher than that of N-type.

[0018] Furthermore, in this specification, the X and Y axes are orthogonal to each other. The X and Y axes are parallel to the front surface of the semiconductor substrate 10. The axis orthogonal to the X and Y axes is defined as the Z axis. In this specification, the Z axis direction is parallel to the depth direction of the semiconductor substrate 10.

[0019] Figure 1A is a top view of the semiconductor device 100 in the first embodiment. Figure 1B is a top view of a modified example of the semiconductor device 100 in the first embodiment. Figure 1A is also a top view of the semiconductor substrate 10. The semiconductor device 100 may be read as a semiconductor chip. The semiconductor device 100 in this example has a semiconductor substrate 10. The semiconductor device 100 in this example has an active portion 80, a pad portion 95 and an edge termination structure 90.

[0020] The active region 80 may refer to a region in the thickness direction of the semiconductor substrate 10 through which current flows. In this example, the active region 80 has a transistor region including a transistor such as an IGBT. In this example, the transistor region is a region obtained by projecting the collector region located on the back side onto the front side of the semiconductor substrate 10 in a direction perpendicular to the back side of the semiconductor substrate 10, and includes an emitter region (emitter region 12 described later) and a contact region (contact region 16 described later), and is a region in which predetermined unit configurations are regularly arranged.

[0021] The active portion 80 may have a diode region including a diode such as an FWD (Free Wheeling Diode). In this example, the diode region is the region obtained by projecting the cathode region located on the back side in a direction perpendicular to the back surface of the semiconductor substrate 10 onto the front surface of the semiconductor substrate 10, or the back surface region that coincides with the cathode region.

[0022] The semiconductor device 100 in this example is an IGBT semiconductor chip. However, the semiconductor device 100 may also be an RC-IGBT (Reverse Conducting-IGBT) semiconductor chip in which the IGBT and FWD are provided on a single semiconductor substrate 10.

[0023] In this example, the edge termination structure 90 surrounds the active portion 80. The edge termination structure 90 may have the function of mitigating electric field concentration near the surface of the semiconductor substrate 10. The edge termination structure 90 may have, for example, a guard ring, a field plate, a resurf, or a structure combining these.

[0024] The pad portion 95 may be provided between the active portion 80 and the edge termination structure 90. In this example, the pad portion 95 is provided in a region where a part of the active portion 80 has been cut out. In this example, the pad portion 95 has a rectangular shape, with three sides in contact with the active portion 80 and the remaining side in contact with the edge termination structure 90. The pad portion 95 has, for example, a gate pad to which a gate terminal is electrically connected. The gate terminal may supply a gate potential to the IGBT of the active portion 80. The pad portion 95 may further have one or more electrode pads, such as an electrode pad for temperature sensing and an electrode pad for a sense IGBT. Alternatively, as shown in Figure 1B, the pad portion 95 may be positioned at the corner of the active portion 80 such that two sides are in contact with the active portion 80 and the remaining two sides are in contact with the edge termination structure 90.

[0025] Figure 2 is an enlarged view of region A in Figures 1A and 1B. The semiconductor device 100 in this example has an emitter electrode 52 and a gate metal layer 55. The emitter electrode 52 and the gate metal layer 55 may be formed from a metal-containing material. For example, at least a portion of each electrode may be formed from aluminum or an aluminum-silicon alloy.

[0026] An interlayer insulating film is provided between the surface of the semiconductor substrate 10 and the gate metal layer 55 and emitter electrode 52. However, for the purpose of facilitating understanding, the interlayer insulating film is omitted in Figure 2. The interlayer insulating film has multiple openings that penetrate it. These multiple openings include a first opening 31, a second opening 32, a third opening 33, a fourth opening 35, and an opening 54. In this specification, openings in the interlayer insulating film may be read as contact holes.

[0027] Region A in this example is a region that includes three trenches 40 adjacent to the edge termination structure 90. For the sake of explanation, in this example, the trenches will be referred to as the first trench 40-1, the second trench 40-2, and the third trench 40-3, starting from the one closest to the inside. Each trench 40 has a trench insulating film, a trench conductive portion, and a trench, which will be described later. Since each trench 40 in this example is a gate trench, the trench insulating film may be read as a gate insulating film, and the trench conductive portion may be read as a gate conductive portion. The width of the trench 40 is, for example, 1 μm.

[0028] The trench section 40 in this example has longitudinal sections 46 and transverse sections 47. The trench section 40 in this example has a substantially rectangular shape, with its four sides defined by two longitudinal sections 46 and two transverse sections 47. However, the corners of the rectangular shape may be smoothly connected by curves between the longitudinal sections 46 and the transverse sections 47.

[0029] In this example, the longitudinal portion 46 has an inner longitudinal portion 46-1 and an outer longitudinal portion 46-2, and the transverse portion 47 has an inner transverse portion 47 and an outer transverse portion 47. In this example, in the Y-axis direction, the position closer to the edge termination structure 90 is referred to as the outer side, and the position closer to the center of the active portion 80 is referred to as the inner side. The Y-axis direction is also the direction parallel to the longitudinal portion 46. In this example, the semiconductor device 100 may have the same structure as region A at the end opposite region A in the Y-axis direction.

[0030] In this example, the semiconductor substrate 10 has a mesa region 60 containing an emitter region 12 of a second conductivity type, a base region 14 of a first conductivity type, and a contact region 16 of a first conductivity type. In this example, the mesa region 60 is a region of the semiconductor substrate 10 located between the longitudinal portions 46-1 and 46-2 of adjacent trench portions 40, and above the bottom of the trench portion 40. The longitudinal portion 46-1 of the trench portion 40 is an example of a first trench portion, and the longitudinal portion 46-2 of the trench portion 40 is an example of a second trench portion.

[0031] The short portion 47 may be located below the gate runner 51. The trench conductive portion of the short portion 47 may be electrically connected to the gate runner 51. The opening 54 is provided on the gate runner 51, which is located outward in the Y-axis direction from the trench portion 40. The gate runner 51 may be electrically connected to the gate metal layer 55 through the opening 54, and the gate potential may be supplied to the trench conductive portion through the gate runner 51.

[0032] In this example, the emitter region 12 is an N+ type semiconductor region, the base region 14 is a P- type semiconductor region, and the contact region 16 is a P+ type semiconductor region. The emitter region 12 may be formed by selectively ion-implanting N-type impurities into the base region 14, and the contact region 16 may be formed by selectively ion-implanting P-type impurities into the base region 14.

[0033] In this example, P+ type well regions 17 are provided at both ends of the mesa region 60 in the Y-axis direction. In the mesa region 60 between the two well regions 17, the base region 14, the contact region 16, and the emitter region 12 may be alternately exposed on the surface of the semiconductor substrate 10 in the Y-axis direction. However, the base region 14 may be provided at a position in contact with the well region 17.

[0034] In the mesa region 60, the base region 14 and the contact region 16 may be alternately exposed on the surface of the semiconductor substrate 10 in the X-axis direction. In the mesa region 60 of this example, the contact region 16 is located between the base region 14 in contact with the longitudinal portion 46-1 and the base region 14 in contact with the longitudinal portion 46-2 in the X-axis direction.

[0035] However, in the mesa region 60 adjacent to the well region 17, one contact region 16 does not divide the base region into two regions. In this region, one side of the contact region 16 is adjacent to the emitter region 12, and the remaining three sides of the contact region 16 that protrude outward or inward from the emitter region 12 are surrounded by the base region 14.

[0036] In this example, the fourth aperture 35 is provided on the mesa region 60. The range of the fourth aperture 35 is shown by a dotted line. The fourth aperture 35 may be provided at a position corresponding to the contact region 16 of the mesa region 60. In this example, the fourth aperture 35 is provided continuously in the mesa region 60, from the outermost contact region 16 to the innermost contact region 16, parallel to the Y-axis direction. In other words, the fourth aperture 35 in this example is also provided on the emitter region 12 sandwiched between two contact regions 16 in the Y-axis direction.

[0037] Furthermore, the fourth opening 35 may have a width corresponding to the width of the contact area 16 in the X-axis direction. In this example, the fourth opening 35 has a width that is the same as or narrower than the width of the contact area 16 in the X-axis direction. However, for the sake of clarity in the drawing, the outer shape of the fourth opening 35 is shown on the outer circumference of the contact area 16 in Figure 2.

[0038] The floating semiconductor region 30 may be provided to a predetermined depth from the surface of the semiconductor substrate 10. In this example, the floating semiconductor region 30 is a region that, when the semiconductor device 100 is viewed from above, is at least partially exposed on the surface of the semiconductor substrate 10 and surrounded by the trench portion 40. The floating semiconductor region 30 may have a substantially rectangular shape, which is longer in the Y-axis direction than in the X-axis direction. The floating semiconductor region 30 may be a region of the semiconductor substrate 10 located above the bottom of the trench portion 40 in a cross-sectional view of the semiconductor device 100.

[0039] In this example, the floating semiconductor region 30 has an outer end 38 at the -Y-axis direction and an inner end at the Y-axis direction. Note that the inner end is omitted in Figure 2 for illustrative purposes. In this example, the outer end 38 of the floating semiconductor region 30 is in contact with the short side portion 47 of the trench portion 40, and the inner end of the floating semiconductor region 30 is in contact with another short side portion 47. In the floating semiconductor region 30, the end region including the outer end 38 and the end region including the inner end may each be a P+ type well region 17. In contrast, in the floating semiconductor region 30, the regions other than the end regions may be the same P- type semiconductor region as the base region 14. Also, the depth of the floating semiconductor region 30 may be greater than the depth of the base region 14.

[0040] The floating semiconductor region 30 does not necessarily have to be electrically isolated from the emitter electrode 52. In other words, the floating semiconductor region 30 does not have to be completely electrically floating. In this example, the floating semiconductor region 30 is electrically connected to the emitter electrode 52 through the first aperture 31, the second aperture 32, and the third aperture 33.

[0041] The first aperture 31, the second aperture 32, and the third aperture 33 may be aligned in a straight line along the Y-axis. In this example, one first aperture 31, one second aperture 32, and multiple third apertures 33 are provided on the floating semiconductor region 30. The first aperture 31 may be closest to the outer edge 38 of the floating semiconductor region 30 in the Y-axis direction. In this example, the first aperture 31, the second aperture 32, and the third aperture 33 are closest to the outer edge 38 in this order along the Y-axis direction. The first aperture 31 may be located on the well region 17 of the floating semiconductor region 30, or it may be located in a region inside the well region 17 (i.e., a P-type region). In this example, the first aperture 31 is located on the well region 17.

[0042] The second opening 32 may be the second closest to the outer edge 38 of the floating semiconductor region 30 in the Y-axis direction. The distance between the first opening 31 and the second opening 32 may be shorter than the distance between any two adjacent openings other than the first opening 31 among the multiple openings. This improves carrier (e.g., holes) extraction compared to the case where openings are provided at equal intervals in the Y-axis direction on the floating semiconductor region 30. Therefore, the carrier density in the shorter portion 47 of the trench 40 can be reduced.

[0043] In this example, the distance between openings refers to the distance between the centers of the two openings. However, in other examples, the distance between openings may refer to the shortest distance between adjacent sides of the two openings. In this example, the distance L1 between the first opening 31 and the second opening 32 is the distance between the center of the first opening 31 and the center of the second opening 32. Similarly, the distance L2 between the second opening 32 and the third opening 33 is the distance between the center of the second opening 32 and the center of the third opening 33.

[0044] Distance L1 may be between 30 μm and 60 μm. In this example, distance L1 is 50 μm. Distance L2 may be between 50 μm and 100 μm, or between 70 μm and 80 μm. In this example, distance L2 is 65 μm. In this example, the distance between two adjacent third apertures 33 is also distance L2. Therefore, in this example, distance L1 is shorter than the distance between all two adjacent apertures other than the first aperture 31 among the multiple apertures. However, distance L1 is assumed to be smaller than distance L2. Distance L1 may be 80% or less of distance L2, or 50% or less.

[0045] The first opening 31 may be located closer to the short side portion 47 than the outermost N+ type emitter region 12 in the mesa region 60. The inner end of the first opening 31 in the Y-axis direction may be located further out than the outer end of the contact region 16 in the Y-axis direction, which is located furthest out in the Y-axis direction. In this example, the distance L between the inner end of the first opening 31 in the Y-axis direction and the outer end of the contact region 16 in the Y-axis direction, which is located furthest out in the Y-axis direction, is... s It is 6 μm.

[0046] Lt is the distance between the center of the first aperture 31 and the outer edge 38 of the floating semiconductor region 30. The distance Lt may be 1 μm or more and 10 μm or less, or 2 μm or more and 5 μm or less. By bringing the first aperture 31 closer to the outer edge 38, the extraction of carriers accumulated near the outer short side portion 47 can be improved.

[0047] The first aperture 31, the second aperture 32, and the third aperture 33 may each be rectangular in shape. In this example, the first aperture 31, the second aperture 32, and the third aperture 33 are each square in shape, with the length of each side of the square being 2 μm. However, the shape of the aperture and the length of the sides of the aperture are not limited to those of this example.

[0048] Furthermore, to improve carrier extraction, at least one of the following methods can be considered for the multiple openings provided on the floating semiconductor region 30: increasing the number of openings or narrowing the spacing between the openings. However, in this case, carriers will be excessively extracted from the floating semiconductor region 30 compared to this example, resulting in a saturation voltage: V CE (sat) becomes higher. Also, compared to this example, in the case of reducing the number of apertures and widening the spacing between apertures, at least one of these cases results in carriers being less extracted from the floating semiconductor region 30 and remaining in that state, so the V at turn-on is higher. CE There is a problem with the surge voltage becoming high.

[0049] Therefore, it is desirable to suppress carrier extraction to a certain level by arranging the openings on the floating semiconductor region 30 at predetermined equal intervals, while also making it easier to extract carriers near the Y-axis end of the trench portion 40 where carriers tend to accumulate, compared to areas other than the end. In this example, an improved arrangement of openings on the floating semiconductor region 30 is provided to achieve this. The number of openings located on the floating semiconductor region 30 may be appropriately calculated from the Y-axis length of the longitudinal portion 46 of the trench portion 40 and the interval between the openings as described above.

[0050] Figure 3 shows the B-B cross-section of Figure 2. The B-B cross-section is a cross-section parallel to the XZ plane, passing through the emitter region 12 and the third aperture 33. In Figure 3, the front surface 11 and back surface 19 of the semiconductor substrate 10 are clearly shown.

[0051] The semiconductor device 100 includes a collector electrode 24, an interlayer insulating film 28, and an emitter electrode 52. The collector electrode 24 may be made of a conductive material such as a metal. At least a portion of the emitter electrode 52 is provided on the interlayer insulating film 28. In this example, the emitter electrode 52 is provided on the interlayer insulating film 28 and in each opening in the interlayer insulating film 28. However, in other examples, each opening in the interlayer insulating film 28 may be provided with a plug consisting of a laminate of barrier metal and tungsten. In these other examples, the emitter electrode 52 is provided on the interlayer insulating film 28 and the plug.

[0052] The semiconductor substrate 10 includes a collector region 22, a field stop (FS) layer 20, a drift region 18, and a base region 14 in the direction from the back surface 19 to the front surface 11 (+Z axis direction). The collector region 22 is a first-conductivity type semiconductor region. In this example, the collector region 22 is a P+ type semiconductor region. The lower surface of the collector region 22 may be exposed to the back surface 19 of the semiconductor substrate 10. In this example, the lower surface of the collector region 22 corresponds to the back surface 19 of the semiconductor substrate 10. By reducing the P-type doping concentration of the collector region 22, the carrier density of the drift region 18 during IGBT operation can be reduced. An FS layer 20 is provided on the upper surface of the collector region 22.

[0053] The FS layer 20 is a second-conductivity semiconductor layer. The FS layer 20 may be located on the collector region 22. The FS layer 20 may have one or more N-type doping concentration peaks discretely arranged in the Z-axis direction. In one example, when ion implanting protons from the back surface 19 of the semiconductor substrate 10, the acceleration energy of ion implantation may be adjusted to adjust the range in the depth direction. This may form one or more N-type doping concentration peaks. In this example, the FS layer 20 is an N+ type semiconductor layer.

[0054] The drift region 18 is a semiconductor region of the second conductivity type. The drift region 18 may be located on the FS layer 20. The N-type doping concentration of the drift region 18 is lower than the N-type doping concentration of the FS layer 20. In this example, the drift region 18 is an N-type semiconductor region.

[0055] The base region 14 is a semiconductor region of the first conductivity type. The base region 14 may be located on the drift region 18. In this example, the base region 14 is a P-type semiconductor region.

[0056] The trench portion 40 is provided from the surface 11 of the semiconductor substrate 10 to a predetermined depth. In this example, the trench portion 40 penetrates the base region 14 and reaches the drift region 18. The bottom of the trench portion 40 is in contact with the drift region 18. Each trench portion 40 has a trench 44, a trench insulating film 42, and a trench conductive portion 43. In each trench portion 40, the trench insulating film 42 may be formed in contact with the inner wall of the trench 44, and the trench conductive portion 43 may be formed in contact with the inner wall of the trench insulating film 42.

[0057] An emitter region 12 is located on the base region 14 of the mesa region 60, which is situated between the first trench portion 40-1 and the second trench portion 40-2. The emitter region 12 is in contact with the first trench portion 40-1 and the second trench portion 40-2 in the X-axis direction. The emitter region 12 is electrically connected to the emitter electrode 52 through the fourth opening 35 of the interlayer insulating film 28. Similarly, the emitter region 12 between the second trench portion 40-2 and the third trench portion 40-3 is in contact with the second trench portion 40-2 and the third trench portion 40-3, and is electrically connected to the emitter electrode 52 through the fourth opening 35.

[0058] In the X-axis direction, the distance between two adjacent trenches 40 separated by a mesa region 60 may be approximately half the distance between two adjacent trenches 40 separated by a floating semiconductor region 30. In this example, the distance L3 between the X-axis center position of the first trench 40-1 and the X-axis center position of the second trench 40-2 is 1.5 μm or more and 5.0 μm or less (for example, 3.0 μm). In contrast, the distance L5 between the X-axis center position of the second trench 40-2 and the X-axis center position of the third trench 40-3 is, for example, 3.0 μm. In this example, the distance L4 between the X-axis center positions in the longitudinal portion 46 of the second trench 40-2 is 2 μm or more and 10 μm or less (for example, 6.0 μm). The width of the trench 40 in the X-axis direction is 1 μm. However, these values ​​are merely examples and can, of course, be changed as appropriate depending on the design of the semiconductor device 100.

[0059] In this example, the floating semiconductor region 30 has a base region 14 and a contact region 37. The contact region 37 is a semiconductor region of the first conductivity type. In this example, the contact region 37 is a P+ type semiconductor region. The contact region 37 is provided in the base region 14, and at least a portion of it may be exposed to the surface 11.

[0060] The contact regions 37 in the floating semiconductor region 30 may be provided in positions corresponding to the locations where multiple openings are provided. In Figure 3, the contact region 37 is located directly below the third opening 33. However, the contact regions 37 may be provided directly below the first opening 31, the second opening 32, and the third opening 33, respectively. This improves the extraction of carriers from the floating semiconductor region 30 to the emitter electrode 52 compared to the case where no contact regions 37 are provided.

[0061] Figure 4 shows the C-C cross-section of Figure 2. The C-C cross-section is a cross-section parallel to the XZ plane that passes through the base region 14 and contact region 16 of the mesa region 60 but does not pass through the emitter region 12 and the third aperture 33. As shown in Figure 4, the floating semiconductor region 30 in this example does not have a contact region 37 in positions where no aperture is provided in the interlayer insulating film 28. The floating semiconductor region 30 also does not have a contact region 37 in positions where the first aperture 31 or the second aperture 32 is not provided.

[0062] Figure 5 shows the D-D cross-section of Figure 2. The D-D cross-section is a cross-section parallel to the YZ plane, passing through the first opening 31, the floating semiconductor region 30, and the outer short side portion 47 of the second trench portion 40-2. In this example, the width D in the Y-axis direction of the trench portion 40 is TY The width is 1 μm, and the width D in the Y-axis direction of the first aperture 31 is 1 μm. Y The width is 2 μm. However, the width D of the trench portion 40 TY and the width D of the first opening 31 Y This is not limited to the length in this example.

[0063] An oxide film 26 is provided between the gate runner 51 and the surface 11. The oxide film 26 is, for example, a thermal oxide film of silicon. The oxide film 26 may electrically isolate the gate runner 51 and the surface 11. However, the oxide film 26 has an opening at the top of the trench portion 40. The gate runner 51 and the trench conductive portion 43 may be electrically connected through this opening.

[0064] In this example, the well region 17 is provided from the surface 11 to a position deeper than the trench portion 40. The bottom of the well region 17 is located below the bottom of the trench portion 40. In this example, the well region 17 is located at a depth D from the surface 11. W The thickness is 8 μm. Channel formation is not required in the vicinity of the trench portion 40 (i.e., the short portion 47) located in the well region 17. In other words, it can be assumed that no collector current (Ic) flows in the vicinity of the trench portion 40 (i.e., the short portion 47) whose bottom is covered by the well region 17.

[0065] The well region 17 may extend from the outside to the inside of the trench region 40 and extend to a position directly below the first opening 31. In this example, the inner end of the contact region 37 of the floating semiconductor region 30 is located outward in the Y-axis direction compared to the inner end of the well region 17. In other words, the well region 17 is located directly below the contact region 37.

[0066] If the contact region 37 were not located directly above the well region 17, carriers directly below the trench region 40 could remain accumulated in the well region 17. In other words, carriers directly below the trench region 40 could continue to accumulate in the well region 17. In contrast, in this example, since the well region 17 is located directly below the contact region 37, in addition to the carriers directly below the contact region 37, carriers directly below the trench region 40 can also be drawn to the emitter electrode 52 through the contact region 37. In this way, the carrier density near the short portion 47 of the trench region 40 can be reduced. Furthermore, in this example, as a result of the reduction in carrier density near the short portion 47 of the trench region 40, the carrier density in the drift region 18 below the edge termination structure 90 is also reduced.

[0067] Figure 6 shows the n-type doping concentration distribution at E-E in Figure 5. E-E passes through the collector region 22, the FS layer 20, and the drift region 18 in a direction parallel to the Z-axis direction. The vertical axis represents the net doping concentration, and the horizontal axis represents the depth position from the back surface 19 to the front surface 11. In Figure 6, the back surface 19 is indicated as depth position zero.

[0068] The FS layer 20 may have one or more doping concentration peaks in the depth direction. In this example, the FS layer 20 has one doping concentration peak. However, in other examples, the FS layer 20 may have two or more doping concentration peaks.

[0069] Of the peaks of one or more doping concentrations, the peak closest to the surface 11 may be located at least 5 μm away from the back surface 19. The peak closest to the surface 11 may be located at least 6 μm away, or even at least 8 μm away. In this example, one doping concentration peak is located at least 5 μm away. In other examples where the FS layer 20 has two or more doping concentration peaks, the peak closest to the surface 11 may be located at least 5 μm away.

[0070] In this example, carriers (holes in this example) are more likely to remain between the peak closest to the front surface 11 and the back surface 19 in the FS layer 20, compared to the case where the position of the peak closest to the front surface 11 is less than 5 μm. Therefore, the slope of the tail current (i) flowing through the semiconductor device 100 during turn-off becomes gentle. As a result, the di / dt and V CE surge voltage becomes smaller.

[0071] Note that reducing the di / dt and V CE surge voltage during turn-off is also related to the arrangement of the openings on the floating semiconductor region 30. As described above, by setting the distance L2 to 100 μm or less, the carrier density during turn-on in the floating semiconductor region 30 is reduced. As a result, compared to the case where the carrier density is not reduced as in this example, the depletion layer is more likely to expand during turn-off, so the time until the depletion layer reaches the FS layer 20 becomes shorter.

[0072] Also, when the depletion layer reaches the FS layer 20 which is N+-type, it becomes difficult for it to expand further. Therefore, the depletion layer does not reach the region between the back surface 19 and the peak closest to the front surface 11. The carriers remaining between the back surface 19 and the peak closest to the front surface 11 are not drawn out by the depletion layer and are only drawn out by the recombination of holes and electrons, so it takes time to draw them out. As a result, the di / dt and V CE surge voltage becomes smaller.

[0073] Figure 7 shows the simulation results of the time change of the hole concentration. In particular, Figure 7 shows the hole concentration between the emitter region 12 and the collector region 22 on a straight line parallel to the Z-axis direction passing through the emitter region 12. The vertical axis is 1.0×10 14 / cm 3The hole concentration is normalized based on ), and the horizontal axis is depth [μm]. Note that -80 [μm] corresponds to the back surface 19, and 0 [μm] corresponds to the front surface 11. In this example, the doping concentration peak closest to the front surface 11 is set at -74 [μm] (i.e., 6.0 [μm] from the back surface 19). Multiple lines show the state as time has passed since the turn-off (solid line). As shown in Figure 7, in the drift region 18, the hole concentration decreases by about half. In contrast, in the FS layer 20, the degree of decrease in hole concentration is significantly smaller compared to the drift region 18.

[0074] Figure 8 shows V during low-current turn-off. GE , V CE and I c This is the simulation result. The horizontal axis represents time. The scale width of the horizontal axis is 200 ns. The vertical axis represents the gate-emitter voltage V. GE , collector-emitter voltage V CE , collector current I C Low-current turn-off refers to a collector current of I C This refers to turn-off when the collector current I is relatively small. C The value is 10[A].

[0075] In this example, di / dt was increased by reducing the carrier density through the arrangement of apertures on the floating semiconductor region 30 and by reducing the P-type doping concentration in the collector region 22. C Compared to the high-current turn-off described later, it settled to zero more quickly. However, as a result of increasing di / dt, V CE The surge voltage increases. However, V CE and I C Since the turn-off loss Eoff, which is expressed as the product of the two factors, can be reduced, this is particularly advantageous for semiconductor device 100 that repeatedly performs low-current turn-on / low-current turn-off.

[0076] Figure 9 shows V during high-current turn-off. GE , VCE and I C This is the simulation result. The horizontal axis represents time, with a scale of 100 ns. The vertical axis has the same scale as Figure 8. High-current turn-off refers to the collector current I C This refers to turn-off when the collector current I is relatively large. C It is approximately 30[A].

[0077] High current collector current I C Since the value is larger than that of low current, di / dt and V CE There is concern that the surge voltage will increase. However, in this example, di / dt and V in the region marked with a dashed circle are considered. CE This allowed us to suppress the surge voltage. The ability to reduce surge voltage is particularly advantageous in high-current turn-off circuits.

[0078] Figure 10 shows I at each distance L2. c and V CE This is a simulation result showing the relationship with surge voltage. The horizontal axis represents the collector current I c [A] is the vertical axis, and V CE This is the surge voltage [V]. Collector current I c As the collector current I increases, the surge voltage tends to increase. However, c If the same, a smaller distance L2 could reduce the surge voltage. Note that the collector current I c The larger the value, the greater the effect of reducing surge voltage.

[0079] Figure 11 shows I at each distance L2. c This is a simulation result showing the relationship between and Eoff. c When the current is 15A or less, if the current is greater than 15A, c Compared to the above, Eoff can be reduced further. In other words, Eoff can be reduced in low-current turn-off. As mentioned above, the distance L2 in this example is between 50 μm and 100 μm.

[0080] Figure 12 is a top view showing the vicinity of the end of the trench portion 40 in the second embodiment. Note that the term "top view" may also be interpreted as a view of the semiconductor substrate 10 from above (viewing the surface 11 of the semiconductor substrate 10). Figure 12 shows an enlarged view of the first trench portion 40-1, but the other trench portions 40 may have the same configuration.

[0081] In this example, the aperture area of ​​the first aperture 31 is larger than the aperture areas of each other aperture on the floating semiconductor region 30. By maximizing the aperture area of ​​the first aperture 31 among the apertures on the floating semiconductor region 30, the carrier density near the short side portion 47 of the trench portion 40 can be further reduced compared to the first embodiment. Note that the aperture area may be the area of ​​the aperture of the interlayer insulating film 28 on the surface 11 of the semiconductor substrate 10, or it may be the area of ​​the aperture on the upper surface of the interlayer insulating film 28. In this example, the aperture area is the area of ​​the aperture of the interlayer insulating film 28 on the surface 11.

[0082] The outer end 71 and inner end 72 of the first opening 31 in the Y-axis direction may extend parallel to the X-axis direction, which is perpendicular to the longitudinal portion 46 of the first trench portion 40-1. Alternatively, the outer end 71 and inner end 72 of the first opening 31 may be parallel to the short portion 47, corresponding to the short portion 47 of the first trench portion 40-1. In this example, the first opening 31 has a rectangular shape with a long side parallel to the X-axis direction and a short side parallel to the Y-axis direction. This makes it possible to increase the opening area of ​​the first opening 31 compared to the first embodiment while avoiding the first opening 31 being positioned below the gate runner 51.

[0083] Of the multiple openings, the openings other than the first opening 31 may have their longer sides in the Y-axis direction parallel to the longitudinal portion 46-1 of the first trench portion 40-1. The second opening 32 and the third opening 33 in this example have a rectangular shape with a longer side parallel to the Y-axis direction and a shorter side parallel to the X-axis direction. As a result, the opening areas of the second opening 32 and the third opening 33 can also be increased compared to the first embodiment. In other examples, only the first opening 31 may have the shape of this embodiment, while the second opening 32 and the third opening 33 may have the same shape as in the first embodiment.

[0084] Figure 13 is a top view showing the vicinity of the end of the trench portion 40 in the third embodiment. In this example as well, the opening area of ​​the first opening 31 is larger than the opening areas of each other opening on the floating semiconductor region 30. Figure 13 shows an enlarged view of the first trench portion 40-1, but the other trench portions 40 may have the same configuration. The short side portion 47 of the trench portion 40 in this example has a curved shape (more specifically, a semicircular arc shape). Also, the outer end portion 71 in the Y-axis direction of the first opening 31 in this example is parallel to the short side portion 47 of the first trench portion 40-1, corresponding to the short side portion 47. In other words, the outer end portion 71 of the first opening 31 is a semicircle similar to the arc shape of the short side portion 47. The first opening 31 in this example has a semicircular disc shape consisting of a semicircular outer end portion 71 and a straight inner end portion 72. In this example as well, the opening area of ​​the first opening 31 can be increased compared to the first embodiment while avoiding the placement of the first opening 31 below the gate runner 51. In this example, the second opening 32 and the third opening 33 have the same shape as in the second embodiment, but in other examples, only the first opening 31 may have the shape of this embodiment, while the second opening 32 and the third opening 33 may have the same shape as in the first embodiment.

[0085] Figure 14 is a top view showing the vicinity of the end of the trench portion 40 in the fourth embodiment. In this example as well, the opening area of ​​the first opening 31 is larger than the opening areas of each other opening on the floating semiconductor region 30. Figure 14 shows an enlarged view of the first trench portion 40-1, but the other trench portions 40 may have the same configuration. In this example, the outer end 71 and inner end 72 of the first opening 31 are parallel to the short side portion 47 of the first trench portion 40-1, corresponding to the short side portion 47. In other words, the first opening 31 in this example has a semicircular band shape. Also, the outer end 71 of the first opening 31 in the Y-axis direction in this example is parallel to the short side portion 47 of the first trench portion 40-1, corresponding to the short side portion 47. In this way, the opening area of ​​the first opening 31 may be enlarged compared to the first embodiment. In this example, the second opening 32 and the third opening 33 have the same shape as in the second embodiment. However, in other examples, only the first opening 31 may have the shape of this embodiment, while the second opening 32 and the third opening 33 may have the same shape as in the first embodiment.

[0086] Figure 15 shows a modified example of region B in Figures 1A and 1B. Region B is the corner region of the active portion 80. In this example, the fourth trench portion 40-4, the fifth trench portion 40-5, and the sixth trench portion 40-6 are arranged inward in the X-axis direction in that order. The fourth trench portion 40-4 has the same shape as the first trench portion 40-1 to the third trench portion 40-3 described above. At the corner of the active portion 80, the lengths of the longitudinal portions 46 of the trench portions 40 may differ. In this example, the longitudinal portion 46 of the sixth trench portion 40-6 is the shortest, the longitudinal portion 46 of the fifth trench portion 40-5 is the next shortest, and the longitudinal portion 46 of the fourth trench portion 40-4 is the longest. The fourth trench portion 40-4 may have a longitudinal portion 46 of the same length as the first trench portion 40-1.

[0087] At the corners of the active portion 80, the position of the first opening 31 may differ depending on the position of the trench portion 40. At the corners of the active portion 80, the first opening 31 may be located more inward in the Y-axis direction the further it is located outward in the X-axis direction. In this example, the first opening 31 on the floating semiconductor region 30-6 surrounded by the sixth trench portion 40-6 is located furthest inward in the Y-axis direction. Also, the first opening 31 on the floating semiconductor region 30-4 surrounded by the fourth trench portion 40-4 is located furthest outward in the Y-axis direction. The first opening 31 on the floating semiconductor region 30-5 surrounded by the fifth trench portion 40-5 may be located between the first opening 31 on the floating semiconductor region 30-4 and the first opening 31 on the floating semiconductor region 30-6 in the Y-axis direction.

[0088] With the configuration of this example, the first opening 31 can be positioned as far outward as possible in the Y-axis direction, depending on the shape of the trench. This makes it possible to reduce the carrier density near the short portion 47 of the trench 40. This example may be combined with the first to fourth embodiments described above.

[0089] In this example, the position of the second aperture 32 in the Y-axis direction is the same on each floating semiconductor region 30. However, in this example, the position of the first aperture 31 in the Y-axis direction differs at the corners of the active portion 80, so the distance between the first aperture 31 and the second aperture 32 differs according to the Y-axis position of each first aperture 31. In this example, the first aperture 31 on floating semiconductor region 30-4 is located furthest out in the Y-axis direction, so the distance L1 defined on floating semiconductor region 30-4 is longer than the distance L1 defined on floating semiconductor regions 30-5 and 30-6. For the same reason, the distance L1 defined on floating semiconductor region 30-5 is longer than the distance L1 defined on floating semiconductor region 30-6. Also, the distance L1 defined on floating semiconductor region 30-6 is the shortest.

[0090] Figure 16 shows a part of the circuit 200 of a welding machine equipped with a semiconductor device 100. The welding machine in this example includes a rectifier 120, an inverter 130, a transformer 135, a rectifier 140, and a low-pass filter (LPF) 150. An AC power supply 110 located outside the welding machine may input AC current to the rectifier 120. The rectifier 120 may half-wave rectify the input AC current and input the rectified current to the inverter 130.

[0091] The inverter 130 has a plurality of semiconductor devices 100 and an electrolytic capacitor 132. The inverter 130 in this example is a so-called full-bridge inverter. The inverter 130 may be constructed using the semiconductor devices 100 (IGBT semiconductor chips and / or RC-IGBT semiconductor chips) as described in the above embodiment. The electrolytic capacitor 132 may appropriately deform the input waveform from the rectifier 120 according to the charging time.

[0092] The inverter 130 may convert the input current from the rectifier 120 into alternating current by switching the gates of each semiconductor device 100 on and off at a frequency of 20 kHz to 100 kHz (for example, 40 kHz). The voltage converted to alternating current by the inverter 130 may then be boosted via the transformer 135. The boosted current may then be used as direct current in the subsequent circuitry after passing through the rectifier 140 and LPF 150.

[0093] In the inverter 130 of this example, the gate on / off ratio is very high, between 20kHz and 100kHz. When operating at such high frequencies, the ability to reduce the turn-off loss Eoff in the inverter 130 is a significant advantage. In the inverter 130 of this example, the semiconductor device 100 is turned on and turned off with low current. As a result, the inverter 130 can enjoy the benefit of reducing the Eoff of the semiconductor device 100. The semiconductor device 100 in the above embodiment may also be used as an inverter in an uninterruptible power supply (UPS) that operates at high frequencies.

[0094] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0095] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0096] 10...Semiconductor substrate, 11...Front surface, 12...Emitter region, 14...Base region, 16...Contact region, 17...Well region, 18...Drift region, 19...Back surface, 20...FS layer, 22...Collector region, 24...Collector electrode, 26...Oxide film, 28...Interlayer insulating film, 30...Floating semiconductor region, 31...First opening, 32...Second opening, 33...Third opening, 35...Fourth opening, 37...Contact region, 38...Outer edge, 40...Trench region, 42...Trench insulating film, 4 3...Trench conductive part, 44...Trench, 46...Long side, 47...Short side, 51...Gate runner, 52...Emitter electrode, 54...Aperture, 55...Gate metal layer, 60...Mesa region, 71...Outer end, 72...Inner end, 80...Active part, 90...Edge termination structure, 95...Pad part, 100...Semiconductor device, 110...AC power supply, 120...Rectifier, 130...Inverter, 132...Electrolytic capacitor, 135...Transformer, 140...Rectifier, 150...LPF, 200...Circuit

Claims

1. A semiconductor device comprising a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a metal electrode provided on the insulating film, The aforementioned semiconductor substrate is The base region of the first conductivity type, A trench portion is provided from the surface of the semiconductor substrate to a position deeper than the base region, and has a longitudinal portion in the first direction, A region between adjacent longitudinal portions, comprising a plurality of mesa regions including a first mesa region and a second mesa region, At the end of the mesa region in the first direction, a well region of a first conductivity type is provided extending from the surface of the semiconductor substrate to a position deeper than the trench portion, The insulating film has a first opening, a second opening, a third opening, and a fourth opening, Includes, The first opening electrically connects the well region and the metal electrode in the first mesa region. The second and third openings electrically connect the base region and the metal electrode in the first mesa region. The first, second, and third openings are rectangular in shape, with equal lengths in the first direction within the first mesa region and equal widths in the second direction perpendicular to the first direction in a top view. The fourth opening is provided continuously in the first direction from the position of the second opening to the position of the third opening that is closest to the second opening, and connects the second mesa region and the metal electrode. Semiconductor equipment.

2. A semiconductor device comprising a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a metal electrode provided on the insulating film, The aforementioned semiconductor substrate is The base region of the first conductivity type, A trench portion is provided from the surface of the semiconductor substrate to a position deeper than the base region, and has a longitudinal portion in the first direction, A region between adjacent longitudinal portions, comprising a plurality of mesa regions including a first mesa region and a second mesa region, At the end of the mesa region in the first direction, a well region of a first conductivity type is provided extending from the surface of the semiconductor substrate to a position deeper than the trench portion, The insulating film has a first opening, a second opening, a third opening, and a fourth opening, Includes, The first opening electrically connects the well region and the metal electrode in the first mesa region. The second and third openings electrically connect the base region and the metal electrode in the first mesa region. The fourth opening is provided continuously in the first direction from the position of the second opening to the position of the third opening that is closest to the second opening, and connects the second mesa region and the metal electrode. The distance between the first opening and the second opening is shorter than the distance between the second opening and the third opening that is closest to the second opening. Semiconductor equipment.

3. The semiconductor substrate includes a second conductivity type emitter region provided in the second mesa region and in contact with the metal electrode through the fourth opening. The semiconductor device according to claim 1 or 2.

4. The first opening, the second opening, and the third opening are aligned in a straight line in the first direction. The semiconductor device according to any one of claims 1 to 3.

5. The first, second, third, and fourth openings are provided with plugs consisting of a laminate of barrier metal and tungsten. The semiconductor device according to any one of claims 1 to 4.

6. The semiconductor substrate includes a first conductivity type contact region with a higher doping concentration than the base region, directly below the first, second, or third opening. The semiconductor device according to any one of claims 1 to 5.

7. The aforementioned contact area is also provided directly below the fourth opening. The semiconductor device according to claim 6.

8. The first opening is located outside the emitter region that is the outermost part of the second mesa region in the first direction. The semiconductor device according to claim 3.

9. The base region of the first mesa region is a floating semiconductor region. The semiconductor device according to any one of claims 1 to 8.

10. The trench portion has a shorter portion in a second direction perpendicular to the first direction when viewed from above. The first mesa region is surrounded by the longitudinal portion and the transverse portion. A semiconductor device according to any one of claims 1 to 9.

11. The mesa widths of the first mesa region and the second mesa region are different. The semiconductor device according to any one of claims 1 to 10.

12. The trench portion has a shorter portion in a second direction perpendicular to the first direction when viewed from above. The first mesa region includes an outer end that is in contact with the shorter portion in the first direction, The distance from the outer end to the center of the first opening is 1 μm or more and 10 μm or less. A semiconductor device according to any one of claims 1 to 9.

13. The distance between the center position of the first aperture and the center position of the second aperture is 30 μm or more and 60 μm or less. The semiconductor device according to claim 12.

14. The insulating film further includes a fifth opening that electrically connects the base region and the metal electrode in the first mesa region, The second, third, and fifth openings are arranged at equal intervals in the first direction. The semiconductor device according to any one of claims 1 to 13.

15. The insulating film further includes a fifth opening that electrically connects the base region and the metal electrode in the first mesa region, The first, second, third, and fifth openings are rectangular in shape, with equal lengths in the first direction and equal widths in the second direction within the first mesa region. The fourth opening is provided continuously in the first direction over a range extending from the second opening, the third opening closest to the second opening, and the fifth opening closest to the third opening, connecting the second mesa region and the metal electrode. The semiconductor device according to claim 1.

16. The first opening, the second opening, the third opening, and the fifth opening are aligned in a straight line in the first direction within the first mesa region. The second, third, and fifth openings are arranged at equal intervals in the first direction. The semiconductor device according to claim 15.

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