Semiconductor device and method for manufacturing the same

Abstract

Provided is a manufacturing method for a semiconductor device capable of suppressing deformation of a lead member that is caused by pressure application and suppressing occurrence of non-bonding between a semiconductor chip and a bonding layer. The manufacturing method for a semiconductor device comprises: a step for preparing a lead member (4) provided with a bonding part (41) and a beam part (42) contiguous from the bonding part (41); a step for preparing a pressure application jig (8) having an opening (8a); a step for disposing the bonding part (41) on a semiconductor chip (3) with a sintered material (2x) therebetween, the semiconductor chip being provided on a conductive layer (12a) of an insulation circuit substrate (1) which has an insulating plate (11) and the conductive layer (12a) provided on the insulating plate (11); a step for disposing the pressure application jig (8) on the bonding part (41), the sintered material (2x), the semiconductor chip (3), and the conductive layer (12a) such that the opening (8a) overlaps the beam part (42); and a step for applying pressure to and heating the bonding part (41), the sintered material (2x), the semiconductor chip (3), and the conductive layer (12a) by means of the pressure application jig (8).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor element having a front surface and a back surface, a main surface electrode formed on the front surface of the element and a back surface electrode formed on the back surface of the element, a first conductive member facing the back surface of the element and having the back surface electrode conductively joined thereto, a second conductive member disposed apart from the first conductive member and conductively connected to the main surface electrode, and a lead member having a lead main surface facing the same direction as the front surface of the element and connecting the main surface electrode and the second conductive member. The lead member includes a protrusion protruding in the thickness direction from the lead main surface and is joined to the main surface electrode via a lead bonding layer. The protrusion overlaps the main surface electrode when viewed in the thickness direction, thereby suppressing deformation of the connection member due to pressure during sintering.

[0003] Patent Document 2 discloses a method for manufacturing a power module in which a silver paste layer is interposed between a circuit layer of a power module substrate and a semiconductor element, and between the semiconductor element and a lead member, and the power module substrate, the semiconductor element, and the lead member are laminated, and then heated while applying a pressure in the lamination direction to sinter the silver paste layer, thereby joining between the circuit layer and the semiconductor element and between the semiconductor element and the lead member, respectively, in order to suppress warpage and join the semiconductor element and the lead member without causing joint failure or damage to the semiconductor element.

[0004] Patent Document 3 discloses a semiconductor device for applying a uniform load to the entire surface of a semiconductor chip and simultaneously pressurizing and bonding the joints on the front and back surfaces of the semiconductor chip, comprising: a substrate; a semiconductor chip mounted on the substrate and having a front electrode and a back electrode on the opposite side of the front electrode; a lead member provided opposite to the front electrode of the semiconductor chip; a first joint formed between the substrate and the back electrode of the semiconductor chip; and a second joint formed between the front electrode of the semiconductor chip and the lead member, wherein the lead member has an electrode portion connected to the front electrode via the second joint, a bridge portion connecting the electrode portions, and a resin layer formed on the upper surface of the electrode portions, the resin layer being formed on the lower surface of the bridge portion and on the portions of the lower surface of the electrode portions that are not bonded to the front electrode. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. 2020 / 075549 [Patent Document 2] Japanese Patent Publication No. 2018-116995 [Patent Document 3] Japanese Patent Publication No. 2018-6492 [Overview of the project] [Problems that the invention aims to solve]

[0006] It is being considered to join semiconductor chips and lead members on an insulated circuit board using a bonding layer containing a sintering material. However, the pressure and heating required to sinter the bonding layer can deform the lead members, sometimes resulting in non-bonding between the lead members and the bonding layer.

[0007] In view of the above problems, the objective is to provide a semiconductor device and a method for manufacturing the same that can suppress deformation of the lead member due to pressure when joining a semiconductor chip and a lead member using a bonding layer containing a sintered material, and can suppress the occurrence of unbonded areas between the semiconductor chip and the bonding layer. [Means for solving the problem]

[0008] One aspect of the present disclosure is a semiconductor device comprising an insulating circuit board having an insulating plate and a conductive layer provided on the insulating plate, a lead member having a semiconductor chip provided on the conductive layer, a bonding layer containing a sintered material provided on the semiconductor chip, a bonding portion provided on the bonding layer, and a beam portion continuous from the bonding portion, wherein the bonding layer comprises a central region directly below the bonding portion and a peripheral region outside the central region, and the sintering density of the portion of the peripheral region directly below the lead member is lower than the sintering density of the portion of the peripheral region excluding the portion directly below the lead member.

[0009] Another aspect of this disclosure is a method for manufacturing a semiconductor device, comprising the steps of: preparing a lead member having a joint and a beam portion continuous with the joint; preparing a pressure jig having an opening; arranging the joint on a semiconductor chip provided on the conductive layer of an insulating circuit board having an insulating plate and a conductive layer provided on the insulating plate, via a sintered material; arranging the pressure jig on the joint, sintered material, semiconductor chip, and conductive layer such that the opening overlaps the beam portion; and pressurizing and heating the joint, sintered material, semiconductor chip, and conductive layer with the pressure jig. [Effects of the Invention]

[0010] According to this disclosure, when joining a semiconductor chip and a lead member using a bonding layer containing a sintered material, deformation of the lead member due to pressure can be suppressed, and the occurrence of unbonded areas between the semiconductor chip and the bonding layer can be suppressed. This disclosure provides a semiconductor device and a method for manufacturing the same. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view of a part of a semiconductor device according to the first embodiment. [Figure 3] This is a plan view of a part of a semiconductor device according to the first embodiment. [Figure 4]Cross-sectional view of the sintered material of the semiconductor device according to the first embodiment. [Figure 5] Cross-sectional view of another sintered material of the semiconductor device according to the first embodiment. [Figure 6] Process cross-sectional view of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] Process cross-sectional view following FIG. 6 of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] Process cross-sectional view following FIG. 7 of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] Process cross-sectional view following FIG. 8 of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 10] Planar view corresponding to FIG. 9. [Figure 11] Process cross-sectional view of the manufacturing method of the semiconductor device according to the first comparative example. [Figure 12] Process cross-sectional view of the manufacturing method of the semiconductor device according to the second comparative example. [Figure 13] Process plan view of the manufacturing method of the semiconductor device according to the second embodiment. [Figure 14] Process plan view of the manufacturing method of the semiconductor device according to the third embodiment. [Figure 15] Process cross-sectional view of the manufacturing method of the semiconductor device according to the fourth embodiment. [Figure 16] Process cross-sectional view of the manufacturing method of the semiconductor device according to the fifth embodiment. [Figure 17] Process cross-sectional view of the manufacturing method of the semiconductor device according to the sixth embodiment. [Figure 18] Process cross-sectional view of the manufacturing method of the semiconductor device according to the seventh embodiment. [Figure 19] Process cross-sectional view of the manufacturing method of the semiconductor device according to the eighth embodiment.

Embodiments for Carrying Out the Invention

[0012] The first to eighth embodiments will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there are parts where the dimensional relationships and ratios differ between drawings. In addition, the first to eighth embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of the present invention. For example, it is obvious that if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0014] (First Embodiment) <Configuration of semiconductor device> As shown in Figure 1, the semiconductor device (semiconductor module) according to the first embodiment comprises an insulating circuit board 1, a semiconductor chip 3 provided on the insulating circuit board 1, and lead members (also referred to as "lead frames" or "terminals," etc.) 4 provided on the semiconductor chip 3 and the insulating circuit board 1.

[0015] The insulated circuit board 1 comprises an insulating plate 11, conductive layers (metal pattern layers) 12a and 12b provided on one main surface (upper surface) of the insulating plate 11 and spaced apart from each other, and a conductive layer (metal pattern layer) 13 provided on the other main surface (lower surface) of the insulating plate 11. A semiconductor chip 3 is bonded to the conductive layer 12a of the insulated circuit board 1 via a bonding layer 2a. One end of a lead member 4 is bonded to the semiconductor chip 3 via a bonding layer 2b. The other end of the lead member 4 is bonded to the conductive layer 12b of the insulated circuit board 1 via a bonding layer 2c.

[0016] The insulating circuit board 1 may be, for example, a direct copper bond (DCB) substrate or an activated brazing (AMB) substrate. The insulating board 11 is made of a ceramic substrate made from one of the following materials: aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc., or a resin insulating substrate made from polymer material, etc. The conductive layers 12a, 12b and conductive layer 13 are made of conductive foil such as copper (Cu) or aluminum (Al).

[0017] Each of the bonding layers 2a to 2c is a bonding layer (also called a "sintered bonding layer") containing a porous sintered material, and has voids (pores) between the metal particles constituting the sintered material. As the metal particles constituting the sintered material, for example, gold (Au), silver (Ag), or copper (Cu) with a particle size of several nanometers or more and several micrometers or less can be used. The bonding layers 2a to 2c have a thermal conductivity of, for example, 150 W / mK or more and 400 W / mK or less, and a thermal conductivity of approximately 19 × 10⁻¹⁶. -16 It has a thermal expansion coefficient of / °C and a melting point of approximately 960°C. Therefore, the bonding layers 2a to 2c have stable strength at the operating temperature of the semiconductor device (e.g., 150°C to 170°C). The sintered material before sintering bonding layers 2a to 2c is made by mixing fine metal particles coated with organic matter in an organic solvent. By pressurizing and heating with the sintered material placed between the objects to be bonded, the organic solvent and the coating organic matter vaporize, and the exposed fine metal particles fuse together and sinter, forming bonding layers 2a to 2c.

[0018] The bonding layers 2a to 2c may be made of the same material or different materials. The bonding layers 2a to 2c may have the same thickness or different thicknesses. The bonding layers 2a to 2c may be formed simultaneously or individually. For example, when bonding layers 2a and 2b are formed simultaneously, it is preferable that bonding layers 2a and 2b have the same thickness.

[0019] The semiconductor chip 3 has its lower surface facing the upper surface of the conductive layer 12a. Examples of semiconductor chips 3 include insulated-gate bipolar transistors (IGBTs), field-effect transistors (FETs), electrostatic induction (SI) thyristors, gate-turn-off (GTO) thyristors, and freewheeling diodes (FWDs). The semiconductor chip 3 may be made of, for example, a silicon (Si) substrate, or a compound semiconductor substrate using a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). The conductive layer 12a is bonded to the lower electrode of the semiconductor chip 3 via a junction layer 2a. A lead member 4 is bonded to the upper electrode of the semiconductor chip 3 via a junction layer 2b. For example, if the semiconductor chip 3 is an IGBT, the lower electrode is the collector electrode, and the upper electrode is the emitter electrode.

[0020] Figure 1 illustrates one semiconductor chip 3, but the number of semiconductor chips can be appropriately set according to the current capacity of the semiconductor module, and it may have two or more semiconductor chips. Also, Figure 1 illustrates one lead member 4, but the number of lead members can be appropriately set according to the number of semiconductor chips, and it may have two or more lead members.

[0021] The semiconductor device according to the first embodiment further comprises an insulating circuit board 1, a semiconductor chip 3, a lead member 4, and a sealing resin 5 that seals bonding layers 2a to 2c, etc., and a case 6 provided around the sealing resin 5.

[0022] The sealing resin 5 mainly comprises a resin such as epoxy resin, phenolic resin, or maleimide resin. In addition to the main component, the sealing resin 5 may also contain an inorganic filler. The inorganic filler may be, for example, a metal oxide or metal nitride, and is composed of a single substance or a mixture of two or more of the following: fused silica, silica (silicon oxide), alumina, aluminum hydroxide, titania, zirconia, aluminum nitride, talc, clay, mica, or glass fiber.

[0023] Case 6 is made of a resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT). Case 6 may be fitted with external terminals (not shown) that can be connected to an external circuit. The external terminals (not shown) may be connected to the semiconductor chip 3 or conductive layers 12a, 12b via bonding wires (not shown), or to the semiconductor chip 3 or conductive layers 12a, 12b via a bonding layer (not shown) such as solder or sintered material.

[0024] The semiconductor device according to the first embodiment further comprises a cooler (heat dissipation fins) 14 provided beneath an insulating circuit board 1. The cooler 14 is bonded to the conductive layer 13 of the insulating circuit board 1 via a bonding layer 2d. The bonding layer 2d is composed of, for example, a sintered material, solder, or a thermal interface material (TIM). As the TIM, thermally conductive materials (thermal compounds) such as thermally conductive grease, elastomer sheets, room-temperature curing (RTV) rubber, gel, phase change material, and silver solder can be used. The cooler 14 is composed of a metal such as copper (Cu) or aluminum (Al). The cooler 14 may have a structure with fins on the top plate, or it may have a flat plate structure without fins below the top plate.

[0025] Figure 2 is a cross-sectional view showing the insulating circuit board 1, semiconductor chip 3, lead member 4, and bonding layers 2a to 2c extracted from Figure 1. Figure 3 is a plan view corresponding to Figure 2. The cross-section of Figure 3 viewed from direction AA corresponds to Figure 2. Figure 4 is a plan view of bonding layer 2b. Figure 5 is a plan view of bonding layer 2c.

[0026] As shown in Figures 2 and 3, the lead member 4 comprises a joint portion 41, a beam portion 42 extending continuously from the joint portion 41, and a joint portion 43 extending continuously from the beam portion 42. The joint portion 41 is the portion that is joined to the upper surface of the semiconductor chip 3 via a bonding layer 2b. The joint portion 41 has a substantially rectangular planar pattern and a lower surface parallel to the upper surface of the semiconductor chip 3. The joint portion 43 is the portion that is joined to the upper surface of the conductive layer 12b of the insulating circuit board 1 via a bonding layer 2c. The joint portion 43 has a substantially rectangular planar pattern and a lower surface parallel to the upper surface of the conductive layer 12b. The horizontal level (vertical height) of the joint portion 41 is higher than the horizontal level (vertical height) of the joint portion 43 by the thickness of the bonding layer 2a and the semiconductor chip 3.

[0027] The beam section 42 includes a first upright section that rises from the upper surface of the joint section 41 and extends vertically, a second upright section that rises from the upper surface of the joint section 43 and extends vertically, and a central section that bends in an L-shape from the upper ends of the first and second upright sections and extends horizontally. The vertical length of the first upright section is shorter than the vertical length of the second upright section so that the central section of the beam section 42 is horizontal.

[0028] As shown in Figure 3, the insulating plate 11 and conductive layers 12a and 12b of the insulating circuit board 1 have a substantially rectangular planar pattern. The arrangement and number of conductive layers 12a and 12b are not limited thereto. The bonding layer 2a has a substantially rectangular planar pattern. The semiconductor chip 3 has a substantially rectangular planar pattern. The size of the planar pattern of the semiconductor chip 3 is smaller than the size of the planar pattern of the bonding layer 2a. The outer periphery of the semiconductor chip 3 is located inward from the outer periphery of the bonding layer 2a.

[0029] As shown in Figures 2 to 4, the bonding layer 2b has a substantially rectangular planar pattern. The size of the planar pattern of the bonding layer 2b is smaller than the size of the planar pattern of the semiconductor chip 3, but larger than the planar pattern of the bonding portion 41. The outer periphery of the bonding layer 2b is located inside the outer periphery of the semiconductor chip 3, but outside the outer periphery of the bonding portion 41.

[0030] The bonding layer 2b comprises a central region 21 and peripheral regions 22 and 23 provided around the central region 21. The central region 21 is located directly below the joint portion 41 of the lead member 4 and is bonded to the joint portion 41.

[0031] The peripheral regions 22 and 23 are located outside the central region 21 in a plan view and are not joined to the joint 41. Of the peripheral regions 22 and 23, peripheral region 22 includes the portion located directly below (below) the beam portion 42 of the lead member 4. Peripheral region 22 is adjacent to one side of the rectangular planar pattern of the central region 21 and has a substantially rectangular planar pattern. Of the peripheral regions 22 and 23, peripheral region 23 is the portion excluding peripheral region 22, which includes the area directly below (below) the beam portion 42 of the lead member 4. Peripheral region 23 surrounds the central region 21 and peripheral region 22 and has a substantially C-shaped planar pattern. In the extending direction of the beam portion 42 of the lead member 4, peripheral region 23 includes the region opposite to peripheral region 22 relative to the central region 21.

[0032] The central region 21 and the peripheral region 23 are pressurized during joining by the bonding layer 2b, while the peripheral region 22 is not pressurized during joining by the bonding layer 2b. Therefore, the sintering density of the central region 21 and the peripheral region 23 is higher than that of the peripheral region 22. In this specification, sintering density is the density of metal particles constituting the sintered material, and is the ratio of the volume of the bonding layer excluding open and closed pores to the total volume of the bonding layer including open and closed pores. Furthermore, the porosity between metal particles in the sintered material constituting the central region 21 and the peripheral region 23 is lower than that between metal particles in the sintered material constituting the peripheral region 22.

[0033] As shown in Figures 2, 3, and 5, the bonding layer 2c has a substantially rectangular planar pattern. The size of the planar pattern of the bonding layer 2c is larger than the size of the planar pattern of the joint 43. The outer periphery of the bonding layer 2c is located outside the outer periphery of the joint 43.

[0034] The bonding layer 2c comprises a central region 24 and peripheral regions 25 and 26 provided around the central region 24. The central region 24 is located directly below the joint portion 43 of the lead member 4 and is bonded to the joint portion 43.

[0035] The peripheral regions 25 and 26 are located outside the central region 24 in a plan view and are not joined to the joint 43. Of the peripheral regions 25 and 26, peripheral region 25 includes the portion located directly below (below) the beam portion 42 of the lead member 4. Peripheral region 25 is adjacent to one side of the rectangular planar pattern of the central region 24 and has a substantially rectangular planar pattern. Of the peripheral regions 25 and 26, peripheral region 26 is the portion of peripheral region 25 excluding the portion directly below (below) the beam portion 42 of the lead member 4. Peripheral region 26 surrounds the central region 24 and peripheral region 25 and has a substantially C-shaped planar pattern.

[0036] The central region 24 and the peripheral region 26 are pressurized during bonding with the bonding layer 2c, while the peripheral region 25 is not pressurized during bonding with the bonding layer 2c. Therefore, the sintering density of the central region 24 and the peripheral region 26 is higher than that of the peripheral region 25. Furthermore, the void ratio between metal particles in the sintered material constituting the central region 24 and the peripheral region 26 is lower than that between metal particles in the sintered material constituting the peripheral region 25.

[0037] According to the semiconductor device of the first embodiment, by joining the semiconductor chip 3 to the lead member 4 via a bonding layer 2a containing a sintered material, high heat resistance, high heat dissipation, and high reliability can be achieved compared to joining via solder.

[0038] <Manufacturing method for semiconductor devices> Next, an example of a method for manufacturing a semiconductor device according to the first embodiment (assembly method) will be described.

[0039] First, an insulating circuit board 1 is prepared, with conductive layers 12a and 12b provided on the upper surface of an insulating plate 11 (see Figure 6). Then, a semiconductor chip 3 is placed on the conductive layer 12a of the insulating circuit board 1 via a sintered material (see Figure 6). The sintered material may be a sheet-like sintered material (sintered sheet) or a paste-like sintered material (sintered paste). The sintered material may be placed on the conductive layer 12a by paste printing or dispensing. Alternatively, the sintered material may be attached to the lower surface of the semiconductor chip 3, and the sintered material attached to the lower surface of the semiconductor chip 3 may be placed on the conductive layer 12a.

[0040] Next, using a mold (not shown) positioned on the lower side of the insulating circuit board 1 and a mold (not shown) positioned on the upper side of the semiconductor chip 3, the insulating circuit board 1, the sintering material, and the semiconductor chip 3 are pressed and heated in the stacking direction to induce a sintering reaction in the sintering material. For example, the pressing force is set to approximately 1 MPa or more and 60 MPa or less, the heating temperature to approximately 150°C or more and 350°C or less, and the heating time to approximately 1 minute or more and 5 minutes or less. As a result, as shown in Figure 6, the semiconductor chip 3 is bonded to the conductive layer 12a of the insulating circuit board 1 via the bonding layer 2a.

[0041] Next, as shown in Figure 7, the lead member 4 is placed on the upper surface of the semiconductor chip 3 and the conductive layer 12b via sintered material 2x, 2y. The sintered material 2x, 2y may be a sheet-like sintered material (sintered sheet) placed on the upper surface of the semiconductor chip 3 and the conductive layer 12b, or a paste-like sintered material (sintered paste) may be applied to the upper surface of the semiconductor chip 3 and the conductive layer 12b. Alternatively, the sintered material 2x, 2y may be attached to the lower surface of the lead member 4, and the sintered material 2x, 2y attached to the lower surface of the lead member 4 may be placed on the upper surface of the semiconductor chip 3 and the conductive layer 12b.

[0042] Next, as shown in Figure 8, prepare the protective sheet 7, the pressure jig 8, and the pressure plate 9. The protective sheet 7 is made of a material and thickness that can be deformed by pressure. As the material for the protective sheet 7, for example, a fluororesin such as polytetrafluoroethylene (PTFE) or a polyimide resin can be used. The thickness of the protective sheet 7 is, for example, about 0.1 mm or more and 1.0 mm or less, but is not limited to this.

[0043] The pressurizing jig 8 is made of a metal such as stainless steel (SUS). The pressurizing jig 8 is provided with an opening 8a. Stepped portions 8b and 8c are provided on the lower surface of the pressurizing jig 8. The stepped portions 8b and 8c have shapes corresponding to the stepped portions formed by the lamination of the insulating circuit board 1, bonding layer 2a, semiconductor chip 3, sintered material 2x, 2y and lead member 4.

[0044] The pressure plate 9 is made of a metal such as stainless steel (SUS). The pressure plate 9 has a flat shape. Note that the protective sheet 7 and the pressure plate 9 do not necessarily have to be placed. Also, a cushioning material made of carbon sheet or the like may be placed between the protective sheet 7 and the pressure jig 8.

[0045] Next, as shown in Figure 9, a pressure jig 8 is placed on the insulating circuit board 1, bonding layer 2a, semiconductor chip 3, sintered material 2x, 2y, and lead member 4 via a protective sheet 7, and a pressure plate 9 is placed on the pressure jig 8. The opening 8a of the pressure jig 8 overlaps the beam portion 42 of the lead member 4, and the beam portion 42 is housed inside. In this state, using a mold (not shown) placed on the lower side of the insulating circuit board 1 and a mold (not shown) placed on the upper side of the pressure plate 9, the insulating circuit board 1, bonding layer 2a, semiconductor chip 3, sintered material 2x, 2y, and lead member 4 are pressed and heated in the direction of their stacking to cause a sintering reaction in the sintered material 2x, 2y. For example, the pressing force is set to approximately 1 MPa or more and 60 MPa or less, the heating temperature to approximately 150°C or more and 350°C or less, and the heating time to approximately 1 minute or more and 5 minutes or less.

[0046] The arrows in Figure 9 schematically indicate the pressurized state. The pressurization by the pressurizing jig 8 selectively pressurizes the conductive layers 12a, 12b, sintered material 2x, 2y, semiconductor chip 3, and joints 41, 43 of the insulating circuit board 1 via the protective sheet 7. The beam portion 42 of the lead member 4 is contained within the opening 8a of the pressurizing jig 8 and is therefore not pressurized by the pressurizing jig 8.

[0047] Figure 10 is a plan view corresponding to Figure 9. In Figure 10, the protective sheet 7 and pressure plate 9 are omitted, and components hidden beneath the pressure jig 8 are schematically shown with dashed lines. As shown in Figure 10, the outer circumference of the pressure jig 8 is approximately the same as the outer circumference of the conductive layers 12a and 12b. The outer circumference of the pressure jig 8 may be located inside or outside the outer circumference of the conductive layers 12a and 12b. The pressure jig 8 applies pressure to the edges of the conductive layers 12a and 12b of the insulating circuit board 1, but it is not necessary to apply pressure to the edges.

[0048] The opening 8a of the pressurizing jig 8 overlaps with the beam portion 42 of the lead member 4. The size of the planar pattern of the opening 8a is larger than the size of the planar pattern of the beam portion 42. In the direction perpendicular to the extension direction of the beam portion 42 (the short side direction of the beam portion 42), the width W2 of the opening 8a is wider than the width W1 of the beam portion 42. In the extension direction of the beam portion 42 (the long side direction of the beam portion 42), the length L1 of the opening 8a is longer than the length L2 of the beam portion 42. The opening 8a has a substantially rectangular planar pattern, but the shape of the planar pattern is not limited to a rectangle and may be, for example, circular.

[0049] As a result, the sintered materials 2x and 2y are sintered to form bonding layers 2b and 2c. As shown in Figures 2 and 3, the bonding portion 41 of the semiconductor chip 3 and the lead member 4 is bonded via bonding layer 2b, and the bonding portion 43 of the conductive layer 12b and the lead member 4 is bonded via bonding layer 2c. Of the bonding layer 2b, the central region 21 and the peripheral region 23 are pressurized, but the peripheral region 22 is not. Therefore, the sintering density of the central region 21 and the peripheral region 23 is higher than that of the peripheral region 22. Also, the porosity between metal particles in the central region 21 and the peripheral region 23 is lower than that of the peripheral region 22. Furthermore, of the bonding layer 2c, the central region 24 and the peripheral region 26 are pressurized, but the peripheral region 25 is not. Therefore, the sintering density of the central region 24 and the peripheral region 26 is higher than that of the peripheral region 25. Furthermore, the porosity between metal particles in the central region 24 and the peripheral region 26 is lower than the porosity between metal particles in the peripheral region 25.

[0050] The area including the portion of the sintered material 2x directly below the beam portion 42 and the portion of the sintered material 2x exposed to the opening 8a, as shown in Figure 10, becomes the unpressurized peripheral region 22 of the bonding layer 2b. Similarly, the area including the portion of the sintered material 2y directly below the beam portion 42 and the portion of the sintered material 2y exposed to the opening 8a, as shown in Figure 10, becomes the unpressurized peripheral region 25 of the bonding layer 2c. Note that the planar pattern of the peripheral region 22 of the bonding layer 2b exemplified in Figure 4 and the planar pattern of the peripheral region 25 of the bonding layer 2c shown in Figure 5 correspond to the shape formed when the width W2 of the opening 8a shown in Figure 10 is made approximately the same as the width W1 of the beam portion 42, and there is almost no portion of the sintered materials 2x and 2y exposed to the opening 8a. In this case, the portion of the sintered material 2x directly below the beam portion 42 approximately coincides with the peripheral region 22 of the bonding layer 2b, and the portion of the sintered material 2y directly below the beam portion 42 approximately coincides with the peripheral region 25 of the bonding layer 2c. Subsequently, the laminated structure of the insulating circuit board 1, bonding layers 2a-2c, semiconductor chip 3, and lead member 4 is removed by taking off the protective sheet 7, pressure jig 8, and pressure plate 9.

[0051] Next, the cooler 14 is bonded to the lower side of the insulating circuit board 1 via a bonding layer 2d. Then, the case 6 is placed on the cooler 14 so as to surround the insulating circuit board 1, semiconductor chip 3, lead member 4, and bonding layers 2a to 2d. Next, the sealing resin 5 is filled inside the case 6 to seal the insulating circuit board 1, semiconductor chip 3, lead member 4, and bonding layers 2a to 2d. As a result, the semiconductor device according to the first embodiment shown in Figure 1 is completed.

[0052] Here, the method for manufacturing a semiconductor device according to the first comparative example will be described. The method for manufacturing a semiconductor device according to the first comparative example differs from the method for manufacturing a semiconductor device according to the first embodiment in that, as shown in Figure 11, the entire lead member 4 is pressurized via a cushioning material 7x made of carbon sheet using a mold (not shown). The arrows in Figure 11 schematically indicate the pressurized state. In the method for manufacturing a semiconductor device according to the first comparative example, not only the joint portions 41 and 43 of the lead member 4 but also the beam portion 42 is pressurized, so the beam portion 42 deforms and the joint portions 41 and 43 float, which may result in a lack of bonding between the joint portions 41 and 43 and the sintered material 2x and 2y.

[0053] In contrast, according to the semiconductor device manufacturing method of the first embodiment, as shown in Figures 9 and 10, the opening 8a of the pressurizing jig 8 is placed on the beam portion 42 of the lead member 4, and pressurizing is applied with the beam portion 42 exposed from the opening 8a, thereby suppressing the pressurization of the beam portion 42. As a result, deformation of the lead member 4 can be suppressed, and non-bonding between the joint portions 41, 43 and the sintered materials 2x, 2y can be suppressed.

[0054] Next, a method for manufacturing a semiconductor device according to the second comparative example will be described. In the method for manufacturing a semiconductor device according to the second comparative example, as shown in Figure 12, the pressurizing jigs 8y and 8z individually pressurize the joint portions 41 and 43 of the lead member 4, which is different from the method for manufacturing a semiconductor device according to the first embodiment. The arrows in Figure 12 schematically indicate the pressurized state. In the method for manufacturing a semiconductor device according to the second comparative example, only the portion directly below the joint portions 41 and 43 of the lead member 4 is pressurized, and the conductive layers 12a and 12b excluding the portion directly below the joint portions 41 and 43 are not pressurized. As a result, the insulating circuit board 1 may warp, and uniform pressurization may not be possible.

[0055] In contrast, according to the semiconductor device manufacturing method of the first embodiment, as shown in Figures 9 and 10, the pressurizing jig 8 pressurizes not only the area directly below the joints 41 and 43 of the lead member 4, but also the areas of the conductive layers 12a and 12b excluding the area directly below the joints 41 and 43. Therefore, warping of the insulating circuit board 1 can be suppressed (corrected), and uniform pressurization can be achieved.

[0056] (Second Embodiment) The method for manufacturing a semiconductor device according to the second embodiment of this disclosure differs from the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 10, in that the pressurizing jig 8 used for pressurizing the sintered material 2x,2y is divided into a first member 81 and a second member 82, as shown in Figure 13.

[0057] The first member 81 and the second member 82 have a substantially rectangular planar pattern. The first member 81 and the second member 82 are spaced apart from each other. The space between the first member 81 and the second member 82 constitutes an opening 8a. Other steps in the manufacturing method of the semiconductor device according to the second embodiment are substantially the same as those in the manufacturing method of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0058] In the semiconductor device manufacturing method according to the second embodiment, the opening 8a overlaps with the beam portion 42 of the lead member 4, exposing the beam portion 42. This suppresses deformation of the lead member 4 and prevents unbonding between the sintered material 2x, 2y and the joint portions 41, 43. Furthermore, since the pressurizing jig 8 pressurizes not only the area directly beneath the joint portions 41, 43 of the lead member 4, but also the areas of the conductive layers 12a, 12b excluding the area directly beneath the joint portions 41, 43, warping of the insulating circuit board 1 can be suppressed, and uniform pressurization can be achieved.

[0059] (Third embodiment) The method for manufacturing a semiconductor device according to the third embodiment of this disclosure differs from the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 10, in that the pressurizing jig 8 used for pressurizing the sintered material 2x,2y is divided into a first member 81 and a second member 82, as shown in Figure 14.

[0060] The first member 81 and the second member 82 have an L-shaped planar pattern. The first member 81 and the second member 82 are arranged so that their ends overlap each other. The thickness of the overlapping ends of the first member 81 and the second member 82 is thinner than the thickness of the other parts, and the thickness of the overlapping ends of the first member 81 and the second member 82 is the same as the thickness of the other parts. The space between the first member 81 and the second member 82 constitutes an opening 8a. The other steps of the manufacturing method of the semiconductor device according to the third embodiment are substantially the same as those of the manufacturing method of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0061] In the semiconductor device manufacturing method according to the third embodiment, the opening 8a overlaps with the beam portion 42 of the lead member 4, exposing the beam portion 42. This suppresses deformation of the lead member 4 and prevents unbonding between the sintered material 2x, 2y and the joint portions 41, 43. Furthermore, since the pressurizing jig 8 pressurizes not only the area directly beneath the joint portions 41, 43 of the lead member 4, but also the areas of the conductive layers 12a, 12b excluding the area directly beneath the joint portions 41, 43, warping of the insulating circuit board 1 can be suppressed, and uniform pressurization can be achieved.

[0062] (Fourth Embodiment) The method for manufacturing a semiconductor device according to the fourth embodiment of this disclosure differs from the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 9, in that the opening 8a of the pressurizing jig 8 used for pressurizing the sintered material 2x,2y is narrower, as shown in Figure 15. The end of the opening 8a is located on the bent portion of the beam portion 42 of the lead member 4. The length L1 of the opening 8a in the extension direction of the beam portion 42 is shorter than the length L2 of the beam portion 42. The other steps of the method for manufacturing a semiconductor device according to the fourth embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0063] In the semiconductor device manufacturing method according to the fourth embodiment, the opening 8a overlaps with the beam portion 42 of the lead member 4, exposing the beam portion 42. This suppresses deformation of the lead member 4 and prevents unbonding between the sintered material 2x, 2y and the joint portions 41, 43. Furthermore, since the pressurizing jig 8 pressurizes not only the area directly beneath the joint portions 41, 43 of the lead member 4, but also the areas of the conductive layers 12a, 12b excluding the area directly beneath the joint portions 41, 43, warping of the insulating circuit board 1 can be suppressed, and uniform pressurization can be achieved.

[0064] (Fifth embodiment) As shown in Figure 16, the manufacturing method of the semiconductor device according to the fifth embodiment of this disclosure differs from the manufacturing method of the semiconductor device according to the first embodiment shown in Figure 9 in that the shapes of the lead member 4 and the pressurizing jig 8 are different. The lead member 4 has a C-shaped cross-section. The lead member 4 has joint portions 41, 43 and a beam portion 42 that is continuous with the joint portions 41, 43. The beam portion 42 does not have a portion that rises vertically, but only has a portion that extends horizontally. The stepped portions 8b, 8c on the lower surface of the pressurizing jig 8 have a shape that matches the shape of the lead member 4. The other steps of the manufacturing method of the semiconductor device according to the fifth embodiment are substantially the same as those of the manufacturing method of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0065] According to the semiconductor device manufacturing method of the fifth embodiment, the opening 8a overlaps with the beam portion 42 of the lead member 4, exposing the beam portion 42. This suppresses deformation of the lead member 4 and prevents unbonding between the sintered material 2x, 2y and the joint portions 41, 43. Furthermore, since the pressurizing jig 8 pressurizes not only the area directly beneath the joint portions 41, 43 of the lead member 4, but also the areas of the conductive layers 12a, 12b excluding the area directly beneath the joint portions 41, 43, warping of the insulating circuit board 1 can be suppressed, and uniform pressurization can be achieved.

[0066] (Sixth Embodiment) The method for manufacturing a semiconductor device according to the sixth embodiment of this disclosure differs from the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 9, in that an opening 7a is provided in the protective sheet 7, as shown in Figure 17. The opening 7a in the protective sheet 7 is provided at a position corresponding to the opening 8a in the pressurizing jig 8. The other steps of the method for manufacturing a semiconductor device according to the sixth embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0067] In the semiconductor device manufacturing method according to the sixth embodiment, the opening 8a overlaps with the beam portion 42 of the lead member 4, exposing the beam portion 42. This suppresses deformation of the lead member 4 and prevents unbonding between the sintered material 2x, 2y and the joint portions 41, 43. Furthermore, since the pressurizing jig 8 pressurizes not only the area directly beneath the joint portions 41, 43 of the lead member 4, but also the areas of the conductive layers 12a, 12b excluding the area directly beneath the joint portions 41, 43, warping of the insulating circuit board 1 can be suppressed, and uniform pressurization can be achieved.

[0068] (Seventh Embodiment) The method for manufacturing a semiconductor device according to the seventh embodiment of this disclosure differs from the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 9, in that, as shown in Figure 18, the stepped portions 8b and 8c on the lower surface side of the pressurizing jig 8 have finer steps. The stepped portions 8b and 8c are shaped to correspond to the steps formed by the bonding layer 2a, semiconductor chip 3, sintered material 2x, 2y and bonding portions 41, 43, but they do not necessarily have to coincide one step at a time. For example, the stepped portions 8b and 8c may have one step opposite the upper surface of the bonding portions 41, 43. The other steps of the method for manufacturing a semiconductor device according to the seventh embodiment are substantially the same as those of the method for manufacturing a semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0069] According to the semiconductor device manufacturing method of the seventh embodiment, the opening 8a overlaps with the beam portion 42 of the lead member 4, exposing the beam portion 42. This suppresses deformation of the lead member 4 and prevents unbonding between the sintered material 2x, 2y and the joint portions 41, 43. Furthermore, since the pressurizing jig 8 pressurizes not only the area directly beneath the joint portions 41, 43 of the lead member 4, but also the areas of the conductive layers 12a, 12b excluding the area directly beneath the joint portions 41, 43, warping of the insulating circuit board 1 can be suppressed, and uniform pressurization can be achieved.

[0070] (Eighth embodiment) The method for manufacturing a semiconductor device according to the eighth embodiment of this disclosure differs from the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 9, in that, as shown in Figure 19, the lower surface of the pressure jig 8 is flat, without a stepped portion on the lower surface of the pressure jig 8. A cushioning material 15 is provided between the lower surface of the pressure jig 8 and the protective sheet 7. The cushioning material 15 can be compressed and deformed by the pressure applied by the pressure jig 8. The cushioning material 15 is made of, for example, a carbon sheet or a PTFE sheet. Other steps in the method for manufacturing a semiconductor device according to the eighth embodiment are substantially the same as those in the method for manufacturing a semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0071] In the semiconductor device manufacturing method according to the eighth embodiment, the opening 8a overlaps with the beam portion 42 of the lead member 4, exposing the beam portion 42. This suppresses deformation of the lead member 4 and prevents unbonding between the sintered material 2x, 2y and the joint portions 41, 43. Furthermore, since the pressurizing jig 8 pressurizes not only the area directly beneath the joint portions 41, 43 of the lead member 4, but also the areas of the conductive layers 12a, 12b excluding the area directly beneath the joint portions 41, 43, warping of the insulating circuit board 1 can be suppressed, and uniform pressurization can be achieved.

[0072] (Other embodiments) As described above, the present invention has been described by the first to eighth embodiments, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0073] For example, in the first to eighth embodiments, an example was given in which the pressurizing jig 8 has one opening 8a. However, when the system includes multiple semiconductor chips and multiple lead members connected to the multiple semiconductor chips, multiple openings may be provided in the pressurizing jig 8 that overlap with the beam portions of the multiple lead members. Alternatively, a single opening may be provided in the pressurizing jig 8 that encompasses and overlaps the beam portions of the multiple lead members.

[0074] Furthermore, in the first to eighth embodiments, an example was given in which a bonding layer 2a is formed by sintering the sintering material that joins the insulating circuit board 1 and the semiconductor chip 3, and then bonding layers 2b and 2c are formed by sintering the sintering materials 2x and 2y. However, the sintering material that joins the insulating circuit board 1 and the semiconductor chip 3 may be placed without sintering, and the bonding layers 2b and 2c may be formed by sintering the sintering materials 2x and 2y by pressurizing and heating, while the bonding layer 2a is formed at the same time as the sintering material that joins the insulating circuit board 1 and the semiconductor chip 3 is sintered.

[0075] Furthermore, the configurations disclosed in each of the first to eighth embodiments can be combined as appropriate, within a non-contradictory range. Thus, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are appropriate from the above description. [Explanation of Symbols]

[0076] 1…Insulated circuit board 2a~2d...Joining layer 2x,2y…Sintered material 3… Semiconductor chips 4…Lead member 5…Sealing resin 6…cases 7… Protective film 7a...Opening 7x…Buffer material 8,8x~8z…Pressure jig 8a…Opening 8b, 8c... Stepped section 9…Pressure plate 11…Insulating board 12a, 12b, 13...conductive layer 14...Cooler 15...Cushioning material 21,24…Central area 22, 23, 25, 26… surrounding areas 41,43...Joint part 42...Beam part

Claims

1. An insulating circuit board having an insulating plate and a conductive layer provided on the insulating plate, A semiconductor chip provided on the conductive layer, A bonding layer including a sintered material provided on the semiconductor chip, A lead member having a joint portion provided on the bonding layer and a beam portion continuous with the joint portion, Equipped with, The bonding layer comprises a central region directly below the bonding portion and a peripheral region outside the central region. A semiconductor device wherein the sintering density of the portion of the peripheral region directly beneath the lead member is lower than the sintering density of the portion of the peripheral region excluding the portion directly beneath the lead member.

2. A step of preparing a lead member comprising a joint portion and a beam portion continuous with the joint portion, A step of preparing a pressurizing jig having an opening, A step of placing the joint portion on a semiconductor chip provided on the conductive layer of an insulating circuit board having an insulating plate and a conductive layer provided on the insulating plate, via a sintered material, A step of arranging the pressurizing jig on the joint, the sintered material, the semiconductor chip, and the conductive layer such that the opening overlaps the beam portion, The process involves applying pressure and heating to the joint, the sintered material, the semiconductor chip, and the conductive layer using the aforementioned pressure jig, Includes, A method for manufacturing a semiconductor device, wherein the step of pressurizing the conductive layer is to pressurize the portion directly below the joint and the portion outside the portion directly below the joint, excluding the portion directly below the lead member.

3. A method for manufacturing a semiconductor device according to claim 2, wherein a stepped portion is provided on the lower side of the pressurizing jig.

4. A step of preparing a lead member comprising a joint portion and a beam portion continuous with the joint portion, A step of preparing a pressurizing jig having an opening, A step of placing the joint portion on a semiconductor chip provided on the conductive layer of an insulating circuit board having an insulating plate and a conductive layer provided on the insulating plate, via a sintered material, A step of arranging the pressurizing jig on the joint, the sintered material, the semiconductor chip, and the conductive layer such that the opening overlaps the beam portion, The process involves applying pressure and heating to the joint, the sintered material, the semiconductor chip, and the conductive layer using the aforementioned pressure jig, Includes, A method for manufacturing a semiconductor device, wherein the size of the opening is larger than the size of the beam.

5. A step of preparing a lead member comprising a joint portion and a beam portion continuous with the joint portion, A step of preparing a pressurizing jig having an opening, A step of placing the joint portion on a semiconductor chip provided on the conductive layer of an insulating circuit board having an insulating plate and a conductive layer provided on the insulating plate, via a sintered material, A step of arranging the pressurizing jig on the joint, the sintered material, the semiconductor chip, and the conductive layer such that the opening overlaps the beam portion, The process involves applying pressure and heating to the joint, the sintered material, the semiconductor chip, and the conductive layer using the aforementioned pressure jig, Includes, A method for manufacturing a semiconductor device, wherein the length of the opening in the longitudinal direction of the beam is longer than the length of the beam.

6. A method for manufacturing a semiconductor device according to claim 2 or 3, wherein the length of the opening in the longitudinal direction of the beam is shorter than the length of the beam.

7. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein the step of applying pressure with the pressure jig involves applying pressure to the joint, the sintered material, the semiconductor chip, and the conductive layer via a protective sheet using the pressure jig.

8. The method for manufacturing a semiconductor device according to claim 7, wherein an opening is provided in the protective sheet at a position corresponding to the opening.

9. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein the step of applying pressure with the pressure jig involves placing a pressure plate on the upper surface side of the pressure jig and applying pressure to the joint, the sintered material, the semiconductor chip, and the conductive layer with the pressure plate and the pressure jig.

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