Back-side incident semiconductor photodetector

Abstract

To provide a back-illuminated semiconductor photodetector that further improves the spectral sensitivity characteristics in the long wavelength range.SOLUTION: A semiconductor substrate 11 has principal surfaces 11a and 11b which face each other. The principal surface 11a is the light incident surface of the semiconductor substrate 11. The semiconductor substrate 11 has a semiconductor region 13 and a plurality of semiconductor regions 15 which are formed on the principal surface 11b side and which form pn junctions with the semiconductor region 13. Each of the semiconductor regions 15 has a region 17 having a textured surface TS, and a region 19. The textured surface TS of the region 17 is located closer to the principal surface 11a than the surface of the region 19 in the thickness direction of the semiconductor substrate 11.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a back-illuminated semiconductor photodetector.

Background Art

[0002] A back-illuminated semiconductor photodetector including a semiconductor substrate having a first main surface and a second main surface facing each other is known (see, for example, Patent Documents 1 and 2). In the back-illuminated semiconductor photodetector described in Patent Document 2, the semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type. The plurality of second semiconductor regions are formed on the second main surface side and form a pn junction with the first semiconductor region. The first main surface is a light incident surface to the semiconductor substrate. The plurality of second semiconductor regions have a textured surface.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] One aspect of the present invention aims to provide a back-illuminated semiconductor photodetector that further improves the spectral sensitivity characteristics in the long wavelength region (for example, the near-infrared wavelength region).

Means for Solving the Problems

[0005] A back-side incident semiconductor photodetector according to one aspect of the present invention comprises a semiconductor substrate having a first main surface and a second main surface facing each other. The first main surface is the surface on which light is incident to the semiconductor substrate. The semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type. The plurality of second semiconductor regions of the second conductivity type are formed on the second main surface side and form a pn junction with the first semiconductor region. Each of the plurality of second semiconductor regions has a first region having a textured surface and a second region not having a textured surface. The thickness of the first region at the deepest position of the depression in the textured surface is smaller than the distance between the surface and the deepest position of the second region in the thickness direction of the semiconductor substrate.

[0006] In the back-incident semiconductor photodetector according to one embodiment described above, the first region of the second semiconductor region has a textured surface. Light in the long-wavelength range has a smaller absorption coefficient than light in the short-wavelength range. Therefore, long-wavelength light incident on the semiconductor substrate from the first main surface travels through the semiconductor substrate and reaches the textured surface. The light that reaches the textured surface is reflected or diffused by the textured surface and travels further through the semiconductor substrate. The distance that long-wavelength light travels through the semiconductor substrate is increased and it is absorbed by the semiconductor substrate. As a result, one embodiment described above improves the spectral sensitivity characteristics in the long-wavelength range.

[0007] Carriers generated by the absorption of light by the semiconductor substrate may recombine in the second semiconductor region. Since carriers that recombine in the second semiconductor region do not contribute to detection sensitivity, the spectral sensitivity characteristics may decrease. When the thickness of the second semiconductor region is large, carrier recombination in the second semiconductor region is more likely to occur than when the thickness of the second semiconductor region is small. In other words, when the distance from the surface of the second semiconductor region to the pn junction is large, carrier recombination in the second semiconductor region is more likely to occur than when the distance from the surface of the second semiconductor region to the pn junction is small.

[0008] In one of the above embodiments, the thickness of the first region at the deepest point of the depression in the textured surface is smaller than the distance between the surface of the second region and the deepest point in the thickness direction of the semiconductor substrate. In this case, the distance from the textured surface to the pn junction is smaller compared to the case where the thickness of the first region at the deepest point of the depression in the textured surface is greater than or equal to the distance between the surface of the second region and the deepest point in the thickness direction of the semiconductor substrate. Therefore, recombination of carriers caused by light incident on the semiconductor substrate in the second semiconductor region is suppressed. As a result, the above embodiment further improves the spectral sensitivity characteristics in the long wavelength range.

[0009] In one of the above embodiments, the thickness of the second region in the thickness direction of the semiconductor substrate may be greater than the thickness of the first region in the thickness direction of the semiconductor substrate. When stress is applied to a semiconductor substrate, carriers not caused by incident light may be generated. These carriers generate dark current. Stress is more likely to act on the second region than on the first region, and carriers not caused by incident light are more likely to be generated there. In a configuration where the thickness of the second region is greater than that of the first region, recombination of carriers not caused by incident light is more likely to occur in the second region compared to a configuration where the thickness of the second region is less than or equal to that of the first region. Therefore, this configuration suppresses the generation of dark current.

[0010] One embodiment described above may include an electrode that is located in the second region and is in contact with the second region. In this configuration, the electrode contacts a second region of the semiconductor substrate, where the thickness in the thickness direction is greater than that of the first region. When the electrode and the semiconductor substrate are in contact, the materials constituting the electrode and the materials constituting the semiconductor substrate may alloy together, potentially causing alloy spikes to form on the semiconductor substrate. When these alloy spikes reach the pn junction, they increase the leakage current. In a configuration where the thickness of the second region is greater than that of the first region, alloy spikes are less likely to reach the pn junction compared to a configuration where the thickness of the second region is less than or equal to that of the first region. Therefore, this configuration suppresses the increase in leakage current.

[0011] In one of the above embodiments, the textured surface of the first region may be located closer to the first principal surface than the surface of the second region in the thickness direction of the semiconductor substrate. In this case, stress is less likely to act on the first region. Therefore, the generation of carriers not caused by incident light is suppressed in the first region. As a result, this configuration suppresses the generation of dark current. In this configuration, for example, if a textured surface is formed in the second semiconductor region, the distance from the textured surface to the pn junction can be made even smaller. Therefore, this configuration can further improve the spectral sensitivity characteristics in the long wavelength range.

[0012] In one of the above embodiments, the edge region of the textured surface of the first region may be continuous with the surface of the second region and may also be inclined with respect to the thickness direction of the semiconductor substrate. When the textured surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate, stress is more likely to act on the second region. In a configuration where the edge region of the textured surface of the first region is inclined with respect to the thickness direction of the semiconductor substrate, the stress acting on the second region is more easily dispersed compared to a configuration where the edge region of the textured surface of the first region is parallel to the thickness direction of the semiconductor substrate. Therefore, even when stress acts on the second region, the concentration of stress on the second region is suppressed. This configuration suppresses the generation of carriers not caused by incident light. As a result, this configuration suppresses the generation of dark current. [Effects of the Invention]

[0013] According to one aspect of the present invention, a back-side incident semiconductor photodetector is provided that further improves spectral sensitivity characteristics in the long-wavelength range. [Brief explanation of the drawing]

[0014] [Figure 1] This is a plan view of a back-incident semiconductor photodetector according to one embodiment. [Figure 2] This figure shows the cross-sectional configuration of the back-side incident semiconductor photodetector according to this embodiment. [Figure 3]It is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to this embodiment. [Figure 4] It is a SEM image observing the texture surface. [Figure 5] It is a SEM image observing the texture surface. [Figure 6] It is a figure showing the cross-sectional configuration of one pixel. [Figure 7] It is a diagram showing the distribution of impurity concentration. [Figure 8] It is a schematic diagram showing an example of the manufacturing process of the back-illuminated semiconductor photodetector according to this embodiment. [Figure 9] It is a schematic diagram showing an example of the manufacturing process of the back-illuminated semiconductor photodetector according to this embodiment. [Figure 10] It is a schematic diagram showing an example of the manufacturing process of the back-illuminated semiconductor photodetector according to this embodiment. [Figure 11] It is a figure showing the cross-sectional configuration of an electronic component device including the back-illuminated semiconductor photodetector according to this embodiment. [Figure 12] It is a figure showing the cross-sectional configuration of the back-illuminated semiconductor photodetector according to the first modification example of this embodiment. [Figure 13] It is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to the first modification example. [Figure 14] It is a figure showing the cross-sectional configuration of an electronic component device including the back-illuminated semiconductor photodetector according to the first modification example. [Figure 15] It is a figure showing the cross-sectional configuration of the back-illuminated semiconductor photodetector according to the second modification example of this embodiment. [Figure 16] It is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to the second modification example. [Figure 17] It is a figure showing the cross-sectional configuration of the back-illuminated semiconductor photodetector according to the third modification example of this embodiment. [Figure 18] It is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to the third modification example. [Figure 19] It is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to the fourth modification example of this embodiment. [Figure 20] This is a plan view showing the configuration of a back-side incident semiconductor photodetector according to a fifth modified example of this embodiment. [Figure 21] This is a plan view showing the configuration of a back-side incident semiconductor photodetector according to the sixth modified example of this embodiment. [Figure 22] This figure shows the cross-sectional configuration of a back-side incident semiconductor photodetector according to the seventh modified example of this embodiment. [Figure 23] This figure shows the cross-sectional structure of a single pixel. [Figure 24] This is a schematic diagram showing an example of the manufacturing process of a back-incident semiconductor photodetector according to the seventh modified example. [Figure 25] This is a schematic diagram showing an example of the manufacturing process of a back-incident semiconductor photodetector according to the seventh modified example. [Figure 26] This is a diagram showing the distribution of impurity concentrations. [Modes for carrying out the invention]

[0015] Embodiments of the present invention will be described in detail below with reference to the attached drawings. In this description, the same reference numerals will be used for elements that are the same or have the same function, and redundant explanations will be omitted.

[0016] The configuration of the back-side-incident semiconductor photodetector 1 according to this embodiment will be described with reference to Figures 1 to 6. Figure 1 is a plan view of the back-side-incident semiconductor photodetector according to this embodiment. Figure 2 is a diagram showing the cross-sectional configuration of the back-side-incident semiconductor photodetector according to this embodiment. Figure 3 is a plan view showing the configuration of the back-side-incident semiconductor photodetector according to this embodiment. Figures 4 and 5 are SEM images of the textured surface. Figure 6 is a diagram showing the cross-sectional configuration of a single pixel. In Figure 6, the hatching representing the cross-section is omitted.

[0017] As shown in Figures 1 and 2, the semiconductor photodetector 1 comprises a semiconductor substrate 11. The semiconductor substrate 11 is a substrate made of silicon (Si). The semiconductor substrate 11 has two opposing main surfaces 11a and 11b. Main surface 11a is the surface on which light is incident to the semiconductor substrate 11. Main surface 11a is the back surface, and main surface 11b is the front surface. In plan view, the semiconductor substrate 11 has, for example, a polygonal shape. In this embodiment, the semiconductor substrate 11 has a rectangular shape in plan view. The thickness of the semiconductor substrate 11 is, for example, 150 μm. The thickness direction of the semiconductor substrate 11 is, for example, the direction parallel to the Z-axis. In this embodiment, the thickness direction of the semiconductor substrate 11 coincides with the direction in which the main surfaces 11a and 11b face each other. The thickness direction of the semiconductor substrate 11 coincides with the direction perpendicular to the semiconductor substrate 11, the direction perpendicular to the main surface 11a, and the direction perpendicular to the main surface 11b.

[0018] The semiconductor substrate 11 has a semiconductor region 13 of a first conductivity type, a plurality of semiconductor regions 15 of a second conductivity type, and a semiconductor region 16 of the first conductivity type. Each semiconductor region 15 is located on the main surface 11b side of the semiconductor substrate 11. The semiconductor region 16 is located on the main surface 11a side of the semiconductor substrate 11. The semiconductor region 16 functions as an accumulation layer. The first conductivity type is, for example, n-type. The second conductivity type is, for example, p-type. When the semiconductor substrate 11 is made of Si, the p-type impurities include, for example, group 13 elements, and the n-type impurities include, for example, group 15 elements. The p-type impurity is, for example, boron (B). The n-type impurity is, for example, nitrogen (N), phosphorus (P), or arsenic (As). The first conductivity type may be p-type and the second conductivity type may be n-type.

[0019] Semiconductor region 13 has a low impurity concentration. Semiconductor regions 15 and 16 have high impurity concentrations. Semiconductor regions 15 and 16 have higher impurity concentrations than semiconductor region 13. The impurity concentration of semiconductor region 13 is, for example, 5 × 10⁻⁶. 12 cm -3 Therefore, the impurity concentration in the semiconductor region 15 is, for example, 1 × 10⁻⁶. 19 cm -3Therefore, the impurity concentration in the semiconductor region 16 is, for example, 1 × 10⁻⁶. 15 cm -3 The maximum thickness of the semiconductor region 15 is, for example, 5 μm. The thickness of the semiconductor region 16 is, for example, 1 μm.

[0020] Multiple semiconductor regions 15 are arranged in a two-dimensional array when viewed from a direction orthogonal to the semiconductor substrate 11. In this embodiment, the multiple semiconductor regions 15 are arranged along a first direction and a second direction that are orthogonal to each other. The multiple semiconductor regions 15 are arranged in an M row and N column (M and N are integers of 2 or more). The multiple semiconductor regions 15 are arranged along a first direction and a second direction that are orthogonal to each other. The first direction is, for example, a direction parallel to the X-axis. The second direction is, for example, a direction parallel to the Y-axis. Each semiconductor region 15 exhibits a polygonal shape when viewed from a direction orthogonal to the semiconductor substrate 11. In this embodiment, each semiconductor region 15 exhibits a rectangular shape. Each semiconductor region 15 may also exhibit a circular shape when viewed from a direction orthogonal to the semiconductor substrate 11. In this embodiment, one semiconductor region 15 constitutes one pixel. The semiconductor photodetector 1 has multiple pixels arranged in a two-dimensional array. The semiconductor region 13 and each semiconductor region 15 constitute a pn junction. The pn junction is formed at the boundary between the semiconductor region 13 and each semiconductor region 15. In each pixel, the region including the semiconductor region 15 and the pn junction is the photosensitive region. The rectangular shape includes shapes with chamfered corners and shapes with rounded corners.

[0021] The semiconductor substrate 11 has a first-conductivity semiconductor region 14. The semiconductor region 14 is located on the main surface 11b side of the semiconductor substrate 11. When viewed from a direction perpendicular to the main surface 11b, the semiconductor region 14 has a frame shape. When viewed from a direction perpendicular to the main surface 11b, the semiconductor region 14 is provided along the edge of the main surface 11b so as to surround the region in which multiple semiconductor regions 15 are arranged. The semiconductor region 14 functions as a channel stop layer, suppressing the depletion layer from reaching the side surface of the semiconductor substrate 11.

[0022] Each semiconductor region 15 has a region 17 having a textured surface TS and a region 19 not having a textured surface TS. The textured surface TS is a surface on which fine irregularities are formed, as shown in Figures 4 and 5. Region 17 is a region on which fine irregularities are formed on its surface. Fine irregularities are formed on the entire surface of region 17. Region 17 has a textured surface TS on its entire surface. The textured surface TS is formed, for example, by wet etching. The textured surface TS may also be formed by dry etching or laser irradiation. A region whose surface is a textured surface TS is a textured region. The textured surface TS shown in Figure 4 is formed by wet etching. The textured surface TS shown in Figure 5 is formed by dry etching. In Figure 3, hatching is applied to the region that is a textured surface TS in order to easily understand it.

[0023] The irregularities of the textured surface TS are formed irregularly. Irregularity of the textured surface TS includes at least one of the following: the spacing between the vertices of the irregularities changes irregularly, and the height difference of the irregularities changes irregularly. In this embodiment, both the spacing between the vertices of the irregularities and the height difference of the irregularities change irregularly. The spacing between the vertices of the irregularities of the textured surface TS is, for example, 0.1 to 1.0 μm. The height difference of the irregularities of the textured surface TS is, for example, 0.5 to 1.5 μm. The irregularities of the textured surface TS may also be formed regularly.

[0024] Region 17, as shown in Figure 3, is located inside region 19 when viewed from a direction perpendicular to the semiconductor substrate 11. In this embodiment, when viewed from a direction perpendicular to the semiconductor substrate 11, region 17 is surrounded by region 19 along its entire edge. The surface of region 19 is flat. Region 19 has two continuous regions 19a and 19b. Region 19a is located along the edge of the semiconductor region 15. Region 19b has a region 19b located at one corner of the semiconductor region 15. The surfaces of region 19a and region 19b are located on the same plane. When viewed from a direction perpendicular to the semiconductor substrate 11, region 17 has a shape in which one corner of a rectangle is cut out in a rectangular shape. As shown in Figure 3, region 17 and region 19b are adjacent in directions that intersect the first and second directions when viewed from a direction perpendicular to the semiconductor substrate 11.

[0025] As shown in Figure 6, the thickness TH1 of region 17 at the deepest point of the depression in the textured surface TS is smaller than the distance D1 between the surface of region 19 (region 19b) and the deepest point in the thickness direction of the semiconductor substrate 11. The deepest point is, for example, the deepest point of the deepest depression among all the depressions. The deepest point may be the deepest point of any one depression among all the depressions. The deepest point may be the average position of the deepest points of all the depressions.

[0026] The impurity concentration in the semiconductor region 15 varies with respect to the depth from the surface (distance from the main surface 11b in the thickness direction of the semiconductor substrate 11), as shown in Figure 7. Figure 7 is a diagram showing the distribution of impurity concentration. The impurity concentration distribution shown in Figure 7 is the distribution when impurities are thermally diffused by the following process. After the semiconductor region 15 is formed, a textured surface TS is formed. Subsequently, impurities are thermally diffused by high-temperature heat treatment. This process will be described later as the manufacturing process of the semiconductor photodetector element 1 according to this embodiment.

[0027] The impurity concentration in the semiconductor region 15 remains high up to a predetermined depth, and gradually decreases as it moves toward the main surface 11a from that depth. The semiconductor region 15 has a region R1 located closer to the main surface 11b and a region R2 located closer to the main surface 11a than region R1, according to the distribution of impurity concentration. Regions R1 and R2 are continuous. Region R1 is a region with a high impurity concentration. Region R2 is a transition region where the impurity concentration gradually decreases from the impurity concentration in region R1. In this embodiment, the predetermined depth is, for example, about 3 μm.

[0028] In this embodiment, the deepest point of the depression in the textured surface TS is located near the boundary between region R1 and region R2. That is, the deepest point is located near the region where the impurity concentration of the semiconductor region 15 begins to decrease. In region 17, the proportion occupied by region R2 is greater than the proportion occupied by region R1. Region 17 may consist only of region R2.

[0029] The thickness of semiconductor region 15 (regions 17, 19) is defined, for example, by the distance from the surface to the depth at which the impurity concentration of semiconductor region 15 becomes equal to that of semiconductor region 16. This distance is also in the thickness direction of the semiconductor substrate 11. In this case, the thickness TH1 is defined by the distance from the deepest position of a depression in the textured surface TS to the depth at which the impurity concentration of semiconductor region 15 becomes equal to that of semiconductor region 16. The deepest position of a depression is, for example, the deepest position of the deepest depression among all depressions. In this case, the thickness TH1 indicates the minimum thickness of region 17. The deepest position of a depression may also be, for example, the deepest position of the shallowest depression among all depressions. In this case, the thickness TH1 indicates the maximum thickness of region 17. The deepest position of a depression may also be, for example, the average position of the deepest positions of all depressions. In this case, the thickness TH1 indicates the average thickness of region 17. The thickness TH1 is, for example, 0.1 to 1.0 μm.

[0030] The thickness of the semiconductor region 15 (regions 17, 19) may be defined, for example, by the distance from the surface to the end of region R2 in the thickness direction of the semiconductor substrate 11. As is clear from Figure 7, the end of region R2 is the position where the decrease in impurity concentration ends. In this case, the thickness TH1 is defined by the distance from the deepest point of the depression in the texture surface TS to the end of region R2.

[0031] The interval D1 is the depth of the depressions on the texture surface TS. If the deepest position is the deepest position of the deepest depression, then the interval D1 is the maximum depth of the depressions on the texture surface TS. If the deepest position is the deepest position of the shallowest depression, then the interval D1 is the minimum depth of the depressions on the texture surface TS. If the deepest position is the average position of the deepest positions of all depressions, then the interval D1 is the average depth of the depressions on the texture surface TS. The interval D1 is, for example, 1.0 to 2.5 μm.

[0032] The thickness TH2 of region 19 (region 19b) in the thickness direction of the semiconductor substrate 11 is greater than the thickness TH3 of region 17 in the thickness direction of the semiconductor substrate 11. The thickness TH2 is, for example, 5 μm. In this embodiment, the thickness TH2 is also the maximum thickness of the semiconductor region 15. The thickness TH3 of region 17 varies according to the irregularities of the textured surface TS. Thickness TH3 is, for example, the thickness at the deepest position of a depression in the textured surface TS. In this case, thickness TH3 is equivalent to thickness TH1. Thickness TH3 may also be, for example, the thickness at the apex of the textured surface TS. The apex that defines thickness TH3 is, for example, the highest apex of all apex. The highest apex is the apex located closest to the main surface 11b in the thickness direction of the semiconductor substrate 11. In this case, thickness TH3 represents the maximum thickness of region 17. The apex that defines thickness TH3 may also be, for example, the lowest apex of all apex. The lowest apex is the apex located closest to the main surface 11a in the thickness direction of the semiconductor substrate 11. Thickness TH3 may also be, for example, the distance from the average height position of the irregularities of the textured surface TS to the end of region R2. Thickness TH3 is, for example, 0.1 to 1.5 μm.

[0033] The textured surface TS is located closer to the main surface 11a than the surface of region 19 (regions 19a, 19b) in the thickness direction of the semiconductor substrate 11. That is, the textured surface TS is located closer to the main surface 11a than the virtual plane VP which includes the surface of region 19 (regions 19a, 19b). The main surface 11b is recessed in region 17. A step is formed between the textured surface TS and the surface of region 19. The edge region TSa of the textured surface TS in region 17 is continuous with the surface of region 19 (regions 19a, 19b) and is inclined with respect to the thickness direction of the semiconductor substrate 11. In this embodiment, the edge region TSa is inclined such that the thickness of region 17 at the edge region TSa gradually increases from region 17 toward region 19.

[0034] The semiconductor photodetector 1 comprises a plurality of insulating films 21, 23, 25, a plurality of pad electrodes 31, a plurality of UBMs (under-bump metals) 33, and a plurality of bump electrodes 35. In this embodiment, the semiconductor photodetector 1 comprises one pad electrode 31, one UBM 33, and one bump electrode 35 for each semiconductor region 15. The semiconductor photodetector 1 includes electrodes (not shown) electrically connected to the semiconductor region 14. The electrodes electrically connected to the semiconductor region 14 are arranged on the main surface 11b side.

[0035] The insulating film 21 is disposed on the main surface 11a of the semiconductor substrate 11. The insulating film 21 is formed on the main surface 11a. The insulating film 21 is, for example, an oxide film. In this embodiment, the insulating film 21 is made of silicon oxide (SiO2). The insulating film 21 is, for example, a silicon thermal oxide film. The insulating film 21 may be made of silicon nitride (SiN). In this case, the insulating film 21 is formed, for example, by plasma-enhanced chemical vapor deposition (Plasma CVD). The insulating film 21 functions as an anti-reflective film. The thickness of the insulating film 21 is, for example, 0.1 μm.

[0036] The insulating film 23 is located on the main surface 11b of the semiconductor substrate 11. The insulating film 23 is formed on the main surface 11b. The insulating film 23 is, for example, an oxide film. In this embodiment, the insulating film 21 is made of silicon oxide. The insulating film 23 is, for example, a silicon thermal oxide film. The insulating film 23 covers the surface of each semiconductor region 15. The insulating film 23 directly covers the entire texture surface TS. The insulating film 23 may be made of silicon nitride. In this case, the insulating film 23 is formed by low-pressure chemical vapor deposition (CVD). The insulating film 23 may be made of aluminum oxide (Al2O3). In this case, the insulating film 23 is formed by atomic layer deposition (ALD). The thickness of the insulating film 23 is, for example, 0.2 μm.

[0037] The insulating film 25 is located on the main surface 11b of the semiconductor substrate 11. The insulating film 25 is formed on the insulating film 23. The insulating film 25 is in contact with the insulating film 23. The insulating film 25 is, for example, a nitride film. In this embodiment, the insulating film 25 is made of silicon nitride. The insulating film 23 is located between the semiconductor substrate 11 and the insulating film 25. The insulating film 25 is indirectly located on the semiconductor substrate 11. The insulating film 25 indirectly covers the surface of each semiconductor region 15. The insulating film 25 directly covers the region corresponding to region 17 in the insulating film 23. The insulating film 25 indirectly covers the entire textured surface TS. The insulating film 25 may be made of silicon oxide. In this case, the insulating film 25 is formed, for example, by plasma CVD. The insulating film 25 functions as a passivation film. The thickness of the insulating film 25 is, for example, 0.1 to 0.4 μm.

[0038] The pad electrode 31 is located in region 19. In this embodiment, the pad electrode 31 is located in region 19b. The pad electrode 31 is formed on region 19b and on the insulating film 23. The pad electrode 31 is connected to region 19b through a contact hole H1 formed in the insulating film 23. The pad electrode 31 is in contact with region 19 and the insulating film 23. The pad electrode 31 is directly located on region 19b. The pad electrode 31 is in contact with the insulating film 25. The insulating film 25 covers the periphery of the pad electrode 31. The pad electrode 31 is made of a conductive material. For example, the pad electrode 31 is made of aluminum (Al). In this case, the pad electrode 31 is formed by sputtering or vapor deposition.

[0039] The pad electrode 31 has two electrode regions 31a and 31b, as shown in Figure 3. In this embodiment, the pad electrode 31 consists of two electrode regions 31a and 31b. Electrode region 31a is located in region 19. In this embodiment, electrode region 31a is located in region 19b. Electrode region 31a is in contact with region 19b. Electrode region 31a is directly located on region 19b. Electrode region 31b is located in at least a portion of the region corresponding to region 17 in the insulating film 23. Electrode region 31b is located in region 17 such that the insulating film 23 is located between region 17 and electrode region 31b. Electrode region 31b is continuous with electrode region 31a. When viewed from a direction perpendicular to the semiconductor substrate 11, the pad electrode 31 overlaps with the entire boundary between region 17 and region 19b. In this embodiment, the electrode region 31b overlaps with the edge region TSa, which is continuous with region 19b, when viewed from a direction perpendicular to the semiconductor substrate 11. The electrode region 31b is indirectly arranged on the edge region TSa. In Figure 3, the insulating films 23 and 25 are not shown.

[0040] UBM33 is located in region 19. In this embodiment, UBM33 is located in region 19b. UBM33 is formed on region 19b and on the insulating film 25. UBM33 is connected to the pad electrode 31 through contact holes H2 formed in the insulating film 25. UBM33 is in contact with the pad electrode 31. UBM33 is in contact with the insulating film 25. UBM33 is made of a material that has excellent electrical and physical connectivity with the bump electrode 35. UBM33 is made of a laminate of, for example, a layer made of titanium (Ti) and a layer made of platinum (Pt). UBM33 is formed, for example, by a multilayer deposition method.

[0041] The bump electrode 35 is located in region 19. In this embodiment, the bump electrode 35 is located in region 19b. The bump electrode 35 is formed on the UBM 33. The bump electrode 35 is in contact with the UBM 33. The UBM 33 is located between the pad electrode 31 and the bump electrode 35. The bump electrode 35 is indirectly located on region 19. The bump electrode 35 is indirectly located on the pad electrode 31. The bump electrode 35 is electrically connected to region 19b (semiconductor region 15) through the UBM 33 and the pad electrode 31. The bump electrode 35 is made of solder material. The bump electrode 35 is made of, for example, indium (In). The bump electrode 35 is formed, for example, by a vapor deposition method.

[0042] In the semiconductor photodetector 1, the semiconductor region 13 is brought into a completely depleted state by the application of a bias voltage. That is, the depletion layer extending from the semiconductor region 15 reaches the semiconductor region 13. The semiconductor region 13 does not necessarily have to be completely depleted.

[0043] Next, an example of the manufacturing process of the semiconductor photodetector 1 will be described with reference to Figures 8 to 10. Figures 8 to 10 are schematic diagrams showing an example of the manufacturing process of a back-side incident semiconductor photodetector according to this embodiment. In Figures 8 to 10, hatching representing cross-sections is omitted.

[0044] As shown in Figure 8(a), an n-type semiconductor substrate 11 is prepared, and an oxide film 51 is formed on the main surface 11a, while an oxide film 53 is formed on the main surface 11b. The oxide films 51 and 53 are formed, for example, by heating the semiconductor substrate 11 in an oxygen atmosphere. In the state shown in Figure 8(a), the semiconductor substrate 11 consists of semiconductor regions 13 and does not have semiconductor regions 15 and 16.

[0045] As shown in Figure 8(b), multiple semiconductor regions 15 and semiconductor regions 16 are formed on the semiconductor substrate 11. Through this process, a semiconductor substrate 11 having a semiconductor region 13, multiple semiconductor regions 15, and semiconductor region 16 is prepared. The semiconductor region 15 is formed as follows: An opening 53a is formed in the oxide film 53 by patterning the oxide film 53. The opening 53a is rectangular in shape. p-type impurities are added to the semiconductor substrate 11 from the main surface 11b through the opening 53a of the oxide film 53. The added p-type impurities diffuse into the semiconductor substrate 11 by high-temperature heat treatment. The semiconductor region 15 is formed by the p-type impurities diffused from the main surface 11b at a high concentration. As a result of the high-temperature heat treatment described above, an oxide film 55 is formed on the semiconductor region 15 (see Figure 8(c)). The semiconductor region 16 is formed as follows: n-type impurities are added to the semiconductor substrate 11 from the main surface 11a. The added n-type impurities diffuse into the semiconductor substrate 11 by the high-temperature heat treatment described above. The semiconductor region 16 is formed by the n-type impurities that have diffused from the main surface 11a at a high concentration.

[0046] As shown in Figure 8(c), a contact hole H1 is formed in the oxide film 55 by patterning the oxide film 55. After the contact hole H1 is formed, a silicon nitride film 57 is formed on the oxide films 51 and 55. The silicon nitride film 57 is formed, for example, by vacuum CVD.

[0047] As shown in Figure 9(a), the silicon nitride film 57 formed on the oxide film 55 and the oxide film 55 are patterned, and an opening 59 is formed at a position corresponding to region 17 of the semiconductor region 15. The opening 59 is formed, for example, by dry etching.

[0048] As shown in Figure 9(b), the textured surface TS is formed in the region of the semiconductor region 15 that is exposed from the opening 59. The textured surface TS is formed, for example, by wet etching, as described above. In the figures from Figure 9(b) onward, the regions with cross-hatching are the regions where the textured surface TS is formed.

[0049] As shown in Figure 9(c), the oxide film 61 is formed in the region of the semiconductor region 15 that is exposed from the opening 59. The oxide film 61 is formed on the textured surface TS. The oxide film 61 is formed, for example, by heating the semiconductor substrate 11 in an oxygen atmosphere. The oxide films 53 and 61 constitute the insulating film 23.

[0050] As shown in Figure 10(a), the silicon nitride film 57 is removed from the oxide film 51 and the insulating film 23 (oxide films 53, 61). Removal of the silicon nitride film 57 exposes the semiconductor region 15 through the contact hole H1. Subsequently, the pad electrode 31 is formed in the region of the semiconductor region 15 that is exposed through the contact hole H1. The pad electrode 31 is also formed so as to be located on the region of the insulating film 23 around the contact hole H1. The oxide film 51 constitutes the insulating film 21.

[0051] As shown in Figure 10(b), after the insulating film 25 is formed on the insulating film 23, the contact hole H2 is formed in the insulating film 25 by patterning the insulating film 25. The formation of the contact hole H2 exposes a portion of the pad electrode 31.

[0052] As shown in Figure 10(c), the UBM 33 is formed in the region of the pad electrode 31 that is exposed from the contact hole H2. The UBM 33 is also formed so as to be located on the region of the insulating film 25 around the contact hole H2. Subsequently, the bump electrode 35 is formed on the UBM 33. Through these processes, the semiconductor photodetector 1 is obtained.

[0053] Next, the configuration of the electronic component device ED equipped with the semiconductor photodetector 1 will be described with reference to Figure 11. Figure 11 is a diagram showing the cross-sectional configuration of the electronic component device equipped with the back-side incident semiconductor photodetector according to this embodiment.

[0054] The electronic component device ED comprises a semiconductor photodetector 1, an electronic component EC on which the semiconductor photodetector 1 is mounted, and a resin layer RL. The electronic component EC includes, for example, a wiring board or an ASIC (Application Specific Integrated Circuit).

[0055] The electronic component EC comprises multiple pad electrodes 71, multiple UBMs 73, and multiple bump electrodes 75. The multiple pad electrodes 71, multiple UBMs 73, and multiple bump electrodes 75 are positioned in a manner corresponding to the multiple bump electrodes 35 provided by the semiconductor photodetector 1. The semiconductor photodetector 1 is mounted on the electronic component EC by joining the corresponding bump electrodes 35 and bump electrodes 75. Electrodes electrically connected to the semiconductor region 14 are also joined to the bump electrodes (not shown) of the electronic component EC.

[0056] The resin layer RL is positioned between the semiconductor photodetector 1 and the electronic component EC. The resin layer RL functions as an underfill layer. The resin layer RL is formed by the curing of a resin material that fills the space formed between the semiconductor photodetector 1 and the electronic component EC. The resin layer RL includes, for example, an epoxy resin, a urethane resin, a silicone resin, or an acrylic resin.

[0057] As described above, in the semiconductor photodetector 1, region 17 of the semiconductor region 15 has a textured surface TS. Light in the long wavelength range has a smaller absorption coefficient than light in the short wavelength range. Therefore, long wavelength light incident on the semiconductor substrate 11 from the main surface 11a travels through the semiconductor substrate 11 and reaches the textured surface TS. The light that reaches the textured surface TS is reflected or diffused by the textured surface TS and travels further through the semiconductor substrate 11. The distance that long wavelength light travels through the semiconductor substrate 11 is increased and it is absorbed by the semiconductor substrate 11. As a result, the semiconductor photodetector 1 improves its spectral sensitivity characteristics in the long wavelength range.

[0058] Carriers generated by the absorption of light by the semiconductor substrate 11 may recombine in the semiconductor region 15. Since carriers that recombine in the semiconductor region 15 do not contribute to detection sensitivity, the spectral sensitivity characteristics may decrease. When the thickness of the semiconductor region 15 is large, carrier recombination in the semiconductor region 15 is more likely to occur than when the thickness of the semiconductor region 15 is small. In other words, when the distance from the surface of the semiconductor region 15 to the pn junction is large, carrier recombination in the semiconductor region 15 is more likely to occur than when the distance from the surface of the semiconductor region 15 to the pn junction is small. In the semiconductor photodetector 1, the thickness TH1 is smaller than the spacing D1. In this case, the distance from the texture surface TS to the pn junction is smaller compared to when the thickness TH1 is greater than or equal to the spacing D1. Therefore, recombination of carriers in the semiconductor region 15 caused by light incident on the semiconductor substrate 11 is suppressed. As a result, the semiconductor photodetector 1 further improves its spectral sensitivity characteristics in the long wavelength range.

[0059] In the manufacturing process described above, multiple semiconductor regions 15 (multiple semiconductor regions 152) are formed in multiple planned regions before the texture region (texture surface TS) is formed on the main surface 11b. During the process of forming the texture region after the multiple semiconductor regions 15 have been formed, it is necessary to ensure that the texture region does not reach the pn junction. In order to ensure that the texture region does not reach the pn junction, it is conceivable to increase the thickness of each semiconductor region 15. However, if the thickness of each semiconductor region 15 is large, as described above, the improvement in spectral sensitivity characteristics may be suppressed. Although the manufacturing process of the semiconductor photodetector 1 includes the formation of a texture region after the formation of multiple semiconductor regions 15, the thickness TH1 of the semiconductor photodetector 1 is smaller than the spacing D1. Therefore, it is difficult to suppress the improvement of spectral sensitivity characteristics in the semiconductor photodetector 1.

[0060] When stress is applied to the semiconductor substrate 11, carriers not caused by incident light may be generated. These carriers not caused by incident light generate dark current. Region 19 is more susceptible to stress than region 17, and therefore more prone to generating carriers not caused by incident light. In the semiconductor photodetector 1, the thickness TH2 is greater than the thickness TH3. Therefore, in the semiconductor photodetector 1, carrier recombination not caused by light incidence is more likely to occur in region 19 compared to a configuration where the thickness TH2 is less than or equal to the thickness TH3. As a result, the semiconductor photodetector 1 suppresses the generation of dark current.

[0061] In the semiconductor photodetector 1, the pad electrode 31 is in contact with region 19 (region 19b). When the pad electrode 31 is in contact with the semiconductor substrate 11, the material constituting the pad electrode 31 (Al) and the material constituting the semiconductor substrate 11 (Si) may alloy together, potentially causing alloy spikes to form on the semiconductor substrate 11. When these alloy spikes reach the pn junction, they increase the leakage current. In the semiconductor photodetector 1, since the thickness TH2 is greater than the thickness TH3, the alloy spike is less likely to reach the pn junction compared to a configuration where the thickness TH2 is less than or equal to the thickness TH3. Therefore, the semiconductor photodetector 1 suppresses an increase in leakage current.

[0062] In the semiconductor photodetector 1, the textured surface TS is located closer to the main surface 11a than the surface of region 19 in the thickness direction of the semiconductor substrate 11. That is, the textured surface TS is located closer to the main surface 11a than the virtual plane VP. In this case, stress is less likely to act on region 17. Therefore, the generation of carriers not caused by incident light is suppressed in region 17. As a result, the semiconductor photodetector 1 suppresses the generation of dark current. In the semiconductor photodetector 1, when the textured surface TS is formed on the semiconductor region 15 as in the manufacturing process described above, the distance from the textured surface TS to the pn junction becomes even smaller. Therefore, the semiconductor photodetector 1 further improves the spectral sensitivity characteristics in the long wavelength range.

[0063] The semiconductor photodetector 1 is mounted on the electronic component EC via the bump electrode 35. Therefore, when the semiconductor photodetector 1 is mounted on the electronic component EC, stress acts on region 19 (region 19b). Since the textured surface TS is located closer to the main surface 11a than the virtual plane VP, stress is less likely to act on region 17 even when the semiconductor photodetector 1 is mounted on the electronic component EC. Therefore, the generation of carriers not caused by incident light is suppressed in region 17. The semiconductor photodetector 1 further suppresses the generation of dark current.

[0064] When the semiconductor photodetector 1 is mounted on the electronic component EC, if the bump electrode 35 (or bump electrode 75) is crushed, the crushed bump electrode 35 (or bump electrode 75) may physically interfere with other parts of the semiconductor photodetector 1 (for example, wiring or textured surface TS). If the bump electrode 35 (or bump electrode 75) physically interferes with other wiring, there is a risk of a short circuit between the bump electrode 35 (or bump electrode 75) and the other wiring. If the bump electrode 35 (or bump electrode 75) physically interferes with the textured surface TS, the textured surface TS may be physically damaged, potentially adversely affecting its spectral sensitivity characteristics in the long-wavelength range. In the semiconductor photodetector 1, the textured surface TS is located closer to the main surface 11a than the virtual plane VP. A step is formed between the textured surface TS and the surface of region 19. Therefore, when the semiconductor photodetector 1 is mounted on the electronic component EC, the crushed bump electrode 35 (or bump electrode 75) is less likely to interfere with parts of the semiconductor photodetector 1 other than the bump electrode 35. The semiconductor photodetector 1 suppresses the occurrence of short circuits between the bump electrode 35 (or bump electrode 75) and other wiring, and also suppresses adverse effects on the spectral sensitivity characteristics in the long wavelength range.

[0065] When forming the bump electrodes 35, there is a risk that the equipment used to form the bump electrodes 35 may physically interfere with the textured surface TS. If the equipment used to form the bump electrodes 35 physically interferes with the textured surface TS, the textured surface TS may be physically damaged, which may adversely affect its spectral sensitivity characteristics in the long-wavelength range. In the semiconductor photodetector 1, the textured surface TS is located closer to the main surface 11a than the virtual plane VP. Therefore, the apparatus for forming the bump electrodes 35 is less likely to physically interfere with the textured surface TS. The semiconductor photodetector 1 suppresses the adverse effects on the spectral sensitivity characteristics in the long wavelength range when forming the bump electrodes 35.

[0066] In the semiconductor photodetector 1, the edge region TSa of the textured surface TS is continuous with the surface of region 19 (regions 19a, 19b) and is inclined with respect to the thickness direction of the semiconductor substrate 11. When the textured surface TS is located closer to the main surface 11a than the virtual plane VP, stress is more likely to act on region 19. In the semiconductor photodetector 1, the stress acting on region 19 is more easily dispersed compared to a configuration where the edge region TSa is parallel to the thickness direction of the semiconductor substrate. Therefore, even when stress acts on region 19, stress concentration on region 19 is suppressed. The semiconductor photodetector 1 suppresses the generation of carriers not caused by incident light. As a result, the semiconductor photodetector 1 further suppresses the generation of dark current.

[0067] In the semiconductor photodetector 1, region 19 (regions 19a, 19b) does not have a textured surface TS. Compared to a configuration in which region 19 has a textured surface TS, the formation of the pad electrode 31 on region 19 (region 19b) is easier in the semiconductor photodetector 1.

[0068] As described above, light reaching the surface of the textured surface TS is reflected or scattered by the textured surface TS. Compared to light reflected from a flat surface, the light reflected or scattered from the textured surface TS travels in various directions that intersect with the thickness direction of the semiconductor substrate 11. Therefore, light reflected or diffused from the textured surface TS may travel to adjacent pixels, potentially causing crosstalk between pixels. Crosstalk is a source of noise. In the semiconductor photodetector 1, the textured surface TS is provided for each semiconductor region 15. The textured surface TS is not provided in areas of the main surface 11b other than the semiconductor regions 15. The configuration in which the textured surface TS is provided for each semiconductor region 15 limits the occurrence of crosstalk compared to a configuration in which the textured surface TS is provided for the entire main surface 11b. Therefore, the semiconductor photodetector 1 suppresses the occurrence of crosstalk.

[0069] In the semiconductor photodetector 1, the pad electrode 31 has an electrode region 31a and an electrode region 31b. Electrode region 31a is located in region 19 (region 19b). Electrode region 31b is located in region 17 such that an insulating film 23 is positioned between it and region 17. Electrode region 31a and electrode region 31b are continuous. That is, the pad electrode 31 is arranged to extend across region 19b and region 17. In this configuration, the area of ​​the pad electrode 31 is larger than in a configuration where the pad electrode 31 is located only in region 19b. The UBM 33 and bump electrode 35 are located on the larger area pad electrode 31. Therefore, the semiconductor photodetector 1 improves the reliability and stability of the electrical connection between the semiconductor region 15 (region 19) and the bump electrode 35.

[0070] A configuration with a large textured surface TS (region 17) area improves spectral sensitivity characteristics in the long-wavelength range compared to a configuration with a small textured surface TS (region 17) area. Therefore, in order to improve spectral sensitivity characteristics in the long-wavelength range, the area of ​​region 17 should be as large as possible, and the area of ​​region 19 (region 19b) should be as small as possible.

[0071] The pad electrode 31 contacts region 19b through the contact hole H1. To facilitate the formation of the contact hole H1, it is formed in a region of the insulating film 23 located on region 19b. Because the surface of region 19b is flat, the contact hole H1 is easily formed in the insulating film 23. If the pad electrode 31 is formed misaligned from the contact hole H1, region 19b will be exposed through the contact hole H1. In this case, deterioration of the breakdown voltage characteristics and a decrease in reliability may occur. Therefore, the area of ​​the pad electrode 31 is set considering the precision of the formation position of the contact hole H1 and the precision of the formation position of the pad electrode 31. As a result, the area of ​​the pad electrode 31 must be large.

[0072] In a configuration where the pad electrode 31 does not have an electrode region 31b, the pad electrode 31 and region 17 do not overlap when viewed from a direction perpendicular to the main surface 11b. In this configuration, in order to secure the area of ​​the pad electrode 31, it is necessary to enlarge the area of ​​region 19b, which requires a reduction in the area of ​​region 17. Therefore, a configuration in which the pad electrode 31 does not have an electrode region 31b makes it difficult to improve the spectral sensitivity characteristics in the long wavelength range. In the semiconductor photodetector 1, the pad electrode 31 has an electrode region 31b. That is, at least a portion of the pad electrode 31 and the region 17 overlap when viewed from a direction perpendicular to the main surface 11b. Therefore, even when the area of ​​the pad electrode 31 is secured, the semiconductor photodetector 1 improves the spectral sensitivity characteristics in the long wavelength range.

[0073] In the semiconductor photodetector 1, the insulating film 25 covers the periphery of the pad electrode 31. Therefore, the insulating film 25 suppresses peeling of the pad electrode 31. The insulating film 25 also suppresses the intrusion of material components of the bump electrode 35 from the interface between the pad electrode 31 and the insulating film 23. The insulating film 25 suppresses the occurrence of leakage current and short circuits.

[0074] In the semiconductor photodetector 1, the insulating film 25 covers the region corresponding to region 17 in the insulating film 23. The laminated film composed of the insulating film 23 and the insulating film 25 covers the entire textured surface TS. By setting the thickness of the insulating film 23 and the insulating film 25 to desired values, the laminated film (insulating films 23, 25) can constitute a highly reflective film. In a configuration where the laminated film (insulating films 23, 25) constitutes a highly reflective film, the spectral sensitivity characteristics in the long wavelength range are further improved.

[0075] Insulating film 23 is an oxide film, and insulating film 25 is a nitride film. Therefore, the multilayer film (insulating films 23, 25) can easily form a highly reflective film. When the insulating film 23 is a silicon thermal oxide film, the heat treatment during the formation of the insulating film 23 smooths out the irregularities of the textured surface TS. When the irregularities of the textured surface TS are smooth, the process of forming the metal wiring including the pad electrodes 31 is easier.

[0076] Next, the configuration of the semiconductor photodetector 1 according to the first modified embodiment described above will be explained with reference to Figures 12 and 13. Figure 12 is a diagram showing the cross-sectional configuration of the back-incident semiconductor photodetector according to the first modified embodiment. Figure 13 is a plan view showing the configuration of the back-incident semiconductor photodetector according to the first modified embodiment. In Figure 13, the insulating films 23 and 25 are not shown. In Figure 13, hatching is applied to the region that is the textured surface TS in order to easily understand the region. The first modified embodiment is generally similar to or the same as the embodiment described above, but the first modified embodiment differs from the embodiment described above in terms of the configuration of the semiconductor substrate 11. The differences between the embodiment described above and the first modified embodiment will be explained below.

[0077] The semiconductor substrate 11 has a first-conductivity semiconductor region 20. The semiconductor region 20 is located on the main surface 11b side of the semiconductor substrate 11. The semiconductor region 20 has a high impurity concentration. The impurity concentration of the semiconductor region 20 is, for example, 1 × 10⁻⁶ 18 cm -3 The semiconductor region 20 has a thickness of, for example, 1.5 μm. The semiconductor region 20 exhibits a lattice shape when viewed from a direction perpendicular to the main surface 11b. The semiconductor region 20 is located between adjacent semiconductor regions 15 in the first direction and between adjacent semiconductor regions 15 in the second direction when viewed from a direction perpendicular to the main surface 11b. The semiconductor region 20 is continuous with the semiconductor region 14. The semiconductor region 20 functions as a channel stop layer and suppresses the spreading of the depletion layer between pixels. The semiconductor region 20 may be divided into multiple regions when viewed from a direction perpendicular to the main surface 11b.

[0078] The semiconductor photodetector 1 comprises a plurality of pad electrodes 41, a plurality of UBMs (under-bump metal) 43, and a plurality of bump electrodes 45. Each pad electrode 41 is arranged in the semiconductor region 20. Each pad electrode 41 is arranged at predetermined intervals when viewed from a direction perpendicular to the main surface 11b. The pad electrodes 41 are formed on the insulating film 23. The pad electrodes 41 are connected to the semiconductor region 20 through contact holes formed in the insulating film 23. The pad electrodes 41 are in contact with both the semiconductor region 20 and the insulating film 23. The pad electrodes 41 are directly arranged on the semiconductor region 20. The pad electrodes 41 are in contact with the insulating film 25. The insulating film 25 covers the periphery of the pad electrodes 41. The pad electrodes 41 are made of a conductive material. For example, the pad electrodes 41 are made of aluminum. In this case, the pad electrodes 41 are formed by sputtering or vapor deposition.

[0079] The UBM43 is located in the semiconductor region 20. The UBM43 is formed on the semiconductor region 20 and on the insulating film 25. The UBM43 is connected to the pad electrode 41 through contact holes formed in the insulating film 25. The UBM43 is in contact with the pad electrode 41. The UBM43 is in contact with the insulating film 25. The UBM43 is made of a material that has excellent electrical and physical connectivity with the bump electrode 45. The UBM43 is made of a laminate of, for example, a layer made of titanium and a layer made of platinum. The UBM43 is formed, for example, by a multilayer deposition method.

[0080] The bump electrode 45 is located in the semiconductor region 20. The bump electrode 45 is formed on the UBM 43. The bump electrode 45 is in contact with the UBM 43. The UBM 43 is located between the pad electrode 41 and the bump electrode 45. The bump electrode 45 is indirectly located on the semiconductor region 20. The bump electrode 45 is indirectly located on the pad electrode 41. The bump electrode 45 is electrically connected to the semiconductor region 20 through the UBM 43 and the pad electrode 41. The bump electrode 45 is made of solder material. The bump electrode 45 is made of, for example, indium (In). The bump electrode 45 is formed, for example, by a vapor deposition method.

[0081] Next, with reference to Figure 14, the configuration of the electronic component device ED equipped with the semiconductor photodetector 1 according to the first modified example will be described. Figure 14 is a diagram showing the cross-sectional configuration of the electronic component device equipped with the back-side incident semiconductor photodetector according to the first modified example.

[0082] The electronic component device ED comprises a semiconductor photodetector 1 according to the first modified example and an electronic component EC. The electronic component EC comprises a plurality of pad electrodes 71, a plurality of UBMs 73, and a plurality of bump electrodes 75. The plurality of pad electrodes 71, a plurality of UBMs 73, and a plurality of bump electrodes 75 are arranged at positions corresponding to the plurality of bump electrodes 35, 45 provided on the semiconductor photodetector 1. The semiconductor photodetector 1 is mounted on the electronic component EC by joining the bump electrodes 35, 45 and bump electrode 75 that correspond to each other.

[0083] Next, the configuration of the semiconductor photodetector 1 according to the second modified embodiment described above will be explained with reference to Figures 15 and 16. Figure 15 is a diagram showing the cross-sectional configuration of the back-side incident semiconductor photodetector according to the second modified embodiment. Figure 16 is a plan view showing the configuration of the back-side incident semiconductor photodetector according to the second modified embodiment. In Figure 16, the insulating films 23 and 25 are not shown. In Figure 16, hatching is applied to the region that is the textured surface TS in order to easily understand the region. The second modified embodiment is generally similar to or the same as the embodiment described above, but the second modified embodiment differs from the embodiment described above in terms of the configuration of the semiconductor substrate 11. The differences between the embodiment described above and the second modified embodiment will be explained below.

[0084] Trenches TR are formed in the semiconductor substrate 11 so as to separate each pixel from one another. The trenches TR open to the main surface 11b. The trenches TR are formed so as to divide the semiconductor region 20 when viewed from a direction perpendicular to the main surface 11b. The trenches TR are formed in a grid pattern so as to pass between adjacent semiconductor regions 15 in a first direction and between adjacent semiconductor regions 15 in a second direction when viewed from a direction perpendicular to the main surface 11b. The width of the opening of the trenches TR is, for example, 5 μm. The depth of the trenches TR is greater than the thickness TH2. The depth of the trenches TR is, for example, 50 μm. The trenches TR are formed, for example, by reactive ion etching (RIE). The trenches TR may be formed discontinuously when viewed from a direction perpendicular to the main surface 11b. In this case, for example, a plurality of trenches extending in a first direction when viewed from a direction perpendicular to the main surface 11b, and a plurality of trenches extending in a second direction when viewed from a direction perpendicular to the main surface 11b, are formed in the semiconductor substrate 11.

[0085] An insulating film 23 is formed on the inner surface (specifically, the sides and bottom) of the trench TR. The insulating film 23 extends from the main surface 11b into the trench TR. An insulating film 25 is formed on the insulating film 23 formed on the inner surface of the trench TR. The insulating film 25 extends from the insulating film 23 located on the main surface 11b into the trench TR. A filling layer may be placed inside the trench TR. The filling layer is made of, for example, metal. In this case, the filling layer (metal layer) is formed, for example, by CVD or electroplating.

[0086] The trench TR suppresses light reflected or diffused at the texture surface TS from traveling to adjacent pixels. Therefore, the second modification further suppresses the occurrence of crosstalk. The trench TR also suppresses carrier movement between adjacent pixels.

[0087] The semiconductor photodetector 1 according to the second modified example may be mounted on an electronic component EC, as shown in Figure 11. In this case, the electronic component device ED comprises the semiconductor photodetector 1 according to the second modified example and the electronic component EC.

[0088] Next, the configuration of the semiconductor photodetector 1 according to the third modified embodiment described above will be explained with reference to Figures 17 and 18. Figure 17 is a diagram showing the cross-sectional configuration of the back-side incident semiconductor photodetector according to the third modified embodiment. Figure 18 is a plan view showing the configuration of the back-side incident semiconductor photodetector according to the third modified embodiment. In Figure 18, the insulating films 23 and 25 are not shown. In Figure 18, hatching is applied to the region that is the textured surface TS in order to easily understand the region. The third modified embodiment is generally similar to or the same as the embodiment described above, but the third modified embodiment differs from the embodiment described above in terms of the configuration of the pad electrode 31. The differences between the embodiment described above and the third modified embodiment will be explained below.

[0089] The pad electrode 31 is positioned to cover the entire semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11. The electrode region 31b is indirectly positioned on the entire region corresponding to region 17 in the insulating film 23. When viewed from a direction perpendicular to the semiconductor substrate 11, the electrode region 31b overlaps with the entire edge region TSa that is continuous with region 19 (regions 19a, 19b). When viewed from a direction perpendicular to the semiconductor substrate 11, the pad electrode 31 overlaps with the entire boundary between region 17 and region 19. The pad electrode 31 is indirectly positioned on the entire semiconductor region 15.

[0090] If the pad electrode 31 is made of Al, the pad electrode 31 may absorb light that reaches it (for example, near-infrared light). Light absorption at the pad electrode 31 reduces the spectral sensitivity characteristics in the long-wavelength range. In the semiconductor photodetector 1, the insulating films 23 and 25 placed on the textured surface TS reflect or diffuse the light that reaches them. Therefore, the amount of light transmitted through the insulating films 23 and 25 is reduced. As a result, the semiconductor photodetector 1 suppresses a decrease in spectral sensitivity characteristics in the long wavelength range.

[0091] Next, the configuration of the semiconductor photodetector 1 according to the fourth and fifth modified embodiments of the above-described embodiment will be explained with reference to Figures 19 and 20. Figure 19 is a plan view showing the configuration of the back-side incident semiconductor photodetector according to the fourth modified embodiment. Figure 20 is a plan view showing the configuration of the back-side incident semiconductor photodetector according to the fifth modified embodiment. In Figures 19 and 20, the insulating films 23 and 25 are not shown. In Figures 19 and 20, hatching is applied to the textured surface TS region to facilitate understanding of the region. The fourth and fifth modified embodiments are generally similar to or the same as the above-described embodiment, however, the fourth modified embodiment differs from the above-described embodiment in terms of the configuration of the semiconductor region 15, and the fifth modified embodiment differs from the above-described embodiment in terms of the configuration of the semiconductor region 15 and the pad electrode 31. The differences between the above-described embodiment and the fourth and fifth modified embodiments will be explained below.

[0092] Region 19b is located in the center of the semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11, as shown in Figure 19. Region 19b is separated from region 19a. Region 17 (texture surface TS) is located between region 19a and region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. Electrode region 31b overlaps with the entire edge region TSa that is continuous with region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. Pad electrode 31 overlaps with the entire boundary between region 17 and region 19b when viewed from a direction perpendicular to the semiconductor substrate 11.

[0093] As shown in Figure 20, region 19b is located in the center of the semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11, as in the fourth modified example. The pad electrode 31 is arranged to cover the entire semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11, as in the third modified example. The electrode region 31b overlaps the entire edge region TSa continuous with region 19a and the entire edge region TSa continuous with region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. The pad electrode 31 overlaps the entire boundary between region 17 and region 19a and the entire boundary between region 17 and region 19b when viewed from a direction perpendicular to the semiconductor substrate 11.

[0094] In the configuration where region 19b is located in the center of the semiconductor region 15, the carrier travel distance is shorter and the time from the incident light to the output of the signal is shorter compared to the configuration where region 19b is located at one corner of the semiconductor region 15. Therefore, each of the fourth and fifth modified semiconductor photodetectors 1 improves the response speed.

[0095] Next, with reference to Figure 21, the configuration of the semiconductor photodetector 1 according to the sixth modified embodiment described above will be explained. Figure 21 is a plan view showing the configuration of the back-side incident semiconductor photodetector according to the sixth modified embodiment. In Figure 21, the insulating films 23 and 25 are not shown. In Figure 21, hatching is applied to the region that is the textured surface TS in order to easily understand it. The sixth modified embodiment is generally similar to or the same as the embodiment described above, but the sixth modified embodiment differs from the embodiment described above in terms of the configuration of the semiconductor region 15. The differences between the embodiment described above and the sixth modified embodiment will be explained below.

[0096] Region 17 and region 19b are adjacent in the first direction when viewed from a direction perpendicular to the semiconductor substrate 11. Regions 17 and 19a, 19b have a rectangular shape when viewed from a direction perpendicular to the semiconductor substrate 11. Region 19b is located outside region 19a. One edge of region 19a and one edge of region 19b are in contact. When viewed from a direction perpendicular to the semiconductor substrate 11, the area of ​​region 19b is smaller than the area of ​​region 19a. The pad electrode 31 is not located on region 17 (texture surface TS). When viewed from a direction perpendicular to the semiconductor substrate 11, the pad electrode 31 does not overlap with the texture surface TS. In the sixth modification, the semiconductor substrate 11 has a semiconductor region 20, but the semiconductor substrate 11 does not have to have a semiconductor region 20. Regions 17 and region 19b are adjacent in the second direction when viewed from a direction perpendicular to the semiconductor substrate 11.

[0097] Next, the configuration of the semiconductor photodetector 1 according to the seventh modification of the above-described embodiment will be explained with reference to Figures 22 and 23. Figure 22 is a diagram showing the cross-sectional configuration of the back-side incident semiconductor photodetector according to the seventh modification. Figure 23 is a diagram showing the cross-sectional configuration of a single pixel. In Figure 23, the hatching representing the cross-section is omitted. The seventh modification is generally similar to or the same as the above-described embodiment, however, the seventh modification differs from the above-described embodiment in terms of the configuration of the semiconductor region 15. The differences between the above-described embodiment and the seventh modification will be explained below.

[0098] Region 17 of semiconductor region 15 is formed along the textured surface TS. The interface between region 17 and semiconductor region 13 exhibits an uneven shape corresponding to the uneven shape of the textured surface TS. The interface between region 17 and semiconductor region 13 exhibits an uneven shape that is gentler than the uneven shape of the textured surface TS, for example. Region 19 of semiconductor region 15 is formed along the main surface 11b. The thickness TH2 of region 19 in the thickness direction of the semiconductor substrate 11 and the thickness TH3 of region 17 in the thickness direction of the semiconductor substrate 11 are equivalent. As described above, region 17 is formed along the textured surface TS. Therefore, the thickness TH3 does not change easily in accordance with the unevenness of the textured surface TS. In the seventh modification, the thickness TH3 is, for example, approximately constant. The thickness TH1 of region 17 at the deepest position of the depression in the textured surface TS is equivalent to the thicknesses TH2 and TH3. The thicknesses TH1, TH2, and TH3 are, for example, 0.5 μm.

[0099] The semiconductor substrate 11 may have a semiconductor region 20, as in the first modification. The semiconductor substrate 11 may have a trench TR formed in it, as in the second modification. The pad electrode 31 may be arranged to cover the entire semiconductor region 15, as in the third modification. Region 19b may be located in the center of the semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11, as in the fourth and fifth modifications. Region 17 and region 19b may be adjacent to each other in the first or second direction when viewed from a direction perpendicular to the semiconductor substrate 11, as in the sixth modification.

[0100] Next, an example of the manufacturing process of the semiconductor photodetector 1 according to the seventh modified example will be described with reference to Figures 24 and 25. Figures 24 and 25 are schematic diagrams showing an example of the manufacturing process of a back-incident semiconductor photodetector according to the seventh modified example. In Figures 24 and 25, hatching representing the cross-section is omitted. The differences between the manufacturing process in the above-described embodiment and the manufacturing process in the seventh modified example will be mainly explained below.

[0101] A semiconductor substrate 11 is prepared in which an oxide film 51 is formed on the main surface 11a and an oxide film 53 is formed on the main surface 11b (see Figure 9(a)). That is, a semiconductor substrate 11 having semiconductor regions 13 is prepared. The semiconductor substrate 11 has multiple planned regions PR on the main surface 11b side that form multiple semiconductor regions 15. In Figures 24 and 25, only one planned region PR is shown.

[0102] As shown in Figure 24(a), a plurality of semiconductor regions 151 and semiconductor region 16 are formed on the semiconductor substrate 11. Each semiconductor region 151 is formed in the corresponding planned region PR among a plurality of planned regions PR. The semiconductor region 151 is formed by the same process as the formation process of the semiconductor region 15 in the embodiment described above. The semiconductor region 151 is formed by p-type impurities diffused at a high concentration from the main surface 11b. The semiconductor region 16 is formed by the same process as the formation process of the semiconductor region 16 in the embodiment described above.

[0103] As shown in Figure 24(b), the contact hole H1, the silicon nitride film 57, and the opening 59 are each formed by the same process as the formation processes in the embodiments described above.

[0104] As shown in Figure 24(c), the textured surface TS is formed on the region of the semiconductor region 151 that is exposed from the opening 59 by the same process as the formation processes in the embodiments described above. That is, multiple textured regions are formed on the surface of the main surface 11b that is included in the multiple planned regions PR described above. A textured region is a region whose surface is a textured surface TS. The formation of the textured surface TS removes the region of the semiconductor region 151 that is exposed from the opening 59. The region of the semiconductor region 151 that is exposed from the opening 59 does not necessarily need to be completely removed, and a part of the region may remain. In Figures 24(c) and later, the regions with cross-hatching are the regions where the textured surface TS is formed.

[0105] As shown in Figure 25(a), a plurality of semiconductor regions 152 are formed on the semiconductor substrate 11. The semiconductor regions 152 are formed along the texture surface TS. That is, the semiconductor regions 152 are formed along the surface shape of the texture surface. Each semiconductor region 152 is formed in the corresponding planned region PR among a plurality of planned regions PR. The semiconductor regions 152 are formed by the same process as the formation process of the semiconductor region 15 in the embodiment described above. The semiconductor regions 152 are formed by p-type impurities diffused at a high concentration from the main surface 11b. The p-type impurities also diffuse in a direction perpendicular to the thickness direction of the semiconductor substrate 11. Therefore, the semiconductor regions 152 are formed continuously with the semiconductor regions 151. The semiconductor regions 152 and semiconductor regions 151 are integrated to constitute a semiconductor region 15. The semiconductor region 152 constitutes region 17. The semiconductor region 151 constitutes region 19. That is, a plurality of semiconductor regions 15 are formed on the semiconductor substrate 11 through this process. High-temperature heat treatment to form the semiconductor region 152 causes an oxide film 61 to form on the textured surface TS (see Figure 25(b)). The oxide films 53 and 61 constitute the insulating film 23.

[0106] As shown in Figure 25(b), the silicon nitride film 57 is removed from the oxide film 51 and the insulating film 23 (oxide films 53, 61). Removal of the silicon nitride film 57 exposes the semiconductor region 15 (semiconductor region 151) through the contact hole H1. Subsequently, as shown in Figure 25(c), the pad electrode 31, insulating film 25, UBM 33, and bump electrode 35 are each formed by the same processes as in the embodiments described above. Through these processes, the semiconductor photodetector element 1 according to the seventh modified example is obtained. The oxide film 51 constitutes the insulating film 21.

[0107] The impurity concentration in the semiconductor region 152 varies with respect to the depth from the surface (distance from the textured surface TS in the thickness direction of the semiconductor substrate 11), as shown in Figure 26. Figure 26 is a diagram showing the distribution of impurity concentrations. In Figure 26, for illustrative purposes, the interface between the textured surface TS and the semiconductor region 152 and the semiconductor region 13 is shown as flat, but in reality, the interface between the textured surface TS and the semiconductor region 152 and the semiconductor region 13 exhibits fine irregularities, as described above.

[0108] The impurity concentration in the semiconductor region 152 remains high up to a predetermined depth, and gradually decreases as it moves from the predetermined depth toward the main surface 11a. The semiconductor region 152 has regions R1 and R2 according to the distribution of impurity concentration. That is, in the seventh modification, region 17 has regions R1 and R2. In the semiconductor region 152 (region 17), the proportion occupied by region R2 is greater than the proportion occupied by region R1. In the seventh modification, the deepest position of the depression in the texture surface TS is separated from the region where the impurity concentration in the semiconductor region 15 begins to decrease by the thickness of region R1. In the seventh modification, the predetermined depth is, for example, about 0.45 μm.

[0109] In the seventh modification, after the texture region is formed on the main surface 11b, multiple semiconductor regions 15 (multiple semiconductor regions 152) are formed on multiple planned regions PR. In the process of forming the texture region (texture surface TS) after the multiple semiconductor regions 15 have been formed, the thickness of each semiconductor region 15 must be increased in order to reliably prevent the texture region from reaching the pn junction. Therefore, in the process of forming the multiple semiconductor regions 15 after the texture region has been formed, the thickness of each semiconductor region 15 can be reduced compared to the process in which the texture region is formed after the multiple semiconductor regions 15 have been formed. As a result, the semiconductor photodetector 1 according to the seventh modification can further improve the spectral sensitivity characteristics in the long wavelength range.

[0110] In the seventh modification, the semiconductor region 152 (region 17) is formed along the surface shape of the texture region. In this case, the thickness of the semiconductor region 152 (region 17) can be made even smaller. Therefore, the semiconductor photodetector 1 can reliably further improve its spectral sensitivity characteristics in the long wavelength range.

[0111] In the seventh modification, the semiconductor region 152 (region 17) is formed by adding p-type impurities within the planned region PR. In this case, the semiconductor region 152 can be easily formed using existing methods.

[0112] While embodiments and modifications of the present invention have been described above, the present invention is not necessarily limited to the embodiments and modifications described above, and various modifications are possible without departing from the spirit of the invention.

[0113] The textured surface TS does not have to be located closer to the main surface 11a than the surface of region 19 in the thickness direction of the semiconductor substrate 11. In other words, the textured surface TS does not have to be located closer to the main surface 11a than the virtual plane VP. For example, the top of the textured surface TS may be at the same position as the virtual plane VP. When the textured surface TS is located closer to the main surface 11a than the virtual plane VP, the semiconductor photodetector 1 suppresses the generation of dark current as described above. The edge region TSa does not have to be continuous with the surface of region 19. For example, the edge region TSa may be spaced apart from the step formed by region 17 and region 19. For example, a region without a textured surface TS may be located between the step formed by region 17 and region 19 and the edge region TSa. In this case, for example, when viewed from a direction orthogonal to the semiconductor substrate 11, the entire edge region TSa may be surrounded by a region without a textured surface TS. Region 17 may, for example, have a region without a textured surface TS. The edge region TSa may be substantially parallel to the thickness direction of the semiconductor substrate. When the edge region TSa is inclined with respect to the thickness direction of the semiconductor substrate 11, the semiconductor photodetector 1 further suppresses the generation of dark current, as described above. The bump electrode 35 may be directly placed on the pad electrode 31. In this case, the semiconductor photodetector 1 does not include the UBM 33.

[0114] This specification discloses the following additional information. (Note 1) A semiconductor substrate having a first main surface and a second main surface facing each other, The semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type formed on the second main surface side and constituting a pn junction with the first semiconductor region. Each of the aforementioned plurality of second semiconductor regions has a first region having a textured surface and a second region, The thickness of the first region at the deepest position of the depression on the textured surface is smaller than the distance between the surface of the second region and the deepest position in the thickness direction of the semiconductor substrate. A back-side incident semiconductor photodetector, wherein the first main surface is the light incidence surface to the semiconductor substrate. (Note 2) The back-side incident semiconductor photodetector as described in Appendix 1, wherein the thickness of the second region in the thickness direction of the semiconductor substrate is greater than the thickness of the first region in the thickness direction of the semiconductor substrate. (Note 3) The back-side incident semiconductor photodetector as described in Appendix 2, further comprising an electrode positioned in the second region and in contact with the second region. (Note 4) The back-side incident semiconductor photodetector according to any one of appendices 1 to 3, wherein the textured surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate. (Note 5) The back-side incident semiconductor photodetector as described in Appendix 4, wherein the edge region of the textured surface of the first region is continuous with the surface of the second region and is inclined with respect to the thickness direction of the semiconductor substrate. (Note 6) The second region is a back-side incident semiconductor photodetector according to any one of appendices 1 to 5, which does not have a textured surface. In the embodiment of Appendix 1, the second region may have a surface with irregularities formed thereon. The second region may have, for example, a textured surface. The second region may have, for example, a surface with irregularities formed thereon in a manner different from that of a textured surface. If the second region has a surface with irregularities, the position of the surface of the second region may be defined as follows. The position of the surface in the second region may be the deepest point of the deepest depression among all the depressions. The position of the surface in the second region may be the deepest point of the shallowest depression among all the depressions. The position of the surface in the second region may be the deepest point of any one of the depressions among all the depressions. The position of the surface in the second region may be the average position of the deepest points of all the depressions. The position of the surface of the second region may be defined by the highest vertex among all the vertices. The position of the surface of the second region may be defined by the lowest vertex among all the vertices. The position of the surface of the second region may be defined by any one vertex among all the vertices. The position of the surface of the second region may also be the average height position of all the vertices. If the second region has a surface with irregularities, the thickness of the second region varies according to the surface irregularities. In this case, the thickness of the second region may be the maximum thickness of the second region, the minimum thickness of the second region, or the average thickness of the second region. The deepest position of the depression on the textured surface in the first region and the thickness of the first region may be defined in the same way as in the embodiments described above. In the embodiment of Appendix 1, the second region may have a surface with irregularities and a flat surface. In this case, the position of the surface of the second region may be defined by the surface with irregularities or by the flat surface. The position of the surface of the second region may also be the average height position between the surface with irregularities and the flat surface.

[0115] This specification also discloses the following notes: (Note 7) A semiconductor substrate having a first main surface and a second main surface facing each other, The semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type formed on the second main surface side and constituting a pn junction with the first semiconductor region. Each of the aforementioned plurality of second semiconductor regions has a textured surface, The thickness of the second semiconductor region at the deepest position of the depression on the textured surface is less than the distance between the top of the textured surface and the deepest position in the thickness direction of the semiconductor substrate. A back-side incident semiconductor photodetector, wherein the first main surface is the light incidence surface to the semiconductor substrate. In the embodiment of Appendix 7, the deepest position may be defined as follows: The deepest position may be the deepest point of the deepest depression among all depressions. The deepest position may be the deepest point of the shallowest depression among all depressions. The deepest position may be the deepest point of any one depression among all depressions. The deepest position may be the average position of the deepest points of all depressions. In the embodiment of Appendix 7, the tops of the textured surface may be defined as follows: A vertex on a texture surface may be the highest vertex among all vertices. A vertex on a texture surface may be the lowest vertex among all vertices. A vertex on a texture surface may be any single vertex among all vertices. A vertex on a texture surface may be the average position of all vertices. In the embodiment of Appendix 7, the distance between the top of the textured surface and the deepest point in the thickness direction of the semiconductor substrate may be defined as follows. The above distance may be the maximum value of the height difference of the unevenness, or the minimum value of the height difference of the unevenness. The above distance may be the height difference of the unevenness at any position on the texture surface. The above distance may be the average value of the height difference of the unevenness. In the embodiment of Appendix 7, the entire surface of each second semiconductor region may be a textured surface. [Explanation of symbols]

[0116] 1...Back-side incident semiconductor photodetector, 11...Semiconductor substrate, 11a,11b...Main surface, 13,15...Semiconductor region, 17...Region with textured surface, 19...Region without textured surface, 31...Pad electrode, D1...Distance between the surface of the region without textured surface and the deepest position of the depression of the textured surface, TH1...Thickness at the deepest position of the depression of the textured surface, TH2...Thickness of the region without textured surface in the thickness direction of the semiconductor substrate, TH3...Thickness of the region with textured surface in the thickness direction of the semiconductor substrate, TS...Textured surface, TSa...Edge region of the textured surface.

Claims

1. A semiconductor substrate having a first main surface and a second main surface facing each other, The semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type formed on the second main surface side and constituting a pn junction with the first semiconductor region. Each of the plurality of second semiconductor regions has a first region having a textured surface and a second region, The textured surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate. The edge region of the textured surface of the first region is continuous with the surface of the second region and is inclined with respect to the thickness direction of the semiconductor substrate. A back-side incident semiconductor photodetector, wherein the first main surface is the light incidence surface to the semiconductor substrate.

2. A semiconductor substrate having a first main surface and a second main surface facing each other, The semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type formed on the second main surface side and constituting a pn junction with the first semiconductor region. Each of the plurality of second semiconductor regions has a first region having a textured surface and a second region, The textured surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate. In the thickness direction of the semiconductor substrate, the distance between the surface of the second region and the top of the textured surface is greater than the thickness of the first region at the deepest position of the depression in the textured surface. A back-side incident semiconductor photodetector, wherein the first main surface is the light incidence surface to the semiconductor substrate.

3. The back-side incident semiconductor photodetector according to claim 1 or 2, wherein the thickness of the second region in the thickness direction of the semiconductor substrate is greater than the thickness of the first region in the thickness direction of the semiconductor substrate.

4. The back-side incident semiconductor photodetector according to claim 3, further comprising an electrode disposed in the second region and in contact with the second region.

5. The back-side incident semiconductor photodetector according to any one of claims 1 to 4, wherein the thickness of the second region of the semiconductor substrate in the thickness direction is greater than the distance between the surface of the second region and the deepest position of the depression of the texture surface in the thickness direction of the semiconductor substrate.

6. The interface between the first region and the first semiconductor region exhibits an uneven shape corresponding to the textured surface. The back-side incident semiconductor photodetector according to claim 1 or 2, wherein the thickness of the second region in the thickness direction of the semiconductor substrate is equal to the thickness of the first region in the thickness direction of the semiconductor substrate.

7. The back-side incident semiconductor photodetector according to any one of claims 2 to 6, wherein the edge region of the textured surface of the first region is continuous with the surface of the second region and is inclined with respect to the thickness direction of the semiconductor substrate.

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