3D stackable bidirectional access device for memory arrays

Abstract

A method of fabricating a vertical metal semiconductor field effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystallized silicon layer, and forming a second oxide layer on a top surface of the second electrode. The method also includes forming a third electrode on a top surface of the crystallized silicon layer.

Description

[Technical Field]

[0001] This disclosure relates to a three-dimensional (3D) stackable bidirectional access device for memory arrays, and a method for manufacturing a 3D stackable bidirectional access device. [Background technology]

[0002] Back-end-of-line (BEOL) access devices can enable 3D memory arrays for storage-class memory or neuromorphic and cognitive computing, or both. Ovonic threshold switches (OTS) are one type of access device that can be used in stackable 3D memory applications. It may be desirable to develop alternative solutions for stackable 3D memory applications. [Overview of the Initiative]

[0003] Embodiments of the present disclosure relate to a method for manufacturing a vertical metal semiconductor field-effect transistor (MESFET) device. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystalline silicon layer on the first electrode, forming a second electrode on the first oxide layer and on the sidewall of the crystalline silicon layer, and forming a second oxide layer on the upper surface of the second electrode. The method also includes forming a third electrode on the upper surface of the crystalline silicon layer.

[0004] Another embodiment relates to a vertical MESFET device. The device includes a first oxide layer, a first electrode formed in the oxide layer, a crystalline silicon layer formed on the first electrode, a second electrode formed on the first oxide layer and on the sidewall of the crystalline silicon layer, and a second oxide layer formed on the upper surface of the second electrode. The device also includes a third electrode formed on the upper surface of the crystalline silicon layer.

[0005] Other embodiments relate to memory devices. The memory device includes a bidirectional access device comprising: a first oxide layer; a first electrode formed in the oxide layer; a crystalline silicon layer formed on the first electrode; a second electrode formed on the first oxide layer and on the sidewall of the crystalline silicon layer; a second oxide layer formed on the upper surface of the second electrode; and a third electrode formed on the upper surface of the crystalline silicon layer. The memory device also includes a memory device connected to the bidirectional access device. Other embodiments relate to methods for manufacturing memory devices.

[0006] The above summary is not intended to describe any of the embodiments or implementations illustrated in this disclosure.

[0007] The drawings included herein are incorporated herein and form part thereof. They illustrate embodiments of the herein and, together with this description, illustrate the principles of the herein. The drawings are illustrative of specific embodiments and do not limit the herein. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view of a BEOL-compatible semiconductor device for a memory array in an intermediate stage of the manufacturing process, according to multiple embodiments. [Figure 2] This is a cross-sectional view of the semiconductor device shown in Figure 1 after an additional manufacturing process, according to multiple embodiments. [Figure 3] This is a cross-sectional view of the semiconductor device shown in Figure 2 after an additional manufacturing process, according to multiple embodiments. [Figure 4] Figure 3 is a cross-sectional view of a semiconductor device after an additional manufacturing process, according to multiple embodiments. [Figure 5] Figure 4 is a cross-sectional view of a semiconductor device after an additional manufacturing process, according to multiple embodiments. [Figure 6] Figure 5 is a cross-sectional view of a semiconductor device after an additional manufacturing process, according to multiple embodiments. [Figure 7]Figure 6 is a cross-sectional view of a semiconductor device after an additional manufacturing process, according to multiple embodiments. [Figure 8] Figure 7 is a cross-sectional view of a semiconductor device after an additional manufacturing process, according to multiple embodiments. [Figure 9] Figure 8 is a cross-sectional view of a semiconductor device after an additional manufacturing process, according to multiple embodiments. [Figure 10] Figure 9 is a cross-sectional view of a semiconductor device after an additional manufacturing process, according to multiple embodiments. [Figure 11] This is a cross-sectional view of the semiconductor device shown in Figure 10 after an additional manufacturing process, according to multiple embodiments. [Figure 12A] Figure 11 is a cross-sectional view of a semiconductor device combined with a mushroom cell type memory device according to multiple embodiments. [Figure 12B] Figure 11 is a cross-sectional view of a semiconductor device combined with a pillar-cell memory (PCM) device or a resistive random-access memory (RRAM) device, according to multiple embodiments. [Figure 12C] Figure 11 is a cross-sectional view of a semiconductor device combined with a confined PCM device according to multiple embodiments. [Modes for carrying out the invention]

[0009] As mentioned above, ovonic threshold switches (OTS) are currently being studied as access devices for stackable 3D memory applications. Some of these OTS devices are two-terminal devices that can be switched between a fully ON state and a fully OFF state by applying a voltage to the device. However, their snap-back behavior involves a rapid turn-on voltage, and as a result, two-terminal devices can only write to memory cells in two states (i.e., SET level and RESET level). Furthermore, the snap-back behavior can make it difficult to control the magnitude of the current flowing through the device. In addition, the materials contained in the OTS device elements may include As and Se, which may be undesirable materials for use in the manufacturing process. Moreover, OTS devices can be difficult to pattern and may be sensitive to reactive ion etching (RIE), which can damage the device during the patterning process. As a result, the yield of OTS devices may decrease.

[0010] Another possible access device for stackable 3D memory applications is a recrystallized Si diode, which is also a two-terminal access device. These recrystallized Si diode access devices may address some of the shortcomings of OTS devices. For example, recrystallized Si diodes have lower RIE sensitivity, lower As content compared to OTS devices, and in some cases lack snapback behavior, potentially allowing the memory to be set to different states (although the IV (current / voltage) characteristics are still exponential). Diodes have a simple structure, a small footprint, and can provide high drive current. Compared to obonic threshold switches (OTS), diodes have advantages such as established device physics / manufacturing techniques, better reliability, and high-temperature stability. However, given that diodes are minority-carrier devices, their OFF characteristics may be more sensitive to grain boundary dislocations than majority-carrier devices such as field-effect transistors. In addition, the presence of crystal grain boundaries can induce non-uniformity between devices in the ON characteristics of the diode. Furthermore, the IV characteristics of recrystallized silicon diodes can be exponential, which may necessitate very precise control of the current level when multi-state memory functionality is desired. Therefore, it may be desirable to find alternative solutions for three-dimensional stackable bidirectional access devices for memory arrays.

[0011] This disclosure describes a three-dimensional (3D) stackable bidirectional access device for memory arrays and a method for manufacturing a 3D stackable bidirectional access device. In particular, this disclosure describes a BEOL-compatible 3D stackable bidirectional access device incorporating crystallized metal-semiconductor field-effect transistor (MESFET) devices in the back-end-of-line (BEOL). Generally, BEOL or BEOL process compatible means that the formation / fabrication of the access device does not damage the high-performance transistors formed in the FEOL / BEOL. According to several embodiments, these access devices can provide bidirectional operation, are BEOL process compatible and can therefore be manufactured, are 3D stackable and can be used in both PCM and RRAM memories. A third terminal of the access device allows for better control of the current level, resulting in multiple bit selections. Therefore, according to embodiments of the present invention, these access devices can enable a significant increase in the bit density of the memory array.

[0012] This specification describes various embodiments of the disclosure with reference to the relevant drawings. Alternative embodiments can be devised without departing from the scope of this disclosure. It should be noted that various connections and positional relationships between elements (e.g., above, below, next to, etc.) are described in the following description and drawings. These connections or positional relationships, or both, may be direct or indirect unless otherwise specified, and this disclosure is not intended to be limiting in this respect. Thus, the joining of entities may refer to either direct or indirect joining, and the positional relationships between entities may be direct or indirect. As an example of an indirect positional relationship, when this specification refers to layer "A" covering layer "B", it includes a situation in which there is one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B" to the extent that the relevant properties and functionality of layer "A" and layer "B" are not substantially altered by the intermediate layer.

[0013] The following definitions and abbreviations are used to interpret the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "have," "having," "contains," or "containing," or any other variations thereof, are intended to include non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises the recited elements is not necessarily limited to only those elements and may include other elements not expressly recited or inherent to such composition, mixture, process, method, article, or apparatus.

[0014] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof are related to the orientation in the figures of the structures and methods described. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, e.g., a first structure, is present over a second element, e.g., a second structure, and in this case there may be intervening elements such as a bonding surface structure between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected without any intermediate conductive, insulating, or semiconductor layer at the interface between the two elements. It should be noted that terms such as "selective with respect to a second element" for a first element mean that the first element can be etched and the second element can function as an etch stop.

[0015] For the sake of brevity, the prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Further still, the various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes having additional steps or functionality not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and thus, for the sake of brevity, many of the conventional steps are only briefly mentioned herein or are completely omitted, and the details of well-known processes are not provided.

[0016] Generally, the various processes used to form the microchips packaged in ICs are classified into four general categories, namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0017] Deposition is any process of depositing, coating, or otherwise transferring a material onto a wafer. Available techniques include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition (「PECVD」), which is a process that utilizes the energy in a plasma to induce reactions on the wafer surface that would otherwise require higher temperatures typically associated with conventional CVD. The electrical and mechanical properties of the film can also be improved by performing high-energy ion bombardment during PECVD deposition.

[0018] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization ("CMP"). One example of a removal process is ion beam etching ("IBE"). Generally, IBE (or milling) refers to a dry plasma etching method that uses a remote broad-beam ion / plasma source to remove a substrate by physical inert gas means, chemical reactive gas means, or both. Like other dry plasma etching techniques, IBE offers advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching ("RIE"). Generally, RIE uses chemically reactive plasma to remove material deposited on a wafer. In RIE, the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma aggressively act on the wafer surface, reacting with it to remove the material.

[0019] Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, typically by diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or fast thermal annealing ("RTA"). Annealing activates the implanted dopants. To connect and insulate the transistor and its components, films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used. By selectively doping different areas of a semiconductor substrate, it becomes possible to change the conductivity of the substrate by applying a voltage. By creating the structures of these various components, millions of transistors can be constructed and wired together to form the complex circuit configurations of modern microelectronic devices.

[0020] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate and then transferring that pattern to the substrate. In semiconductor lithography, the pattern is formed using a photosensitive polymer called a photoresist. The lithography and etching pattern transfer processes are repeated multiple times to construct the complex structures that make up transistors and the numerous wires that connect millions of transistors in a circuit. Each pattern printed on the wafer is aligned with a pre-formed pattern, and conductors, insulators, and selectively doped areas are built over time to form the final device.

[0021] Turning to an overview of memory technologies more specifically relevant to the aspects of this disclosure, embedded DRAM ("eDRAM") is dynamic random-access memory ("DRAM") embedded on the same die or multi-chip module ("MCM") of an application-specific integrated circuit ("ASIC") or microprocessor. eDRAM is implemented using silicon-on-insulator ("SOI") technology, which refers to the use of a layered silicon-insulator-silicon substrate in semiconductor manufacturing as an alternative to conventional silicon substrates. eDRAM technology has achieved varying degrees of success, and demand for SOI technology as a server memory option has decreased in recent years.

[0022] Magnetoresistive Random-Access Memory (MRAM) devices using magnetic tunnel junctions (MTJs) are one of the alternatives to existing eDRAM technology. MRAM is a non-volatile memory, and this advantage is a driving force behind the acceleration of its development. Current MRAM MTJ structures are relatively slow, and the only way to achieve MTJ write speeds comparable to eDRAM (approximately 5 nanoseconds) is to use dual magnetic tunnel junctions ("DMTJs").

[0023] Phase-change memory (also known as PCM, PCME, PRAM, PCRAM, OUM (Ovonic Unified Memory), C-RAM, or CRAM (Chalcogenide RAM)) is a type of non-volatile random-access memory. PMC utilizes the inherent properties of chalcogenide glass. Phase-change materials such as chalcogenides can change phases between amorphous and crystalline states by applying a current at a level suitable for implementation in integrated circuits. The overall amorphous state is characterized by a higher resistivity than the overall crystalline state, which can be easily detected to indicate data.

[0024] Phase-change materials in PCM devices can switch between a first structural state in the active region of the cell, where the material is entirely amorphous solid, and a second structural state, where the material is entirely crystalline solid. The term "amorphous" is used to refer to a relatively less ordered structure, more disordered than a single crystal, with detectable properties such as higher electrical resistivity than the crystalline phase. The term "crystalline" is used to refer to a relatively more ordered structure, more ordered than the amorphous structure, with detectable properties such as lower electrical resistivity than the amorphous phase. Other material properties affected by the transition between amorphous and crystalline phases include atomic order, free electron density, and activation energy. Materials can switch to various solid phases or mixtures of two or more solid phases, providing a gray scale between a completely amorphous state and a completely crystalline state.

[0025] The transition from amorphous to crystalline states in PCM devices generally involves relatively low current operation, requiring only enough current to raise the phase transition material to a level between its phase transition temperature and melting temperature. The transition from crystalline to amorphous, called a "reset," generally involves relatively high current operation, including a short, high-current-density pulse to melt or break the crystalline structure. Subsequently, the phase transition material is rapidly cooled, quenching the phase transition process and allowing at least a portion of the phase transition structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to induce the phase transition of the material from crystalline to amorphous states. The required magnitude of the reset current can be reduced by decreasing the volume of the active region of the phase transition material element within the cell.

[0026] Embodiments provided herein offer methods and devices for utilizing a three-dimensional (3D) stackable bidirectional access device in combination with a PCM-based memory device.

[0027] Resistive random-access memory (RRAM) structures can be used as a type of non-volatile (NV) random-access memory (RAM) in computing resources. RRAM devices, with their simple metal-insulator-metal structure, exhibit promising characteristics in terms of scalability, low-power operation, and multi-level data storage capabilities, making them potentially suitable for next-generation memory applications. RRAM typically operates by controlling changes in the resistance of a dielectric solid material, sometimes referred to as a memristor. RRAM can be considered a promising technology as an electronic synapse device (or memristor) for neuromorphic computing, as well as for high-density and high-speed non-volatile memory applications. In neuromorphic computing applications, resistive memory devices can be used as connections (synapses) between pre-neurons and post-neurons, where the connection weights are expressed in the form of device resistance. Multiple pre-neurons and post-neurons can be connected via a crossbar array of RRAM, enabling fully connected neural networks. Oxygen vacancies in the metal oxide layer of an RRAM device are the building blocks of current-conducting filaments.

[0028] In neuromorphic computing applications, resistive memory devices (e.g., RRAM devices) can be used as connections (synapses) between preneurons and postneurons, where connection weights are represented in the form of device resistance. Multiple preneurons and postneurons can be connected via an RRAM crossbar array, which naturally represents a fully connected neural network. The RRAM crossbar array can be fabricated by bonding a resistive switching material formed on the bottom electrode. The top electrode is formed on the junction with the resistive switching material to form the RRAM crossbar array. x TaO x AlO x , ZrO x , TiO xNon-volatile resistive switching metal oxides, or combinations thereof, are incorporated into nano-crossbar arrays and nano-cross points scaled down to feature size by electron beam lithography. This enables a rapid fabrication route for high-density prototype test structures of passive memory cores with two terminal devices. To understand the general properties of nano-crossbar arrays using resistive switching metal oxides and to define the requirements for an external CMOS control system, the structure and the electrical characterization of the incorporated materials are performed.

[0029] To efficiently generate RRAM bit patterns, HfO x Non-volatile resistive switching materials having two or more stable states are integrated as a two-terminal memory device. These cells can be incorporated into a crossbar array, thereby reducing the cell size per bit to 4. The switching material can cover the entire area of ​​the chip, and all junctions at the intersections are addressable cells of the RRAM. Since the array consists of passive elements, additional active external circuitry is required for addressing the cells, setting and resetting their states, and reading the stored information.

[0030] Embodiments provided herein offer methods and devices for utilizing a three-dimensional (3D) stackable bidirectional access device in combination with an RRAM-based memory device.

[0031] In certain embodiments, the memory access device is configured as a metal semiconductor field effect transistor (MESFET). Generally, a MESFET is a field effect transistor semiconductor device similar to a junction gate field effect transistor (JFET) that has a Schottky (metal semiconductor) junction instead of a p-n junction at the gate. In this case, the MESFET has a metal contact formed directly on silicon (or polysilicon), which forms a Schottky barrier diode junction. In that case, the Schottky diode is used as a reverse bias diode in the same manner as in the case of a JFET. However, the Schottky diode can form a smaller diode than a JFET.

[0032] Referring now to the drawings in which like numerals represent like or similar elements and first to FIG. 1, an exemplary method of manufacturing a three-dimensional (3D) stackable bidirectional access device to which embodiments of the present invention may be applied is shown. As shown in FIG. 1, a plurality of back end of line ("BEOL") layers and front end of line (FEOL) layers (FEOL / BEOL layer 102) are formed.

[0033] Generally, the front end of line (FEOL) is the first part of IC manufacturing, where individual devices (transistors, capacitors, resistors, etc.) are patterned onto the semiconductor. The FEOL generally includes up to but not including the deposition of metal interconnect layers.

[0034] Generally, the BEOL is the second part of IC manufacturing, where individual devices (transistors, capacitors, resistors, etc.) are interconnected with the wiring on the wafer. The BEOL metal layer (not shown) can include, for example, Cu, TaN, Ta, Ti, TiN, or combinations thereof. The BEOL dielectric layer (not shown) can be formed laterally to one or more BEOL metal layers. The BEOL dielectric layer is, for example, SiO x 、SiN x 、SiBCN、low -kIt may consist of NBLOK, or any other suitable dielectric material. The structure including the FEOL / BEOL layer 102 shown in Figure 1 is an initiation structure on which a three-dimensional (3D) stackable bidirectional access device of an embodiment of the present invention is formed on the surface. It should be understood that with respect to the three-dimensional (3D) stackable bidirectional access device of an embodiment of the present invention, any suitable number or combination of FEOL / BEOL layers may be contemplated.

[0035] As shown in Figure 1, a first oxide layer 104 is provided on the FEOL / BEOL layer 102. The first oxide layer 104 may contain any material known in the art, such as porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. In certain examples, the material of the first oxide layer 104 is SiO2 or SiN. In certain examples, the material of the first oxide layer 104 is a material that can be formed at a temperature of 400°C or less so as not to impair any component of the BEOL layer. The first oxide layer 104 may be formed using any method known in the art, such as chemical vapor deposition, plasma-accelerated chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The first oxide layer 104 may have a thickness ranging from about 25 nm to about 200 nm. However, it should be understood that the first oxide layer 104 may be formed to any preferred thickness and may contain materials other than those listed above. Next, the first oxide layer 104 is patterned, and a bottom electrode 106 is formed in the first oxide layer 104. The bottom electrode 106 can function as the first terminal (or source) of the MESFET memory access device of the semiconductor device 100.

[0036] Referring now to Figure 2, this figure is a cross-sectional view of the semiconductor device 100 of Figure 1 after an additional manufacturing process according to one of several embodiments. As shown in Figure 2, a silicon layer 108 is blanket-deposited on the first oxide layer 104 and the bottom electrode 106. The thickness of the silicon layer 108 may be, for example, about 50 to 100 nm. However, it should be understood that a silicon layer 108 of any other suitable thickness may be used. The silicon layer 108 may be formed by any suitable material deposition technique, such as physical vapor deposition (PVD) or plasma-accelerated chemical vapor deposition (PECVD). In certain embodiments, the silicon layer 108 may be doped with, for example, arsenic (As), antimony (Sb), boron (B), phosphorus (P), or any suitable combination of these elements. It should be understood that other suitable dopants may also be used to form the silicon layer 108. It should also be understood that in other examples, the silicon layer 108 may not be doped.

[0037] Referring now to Figure 3, this figure is a cross-sectional view of the memory access device of Figure 2 after an additional manufacturing process, according to several embodiments. As shown in Figure 3 (i.e., indicated by the change in the cross-hatching pattern), the silicon layer 108 of Figure 2 undergoes a laser annealing process, resulting in the conversion of the relatively amorphous silicon layer 108 of Figure 2 into a polycrystalline silicon layer 108'. In certain embodiments, it may be desirable to perform the laser annealing process to achieve a larger grain size in the polycrystalline silicon layer 108'. In examples where a dopant is used in the silicon layer 108, the laser annealing process associated with Figure 3 also activates the dopant in the annealed polycrystalline silicon layer 108'.

[0038] Referring now to Figure 4, this figure is a cross-sectional view of the memory access device of Figure 3 after additional manufacturing steps according to one of several embodiments. As shown in Figure 4, the polycrystalline silicon layer 108' is patterned using a hard mask 110. In a particular example, the width of the patterned polycrystalline silicon layer 108' is wider than the width of the underlying bottom electrode 106 to prevent a short circuit between the second terminal (see, for example, the gate electrode 112 in Figure 5) and the bottom electrode 106. In this regard, a certain amount of oxide layer 104 is present to separate the bottom electrode from the gate electrode to minimize the possibility of a short circuit. It should be understood that the polycrystalline silicon layer 108' can be fabricated by any preferred combination of lithography, material deposition, and material removal processes known to those skilled in the art.

[0039] Referring now to Figure 5, this figure is a cross-sectional view of the semiconductor device 100 of Figure 4 after additional manufacturing steps according to one of several embodiments. As shown in Figure 5, the gate electrode 112 is conformally deposited covering the entire wafer surface. In this case, the gate electrode 112 is formed at least initially on the first oxide layer 104, on the sidewall of the polycrystalline silicon layer 108', and on the top surface of the hard mask 110. In certain examples, the hard mask 110 may be removed before the formation of the gate electrode 112. The conformal gate electrode 112 may be formed to a thickness of, for example, about 20 nm. However, it should be understood that gate electrode 112 of any other suitable thickness may be used. The gate electrode 112 may be formed of a metal (e.g., tungsten(W) or any other suitable conductive metal). The film of the gate electrode 112 is then patterned so that the gate electrode 112 is connected to a single row of the memory access device 100. The gate electrode 112 is the second terminal (or gate) of the 3-terminal MESFET memory access device 100.

[0040] Referring now to Figure 6, this figure is a cross-sectional view of the semiconductor device 100 of Figure 5 after an additional manufacturing step according to one of several embodiments. As shown in Figure 6, a second oxide layer 114 is formed over the pre-patterned gate electrode 112. The second oxide layer 114 may contain any material known in the art, such as porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. The second oxide layer 114 may be formed using any method known in the art, such as chemical vapor deposition, plasma-accelerated chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The second oxide layer 114 may have a thickness ranging from about 25 nm to about 200 nm, for example. However, it should be understood that in certain examples, the second oxide layer 114 may be formed to any preferred thickness (provided that at least the top surface of the second oxide layer 114 is at the same height as the top surface of the polycrystalline silicon layer 108') and may contain materials other than those listed above.

[0041] Next, referring to Figure 7, this figure is a cross-sectional view of the semiconductor device 100 of Figure 6 after an additional manufacturing process according to one of several embodiments. As shown in Figure 7, the semiconductor device 100 is subjected to a planarization technique (e.g., CMP) to flatten its upper surface and remove the upper part of the gate electrode 112 that is above the hard mask 110. This makes it possible to recess the side wall (or vertical portion) of the gate electrode 112 in subsequent processing operations.

[0042] Next, referring to Figure 8, this figure is a cross-sectional view of the semiconductor device 100 of Figure 7 after an additional manufacturing process according to one of several embodiments. As shown in Figure 8, a material removal process (e.g., etching) is performed on the semiconductor device 100 to recess the side wall (i.e., vertical portion) of the gate electrode 112 to a level lower than the upper surface of the polycrystalline silicon layer 108'. As a result, a recess 111 is formed in the region of the gate electrode 112 between the second oxide layer 114, the polycrystalline silicon layer 108', and the hard mask 110.

[0043] Next, referring to Figure 9, this figure is a cross-sectional view of the semiconductor device 100 of Figure 8 after an additional manufacturing step according to one of several embodiments. As shown in Figure 9, after the formation of the recess 111, a dielectric layer 116 is deposited to fill the recess 111. In certain examples, the dielectric layer 116 is formed to at least the height of the upper surface of the second oxide layer 114.

[0044] Next, referring to Figure 10, this figure is a cross-sectional view of the semiconductor device 100 of Figure 9 after an additional manufacturing process according to one of several embodiments. As shown in Figure 10, in certain embodiments, a material removal process (e.g., CMP) is performed to flatten the top surface of the semiconductor device 100 again and to remove the hard mask 110 to expose the top surface of the polycrystalline silicon layer 108'.

[0045] Referring now to Figure 11, this figure is a cross-sectional view of the semiconductor device 100 of Figure 10 after an additional manufacturing process according to one of several embodiments. As shown in Figure 11, the top electrode 118 is formed covering the dielectric layer and the polycrystalline silicon layer 108'. With respect to the three-terminal structure of this memory access structure of the semiconductor device 100, the first terminal may be the source (e.g., the bottom electrode 106), the second terminal may be the gate electrode 112, and the third terminal may be the drain (e.g., the top electrode 118). It should be understood that forming the dielectric layer 116 in the recess 111 functions as an insulating layer to prevent electrical short circuits between the gate electrode 112 and the top electrode 118. It should be understood that the material of the dielectric layer 116 may be the same as or different from the material of the second oxide layer 114. Thus, in a particular embodiment, a vertically oriented MESFET type memory access device 150 is formed, its overall boundary shown by a thick dashed line in Figure 11. Accordingly, the embodiments described herein realize a structure and method for incorporating crystallized Si MESFET devices (i.e., MESFET-type memory access devices 150) into BEOL. These MESFET-type memory access devices 150 enable bidirectional operation and can be manufactured using a process compatible with the BEOL process. This makes the MESFET-type memory access devices 150 3D stackable and usable in both PCM and RRAM memories. Furthermore, a third terminal of the device (e.g., gate electrode 112) provides better control of the current level, enabling the selection of multiple bits, which can significantly increase the bit density of the memory array.

[0046] Next, referring to Figure 12A, this figure is a cross-sectional view of the semiconductor device 100 of Figure 11 combined with a mushroom cell type memory device according to one of several embodiments. As shown in Figure 12A, a mushroom type memory stack 120A is formed on the top electrode 118 of the MESFET type memory access device 150. It should be understood that a mushroom type memory stack refers to the idea that the critical dimensions (CD) (e.g., width, length, or diameter) of the memory stack 120A are greater than the CD of the MESFET type memory access device 150. Also as shown in Figure 12A, a second top electrode 122A is formed on the memory stack 120A. In this case, the combination of the MESFET type memory access device 150 and the memory stack 120A can be 3D stackable (repeatedly formed vertically). In certain embodiments, the mushroom type memory stack 120A may be a PCM memory device or an RRAM memory device.

[0047] Next, referring to Figure 12B, this figure is a cross-sectional view of the semiconductor device 100 of Figure 11 combined with a pillar-cell memory (PCM) device or a resistive random-access memory device (RRAM) according to several embodiments. As shown in Figure 12B, a pillar-cell memory stack 120B is formed on the top electrode 118 of the MESFET memory access device 150. It should be understood that a pillar-cell memory stack refers to the idea that the critical dimensions (CD) (e.g., width, length, or diameter) of the memory stack 120B are smaller than the CD of the MESFET memory access device 150. Also as shown in Figure 12B, a second top electrode 122B is formed on the pillar-cell memory stack 120B. In this case, the combination of the MESFET memory access device 150 and the pillar-cell memory stack 120B can be 3D stackable (repeatedly formed vertically). In certain embodiments, the pillar-type memory stack 120B may be a PCM memory device or an RRAM memory device.

[0048] Next, referring to Figure 12C, this figure is a cross-sectional view of the semiconductor device 100 of Figure 11 combined with a confined PCM device according to one of several embodiments. As shown in Figure 12C, a confined PCM memory stack 120C is formed on the top electrode 118 of the MESFET type memory access device 150. It should be understood that a confined PCM type memory stack refers to the idea that the critical dimensions (CD) (e.g., width, length, or diameter) of the PCM type memory stack 120C are approximately equal to the CD of the MESFET type memory access device 150. Also as shown in Figure 12C, a second top electrode 122C is formed on the confined PCM memory stack 120C. In this case, the combination of the MESFET type memory access device 150 and the confined PCM memory stack 120C can be 3D stackable (repeatedly formed vertically). In certain embodiments, the confined PCM type memory stack 120C may be a PCM memory device.

[0049] The descriptions of various embodiments are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the embodiments disclosed. Many changes and modifications will be apparent to those skilled in the art without departing from the scope and concept of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or technical improvements to the technology available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device, To form a first oxide layer, Forming a first electrode in the first oxide layer, Forming a single layer of crystallized silicon on the first electrode, The second electrode is formed directly on the first oxide layer and on the sidewall of the crystallized silicon single layer, Forming a second oxide layer on the upper surface of the second electrode, A third electrode is formed on the upper surface of the crystallized silicon single layer, Methods that include...

2. The method according to claim 1, wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.

3. The method according to claim 1, wherein at least a portion of the second oxide layer is formed between the second electrode and the third electrode.

4. The method according to claim 1, wherein forming the crystallized silicon single layer includes laser annealing the crystallized silicon single layer.

5. The method according to claim 1, wherein the vertical metal-semiconductor field-effect transistor (MESFET) device is formed on the BEOL layer of the semiconductor device.

6. The method according to claim 1, wherein the width of the crystallized silicon single layer is wider than the width of the first electrode.

7. The method according to claim 1, wherein forming the crystalline silicon monolayer comprises doping with at least one material selected from the group consisting of arsenic (As), antimony (Sb), boron (B), and phosphorus (P).

8. The first oxide layer and A first electrode formed in the first oxide layer, A single layer of crystallized silicon formed on the first electrode, A second electrode formed directly on the first oxide layer and on the sidewall of the crystallized silicon single layer, The second oxide layer formed on the upper surface of the second electrode, A third electrode formed on the upper surface of the crystallized silicon single layer, A vertical MESFET device equipped with the following features.

9. The device according to claim 8, wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.

10. The device according to claim 8, wherein at least a portion of the second oxide layer is formed between the second electrode and the third electrode.

11. The vertical MESFET device is formed on the BEOL layer of a semiconductor device, as described in claim 8.

12. The device according to claim 8, wherein the width of the crystallized silicon single layer is wider than the width of the first electrode.

13. The device according to claim 8, wherein the crystalline silicon single layer is doped with at least one material selected from the group consisting of arsenic (As), antimony (Sb), boron (B), and phosphorus (P).

14. A bidirectional access device, First oxide layer, The first electrode formed in the first oxide layer, A single layer of crystallized silicon formed on the first electrode, A second electrode formed directly on the first oxide layer and on the sidewall of the crystallized silicon single layer, The second oxide layer formed on the upper surface of the second electrode, The third electrode formed on the upper surface of the crystallized silicon single layer The bidirectional access device includes, A memory device connected to the aforementioned bidirectional access device, A semiconductor device equipped with the following features.

15. The semiconductor device according to claim 14, wherein the bidirectional access device is a vertical MESFET device.

16. The semiconductor device according to claim 14, wherein the memory device is a phase-change memory (PCM) device.

17. The semiconductor device according to claim 14, wherein the memory device is a resistive random-access memory (RRAM) device.

18. The semiconductor device according to claim 14, further comprising a plurality of vertical MESFET devices and memory devices stacked three-dimensionally in the vertical direction of the semiconductor device.

19. The semiconductor device according to claim 14, wherein the width of the crystallized silicon single layer is wider than the width of the first electrode.

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