Complementary FET (CFET) embedded sidewall contact with spacer foot

Abstract

The CFET includes a fin having a bottom channel portion, a top channel portion, and a channel isolator between the bottom and top channel portions. The CFET further includes a source and drain stack having a bottom source or drain (S / D) region connected to the bottom channel portion, a top S / D region connected to the top channel portion, and a source-drain isolator between the bottom and top S / D regions. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S / D region, and a buried S / D contact physically connected to a top sidewall portion of the bottom S / D region. The CFET can further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

Description

Technical Field

[0001] Various embodiments of the present application generally relate to semiconductor device manufacturing methods and the resulting structures. More particularly, various embodiments relate to a complementary field effect transistor (CFET) including an embedded sidewall contact having a spacer foot at the bottom or foot of the source or drain (S / D) region of the bottom transistor of the CFET.

Summary of the Invention

[0002] In one embodiment of the present invention, a semiconductor device is presented. The device includes a fin having a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The device further includes a source and drain stack having a bottom source or drain (S / D) region connected to the bottom channel portion, a top S / D region connected to the top channel portion, and a source-drain isolator between the bottom S / D region and the top S / D region. The device further includes a spacer foot physically connected to the base sidewall portion of the bottom S / D region and an embedded S / D contact physically connected to the upper sidewall portion of the bottom S / D region.

[0003] In another embodiment, another semiconductor device is presented. This device includes a fin pair comprising a first fin and a second fin. The first fin has a first bottom channel portion, a first top channel portion, and a first channel isolator between the first bottom channel portion and the first top channel portion. The second fin has a second bottom channel portion, a second top channel portion, and a second channel isolator between the second bottom channel portion and the second top channel portion. This device includes a source and drain stack having a bottom source or drain (S / D) region connected to the first bottom channel portion and the second bottom channel portion, a top S / D region connected to the first top channel portion and the second top channel portion, and a source-drain isolator between the bottom S / D region and the top S / D region. The device further includes a spacer foot physically connected to the base sidewall portion of the first bottom S / D region and an embedded S / D contact physically connected to the upper sidewall portion of the first bottom S / D region.

[0004] In yet another embodiment of the present invention, a method for manufacturing a semiconductor device is presented. The method comprises forming a pair of spacers on a substrate. The method further comprises forming a fin trench between the pair of spacers. The fin trench exposes the sidewall of a bottom fin channel region, the sidewall of a top fin channel region, and the sidewall of a fin channel isolator between the bottom fin channel region and the top fin channel region. The method further comprises forming a bottom source or drain (S / D) region within the fin trench between the pair of spacers and on the exposed sidewall of the bottom channel region. The method further comprises forming a source-drain isolator within the fin trench between the pair of spacers and on the bottom S / D region. The method further comprises forming a top S / D region within the fin trench between the pair of spacers and on the source-drain isolator, and forming a spacer foot by partially recessing at least one spacer of the pair of spacers.

[0005] These and other embodiments, features, aspects, and advantages will be better understood by referring to the following description, the appended claims, and the appended drawings. [Brief explanation of the drawing]

[0006] [Figure 1] This is a perspective view of conventional semiconductor devices, including known CFETs. [Figure 2] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 3] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 4] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 5] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 6] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 7] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 8] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 9] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 10] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 11] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 12] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 13]This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 14] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 15] This is a cross-sectional view of a semiconductor device after each manufacturing operation according to one or more embodiments. [Figure 16] This is a flowchart illustrating a semiconductor device manufacturing method according to one or more embodiments. [Modes for carrying out the invention]

[0007] A detailed description of an exemplary CFET architecture is provided herein, having a top source or drain (S / D) region above a bottom S / D region (e.g., the S / D region of an NFET above the S / D region of a PFET, or vice versa), spacer feet on the sidewall of the bottom S / D region, and embedded sidewall contacts that physically connect the sidewall of the bottom S / D region to an embedded power rail. However, it should be understood that embodiments of the teachings described herein are not limited to the specific FET architecture described herein. Rather, embodiments of the present invention can be implemented in relation to any other suitable type of FET device that is currently known or will be developed later.

[0008] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments can be devised without departing from the scope of the present invention. Note that various connections and positional relationships (e.g., above, below, adjacent, etc.) are described between elements in the following description and drawings. These connections or positional relationships, or both, may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, the joining of entities may refer to either direct or indirect joining, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, the reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant properties and functionality of layers "A" and "B" are not substantially altered by the intermediate layers.

[0009] For the purposes of the following explanation, the terms “top,” “bottom,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives refer to the structures and methods described as oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, lies on a second element, such as a second structure, and that an intervening element, such as an interface structure, may exist between the first and second elements. Terms such as “direct contact” mean that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating, or semiconductor layer. Note that the term “selective to” means, for example, “a first element selective to a second element,” that the first element can be etched and the second element can act as an etch stop.

[0010] The terms “about,” “substantially,” “approximately,” and their variations are intended to include the degree of error associated with measurements of a particular quantity based on equipment available at the time of filing of this application. For example, substantial coplanarity between various materials may include appropriate manufacturing tolerances such as ±8%, ±5%, ±2%, and differences between coplanar materials.

[0011] For the sake of brevity, prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes that have additional steps or functions not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or are completely omitted without providing details of well known processes.

[0012] Generally, the various processes used to form microchips that are packaged into ICs are classified into four common categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available techniques include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process of removing material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP). Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, generally by diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing works to activate the implanted dopants. Transistors and their components are connected and isolated using films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.). By selectively doping different areas of a semiconductor substrate, the conductivity of the substrate can be changed by applying a voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate and then transferring that pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called photoresist. The lithography and etching-pattern transfer steps are repeated multiple times to build the complex structures that make up the transistors and the numerous wires that connect the millions of transistors in the circuit.Each pattern printed on the wafer is aligned with previously formed patterns, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0013] Turning now to a more detailed description of the technology more specifically related to aspects of the present invention, a transistor is a semiconductor device commonly found in a wide variety of integrated circuits. A transistor is essentially a switch. When a voltage greater than the threshold voltage is applied to the gate of the transistor, the switch turns on and current flows through the transistor. When the voltage of the gate is less than the threshold voltage, the switch turns off and current does not flow through the transistor.

[0014] Semiconductor devices can be formed in the active regions of a wafer. The active regions are defined by insulating regions used to separate and electrically insulate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain formed in the active region of a semiconductor layer by implanting n-type or p-type impurities into the semiconductor material layer. A channel (or body) region is disposed between the source and the drain. A gate is disposed above the body region. The gate and the body are separated by a gate dielectric layer. The channel connects the source and the drain, and current flows from the source to the drain through the channel. The flow of current is induced in the channel region by the voltage applied to the gate.

[0015] One or more embodiments of the present invention relate to a manufacturing method that can be formed with respect to a top S / D region over a bottom S / D region, spacer feet on sidewalls of the bottom S / D region, and an embedded contact that physically connects the bottom S / D region to an embedded power rail, and a resulting CFET structure. The spacer feet can prevent a short circuit between the embedded contact and the semiconductor substrate. By referring to the accompanying drawings, such a manufacturing method and the resulting semiconductor device structure according to embodiments of the present invention will be described in detail below.

[0016] FIG. 1 shows a perspective view of a prior art semiconductor device including a known CFET. A CFET is a type of gate-all-around semiconductor device. In a CFET, one transistor (nFET or pFET) is stacked over another transistor (pFET or nFET). For example, a CFET can stack one nFET over a pFET transistor or one pFET over an nFET transistor. By folding nFET and pFET in this way, the n-p separation bottleneck can be eliminated, the footprint of the cell active region can be reduced, and the overall efficiency of the device can be improved.

[0017] FIG. 2 shows a cross-sectional view of a semiconductor device 100 shown after manufacturing operations according to one or more embodiments. The semiconductor device 100 includes a top S / D region 144 over a bottom S / D region 140 (both shown, for example, in FIG. 6), spacer feet 132' on sidewalls of the bottom S / D region 140 (shown, for example, in FIG. 8), and an embedded sidewall contact 176 that physically connects the sidewalls of the bottom S / D region 140 to an embedded power rail 124 (shown, for example, in FIG. 14), and is depicted in FIGS. 2 to 15 at various manufacturing stages where they can be formed.

[0018] The cross-sectional views of the semiconductor device structure depicted in FIGS. 2 to 15 are defined by the cross-section depicted in FIG. 2 and are used throughout the remaining structural diagrams.

[0019] Following the associated manufacturing operations, the semiconductor device 100 may include a substrate 102, one or more channel fins 120 (hereinafter referred to as fins 120), one or more shallow trench isolation (STI) regions 122, one or more embedded power rails 124, and one or more sacrificial gates 110 having a gate mask 112 on top of it.

[0020] Non-limiting examples of materials suitable for substrate 102 include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon-germanium), SiGe:C (silicon-germanium-carbon), Si alloys, Ge alloys, Group III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), Group II-VI materials (e.g., CdSe (cadmium selenium), CdS (cadmium sulfide), CdTe (cadmium tellurium), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. Other non-limiting examples of semiconductor materials include Group III-V materials, such as indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combination thereof. Group III-V materials may include at least one "Group III element," such as aluminum (Al), boron (B), gallium (Ga), or indium (In), and at least one "Group V element," such as nitrogen (N), phosphorus (P), arsenide (As), or antimony (Sb). The substrate 102 may be a bulk semiconductor material. Alternatively, as shown, the substrate 102 may be a substrate on an insulator (e.g., silicon-on-insulator (SOI)), which may include a substrate 104, such as a Si substrate 104, an insulator 106, such as an SiO insulator on the substrate 104, and a semiconductor layer 108, such as a Si semiconductor layer 108 on the insulator 106.

[0021] Unwanted portions of the substrate 102 can be removed using known patterning, lithography, etching, and other techniques, while desired portions of the substrate can be retained to form the fins 120. The fins can be patterned using conventional patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

[0022] The STI region 122 or a portion thereof can be formed by depositing an STI material, such as a dielectric known in the art, on the substrate 102, on the fins 120, and between the fins 120. The STI region 122 may also be formed by depositing the STI material by, for example, PVD, CVD, ALD, and then performing chemical mechanical polishing (CMP). As known in the art, the STI region 122 can electrically isolate, at least partially, adjacent CFET components or features. The material of an exemplary STI region 122 may be a thin layer of conformal SiN and SiO2 overfill.

[0023] Using known techniques such as patterning, lithography, and etching, the embedded power rail trench can be defined within the STI area 122 or a portion thereof.

[0024] The embedded power rail 124 may be formed within the embedded power rail trench. The embedded power rail 124 may be formed by depositing a metal adhesive layer, such as a titanium nitride (TiN) adhesive layer, followed by depositing a conductive embedded power rail metal, such as cobalt (Co), tungsten (W), ruthenium (Ru), or copper (Cu), by PVD, CVD, ALD, plating, etc. The embedded power rail metal may then be planarized by CMP, recessing, or both. Subsequently, additional STI 122 material can be deposited on the embedded power rail 124, and the STI dielectric may be recessed as desired. In some embodiments, the top surface of the STI region 122 may be below the bottom surface of the insulator 106 within the fin 120 after recessing. In some embodiments, the surface of the exposed fin 120 above the insulator 106 (e.g., the semiconductor layer 108 portion of the exposed fin 120) defines the top channel of the top FET, and the surface of the exposed fin 120 below the insulator 106 (e.g., the substrate 104 portion of the exposed fin 120) defines the bottom channel of the bottom FET.

[0025] Sacrificial gates 110 may be formed on the STI region 122 and on and between the fins 120. Sacrificial gates 110 can be formed by depositing a sacrificial gate material, material, or layer of material by PVD, CVD, ALD, etc. An exemplary sacrificial gate 110 material may be a thin silicon oxide layer followed by amorphous Si or polySi.

[0026] In some embodiments, the sacrificial gate 110 material layer can be formed on the STI region 122 and on and between the fins 120. Subsequently, the gate mask 112 layer can be formed on the sacrificial gate 110 material layer. The gate mask 112 layer may be a hard mask layer. Exemplary mask 112 layer materials may be silicon nitride (SiN), a combination of SiN and silicon dioxide (SiO2), etc.

[0027] By utilizing known techniques such as patterning, lithography, and etching, unwanted portions of the gate mask 112 can be removed, and then the sacrificial gate 110 material layer not covered by the gate hard mask can be further removed, while desired portions of the sacrificial gate 110 material layer and associated desired portions of the gate mask 112 layer can be retained. These retained features can each form a sacrificial gate 110 having the gate mask 112 on top of it. The structure combining the sacrificial gate 110 and the associated gate mask 112 may be referred to herein as a sacrificial gate structure.

[0028] Figure 3 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, the sacrificial plug 130 may be formed to pinch off or otherwise fill the area between the fins 120 that is not covered by the sacrificial gate 110.

[0029] The sacrificial plug 130 can be formed by depositing conformal material by ALD or the like. An example of the material for the sacrificial plug 130 is titanium oxide (TiO2). x ), aluminum oxide (AlO x ), SiC, etc. may also be used, but are not limited to these.

[0030] Sacrificial plugs 130 can be formed between fins 120 on the top surface of the STI region 122. The top surface of the sacrificial plug 130 may be substantially coplanar with the top surface of the associated or physically connected fin 120. Such coplanarity can be achieved by first depositing the sacrificial plug 130 material (e.g., ALD) to completely fill the narrow space between the fins 120, and then isotropically etching back the sacrificial plug material 130 to remove any excess sacrificial plug material other than the sacrificial plug material in the cavity above the STI region 122 between the opposing side walls of adjacent fins 120.

[0031] Figure 4 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, spacers 132 may be formed on the side walls of the fins 120 and on the side walls of the sacrificial gate structure.

[0032] The spacer 132 can be formed by depositing a conformal dielectric material by CVD, ALD, or the like. The material of the exemplary spacer 132 may be, but is not limited to, SiN, SiBCN, SiOCN, or SiOC.

[0033] The spacer 132 may be formed by depositing layers of spacer 132 material on the STI region 122, on and around the fin 120, on the sacrificial plug 130, and on and around the sacrificial gate structure.

[0034] The spacer 132 layer can have a thickness of approximately 5 nm to approximately 15 nm, but other thicknesses are also within the intended range. The spacer 132 layer can be made of a low k material with a dielectric constant such as less than approximately 7 or less than approximately 5. After the deposition of the spacer 132, the horizontal portion of the spacer 132 layer may be removed, for example, by an anisotropic etching process, while the desired portion of the spacer 132 layer may be retained to form the spacer 132. Thus, the formed spacer 132 can be effectively formed on the vertical sidewalls of the sacrificial gate structure and on the vertical sidewalls of the fin 120.

[0035] Figure 5 shows a cross-sectional view of the semiconductor structure 100 after a manufacturing operation according to one or more embodiments. In this manufacturing operation, a fin trench 134 can be formed by partially recessing the fins 120 and removing the sacrificial plugs 130 between the spacers 132. The fin trench 134 may be a cavity or recess formed within the fins 120.

[0036] Unwanted portions of the fins 120 and sacrificial plugs 130 can be removed by known patterning, lithography, and etching techniques. In some embodiments, the unwanted portions of the fins 120 and sacrificial plugs 130 may be removed between opposing spacers 132 of adjacent sacrificial gate structures in the X section, as shown, and between spacers 132 in the Y section. The bottom surface of the fin trench 134 may be coplanar with the top surface of the STI region 122. Since the fins 120 can be recessed by the fin trench 134, the top surface of the fins 120 may also be coplanar with the top surface of the STI region 122.

[0037] The fin trenches 134 can expose the opposing vertical sidewalls of the spacers 132, form the bottom well surface and their opposing vertical sidewalls of the substrate 104, form the opposing vertical sidewalls of the insulator 106, and form the opposing vertical sidewalls of the semiconductor layer 108. Each of these vertical sidewalls may be coplanar with the outer sidewall of the spacer 132 associated with the sacrificial gate structure above it.

[0038] Figure 6 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, the bottom S / D region 140 and the top S / D region 144 may be formed within the fin trench 134.

[0039] The bottom S / D region 140 is formed epitaxially on the exposed semiconductor surface (e.g., substrate 104 and semiconductor layer 108), and then the S / D epitaxy material is recessed to remove the S / D epitaxy material that has grown on the semiconductor layer 108 of the fin 120. Subsequently, an S / D isolator 142 is deposited on the bottom S / D region 140, and then the S / D isolator 142 material is recessed to expose the sidewall of the semiconductor layer 108. Subsequently, the top S / D region 144 can be formed on the exposed fin surface 108.

[0040] In some embodiments, the top surface of the bottom S / D region 140 is above the top surface of the substrate 104, substantially coplanar with the top surface of the substrate 104, or coplanar with the top surface of the substrate 104. Similarly, the bottom surface of the top S / D region 144 is below the bottom surface of the semiconductor layer 108, substantially coplanar with the bottom surface of the semiconductor layer 108, or coplanar with the bottom surface of the semiconductor layer 108. Therefore, the top and bottom surfaces of the S / D isolator 142 may be located between the top and bottom surfaces of the insulator 106.

[0041] In other embodiments, the top surface of the bottom S / D region 140 is below the top surface of the substrate 104. Similarly, the bottom surface of the top S / D region 144 is above the bottom surface of the semiconductor layer 108. Therefore, the top and bottom surfaces of the insulator 106 may be located between the top and bottom surfaces of the isolator 142.

[0042] In some embodiments, the bottom S / D region 140 and the top S / D region 144 may be formed within the fin trench 134 by epitaxially growing S / D material from one or more exposed semiconductor surfaces (e.g., substrate 104 and semiconductor layer 108). The material of the exemplary S / D regions 140 / 144 may be, but is not limited to, Si, Ge, SiGe, SiC, etc.

[0043] Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using gas-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. Epitaxial Si, SiGe, or SiC, or a combination thereof, can be doped during deposition (in-situ doped) by adding dopants, i.e., n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the dopants contained within the pFET or nFET.

[0044] The terms "epitaxial growth or deposition or both" and "epitaxially formed or grown or both" refer to the growth of one semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and system parameters are set so that the deposited atoms reach the deposition surface of the semiconductor substrate with enough energy to move around on the surface so that the deposited atoms are oriented in accordance with the crystalline arrangement of atoms on the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material was formed. For example, an epitaxially grown semiconductor material deposited on a {100}-oriented crystalline surface will have a {100} orientation. In some embodiments of the present invention, the epitaxial growth or deposition process, or both, is selective for formation on semiconductor surfaces, and generally, material is not deposited on exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0045] In some embodiments of the present invention, the gas source for depositing epitaxial semiconductor materials may include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of german, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. An epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0046] The S / D isolator 142 may be formed within the fin trench 134 on the bottom S / D region 140 between the spacers 132 and between the insulators 106. The S / D isolator 142 may be formed by depositing dielectric material, material, or a layer of material by PVD, CVD, ALD, etc. Exemplary materials for the S / D isolator 142 may be SiO2, a combination of a thin SiN liner and SiO2, etc. In some embodiments, the material for the S / D isolator 142 is selected so that the material electrically insulates the bottom S / D region 140 from the top S / D region 144, or provides sufficient electrical insulation.

[0047] In some embodiments, as illustrated, the material layer of the S / D isolator 142 may be formed in the fin trenches 134 on the bottom S / D region 140 between the spacers 132 and between the insulators 106, or on the STI region 122 and on the sidewalls of the spacers 132. The thickness of the material layer of the S / D isolator 142 can be selected such that the material layer of the S / D isolator 142 has a top surface that is coplanar, substantially coplanar, or below the bottom surface of the semiconductor layer 108.

[0048] Figure 7 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, the S / D isolator 142 can be formed by removing the material layer of the S / D isolator 142 outside the fin trench 134, while retaining the material layer of the S / D isolator 142 inside the fin trench 134.

[0049] By utilizing known techniques such as patterning, lithography, and etching, unwanted portions of the material layer of the S / D isolator 142 can be removed, while desired portions of the material layer of the S / D isolator 142 can be retained. These retained features can form an S / D isolator 142 that lies between the bottom S / D region 140 and the top S / D region 144, at least partially electrically insulating them. The fabricated stack of the bottom S / D region 140, the S / D isolator 142, and the top S / D region 144 may be referred to herein as an S / D region stack.

[0050] Figure 8 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, the spacers 132 around the sacrificial gate structure may be protected, while the spacers 132 associated with the S / D region stack may be partially recessed.

[0051] The spacers 132 around the sacrificial gate structure can be protected by partially recessing the spacers 132 around the sacrificial gate structure and forming a spacer cap 150 over them around the sacrificial gate structure. In such a process, sacrificial material such as OPL may be formed following the OPL recess, so that the spacers 132 on the side walls of the S / D region 140 and S / D region 144 are protected by the OPL, while the tops of the spacers 132 on the side walls of the sacrificial gate structure are exposed and can be removed.

[0052] After that, TiO x AlO x A spacer cap 150 can be formed by depositing a conformal liner such as SiO2, SiCO, or SiC onto the spacers 132 around the sacrificial gate structure, and then anisotropic etching can be performed to remove the spacer cap 150 from the horizontal plane. Next, the sacrificial OPL can be removed by, for example, N2 / H2 ashing. The spacer cap 150 can prevent the spacers 132 around the sacrificial gate structure from being further recessed or removed. By thus locally stopping the removal of the spacers 132 around the sacrificial gate structure, these spacers 132 can be retained in the desired location, while the spacers 132 on the sidewalls of the S / D region stack can be further recessed. The spacers 132 on the sidewalls of the S / D region stack may be further recessed by an anisotropic etching process. Some of the spacers 132 on the STI region 122 and on the sidewalls of the S / D region stack (e.g., on the sidewalls of the bottom S / D region 140) can be retained to form spacer feet 132'.

[0053] Figure 9 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process according to one or more embodiments. In this manufacturing process, a sacrificial interlayer dielectric (ILD) 158 may be formed, the sacrificial gate structure may be removed, or a replacement gate structure may be formed instead.

[0054] Sacrificial ILD158 may be formed by depositing dielectric material by PVD, CVD, ALD, etc. Exemplary ILD158 materials may be, but are not limited to, SiO2, a thin liner of SiN followed by SiO2, amorphous Si, etc.

[0055] ILD158 may be formed in cracks, trenches, etc., within the semiconductor structure 100. For example, ILD158 may be formed in trenches between spacers 132 of adjacent sacrificial gate structures, in fin trenches 134 around S / D region stacks, and on spacer feet 132'. Subsequently, the top surface of the semiconductor structure 100 may be planarized by, for example, CMP. For example, the top surfaces of ILD158, spacers 132, sacrificial gate structures, etc., may lie on the same plane.

[0056] Sacrificial gate structures (e.g., mask 112 and sacrificial gate 110) can be removed by known techniques such as patterning, lithography, and etching to form replacement gate trenches. These replacement gate trenches can expose at least a portion of the sidewalls or sides of the fin 120. For example, the replacement gate trenches can expose at least a portion of the semiconductor layer 108 of the fin 120, the isolator 106, and the sidewalls or sides of the substrate 104.

[0057] The replacement gate structure may be formed by depositing a gate dielectric liner, depositing a work function metal 160, recessing the work function metal 160 (if necessary), and subsequently forming a gate cap 162 material in the replacement gate trench by PVD, CVD, ALD, etc. Exemplary gate dielectric materials include SiO2, HfO2, ZrO2, HfZrO2, and HfAlO2. x , HfSiO xThe exemplary work function metal 160 material may be, but is not limited to, TiN, TiC, TiAlC, TaN, etc. After the deposition of the work function metal 160, a low-resistance conductive gate metal such as W or Al can be further deposited. The exemplary gate cap 162 material may be, but is not limited to, nitrides, SiBCN, SiOCN, SiOC, etc.

[0058] The replacement gate structure may be formed around the fin 120 such that the replacement gate structure is formed around or on the exposed portion of the sidewall or side of the fin 120 (for example, formed on the semiconductor layer 108, isolator 106, and substrate 104). Thus, the replacement gate structure can function as a common gate for two vertically stacked FETs. For example, the replacement gate structure may be a common gate for a top FET including a top S / D region 144 and a fin 120 channel region 109 between them, and for a bottom FET including a bottom S / D region 140 and a fin 120 channel region 105 between them.

[0059] Figure 10 shows a cross-sectional view of a semiconductor structure 100 after a manufacturing operation, according to one or more embodiments. In this manufacturing operation, the sacrificial ILD 158 can be removed. Known techniques such as patterning, lithography, and etching can be used to remove the sacrificial ILD 158, thereby exposing the semiconductor structure 100 beneath it. For example, the sacrificial ILD 158 can be removed between adjacent replacement gate structures and on the top S / D region 144 to expose the spacers 132 of adjacent replacement gate structures, the top S / D region 144, and the bottom S / D region 140. Similarly, the sacrificial ILD 158 can be removed on the STI region 122, on the spacer feet 132', and around the S / D region stack to expose the STI region 122, the spacer feet 132', and so on.

[0060] Figure 11 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, the S / D region stack can be cleaned and appropriate S / D region 140, 144 treatments can be injected. For example, after exposing the bottom S / D region 140 and top S / D region 144 (including their sidewalls), pre-amorphizing injections may be performed on such regions. For example, if appropriate, Si, Ge, or Xe injections can be performed on the bottom S / D region 140 and top S / D region 144 to amorphousize their surfaces. Surface amorphization can reduce the electrical resistance between each of these regions and the associated S / D contacts, such as the S / D contact 176 or contact 182 as depicted in Figure 15.

[0061] Figure 12 shows a cross-sectional view of a semiconductor structure 100 after a manufacturing operation according to one or more embodiments. In this manufacturing operation, an ILD172 can be formed. The ILD172 may be formed by depositing dielectric material by PVD, CVD, ALD, etc. The material of the exemplary ILD172 may be, but is not limited to, SiO2, a thin liner with SiN followed by SiO2, etc.

[0062] ILD172 may be formed in cracks, trenches, etc., within the semiconductor structure 100. For example, ILD172 may be formed in trenches between spacers 132 of adjacent replacement gate structures, around S / D region stacks, or on spacer feet 132'. Subsequently, the top surface of the semiconductor structure 100 may be planarized by, for example, CMP. For example, the top surfaces of ILD172, spacers 132, and replacement gate structures (e.g., the top surface of gate cap 162) may lie on the same plane.

[0063] Figure 13 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, a metallization contact trench 174 can be formed within the ILD 172.

[0064] By known patterning, lithography, and etching techniques, unwanted portions of the ILD 172 can be removed, thereby forming a metallization contact trench 174, exposing at least a portion of the sidewall or lateral surface of the bottom S / D region 140 and at least a portion of the embedded power rail 124. The metallization contact trench 174 can further expose portions of the STI region 122 above the exposed embedded power rail 124, further expose portions of the spacer feet 132', further expose at least a portion of the sidewall or lateral surface of the S / D isolator 142, further expose at least a portion of the sidewall or lateral surface of the top S / D region 144, further expose at least a portion of the top surface of the top S / D region 144, and further expose at least a portion of the respective sidewalls or lateral surfaces of the opposing spacers 132 of adjacent replacement gate structures. In some embodiments, as shown in the illustration, a portion of the embedded power rail 124 may be partially recessed by a metallization contact trench 174.

[0065] Figure 14 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process, according to one or more embodiments. In this manufacturing process, bottom contact metallization (BCM) 176 can be formed within the metallization contact trench 174.

[0066] The BCM176 may be formed within the metallization contact trench 174, on at least a portion of the embedded power rail 124, and on at least a portion of the side or side wall of the bottom S / D area 140. The BCM176 may also be formed within the metallization contact trench 174 around the spacer foot 132'.

[0067] BCM176 may be formed by depositing a silicide liner, followed by an adhesive layer, and then a conductive metal. Exemplary silicide liner materials include Ti, Ni, NiPt, etc. Exemplary adhesive layer materials may include, but are not limited to, TiN, TaN, etc. Exemplary conductive metals may include, but are not limited to, Co, W, Cu, Ru, etc. After the deposition of the conductive metal, a metal recess may be applied to remove or flatten the top surface of the formed BCM176.

[0068] In some embodiments, as shown, the top surface of the BCM176 may be between the top and bottom surfaces of the S / D isolator 142. In other embodiments, the top surface of the BCM176 may be below the top surface of the S / D isolator 142, and the top surface of the BCM176 may be below the bottom surface of the S / D isolator 142, and so on. In some embodiments, the distance between the top surface of the BCM176 and the top surface of the S / D isolator 142 may be selected to adequately electrically isolate the BCM176 from the top S / D region 144 by the selected dielectric material used to fill the metallization contact trench 174, as shown in Figure 15.

[0069] In certain embodiments, the BCM176 is formed to self-align with the spacer foot 132'. For example, when the metallization contact trench 174 is formed, the ILD172 and STI122 may be selectively removed relative to the spacer foot 132' so that the bottom of the metallization contact trench 174 is separated from the fin 120 located below the bottom S / D region 140. This retained spacer foot 132' and the STI region 122 between the metallization contact trench 174 and these fins 120 can prevent an electrical short circuit between the formed BCM176 and the fins 120.

[0070] Figure 15 shows a cross-sectional view of the semiconductor structure 100 after the manufacturing process according to one or more embodiments. In this manufacturing process, the ILD 172' can be formed on the BCM 176 to fill the metallization contact trench 174, and the apex contact metallization (TCM) 182 is formed on the apex S / D region 144 within the apex contact metallization trench 180.

[0071] ILD172' may be formed on BCM176 to fill the metallization contact trench 174 by depositing dielectric material by PVD, CVD, ALD, etc. The material of exemplary ILD172' may be, but is not limited to, SiO2, a thin liner of SiN followed by SiO2, etc. In some embodiments, ILD172' may be the same as or different from ILD172. ILD172' may be formed in cracks, trenches, etc., within the semiconductor structure 100. For example, ILD172' may be formed on BCM176 within the metallization contact trench 174, or around the remaining exposed S / D region stack, etc.

[0072] After forming ILD172' on the BCM176 within the metallization contact trench 174, a metallization contact trench 180 can be formed within ILD172, ILD172', or both, to expose at least a portion of the top S / D region 144. For example, the metallization contact trench 180 can be formed by removing unwanted portions of ILD172, ILD172', or both, using known patterning, lithography, and etching techniques. The metallization contact trench 180 can expose at least a portion of the top surface of the top S / D region 144. The metallization contact trench 180 can further expose at least a portion of the respective sidewalls or sides of the opposing spacers 132 of the adjacent replacement gate structure.

[0073] The TCM182 can be formed within the metallization contact trench 180, on at least a portion of the apex S / D region 144, and on the respective sidewalls or sides of the opposing spacers 132 of the adjacent replacement gate structure. The TCM182 can be formed by depositing a silicide liner, followed by depositing an adhesive layer, and then depositing a conductive metal.

[0074] Subsequently, the top surface of the semiconductor structure 100 may be planarized by, for example, CMP. For example, the top surfaces of ILD 172, 172', spacer 132, replacement gate structure (e.g., the top surface of gate cap 162), TCM 182, etc., may lie on the same plane.

[0075] As illustrated, the semiconductor structure 100 may be formed to include a CFET that includes a bottom S / D region 140 separated from the top S / D region 144 by an S / D isolator 142. The CFET may further include a common substitution gate structure that can be physically connected to the channel region 109 of one or more fins 120 and to the channel region 105 of one or more fins 120. The channel regions 109 and 105 may also be physically connected to the bottom S / D region 140 and the top S / D region 144. A portion of the isolator 106 between the channel regions 109 and 105 may be called a channel isolator. The common substitution gate structure may be electrically connected to a BEOL gate contact as is known in the art. Each top S / D region 144 may be further connected to a TCM 182, and each bottom S / D region 140 may be further connected to a BCM 176. The TCM182 may be electrically connected to the BEOL gate contact as is known in the art. The CFET may further include spacer feet 132' at the bottom of the bottom S / D region 140. The spacer feet 132' can physically and at least partially electrically isolate the BCM176 from the rest of the fins 120 or substrate 104 or both, which are located entirely below the bottom S / D region 140.

[0076] Figure 16 is a flowchart showing a method 200 for manufacturing a semiconductor device 100 according to one or more embodiments. The method 200 begins with block 202, and subsequently, one or more multi-channel fins 120 can be formed on a substrate (block 204). For example, a first fin 120 and a second fin 120 (i.e., a fin pair) may be formed on or within the substrate 102. The multi-channel fin may include lower channel portions 105, each separated from the upper channel portion 109 by an isolator 106.

[0077] Method 200 can subsequently form an embedded power rail 124 within the STI region (block 206). For example, an STI region 122 material can be formed, the STI region 122 material can be flattened and stopped on the top surface of the fin 120 mask 112, an embedded power rail trench can be formed within the STI region 122 material, an embedded power rail 124 can be formed within the embedded power rail trench, the embedded power rail 124 can be flattened or recessed or both, further STI region 122 material can be formed, the additional STI region 122 material can be flattened and stopped on the top surface of the fin 120 mask 112, the STI region 122 material can be recessed, and any masks that may be on the fins can be removed, and so on.

[0078] Method 200 can subsequently form a sacrificial gate structure on the STI region around the dual channel fin (block 208). The sacrificial gate structure may be formed by depositing a sacrificial gate 110 material layer on the STI region 122, as well as on and between the fins 120. A gate mask 112 layer can then be formed on the sacrificial gate 110 material layer. Unwanted portions of the sacrificial gate 110 material layer and the associated gate mask 112 layer may be removed, while desired portions of the sacrificial gate 110 material layer and the associated gate mask 112 layer may be retained. These retained features can each form a sacrificial gate structure that includes a sacrificial gate 110 having a gate mask 112 on top.

[0079] Method 200 can subsequently form sacrificial plugs 130 between the fins 120 on the STI region 122, adjacent to the fins 120, or both (block 210). The sacrificial plugs 130 can fill the region between the fins 120 by pinching off or other means. Method 200 can subsequently form spacers 132 on the exposed sidewalls of the fins 120 and on the sidewalls of the sacrificial gate structure (block 212). For example, if two fins 120 are formed, the spacers 132 may be formed on the sidewall facing outward of the first fin 120 and on the sidewall facing outward of the second fin 120. Similarly, the spacers 132 may be formed on the coplanar sidewalls of the sacrificial gate 110 and the gate mask 112, respectively. For example, if one fin 120 is formed, the spacers 132 may be formed on the side wall of the fin 120 facing outward from the first sacrificial plug 130, and on the side wall of the fin facing outward from the second sacrificial plug 130.

[0080] Method 200 can subsequently form a fin trench 134 by recessing the fin 120 and the sacrificial plug 130 between the spacers 132 (block 214). The fin trench 134 may also be a cavity or recess formed within the first fin 120 and the second fin 120. Unwanted portions of the fin 120 and sacrificial plug 130 may be removed between the opposing spacers 132 of adjacent sacrificial gate structures in the X section, and between the spacers 132 in the Y section. The fin trench 134 can expose the respective opposing vertical sidewalls of the spacers 132, form the bottom well surface and its respective opposing vertical sidewalls of the substrate 104, form the respective opposing vertical sidewalls of the insulator 106, and form the respective opposing vertical sidewalls of the semiconductor layer 108. Each of these vertical sidewalls may be coplanar with the outer sidewall of the spacer 132 associated with the sacrificial gate structure above it.

[0081] Method 200 can subsequently form S / D regions 140 between spacers 132 on the STI region 122 (block 216). For example, in cross-section X, the bottom S / D region 140 may be formed on the exposed fin trench 134 surface of the substrate 104 of each first fin 120 and second fin 120, or partially on the exposed fin trench 134 surface of the insulator 106 of each first fin 120 and second fin 120. In cross-section Y, the bottom S / D region 140 may be formed on the exposed fin trench 134 surface of the inner opposing surfaces of the spacers 132, or on the partially recessed first fin 120 and second fin 120, as well as on the STI region 122 between the first fin 120 and the second fin 120.

[0082] Method 200 can subsequently form an S / D isolator 142 on the bottom S / D region 140 (block 218). The S / D isolator 142 may be formed on the bottom S / D region 140. The S / D isolator 142 may be formed on the exposed fin trench 134 surface of the insulator 106. In some embodiments, the S / D isolator 142 material layer may be formed in the fin trench 134 on the bottom S / D region 140 between spacers 132 and between insulators 106, on the STI region 122 and on the sidewalls of spacers 132.

[0083] Method 200 can subsequently form a top S / D region 144 on the S / D isolator between the spacers 132 (block 220). For example, in the X section, the top S / D region 144 may be formed on the exposed fin trench 134 surface of the semiconductor layer 108 of the first fin 120 and the second fin 120, or partially on the exposed fin trench 134 surface of the insulator 106 of the first fin 120 and the second fin 120. In the Y section, the top S / D region 144 may be formed on the exposed fin trench 134 surface of the inner opposing surfaces of the spacers 132.

[0084] Method 200 may subsequently partially remove the spacer 132 to form spacer feet 132' on the STI region 122 and on the lower or bottom sidewall of the bottom S / D region 140 (block 222). The spacer feet 132' may be formed by partially recessing the spacer 132 that is positioned on or associated with the sidewall of the S / D region stack while protecting the spacer 132 positioned around the sacrificial gate structure. The portion of the spacer 132 that is on the STI region 122 and on the sidewall of the S / D region stack (e.g., on the sidewall of the bottom S / D region 140) may be retained to form the spacer feet 132'.

[0085] Method 200 can then remove the sacrificial gate structure and form a replacement gate structure in its place (block 224). The sacrificial gate structure may be removed by known techniques such as patterning, lithography, or etching to form a replacement gate trench. The replacement gate trench can expose at least a portion of the sidewall or side of the fin 120. For example, the replacement gate trench can expose at least a portion of the semiconductor layer 108 of the fin 120, the isolator 106, and the sidewall or side of the substrate 104.

[0086] The replacement gate structure may be formed by depositing a gate dielectric liner, a work function metal 160, and a gate cap 162 material within a replacement gate trench. The replacement gate structure may be formed around the first fin 120 and the second fin 120 such that the replacement gate structure is formed around or on the exposed portion of the sidewall or side of the fin 120 (formed, for example, on the semiconductor layer 108, the isolator 106, and the substrate 104). Thus, the replacement gate structure can function as a common gate for two vertically stacked FETs. For example, the replacement gate structure may be a common gate for a top FET including a top S / D region 144 and a first fin 120 and second fin 120 channel region 109 between them, and for a bottom FET including a bottom S / D region 140 and a first fin 120 and second fin 120 channel region 105 between them.

[0087] Method 200 can subsequently perform processing on the S / D region 140 or the S / D region 144 or both (block 226). For example, where appropriate, Si, Ge, or Xe implantation can be applied to the bottom S / D region 140 and the top S / D region 144 to amorphousize their surfaces. Amorphization of the surfaces can reduce the electrical resistance between each of these regions and the associated S / D contacts.

[0088] Method 200 can subsequently form ILD 172 on the STI region, on the spacer foot 132', on the lower S / D region 140, on the S / D isolator 142, and on the S / D region 144 (block 228).

[0089] Method 200 can subsequently form a metallization contact trench 174 within the ILD 172 (block 230). The metallization contact trench 174 can expose at least a portion of the foot side wall or lateral surface or the bottom region of the bottom S / D region 140 and at least a portion of the embedded power rail 124. The metallization contact trench 174 can further expose a portion of the STI region 122 above the exposed embedded power rail 124, further expose a portion of the spacer foot 132', further expose at least a portion of the side wall or lateral surface of the S / D isolator 142, further expose at least a portion of the side wall or lateral surface of the top S / D region 144, further expose at least a portion of the top surface of the top S / D region 144 and further expose at least a portion of the respective side walls or lateral surfaces of the opposing spacers 132 of the adjacent replacement gate structure.

[0090] Method 200 can subsequently form a BCM 176 within the metallization contact trench 174 (block 232). The BCM 176 can be formed within the metallization contact trench 174 on at least a portion of the embedded power rail 124 and on at least a portion of the side or side wall of the bottom S / D area 140. The BCM 176 may be further formed within the metallization contact trench 174 around the spacer foot 132'. In some embodiments, the BCM 176 is formed to self-align with the spacer foot 132'.

[0091] Method 200 can subsequently form a metallization contact trench 180 inside ILD172 or ILD172' or both to expose at least a portion of the top S / D region 144 (block 234). For example, the metallization contact trench 180 can be formed by removing unwanted portions of ILD172 or ILD172' or both by known patterning, lithography, and etching techniques. The metallization contact trench 180 can expose at least a portion of the top surface of the top S / D region 144. The metallization contact trench 180 can further expose at least a portion of the respective sidewalls or sides of the opposing spacers 132 of the adjacent replacement gate structure.

[0092] Method 200 can subsequently form a TCM 182 on the top S / D region 144 (block 236). The TCM 182 can be formed within the metallization contact trench 180 on at least a portion of the top S / D region 144 and on the respective sidewalls or sides of the opposing spacers 132 of the adjacent replacement gate structure. The top surface of the semiconductor structure 100 may then be planarized, for example by CMP. For example, the top surfaces of ILD 172, 172', spacers 132, replacement gate structure (e.g., the top surface of the gate cap 162), and TCM 182 may be coplanar. Method 200 can terminate in block 238.

[0093] The method flowcharts shown herein are illustrative. Many variations of the drawings or operations described herein are possible without departing from the scope of the embodiments. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. All of these variations are considered part of the applicable claimed embodiments.

[0094] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the embodiments described. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications, or technical improvements to the art found in the market, or to enable those else skilled in the art to understand the embodiments described herein.

Claims

1. A fin comprising a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion, A source and drain stack comprising a bottom source or drain (S / D) region connected to the bottom channel portion, a top S / D region connected to the top channel portion, and a source-drain isolator in contact with the bottom S / D region between the bottom S / D region and the top S / D region, The spacer consists of a spacer layer on the side wall of the bottom S / D region, and the spacer foot is physically connected to the base side wall portion of the bottom S / D region. The embedded S / D contact is physically connected to the upper side wall portion of the bottom S / D region. Equipped with, The aforementioned embedded S / D contact is further physically connected to the embedded power rail. Semiconductor devices.

2. The semiconductor device according to claim 1, further comprising a top S / D contact physically connected to the upper surface of the top S / D region.

3. The semiconductor device according to claim 1, wherein the top surface of the embedded S / D contact is located between the top surface of the source-drain isolator and the bottom surface of the source-drain isolator.

4. The semiconductor device according to claim 1, further comprising a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

5. The semiconductor device according to claim 1, wherein the embedded S / D contact is further physically connected to the top surface of the spacer foot and to the side wall of the spacer foot.

6. The semiconductor device according to claim 1, wherein the top surface of the bottom S / D region is completely covered by the source-drain isolator.

7. A pair of fins comprising: a first fin having a first bottom channel portion, a first top channel portion, and a first channel isolator between the first bottom channel portion and the first top channel portion; and a second fin having a second bottom channel portion, a second top channel portion, and a second channel isolator between the second bottom channel portion and the second top channel portion; A source and drain stack including a bottom source or drain (S / D) region connected to the first bottom channel portion and the second bottom channel portion, a top S / D region connected to the first top channel portion and the second top channel portion, and a source-drain isolator between the bottom S / D region and the top S / D region, A spacer foot that is physically connected to the base side wall portion of the first bottom S / D region, The embedded S / D contact is physically connected to the upper side wall portion of the first bottom S / D region and Equipped with, The aforementioned embedded S / D contact is further physically connected to the embedded power rail. Semiconductor devices.

8. The semiconductor device according to claim 7, further comprising a top S / D contact physically connected to the upper surface of the first top S / D region.

9. The semiconductor device according to claim 7, wherein the top surface of the embedded S / D contact is located between the top surface of the source-drain isolator and the bottom surface of the source-drain isolator.

10. The semiconductor device according to claim 7, further comprising a common gate around the fin pair.

11. The semiconductor device according to claim 7, wherein the embedded S / D contact is further physically connected to the top surface of the spacer foot and to the side wall of the spacer foot.

12. The semiconductor device according to claim 7, wherein the side walls of the source-drain isolator are coplanar with the respective side walls of the bottom S / D region and coplanar with the respective side walls of the top S / D region.

13. Forming spacer pairs on the substrate, The process involves forming a fin trench between the spacer pair, wherein the fin trench exposes the side wall of the bottom fin channel region, exposes the side wall of the top fin channel region, and exposes the side wall of the fin channel isolator between the bottom fin channel region and the top fin channel region. A bottom source or drain (S / D) region is formed within the fin trench between the spacer pair and on the exposed side wall of the bottom fin channel region. Forming source-drain isolators within the fin trench between the spacer pairs and on the bottom S / D region, To form a top S / D region within the fin trench between the spacer pair and on the source-drain isolator, The spacer foot is formed by partially recessing at least one spacer of the spacer pair. Includes, Sacrificial gate structures are formed around the bottom fin channel region, around the fin channel isolator, and around the top fin channel region. Forming a sacrificial interlayer dielectric (ILD) on the substrate, around the spacer feet, around the bottom S / D region, around the source-drain isolator, and around the top S / D region, After forming the sacrificial ILD, the sacrificial gate structure is removed and a replacement gate structure is formed in its place. Removing the sacrificial ILD from the substrate, as well as around the spacer feet, around the bottom S / D region, around the source-drain isolator, and around the top S / D region, Injecting ions into the bottom S / D region and the top S / D region, After implanting ions into the bottom S / D region and the top S / D region, respectively, a replacement ILD is formed on the substrate, around the spacer feet, around the bottom S / D region, around the source-drain isolator, and around the top S / D region. A recessed contact trench is formed within the replacement ILD, exposing the recessed power rail, a portion of the spacer foot, and a portion of the side wall of the bottom S / D region. The method involves forming an embedded S / D contact within the embedded contact trench, wherein the embedded S / D contact physically connects the embedded power rail to a portion of the side wall of the bottom S / D region. Further including, A method for manufacturing semiconductor devices.

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