Hybrid complementary field-effect transistor device

Abstract

A stacked transistor device is provided, comprising a nanosheet transistor device on a substrate and a fin field effect transistor device on the nanosheet transistor device to form the stacked transistor device, the fin field effect transistor device configured such that current flow through the fin field effect transistor device is perpendicular to current flow through the nanosheet transistor device.

Description

Technical Field

[0001] The present invention generally relates to stacked transistor devices, and more particularly to stacked transistor devices having fin transistors on nanosheet transistors.

Background Art

[0002] A field effect transistor (FET) typically has a source, a channel, and a drain through which current flows from the source to the drain, and a gate that controls the flow of current through the device channel. The field effect transistor (FET) can have various different structures. For example, the FET is manufactured using a source, a channel, and a drain formed in the substrate material itself, and the current flows horizontally (i.e., parallel to the plane of the substrate). A FinFET is formed using a channel that extends outward from the substrate, and the current also flows horizontally from the source to the drain. The channel of the FinFET can be a thin rectangular silicon (Si) upright slab, usually called a fin, having a gate on the fin as compared to a MOSFET having a single gate parallel to the plane of the substrate. Depending on the doping of the source and the drain, an n-FET or a p-FET can be formed. Two FETs can also be combined to form a complementary metal oxide semiconductor (CMOS) device in which a p-channel MOSFET and an n-channel MOSFET are electrically coupled to each other.

Summary of the Invention

[0003] According to one embodiment of the present invention, a stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate, and a fin field effect transistor device on the nanosheet transistor device for forming the stacked transistor device, the fin field effect transistor device being configured such that the flow of current through the fin field effect transistor device is perpendicular to the flow of current through the nanosheet transistor device.

[0004] According to another embodiment of the present invention, a stacked transistor device is provided. The stacked transistor device includes a plurality of stacked semiconductor channel segments on a substrate, and nanosheet source / drain regions on each side of the plurality of stacked semiconductor channel segments. The stacked transistor device further includes a fin section on the plurality of stacked semiconductor channel segments, and fin source / drain regions on each side of the fin section. The stacked transistor device further includes a shared gate structure on the fin section and the plurality of stacked semiconductor channel segments, such that two nanosheet source / drain regions are on each side of the shared gate structure, two fin source / drain regions are on each side of the shared gate structure, and two nanosheet source / drain regions are on different sides of the shared gate structure from the two fin source / drain regions.

[0005] A method for forming a stacked transistor device is provided according to yet another embodiment of the present invention. The method comprises forming a plurality of stacked semiconductor channel segments and a fin section on the plurality of stacked semiconductor channel segments on a substrate. The method further comprises forming nanosheet source / drain regions on each side of the plurality of stacked semiconductor channel segments and forming fin sources / drains on each side of the fin section. The method further comprises forming a shared gate structure on the fin section and the plurality of stacked semiconductor channel segments such that two nanosheet source / drain regions are on both sides of the shared gate structure, two fin sources / drains are on both sides of the shared gate structure, and the two nanosheet source / drain regions are on different sides of the shared gate structure from the two fin sources / drains.

[0006] These and other features and advantages will become apparent from the following detailed description of the exemplary embodiment, which should be read in conjunction with the attached drawings.

[0007] The following description provides details of preferred embodiments with reference to the following drawings. [Brief explanation of the drawing]

[0008] [Figure 1] These are a top view and a side cross-sectional view showing an insulating layer on a substrate, a stack of alternating sacrificial semiconductor layers and semiconductor nanosheet layers on the insulating layer, and a fin semiconductor layer on the stack of alternating layers, according to one embodiment of the present invention. [Figure 2] These are top and side cross-sectional views showing a fin template on a vertical fin formed from fin semiconductor layers on a sacrificial beam above a stack of alternating layers, according to one embodiment of the present invention. [Figure 3] A top view and a side cross-sectional view showing a fin template and sacrificial spacers formed on both sides of a vertical fin, and alternating sacrificial semiconductor sections and semiconductor nanosheet sections formed from a stack of alternating layers by trimming, according to one embodiment of the present invention. [Figure 4] This is a top view and a side cross-sectional view showing an internal spacer formed in a recess of a sacrificial semiconductor section and nanosheet source / drain regions formed on both sides of a semiconductor nanosheet section above an insulating layer, according to one embodiment of the present invention. [Figure 5] These are a top view and a side cross-sectional view showing a dielectric packing layer formed on a nanosheet source / drain region and a sacrificial spacer according to one embodiment of the present invention. [Figure 6]This is a top view and a side cross-sectional view showing, according to one embodiment of the present invention, the formation of a gate template from a gate template layer on a fin template, and the removal of exposed portions of the fin template and the underlying vertical fins from both sides of the gate template to form a fin section, a sacrificial pad, and a sacrificial plate from a sacrificial beam. [Figure 7] These are a top view and a side cross-sectional view showing a state according to one embodiment of the present invention, in which a portion of the sacrificial spacer section is removed from both sides of the vertical fin section, and the remaining portion of the sacrificial spacer is on both sides of the vertical fin section. [Figure 8] A top view and a side cross-sectional view showing the removal of a portion of the sacrificial pad and sacrificial plate from beneath a fin section to form a collar indentation directly below the outer edge of the fin section, according to one embodiment of the present invention, and the remaining portion of the sacrificial beam. [Figure 9] A top view and a side cross-sectional view showing the formation of a protective filler in the gap between the fin section and the dielectric packing layer, and a collar spacer directly below the vertical fin section, which is generated by removing a portion of the sacrificial spacer, according to one embodiment of the present invention. [Figure 10] These are a top view and a side cross-sectional view showing the formation of nanosheet templates on both sides of a fin section and the removal of exposed portions of the laminated layer according to one embodiment of the present invention. [Figure 11] These are a top view and a side cross-sectional view showing the formation of a sacrificial gate extension on a laminated layer according to one embodiment of the present invention. [Figure 12] This is a top view and a side cross-sectional view showing the removal of a nanosheet template and the formation of a bottom dielectric shell on a sacrificial gate extension according to one embodiment of the present invention. [Figure 13] A top view and a side cross-sectional view illustrating an embodiment of the present invention in which a portion of the fin template is replaced by a top internal spacer located between the fin template on both sides and a portion of the protective filler. [Figure 14] This is a top view and a side cross-sectional view showing the formation of fin sources / drains on both sides of a fin section and the positions of the nanosheet sources / drains on both sides of a nanosheet stack, according to one embodiment of the present invention. [Figure 15] A top view and a side cross-sectional view illustrating the formation of a cover layer on a fin source / drain and bottom dielectric shell according to one embodiment of the present invention. [Figure 16] This is a top view and a side cross-sectional view showing the removal of a fin template section and the removal of a sacrificial semiconductor section between a sacrificial gate extension and a semiconductor nanosheet section, according to one embodiment of the present invention, in order to form a gate channel. [Figure 17] These are a top view and a side cross-sectional view illustrating the formation of a gate structure in a gap and a gate channel according to one embodiment of the present invention. [Figure 18] These are top and side cross-sectional views illustrating the formation of source / drain and gate contacts for a lower nanosheet device and an upper vertical fin device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Embodiments of the present invention provide a hybrid complementary field-effect transistor (CFET) device having a fin field-effect transistor (FinFET) on top of a nanosheet field-effect transistor (NSFET). In various embodiments, the FinFET can be a p-type field-effect transistor (pFET) and the NSFET can be an n-type field-effect transistor (nFET) to form a complementary device. In a stacked transistor device having a fin transistor on a nanosheet transistor, the direction of current flow between the top device and the bottom device is orthogonal. In various embodiments, the direction of current flow in the top FinFET is perpendicular to the direction of current flow in the bottom NSFET. This facilitates S / D contact formation because the S / D epitaxy of the top device does not overlap with the S / D epitaxy of the bottom device.

[0010] Embodiments of the present invention provide a method for forming a hybrid complementary field-effect transistor (CFET) device, comprising forming a set of alternately stacked nanosheet sections on a substrate and forming vertical fins on the stack of nanosheet sections. In various embodiments, the gate structure may be a shared gate structure present in both the FinFET and NSFET, controlling switching and current flowing through both devices.

[0011] Exemplary applications / uses to which the present invention can be applied include, but are not limited to, logic devices (e.g., NAND gates, NOR gates, XOR gates, etc.), processors (e.g., central processing units (CPUs), graphics processing units (GPUs)), and memory devices (e.g., static random-access memory (SRAM)).

[0012] While aspects of the present invention are described in terms of a given exemplary architecture, it should be understood that other architectures, structures, substrate materials, and process features and steps may be modified within the scope of the present invention.

[0013] Here, referring to the drawings in which like numerals represent the same or similar elements, and first referring to FIG. 1, FIG. 1 illustrates a top view and a side cross-sectional view showing an insulating layer on a substrate, a stack of alternating sacrificial semiconductor layers and semiconductor nanosheet layers on the insulating layer, and a fin semiconductor layer on the stack of alternating layers, according to an embodiment of the present invention.

[0014] In one or more embodiments, a series of alternating sacrificial spacer layers 130 and semiconductor channel layers 140 can be formed on the insulating layer 120, and the insulating layer can be part of the substrate 110. In various embodiments, the sacrificial spacer layers 130 and semiconductor channel layers 140 can be formed by epitaxial growth or heteroepitaxial growth on a bottom layer, and the bottom layer can be a single crystal. In various embodiments, the top sacrificial spacer layer 150 can be present on the channel layer 140, and the top sacrificial spacer layer 150 can be made thicker than the other alternating sacrificial spacer layers 130.

[0015] In one or more embodiments, the substrate 110 can be a Group-IV semiconductor material (e.g., silicon (Si), germanium (Ge)), a Group-IV-IV semiconductor material (e.g., silicon carbide (SiC), silicon-germanium (SiGe)), or a Group-III-V semiconductor material (e.g., gallium arsenide (GaAs), indium phosphide (InP)), and the material of the active semiconductor layer can be selectively removable with respect to the overlying channel layer 140. In various embodiments, the substrate 110 can be a semiconductor material, and the semiconductor material can be a single crystal, polycrystal, microcrystal, or amorphous, or a combination thereof, and the substrate 110 can provide physical support for the insulating layer 120.

[0016] In one or more embodiments, the insulating layer 120 can be an insulating dielectric material, such as silicon oxide (SiO) or silicon nitride (SiN), and the insulating layer 120 can be a buried oxide layer (BOX) on the substrate 110. The substrate 110 can function as a carrier layer for the insulating layer 120.

[0017] In one or more embodiments, the sacrificial spacer layer 130 can be a Group IV semiconductor material (e.g., silicon (Si), germanium (Ge)), a Group IV-IV semiconductor material (e.g., silicon carbide (SiC), silicon-germanium (SiGe)), or a Group III-V material (e.g., gallium arsenide (GaAs), indium phosphide (InP)), and the material of the sacrificial spacer layer 130 is different from the material of the semiconductor channel layer 140 to enable selective removal, but provides epitaxial or heteroepitaxial growth on alternating layers.

[0018] In a non-limiting exemplary embodiment, the sacrificial spacer layer 130 can be silicon-germanium (SiGe) having a predetermined germanium concentration that enables selective removal of the spacer layer 130.

[0019] In one or more embodiments, the sacrificial spacer layer 130 can have a thickness in the range of about 6 nanometers (nm) to about 30 nm, or about 8 nm to about 15 nm, and provides a distance between the channel layers 140 sufficient to form a gate all around (GAA) structure.

[0020] In one or more embodiments, the channel layer 140 can have a thickness in the range of about 4 nanometers (nm) to about 12 nm, or about 6 nm to about 9 nm, but other thicknesses are also contemplated.

[0021] In one or more embodiments, the top sacrificial spacer layer 150 may have a thickness in the range of about 12 nanometers (nm) to about 60 nm, or about 16 nm to about 30 nm, and the top sacrificial spacer layer 150 may be about twice the thickness of the sacrificial spacer layer 130 (2x) to provide sufficient distance between the fin semiconductor layer 160 and the uppermost channel layer 140 for over-etching and vertical fins 162.

[0022] In one or more embodiments, the fin semiconductor layer 160 can be a group IV semiconductor material (e.g., silicon (Si), germanium (Ge)), a group IV-IV semiconductor material (e.g., silicon carbide (SiC), silicon-germanium (SiGe)), or a group III-V semiconductor material (e.g., gallium arsenide (GaAs), indium phosphide (InP)). The semiconductor channel layer 140 can be a single crystal to provide epitaxial or heteroepitaxial growth.

[0023] In one or more embodiments, the fin semiconductor layer 160 may have a thickness in the range of about 20 nanometers (nm) to about 100 nm, or about 35 nm to about 60 nm, although other thicknesses are also intended. The thickness of the fin semiconductor layer 160 may be sufficient to provide a channel width for the upper FinFET device that is suitable for the intended device characteristics (e.g., current capacity, switching time, etc.).

[0024] In non-limiting exemplary embodiments, the device stack can be formed on an SOI substrate where an insulating layer 120 (embedded oxide) is formed on a substrate 110. A semiconductor layer (e.g., a silicon (Si) layer (not shown)) can be provided on the insulating layer 120 and thinned, then silicon-germanium (SiGe) epitaxial growth can be performed, and then the SiGe can be condensed to convert the first semiconductor layer on the insulating layer 120 into a SiGe sacrificial spacer layer 130. Subsequently, an oxide layer (not shown) on the bottom last SiGe layer 130 can be removed by DHF, and then alternating Si and SiGe layers (140, 130, 150, 160) can be epitaxi-grown. While the present invention is described using an SOI substrate, it should be noted that the methods and structures of the present invention also work for different substrates, such as bulk Si substrates without the embedded oxide 120, and alternative SiGe and Si epitaxy layers grown directly on a Si substrate 110.

[0025] Figure 2 shows a top view and a side cross-sectional view of a fin template on a vertical fin formed from a fin semiconductor layer on a sacrificial beam above a stack of alternating layers, according to one embodiment of the present invention.

[0026] In various embodiments, a patterning process can be used to form vertical fins having a top semiconductor layer 160 and a portion of the top sacrificial spacer layer 150.

[0027] In one or more embodiments, one or more fin templates 170 can be formed on the fin semiconductor layer 160, and the fin templates 170 can be formed by patterning and etching the fin template layer using lithography and etching methods.

[0028] In various embodiments, the fin template 170 can be a dielectric hard mask material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon bonitride (SiBN), silicon carbonitride (SiCN), silicon boronite (SiBCN), or a combination thereof.

[0029] In one or more embodiments, the vertical fins 162 can be formed from the fin semiconductor layer 160 using selective directional etching, such as reactive ion etching (RIE). The exposed portions of the fin semiconductor layer 160 and the upper part of the top sacrificial spacer layer 150 can be removed so as to reduce the height of the top sacrificial spacer layer 150 and form a sacrificial beam 152 directly beneath the vertical fins 162.

[0030] Figure 3 shows a top view and a side cross-sectional view of a fin template and sacrificial spacers formed on both sides of a vertical fin, and alternating sacrificial semiconductor sections and semiconductor nanosheet sections formed from a stack of alternating layers by trimming, according to one embodiment of the present invention.

[0031] In one or more embodiments, sacrificial spacers 180 may be formed on both sides of the fin template 170 and the vertical fin 162, and the sacrificial spacers 180 may be formed, for example, by depositing conformal layers using atomic layer deposition (ALD) and removing the horizontal portion from the top sacrificial spacer layer 150 using anisotropic spacer etching (e.g., RIE).

[0032] In various embodiments, the sacrificial spacer 180 can be a dielectric hard mask material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon bonitride (SiBN), silicon carbonitride (SiCN), silicon boronite (SiBCN), or a combination thereof.

[0033] In one or more embodiments, the sacrificial spacer 180 may have a width in the range of about 5 nm to about 25 nm, or about 8 nm to about 15 nm, but other thicknesses are also intended.

[0034] In one or more embodiments, the top sacrificial spacer layer 150, the semiconductor channel layer 140, and the sacrificial spacer layer 130 can be trimmed by removing portions not covered by the fin template 170 and the sacrificial spacer 180 using directional etching (e.g., RIE). The etching can be carried out down to the insulating layer 120 so that the surface of the insulating layer 120 is exposed.

[0035] By removing the top sacrificial spacer layer 150, the semiconductor channel layer 140, and a portion of the sacrificial spacer layer 130, the top sacrificial spacer section 156, the sacrificial semiconductor section 135, and the semiconductor channel section 145 are formed.

[0036] Figure 4 illustrates a top view and a side cross-sectional view showing an internal spacer formed in a recess of a sacrificial semiconductor section and nanosheet source / drain regions formed on both sides of a semiconductor nanosheet section above the insulating layer, according to one embodiment of the present invention.

[0037] In one or more embodiments, portions of the sacrificial semiconductor section 135 and the top sacrificial spacer section 156 can be removed using isotropic etching, e.g., wet chemical etching or dry plasma etching, to form recesses. Conformal deposition, e.g., atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD), can be used to deposit an internal spacer layer, and portions of the internal spacer layer can be removed by selective etching to form internal spacers 190. By removing portions of the sacrificial semiconductor section 135 and the top sacrificial spacer section 156, a sacrificial beam 152 can be formed directly beneath the vertical fin 162, and a wider top sacrificial bar 157 can be formed on the uppermost semiconductor nanosheet section 145.

[0038] In various embodiments, the internal spacer 190 can be an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), low-k dielectric materials, or combinations thereof. Examples of low-k dielectric materials include fluorine-doped silicon oxide (SiO:F), carbon-doped silicon oxide (SiO:C), polymer materials such as tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and methylsilsesquioxane (MSQ), organosilicon compounds (SiCOH), and combinations thereof.

[0039] In one or more embodiments, the nanosheet source / drain region 200 can be formed on both sides of the semiconductor nanosheet section 145 above the insulating layer 120, and the nanosheet source / drain region 200 can be formed by a lateral epitaxial growth process. In various embodiments, another stacked FET can be formed next to the S / D epi 200, so there is no empty space next to the S / D epi 200.

[0040] In various embodiments, the nanosheet source / drain region 200 is a doped semiconductor material (e.g., Si, SiGe, etc.), and the semiconductor material can be n-doped or p-doped depending on the type of device to be formed (i.e., n-type or p-type).

[0041] In various embodiments, the nanosheet source / drain region 200 may have a width in the range of about 8 nm to about 100 nm, or about 12 nm to about 30 nm, although other thicknesses are also intended.

[0042] Figure 5 shows a top view and a side cross-sectional view of a dielectric packing layer formed on a nanosheet source / drain region and sacrificial spacer according to one embodiment of the present invention.

[0043] In one or more embodiments, the dielectric packing layer 210 can be formed on the nanosheet source / drain region 200 and the sacrificial spacer 180, and the dielectric packing layer 210 can be formed by blanket deposition, for example, chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD). The dielectric packing layer 210 can be an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), low-k dielectric material, or a combination thereof.

[0044] Figure 6 shows a top view and a side cross-sectional view illustrating, according to one embodiment of the present invention, the formation of a gate template from a gate template layer on a fin template, and the removal of the exposed portions of the fin template and the underlying vertical fins from both sides of the gate template to form a fin section, a sacrificial pad, and a sacrificial plate from a sacrificial beam.

[0045] In one or more embodiments, the gate template 220 can be formed from a gate template layer on a fin template 170, a sacrificial spacer 180, and a dielectric packing layer 210, and the gate template 220 can be formed using lithography and etching. The gate template 220 can be substantially perpendicular (within the tolerance range of the manufacturing process used) to the fin template 170 and the sacrificial spacer 180.

[0046] In one or more embodiments, the fin template 170, sacrificial spacer 180, and portions of the dielectric packing layer 210 exposed on both sides of the gate template 220 can be removed using directional etching to trim the vertical fin 162 and form a fin section 165 on a sacrificial pad 153 directly below the fin section. The exposed portion of the sacrificial spacer 180 can be removed to form a sacrificial spacer section 182. The exposed portion of the fin template 170 can be removed to form a fin template section 172. The exposed upper part of the sacrificial beam 152 can be removed to form a sacrificial pad 153 below the fin section, and the remaining portion of the sacrificial beam 152 can form a sacrificial plate 155 extending outward from both sides of the gate template 220. A wider top sacrificial bar 157 below the sacrificial spacer section 182 can extend outward from both sides of the gate template 220.

[0047] Figure 7 shows a top view and a side section view illustrating a state according to one embodiment of the present invention, in which a portion of the sacrificial spacer section is removed from both sides of the vertical fin section, and the remaining portion of the sacrificial spacer is on both sides of the vertical fin section.

[0048] In one or more embodiments, the outer portions of the sacrificial spacer sections 182 on both sides of the gate template 220 can be removed from both sides of the vertical fin section 165 (see section X'), while the inner portions of the sacrificial spacer sections 182 remain on both sides of the vertical fin section 165 (see section X). Part of the sacrificial spacer section 182 can be removed using selective isotropic etching (e.g., dry plasma etching), thereby forming a gap 230 between the fin section 165 and the dielectric packing layer 210. The fin template section 172 can remain on the fin section 165. Removal of the sacrificial spacer section 182 exposes the uppermost internal spacer 190, the side walls of the sacrificial pad 153 and sacrificial plate 155, and the upper surface of the top sacrificial bar 157.

[0049] Figure 8 illustrates a top view and a side section view showing the removal of a portion of the sacrificial pad and sacrificial plate from beneath the fin section to form a collar recess directly below the outer edge of the fin section, according to one embodiment of the present invention, and the remaining portion of the sacrificial beam.

[0050] In one or more embodiments, selective etching can be used to remove the outer portions of the sacrificial pad 153 and sacrificial plate 155 in order to form a collar recess 235 directly below the outer edge of the fin section 165 (see section Y). The upper part of the top sacrificial bar 157 may also be removed by selective etching (see section X').

[0051] Figure 9 illustrates a top view and a side section view showing the formation of a protective filler in the gap between the fin section and the dielectric packing layer, and a collar spacer directly beneath the vertical fin section, which is created by removing a portion of the sacrificial spacer, according to one embodiment of the present invention.

[0052] In one or more embodiments, a protective filler 240 can be formed in the gap 230 between the fin section 165 and the dielectric packing layer 210, and a color spacer 240 can be formed in the color recess 235 directly below the vertical fin section. The protective filler 240 can be formed by conformal deposition followed by isotropic etch-back. The protective filler 240 can be an insulating dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a low-k dielectric material, or a combination thereof. The color spacer 240 may be present on both sides of the sacrificial pillar 154 formed by the sacrificial pad 153 and the remaining portion of the sacrificial plate 155 directly below the fin section 165.

[0053] Figure 10 shows a top view and a side cross-sectional view illustrating the formation of nanosheet templates on both sides of a fin section and the removal of exposed portions of the laminated layer according to one embodiment of the present invention.

[0054] In one or more embodiments, the nanosheet template 250 can be formed on both sides of the fin section 165, and the nanosheet template 250 can be formed by layer deposition and directional etching.

[0055] In one or more embodiments, the nanosheet template 250 may have a width in the range of about 20 nm to about 100 nm, or about 35 nm to about 60 nm, but other thicknesses are also intended.

[0056] In one or more embodiments, the exposed portions of the semiconductor channel section 145, the sacrificial semiconductor section 135, and the apex sacrificial bar 157 can be removed using selective directional etching to form the semiconductor channel segment 148, the apex sacrificial semiconductor segment 159, and the sacrificial semiconductor segment 137.

[0057] Figure 11 illustrates a top view and a side cross-sectional view showing the formation of a sacrificial gate extension on a laminated layer according to one embodiment of the present invention.

[0058] In one or more embodiments, a sacrificial gate extension 260 can be formed on the remaining laminated layer including a semiconductor channel segment 148, a top sacrificial semiconductor segment 159, and a sacrificial semiconductor segment 138. The sacrificial gate extension 260 can be formed by epitaxial growth on the exposed surfaces of the sacrificial semiconductor segment 138 and the semiconductor channel segment 148, and the sacrificial gate extension 260 can be made of the same material as the sacrificial semiconductor segment 138 so that both the sacrificial semiconductor segment 138 and the sacrificial gate extension 260 can be selectively removed simultaneously.

[0059] Figure 12 shows a top view and a side cross-sectional view illustrating the removal of a nanosheet template and the formation of a bottom dielectric shell on the sacrificial gate extension according to one embodiment of the present invention.

[0060] In one or more embodiments, the nanosheet template 250 can be removed using selective etching.

[0061] In one or more embodiments, a bottom dielectric shell 270 can be formed on the sacrificial gate extensions 260 on both sides of the fin section 165. The bottom dielectric shell 270 can be formed by overfilling the substrate 110 with dielectric material, followed by chemical mechanical polishing (CMP) and recessing. The top surface of the bottom dielectric shell 270 can be made level with the bottom of the fin section 165 by controlled recessing.

[0062] In various embodiments, the bottom dielectric shell 270 can be a dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBCN), low-k dielectrics, and combinations thereof.

[0063] Figure 13 illustrates a top view and a side section view showing an embodiment of the present invention in which a portion of the fin template is replaced with a top internal spacer located between both sides of the fin template and a portion of the protective filler.

[0064] In one or more embodiments, a portion of the fin template 172 can be replaced by top internal spacers 280 on both sides of the fin template, the outer portion of the fin template can be removed by isotropic etching, and the top internal spacers 280 can be formed from conformal layer deposition followed by isotropic etch-back.

[0065] In various embodiments, the top internal spacer 280 can be a dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBCN), low-k dielectrics, and combinations thereof. Since the top internal spacer 280 can be made of a different material from the fin template section 172, the fin template section 172 can be selectively removed.

[0066] Figure 14 illustrates a top view and a side cross-sectional view showing the formation of fin sources / drains on both sides of a fin section and the positions of nanosheet sources / drains on both sides of a nanosheet stack according to one embodiment of the present invention.

[0067] In one or more embodiments, the fin source / drain 290 can be formed on both sides of the fin section 165, and the fin source / drain 290 can be formed by lateral epitaxial growth on the exposed surface of the fin section 165. A bottom dielectric shell 270 located below the shared gate structure can electrically isolate the fin source / drain 290 from the bottom of the shared gate structure of the NSFET.

[0068] Figure 15 illustrates a top view and a side cross-sectional view showing the formation of a cover layer on the fin source / drain and bottom dielectric shell according to one embodiment of the present invention.

[0069] In one or more embodiments, the cover layer 300 can be formed on the fin source / drain 290 and the bottom dielectric shell 270, and the cover layer 300 can be formed by blanket deposition. The cover layer 300 can fill the spaces between portions of the dielectric packing layer 210.

[0070] In various embodiments, the cover layer 300 can be a dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBCN), low-k dielectrics, and combinations thereof. The cover layer 300 can be the same dielectric material as the dielectric packing layer 210.

[0071] Figure 16 shows a top view and a side cross-sectional view illustrating the removal of a fin template section and a sacrificial semiconductor section between a sacrificial gate extension and a semiconductor nanosheet section in order to form a gate channel, according to one embodiment of the present invention.

[0072] In one or more embodiments, the fin template section 172 can be removed using selective etching.

[0073] In one or more embodiments, the sacrificial spacer section 182 can be removed using selective etching.

[0074] In one or more embodiments, the sacrificial pillar 154, the apex sacrificial semiconductor segment 159, the sacrificial gate extension 260, and the sacrificial semiconductor segment 138 can be removed using selective etching to form a gate channel 310 adjacent to the fin section 165 and the semiconductor channel segment 148. By removing the sacrificial gate extension 260, space can be provided for forming a wrap-around gate on the semiconductor channel segment 148.

[0075] Figure 17 illustrates a top view and a side cross-sectional view showing the formation of a gate structure in a gap and a gate channel according to one embodiment of the present invention.

[0076] In one or more embodiments, the gate structure 320 can be formed in the gap and gate channel 310, and the gate structure 320 can be formed by a series of conformal depositions for forming a gate dielectric layer, a work function layer, and a conductive gate filler. In various embodiments, the gate structure can be a shared gate structure in which the conductive gate filler is located on both the fin section 165 and the semiconductor channel segment 148, so that the gate structure 320 controls the flow of current through both the fin section 165 and the semiconductor channel segment 148.

[0077] In various embodiments, the lower part of the shared gate structure 320 can control the current flow and switching of the nanosheet field-effect transistor, and the upper part of the shared gate structure 320 can control the current flow and switching of the fin field-effect transistor. This allows the fin field-effect transistor and the nanosheet field-effect transistor to operate simultaneously.

[0078] In various embodiments, the gate dielectric layer can be a dielectric material including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), high-k dielectrics, and combinations thereof. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), scandium tantalum lead oxide (PbScTaO), and zinc lead niobate (PbZnNbO). High-k materials may further include dopants such as lanthanum, aluminum, magnesium, or combinations thereof.

[0079] In various embodiments, the gate dielectric layer may have a thickness in the range of about 1 nm to about 5 nm, or about 2 nm to about 4 nm, but other thicknesses are also intended.

[0080] In various embodiments, the conductive gate packing is doped polycrystalline or amorphous silicon, germanium, silicon-germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au)), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tan carbide) This can include, but is not limited to, any suitable conductive material, including, talc (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silide (CoSi), nickel silide (NiSi), transition metal aluminides (e.g., Ti3Al, ZrAl), magnesium tantalum carbide (TaMgC), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials.

[0081] Work function materials (WFMs) can be any suitable material, including but not limited to nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), and niobium nitride (NbN); carbides such as titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), and hafnium carbide (HfC); and combinations thereof. In some embodiments, a conductive material or a combination of several conductive materials can function as both a gate conductor and a work function material (WFM).

[0082] Figure 18 illustrates a top view and a side cross-sectional view showing the formation of source / drain contacts and gate contacts for a lower nanosheet device and an upper vertical fin device according to one embodiment of the present invention.

[0083] In one or more embodiments, an interlayer dielectric (ILD) layer 330 can be formed on a lower layer, and the ILD layer 330 can be formed by blanket deposition.

[0084] In various embodiments, the interlayer dielectric (ILD) layer 330 may be made of dielectric materials including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBCN), low-k dielectrics, and combinations thereof. The interlayer dielectric (ILD) layer 330 may be made of the same dielectric material as the cover layer 300 and the dielectric packing layer 210.

[0085] In one or more embodiments, nanosheet source / drain contacts 340 can be formed in the ILD layer 330 and the dielectric packing layer 210, and gate contacts 350 for a shared gate structure of the lower nanosheet device and the upper vertical fin device can be formed in the ILD layer 330.

[0086] In one or more embodiments, the fin source / drain contact 360 can be formed in the ILD layer 330, the cover layer 300, and the dielectric packing layer 210. The nanosheet source / drain contact 340, the gate contact 350, and the fin source / drain contact 360 can be made of conductive materials including, but not limited to, metals (e.g., W, Cu, Ta, etc.), conductive metal compound materials (e.g., TaC, WN, TiN, etc.), doped semiconductor materials (e.g., doped Si), carbon nanotubes, conductive carbon, and combinations thereof. The nanosheet source / drain contacts 340 are located on each of the two nanosheet source / drain regions 200 and can be electrically connected to them, the fin source / drain contacts 360 are located on each of the two fin source / drain regions 290 and can be electrically connected to them, and the nanosheet source / drain contacts 340 are on different sides of the gate contacts 350 and shared gate structure from the two fin source / drain contacts 360.

[0087] In various embodiments, the two nanosheet source / drain regions 200 on either side of the shared gate structure of a nanosheet transistor device, and the two fin source / drain regions on either side of the shared gate structure of a fin field-effect transistor device, are positioned such that a first axis between the two nanosheet source / drain regions penetrating the shared gate structure intersects a second axis between the two fin source / drain regions penetrating the shared gate structure at approximately 90 degrees (e.g., + / - 5 degrees). The first and second axes can determine the direction of current flow in the NSFET and FinFET.

[0088] Because the current flow directions of the top and bottom devices are perpendicular to each other, the contacts are located in the nanosheet source / drain region 200 of the bottom device in the X direction and are accessible, and in the fin source / drain (S / D) 290 of the top device in the Y direction and are accessible. In contrast, in conventional CFETs, the currents of both the top and bottom devices flow parallel to each other, and the bottom S / D epitaxial overlaps the top S / D epitaxial, resulting in the contacts not being able to easily access the bottom S / D epitaxial.

[0089] This embodiment may include a design for an integrated circuit chip, created in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive within a storage access network). If the designer does not manufacture the chip or the photolithograph mask used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium on which the design is stored) or electronically (e.g., via the Internet). The stored design is then converted to a format suitable for the manufacture of a photolithograph mask (e.g., GDSII), which typically includes multiple copies of the chip design in question to be formed on a wafer. The photolithograph mask is used to define areas of the wafer (or layers on it or both) to be processed by etching or other methods.

[0090] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with either surface-mounted or embedded-mounted wiring, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with central processing units.

[0091] It should also be understood that material compounds are described with respect to the enumerated elements, for example, SiGe. These compounds contain different proportions of elements within the compound; for example, SiGe contains Si x Ge 1-x This includes (where x is less than or equal to 1) and so on. In addition, other elements may be included in the compound, and it can still function according to this principle. Compounds containing additional elements are referred to as alloys in this specification.

[0092] In this specification, the terms "one embodiment" or "an embodiment," as well as references to other variations, mean that certain features, structures, characteristics, etc., described in relation to that embodiment are included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in one embodiment," and any other variations appearing in various places throughout this specification, do not necessarily all refer to the same embodiment.

[0093] For example, in the cases of "A / B", "A or B or both", and "at least one of A and B", it should be understood that the use of " / ", "or... or both", and "at least one of" is intended to encompass the selection of only the first listed option (A), or only the second listed option (B), or both options (A and B). As a further example, in the cases of "A, B, or C, or a combination thereof", and "at least one of A, B, and C", such phrasing is intended to encompass the selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). This can be extended to many of the listed items, as will be readily apparent to those skilled in the art.

[0094] The terminology used herein is intended to describe only specific embodiments and not to limit the exemplary embodiments. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context explicitly indicates otherwise. Where used herein, the terms “comprises,” “comprising,” “includes,” or “including,” or any combination thereof, specify the presence of a described feature, complete, step, action, element, or component, or a combination thereof, but do not exclude the presence or addition of one or more other features, complete, step, action, element, component, or groups thereof, or combination thereof.

[0095] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate descriptions of the relationship between one element or feature and another, as shown in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. For example, if the device in the figure is turned over, an element described as “below” or “directly below” another element or feature will face “above” the other element or feature. Thus, the term “below” can encompass both upward and downward orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being “between” two layers, that layer may be the sole layer between the two layers, or there may be one or more intervening layers.

[0096] In this specification, various elements may be described using terms such as "first," "second," etc., but it should be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Therefore, the first element discussed below can be called the second element without deviating from the scope of this concept.

[0097] When an element such as a layer, region, or substrate is described as being "on" or "over" another element, it will be understood that the element may be directly on top of the other element, or there may be an intervening element. In contrast, when an element is described as being "directly on" or "directly over" another element, there is no intervening element. Similarly, when an element is described as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or there may be an intervening element. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there is no intervening element.

[0098] Preferred embodiments (intended to be illustrative and not limiting) of the device and the method of manufacturing the device have been described, but it should be noted that modifications and variations may be made in light of the above teachings by those skilled in the art. Therefore, it should be understood that modifications may be made to specific embodiments of the disclosed model that fall within the scope of the invention as outlined by the appended claims. Accordingly, aspects of the invention have been described, along with the details and specificities required by patent law, but those claimed and desired to be protected by patent are described in the appended claims.

Claims

1. A stacked transistor device, Nanosheet transistor devices on a substrate, A fin field-effect transistor device on a nanosheet transistor device for forming the stacked transistor device, wherein the fin field-effect transistor device is configured such that the current flow parallel to the upper surface of the substrate passing through the fin field-effect transistor device is perpendicular to the current flow parallel to the upper surface of the substrate passing through the nanosheet transistor device, The shared gate structure of the nanosheet transistor device and the fin field-effect transistor device, A stacked transistor device equipped with [a specific feature].

2. The stacked transistor device according to claim 1, further comprising a gate contact located on the shared gate structure and electrically in contact with the shared gate structure.

3. The stacked transistor device according to claim 2, wherein the nanosheet transistor device includes two nanosheet source / drain regions on both sides of the shared gate structure, and the fin field-effect transistor device includes two fin source / drain regions on both sides of the shared gate structure, wherein the two nanosheet source / drain regions are on different sides of the shared gate structure from the two fin source / drain regions.

4. The stacked transistor device according to claim 3, further comprising: a nanosheet source / drain contact located on each of the two nanosheet source / drain regions and electrically communicating with each of the two nanosheet source / drain regions; and a fin source / drain contact located on each of the two fin source / drains and electrically communicating with each of the two fin source / drains, wherein the nanosheet source / drain contacts are on different sides of the gate contacts and the shared gate structure from the two fin source / drain contacts.

5. Multiple stacked semiconductor channel segments on a substrate, Nanosheet source / drain regions located on both sides of the aforementioned plurality of stacked semiconductor channel segments, A fin section located on the plurality of stacked semiconductor channel segments, Fin sources / drains located on both sides of the aforementioned fin section, A shared gate structure on the fin section and the plurality of stacked semiconductor channel segments, wherein two nanosheet source / drain regions are located on both sides of the shared gate structure, two fin source / drain regions are located on both sides of the shared gate structure, and the two nanosheet source / drain regions are located on different sides of the shared gate structure from the two fin source / drain regions, A stacked transistor device equipped with [a specific feature].

6. The stacked transistor device according to claim 5, further comprising protective filler on a portion of the fin section.

7. The stacked transistor device according to claim 6, further comprising a gate contact located on the shared gate structure and electrically in contact with the shared gate structure.

8. The stacked transistor device according to claim 7, further comprising: nanosheet source / drain contacts located on each of the nanosheet source / drain regions and electrically communicating with each of the nanosheet source / drain regions; and fin source / drain contacts located on each of the fin source / drains and electrically communicating with each of the fin source / drains, wherein the nanosheet source / drain contacts are on different sides of the gate contacts and the shared gate structure from the two fin source / drain contacts.

9. The stacked transistor device according to claim 8, further comprising a bottom dielectric shell at the bottom of the shared gate structure, wherein a portion of the bottom dielectric shell electrically isolates the fin source / drain from the bottom of the shared gate structure.

10. The stacked transistor device according to claim 8, further comprising an insulating layer between the substrate and the shared gate structure.

11. A method for forming a stacked transistor device, The process involves forming multiple stacked semiconductor channel segments on a substrate, and fin sections on the multiple stacked semiconductor channel segments, Forming nanosheet source / drain regions on each of the multiple stacked semiconductor channel segments, Fin sources / drains are formed on each side of the fin section, The formation of a shared gate structure on the fin section and the plurality of stacked semiconductor channel segments, wherein two nanosheet source / drain regions are located on both sides of the shared gate structure, two fin source / drain regions are located on both sides of the shared gate structure, and the two nanosheet source / drain regions are located on different sides of the shared gate structure from the two fin source / drain regions. Methods that include...

12. The method according to claim 11, further comprising forming a bottom dielectric shell at the bottom of the shared gate structure, wherein a portion of the bottom dielectric shell electrically isolates the fin source / drain from the bottom of the shared gate structure.

13. The method according to claim 12, further comprising forming a cover layer on the fin source / drain and the bottom dielectric shell.

14. The method according to claim 13, further comprising forming a nanosheet source / drain contact on each of the nanosheet source / drain regions that is electrically in communication with each of the nanosheet source / drain regions.

15. The method according to claim 14, further comprising forming a fin source / drain contact on each of the fin source / drains that is electrically in communication with each of the fin source / drains.

16. The method according to claim 15, further comprising forming a gate contact located on the shared gate structure and electrically contacting the shared gate structure.

17. The method according to claim 16, wherein the nanosheet source / drain contact is on a different side from the gate contact and the shared gate structure from the two fin source / drain contacts.

18. The method according to claim 17, further comprising forming a dielectric packing layer on the fin source / drain and the nanosheet source / drain regions.

19. The method according to claim 18, further comprising forming a protective filler on a portion of the fin section and on the dielectric filling layer.

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