Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device in which reliability can be improved.SOLUTION: In a silicon carbide semiconductor device 100, an active region IR comprises: a first super junction layer 10; and an element layer 40. The first super junction layer alternately has a first region 41 and a second region 42. A peripheral region OR comprises: a second super junction layer 20; a termination layer 50; and an insulation layer 7. The second super junction layer alternately has a third region 43 and a fourth region 44. The termination layer is provided above the second super junction layer by being contacted with the second super junction layer, and alternately has a fifth region 45 and a sixth region 46. The fifth region is provided corresponding to the third region, and the sixth region is provided corresponding to the fourth region. Impurity density of the sixth region is larger than impurity density of the fifth region, and is less than or equal to 68 times of the impurity density of the fifth region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide semiconductor devices. This application claims priority under Japanese Patent Application No. 2020-118900, filed on 10 July 2020. All contents contained in said Japanese Patent Application are incorporated herein by reference. [Background technology]

[0002] Japanese Patent Publication No. 2006-73987 (Patent Document 1) and Japanese Patent Publication No. 2003-273355 (Patent Document 2) describe MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having a superjunction structure, primarily focusing on silicon semiconductors. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2006-73987 [Patent Document 2] Japanese Patent Publication No. 2003-273355 [Overview of the Initiative]

[0004] The silicon carbide semiconductor device according to this disclosure comprises a substrate, an active region, a peripheral region, and a first electrode. The substrate is made of a silicon carbide semiconductor of a first conductivity type. The active region is provided on a part of the first main surface of the substrate. The peripheral region is provided on the substrate and surrounds the active region in a plan view. The first electrode is provided on a second main surface of the substrate opposite the first main surface. The active region includes a first superjunction layer, an element layer, and a second electrode. The first superjunction layer is provided above the substrate and alternately has a first region of the first conductivity type and a second region of the second conductivity type. The element layer is provided above the first superjunction layer. The second electrode is provided on top of the element layer. The peripheral region includes a second superjunction layer, a termination layer, and an insulating layer. The second superjunction layer is provided above the substrate and alternately has a third region of the first conductivity type and a fourth region of the second conductivity type. The termination layer is provided in contact with the second superjunction layer and alternately has a fifth region of the second conductivity type and a sixth region of the second conductivity type. The insulating layer is in contact with the upper end surfaces of the fifth region and the sixth region, respectively. The fifth region is provided in correspondence with the third region, and the sixth region is provided in correspondence with the fourth region. The impurity concentration of the sixth region is greater than that of the fifth region, and no more than 68 times the impurity concentration of the fifth region. [Brief explanation of the drawing]

[0005] [Figure 1] Figure 1 is a schematic longitudinal cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the second embodiment. [Figure 3] Figure 3 is a schematic longitudinal section along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic longitudinal section along the line IV-IV in Figure 2. [Figure 5] Figure 5 is a schematic longitudinal cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the third embodiment. [Figure 6]FIG. 6 is a partial cross-sectional schematic view showing the configuration of a silicon carbide semiconductor device according to the fourth embodiment. [Figure 7] FIG. 7 is a longitudinal cross-sectional schematic view taken along line VII-VII of FIG. 6. [Figure 8] FIG. 8 is a longitudinal cross-sectional schematic view taken along line VIII-VIII of FIG. 6. [Figure 9] FIG. 9 is a longitudinal cross-sectional schematic view showing the configuration of a silicon carbide semiconductor device according to the fifth embodiment. [Figure 10] FIG. 10 is a longitudinal cross-sectional schematic view showing the configuration of a silicon carbide semiconductor device according to the sixth embodiment. [Figure 11] FIG. 11 is a diagram showing the breakdown voltage simulation results. [Embodiments for Carrying Out the Invention]

[0006] [Problems to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide semiconductor device capable of improving reliability. [Effects of the Present Disclosure] According to the present disclosure, a silicon carbide semiconductor device capable of improving reliability can be provided. [Description of Embodiments of the Present Disclosure] First, the embodiments of the present disclosure will be listed and described. In the crystallographic description of this specification, individual orientations are indicated by [], collective orientations are indicated by <>, individual planes are indicated by (), and collective planes are indicated by {}. That a crystallographic index is negative is usually expressed by attaching "-" (bar) above the number, but in this specification, a negative crystallographic index is expressed by attaching a negative sign before the number.

[0007] (1) The silicon carbide semiconductor device 100 according to this disclosure comprises a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The active region IR is provided on a part of the first main surface 1 of the substrate 90. The peripheral region OR is provided on the substrate 90 and surrounds the active region IR in a plan view. The first electrode 61 is provided on the second main surface 2 of the substrate 90 that is opposite the first main surface 1. The active region IR includes a first superjunction layer 10, an element layer 40, and a second electrode 62. The first superjunction layer 10 is provided above the substrate 90 and alternately has a first region 41 of a first conductivity type and a second region 42 of a second conductivity type. The element layer 40 is provided above the first superjunction layer 10. The second electrode 62 is provided on the element layer 40. The peripheral region OR includes a second superjunction layer 20, a termination layer 50, and an insulating layer 7. The second superjunction layer 20 is provided above the substrate 90 and alternately has a third region 43 of the first conductivity type and a fourth region 44 of the second conductivity type. The termination layer 50 is provided in contact with the second superjunction layer 20 and alternately has a fifth region 45 of the second conductivity type and a sixth region 46 of the second conductivity type. The insulating layer 7 is in contact with the upper end surfaces of the fifth region 45 and the sixth region 46, respectively. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45, and is 68 times or less the impurity concentration of the fifth region 45.

[0008] (2) In the silicon carbide semiconductor device 100 according to (1) above, the impurity concentration in the sixth region 46 may be greater than the impurity concentration in the fourth region 44.

[0009] (3) In the silicon carbide semiconductor device 100 according to (1) or (2) above, the absolute value of the difference between the impurity concentration in the fifth region 45 and the impurity concentration in the sixth region 46 may be substantially equal to the sum of the impurity concentration in the third region 43 and the impurity concentration in the fourth region 44.

[0010] (4) In the silicon carbide semiconductor device 100 according to any of (1) to (3) above, the first distance D1 between the upper end surface of the element layer 40 and the interface between the element layer 40 and the first superjunction layer 10 may be greater than the second distance D2 between the upper end surface of the termination layer 50 and the interface between the termination layer 50 and the second superjunction layer 20.

[0011] (5) In a silicon carbide semiconductor device 100 according to any of (1) to (4) above, each of the first region 41 and the third region 43 may have a first portion 71 and a second portion 72 located between the first portion 71 and the substrate 90. Each of the second region 42 and the fourth region 44 may have a third portion 73 in contact with the first portion 71 and a fourth portion 74 in contact with the second portion 72 and located between the third portion 73 and the substrate 90. In a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the second portion 72 may be greater than the width of the first portion 71, the width of the fourth portion 74 may be less than the width of the third portion 73, the width of the first portion 71 may be less than the height of the first portion 71, and the width of the third portion 73 may be less than the height of the third portion 73. The impurity concentrations in the first part 71 and the third part 73 may be greater than the impurity concentrations in the second part 72 and the fourth part 74.

[0012] (6) In the silicon carbide semiconductor device 100 according to any of (1) to (5) above, the impurity concentration of the first region 41 and the third region 43 is 3 × 10 16 cm -3 The above 5 x 10 17 cm -3 The following may also be true: The impurity concentrations in the second region 42 and the fourth region 44 are 3 × 10⁻⁶. 16 cm -3 The above 5 x 10 17 cm -3 The following is also acceptable.

[0013] (7) In the silicon carbide semiconductor device 100 according to any of (1) to (6) above, a first buffer layer 12 of the first conductivity type may be provided between the first superjunction layer 10 and the substrate 90. A second buffer layer 52 of the first conductivity type may be provided between the second superjunction layer 20 and the substrate 90.

[0014] (8) In a silicon carbide semiconductor device 100 according to any of (1) to (7) above, the element layer 40 may include a first impurity region 14 having a first conductivity type, a second impurity region 23 in contact with the first impurity region 14 and having a second conductivity type, and a third impurity region 30 separated from the first impurity region 14 by the second impurity region 23 and having a first conductivity type. The element layer 40 may be provided with a trench 5 having a side surface 8 composed of the first impurity region 14, the second impurity region 23, and the third impurity region 30, and a bottom portion 9 connected to the side surface 8 and composed of the first impurity region 14. The first electrode 61 may be a source electrode. The second electrode 62 may be a drain electrode. A gate electrode 63 may be provided inside the trench 5.

[0015] (9) In a silicon carbide semiconductor device 100 according to any of (1) to (8) above, the first main surface 1 may be a {0001} surface or a surface inclined at an angle of 8° or less with respect to the {0001} surface. [Details of the embodiments of this disclosure] The embodiments of this disclosure are described below in detail. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description of them is not repeated.

[0016] (First Embodiment) First, the configuration of the silicon carbide semiconductor device 100 according to the first embodiment will be described. Figure 1 is a schematic longitudinal cross-sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0017] As shown in Figure 1, the silicon carbide semiconductor device 100 according to the first embodiment is a planar MOSFET. The silicon carbide semiconductor device 100 according to the first embodiment mainly comprises, for example, a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The first conductivity type is, for example, n-type. The substrate 90 contains n-type impurities that can impart n-type properties, such as N (nitrogen). The substrate 90 has a first main surface 1 and a second main surface 2. The second main surface 2 is opposite to the first main surface 1.

[0018] The substrate 90 is made of, for example, polytype 4H hexagonal silicon carbide. The first main surface 1 may be, for example, a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. Specifically, the first main surface 1 may be a (0001) plane or a plane inclined at an angle of 8° or less with respect to the (0001) plane. The first main surface 1 may be a (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane. The substrate 90 has a first substrate portion 11 and a second substrate portion 51.

[0019] The active region IR is provided on a part of the first main surface 1 of the substrate 90. The first main surface 1 has a first region 91 and a second region 92. The active region IR is located on the first region 91. The active region IR mainly includes a first buffer layer 12, a first superjunction layer 10, an element layer 40, a second electrode 62, a gate electrode 63, a gate insulating film 6, and a isolation insulating film 64. The first buffer layer 12 is located between the first superjunction layer 10 and the substrate 90. The first buffer layer 12 has, for example, an n-type (first conductivity type). The first buffer layer 12 contains an n-type impurity that can impart n-type properties, such as N (nitrogen). The first buffer layer 12 is in contact with the first region 91.

[0020] The first superjunction layer 10 is located above the substrate 90. The first superjunction layer 10 is in contact with, for example, the first buffer layer 12. The first superjunction layer 10 alternately comprises a first region 41 and a second region 42. The first region 41 and the second region 42 are arranged alternately, for example, along a direction parallel to the first main surface 1. In other words, the first region 41 and the second region 42 are arranged alternately, for example, along a direction intersecting the thickness direction of the substrate 90.

[0021] The first region 41 has an n-type (first conductivity type). The first region 41 contains n-type impurities that can impart n-type properties, such as N (nitrogen). The second region 42 has a p-type (second conductivity type). The second region 42 contains p-type impurities that can impart p-type properties, such as Al (aluminum).

[0022] The element layer 40 is provided above the first superjunction layer 10. The element layer 40 is, for example, a switching element. The element layer 40 has, for example, a first impurity region 14, a second impurity region 23, a third impurity region 30, and a fourth impurity region 24. The first impurity region 14 is, for example, a drift region. The first impurity region 14 has an n-type (first conductivity type). The first impurity region 14 contains, for example, an n-type impurity such as N (nitrogen) that can impart an n-type. The first impurity region 14 is in contact with the first region 41.

[0023] The second impurity region 23 is, for example, a body region. The second impurity region 23 is in contact with the first impurity region 14. The second impurity region 23 has a p-type (second conductivity type). The second impurity region 23 contains p-type impurities that can impart p-type properties, such as Al (aluminum). The second impurity region 23 is in contact with the first region 41 and the second region 42. The concentration of p-type impurities in the second impurity region 23 may be higher than the concentration of n-type impurities in the first impurity region 14.

[0024] The third impurity region 30 is, for example, the source region. The third impurity region 30 is separated from the first impurity region 14 by the second impurity region 23. The third impurity region 30 has an n-type (first conductivity type). The third impurity region 30 contains n-type impurities that can impart n-type, such as P (phosphorus). The concentration of n-type impurities contained in the third impurity region 30 may be higher than the concentration of p-type impurities contained in the second impurity region 23.

[0025] The fourth impurity region 24 is, for example, a contact region. The fourth impurity region 24 is in contact with the second impurity region 23 and the third impurity region 30. The fourth impurity region 24 has a p-type (second conductivity type). The fourth impurity region 24 contains a p-type impurity that can impart p-type properties, such as Al (aluminum). The concentration of the p-type impurity contained in the fourth impurity region 24 may be higher than the concentration of the p-type impurity contained in the second impurity region 23.

[0026] The gate insulating film 6 is provided on the element layer 40. The gate insulating film 6 is made of, for example, silicon dioxide. The gate insulating film 6 is in contact with, for example, the first impurity region 14, the second impurity region 23, and the third impurity region 30. A channel can be formed in the second impurity region 23 that is in contact with the gate insulating film 6.

[0027] The gate electrode 63 is provided on the gate insulating film 6. The gate electrode 63 is in contact with the gate insulating film 6. The gate electrode 63 is made of a conductor such as polysilicon doped with impurities.

[0028] The second electrode 62 is, for example, a source electrode. The second electrode 62 is provided on the element layer 40. The second electrode 62 is in contact with the third impurity region 30 and the fourth impurity region 24. The second electrode 62 may cover the isolation insulating film 64.

[0029] The isolation insulating film 64 is provided so as to cover the gate electrode 63. The isolation insulating film 64 is in contact with both the gate electrode 63 and the gate insulating film 6. The isolation insulating film 64 is made of, for example, an NSG (None-doped Silicate Glass) film or a PSG (Phosphorus Silicate Glass) film. The isolation insulating film 64 electrically insulates the gate electrode 63 from the second electrode 62.

[0030] The first electrode 61 is, for example, a drain electrode. The first electrode 61 is provided on the second main surface 2 of the substrate 90. The second main surface 2 has a third area 93 and a fourth area 94. The third area 93 is on the opposite side of the first area 91. The fourth area 94 is on the opposite side of the second area 92. The first electrode 61 is in contact with each of the third area 93 and the fourth area 94.

[0031] The peripheral region OR is provided on the substrate 90. The peripheral region OR is located on the second area 92 of the first main surface 1. In a plan view, the peripheral region OR surrounds the active region IR. The plan view is the field of view of the silicon carbide semiconductor device 100 in a direction perpendicular to the first main surface 1. The peripheral region OR mainly includes the second buffer layer 52, the second superjunction layer 20, the termination layer 50, and the insulating layer 7.

[0032] The second buffer layer 52 is located between the second superjunction layer 20 and the substrate 90. The second buffer layer 52 has, for example, an n-type (first conductivity type). The second buffer layer 52 contains n-type impurities that can impart n-type properties, such as N (nitrogen). The second buffer layer 52 is in contact with the second region 92 of the first main surface 1. The second buffer layer 52 is electrically connected to the first buffer layer 12.

[0033] The second superjunction layer 20 is located above the substrate 90. The second superjunction layer 20 is in contact with, for example, the second buffer layer 52. The second superjunction layer 20 alternately comprises a third region 43 and a fourth region 44. The third region 43 and the fourth region 44 are arranged alternately, for example, along a direction parallel to the first main surface 1. In other words, the third region 43 and the fourth region 44 are arranged alternately, for example, along a direction intersecting the thickness direction of the substrate 90. The arrangement direction of the third region 43 and the fourth region 44 is the same as the arrangement direction of the first region 41 and the second region 42.

[0034] The third region 43 has an n-type (first conductivity type). The third region 43 contains n-type impurities that can impart n-type properties, such as N (nitrogen). The fourth region 44 has a p-type (second conductivity type). The fourth region 44 contains p-type impurities that can impart p-type properties, such as Al (aluminum).

[0035] The termination layer 50 is provided in contact with the second superjunction layer 20. The termination layer 50 alternately has a fifth region 45 and a sixth region 46. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The fifth region 45 is in contact with the third region 43. The sixth region 46 is in contact with the fourth region 44. The fifth region 45 and the sixth region 46 are arranged alternately, for example, along a direction parallel to the first main surface 1. From another point of view, the fifth region 45 and the sixth region 46 are arranged alternately, for example, along a direction intersecting the thickness direction of the substrate 90.

[0036] Each of the fifth region 45 and the sixth region 46 has a p-type (second conductivity type). Each of the fifth region 45 and the sixth region 46 contains a p-type impurity capable of imparting p-type, such as Al (aluminum). The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45 and is not more than 68 times the impurity concentration of the fifth region 45. The lower limit of the impurity concentration of the sixth region 46 is not particularly limited, but may be, for example, 1.09 times or more, or 1.58 times or more, the impurity concentration of the fifth region 45. The upper limit of the impurity region of the sixth region 46 is not particularly limited, but may be, for example, 20 times or less, or 33.3 times or less, or 55 times or less, the impurity concentration of the fifth region 45.

[0037] The fifth region 45 is formed, for example, by implanting a p-type impurity into the third region 43. Similarly, the sixth region 46 is formed, for example, by implanting a p-type impurity into the fourth region 44. In this case, the impurity concentration of the sixth region 46 is greater than the impurity concentration of the fourth region 44. The absolute value of the difference between the impurity concentration of the fifth region 45 and the impurity concentration of the sixth region 46 may be substantially equal to the sum of the impurity concentration of the third region 43 and the impurity concentration of the fourth region 44. Specifically, the value obtained by dividing the absolute value of the difference between the impurity concentration of the fifth region 45 and the impurity concentration of the sixth region 46 by the sum of the impurity concentration of the third region 43 and the impurity concentration of the fourth region 44 is, for example, 0.8 or more and 1.2 or less.

[0038] The impurity concentration of the first region 41 is substantially the same as the impurity concentration of the third region 43. The impurity concentration of each of the first region 41 and the third region 43 is, for example, 3×10 16 cm -3 or more and 5×10 17 cm -3 or less. The lower limit of the impurity concentration of each of the first region 41 and the third region 43 is not particularly limited, but may be, for example, 4×10 16 cm -3 or more, or 5×10 16 cm -3The above is also acceptable. The upper limits of the impurity concentrations in the first region 41 and the third region 43 are not particularly limited, but for example, 4 × 10 17 cm -3 The following is also acceptable, or 3 x 10 17 cm -3 The following is also acceptable.

[0039] The impurity concentration in the second region 42 is substantially the same as the impurity concentration in the fourth region 44. The impurity concentrations in the second region 42 and the fourth region 44 are, for example, 3 × 10⁻⁶. 16 cm -3 The above 5 x 10 17 cm -3 The following may also apply: The lower limits of the impurity concentrations in the second region 42 and the fourth region 44 are not particularly limited, but for example, 4 × 10 16 cm -3 It may be more than that, or 5 x 10 16 cm -3 The values ​​may be greater than or equal to the above. The upper limits of the impurity concentrations in the second region 42 and the fourth region 44 are not particularly limited, but for example, 4 × 10 17 cm -3 The following is also acceptable, or 3 x 10 17 cm -3 The following is also acceptable.

[0040] The insulating layer 7 is provided on the termination layer 50. The termination layer 50 has a third main surface 3. The third main surface 3 is in contact with the insulating layer 7. The third main surface 3 has a first upper end surface 3a and a second upper end surface 3b. The insulating layer 7 is in contact with the upper end surface (first upper end surface 3a) of the fifth region 45 and the upper end surface (second upper end surface 3b) of the sixth region 46, respectively. The fifth region 45 is located between the third region 43 and the insulating layer 7. The sixth region 46 is located between the fourth region 44 and the insulating layer 7. The insulating layer 7 is composed of an oxide film such as an LTO (Low Temperature Oxide) film, an HTO (High Temperature Oxide) film, an NSG film, or a PSG film. A thermal oxide film may be formed on the substrate of the insulating layer 7.

[0041] As shown in Figure 1, the first distance D1 between the upper end surface (fourth main surface 4) of the element layer 40 and the interface surface (first interface surface 81) between the element layer 40 and the first superjunction layer 10 is greater than the second distance D2 between the upper end surface (third main surface 3) of the termination layer 50 and the interface surface (second interface surface 82) between the termination layer 50 and the second superjunction layer 20. The value obtained by subtracting the second distance D2 from the first distance D1 may be 0.5 μm or more, or 1 μm or more. The thickness of the second superjunction layer 20 (fourth thickness T4) is greater than the thickness of the first superjunction layer 10 (third thickness T3).

[0042] (Second Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the second embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the second embodiment differs from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment mainly in that the peripheral region OR has multiple peripheral regions, while other aspects are the same as the configuration of the silicon carbide semiconductor device 100 according to the first embodiment. The following description will focus on the configurations that differ from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0043] Figure 2 is a schematic partial cross-sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the second embodiment. As shown in Figure 2, in a plan view, the peripheral region OR surrounds the active region IR. The peripheral region OR has a first peripheral region OR1, a second peripheral region OR2, and a third peripheral region OR3. In a plan view, the first peripheral region OR1 surrounds the active region IR. The first peripheral region OR1 is connected to the active region IR. In a plan view, the second peripheral region OR2 surrounds the first peripheral region OR1. The second peripheral region OR2 is connected to the first peripheral region OR1.

[0044] The silicon carbide semiconductor device 100 has a first superjunction layer 10 and a second superjunction layer 20. The first superjunction layer 10 has a first region 41 and a second region 42. The first region 41 and the second region 42 are arranged alternately along a first direction 101. In a plan view, the longitudinal direction of each of the first region 41 and the second region 42 is the second direction 102. In a plan view, the short direction of each of the first region 41 and the second region 42 is the first direction 101.

[0045] Each of the first direction 101 and the second direction 102 is parallel to the first principal plane 1. The first direction 101 is perpendicular to the second direction 102. The first direction 101 is, for example, the <1-100> direction. The second direction 102 is, for example, the <11-20> direction. The first direction 101 may also be, for example, the direction obtained by projecting the <1-100> direction onto the first principal plane 1. The second direction 102 may also be, for example, the direction obtained by projecting the <11-20> direction onto the first principal plane 1.

[0046] The second superjunction layer 20 has a third region 43 and a fourth region 44. The third region 43 and the fourth region 44 are arranged alternately along the first direction 101. In a plan view, the longitudinal direction of each of the third region 43 and the fourth region 44 is the second direction 102. In a plan view, the short direction of each of the third region 43 and the fourth region 44 is the first direction 101.

[0047] In a plan view, the third peripheral region OR3 surrounds the second peripheral region OR2. The third peripheral region OR3 is connected to the second peripheral region OR2. The third peripheral region OR3 has, for example, a channel stopper 66. In a plan view, the channel stopper 66 surrounds the second peripheral region OR2. The channel stopper 66 has, for example, an n-type (first conductivity type). The impurity concentration of the channel stopper 66 is, for example, greater than the impurity concentrations of the first region 41 and the third region 43, respectively.

[0048] As shown in Figure 2, the channel stopper 66 has a first channel stopper region 66a extending along a first direction 101 and a second channel stopper region 66b extending along a second direction 102. The second channel stopper region 66b may be provided along a third region 43. The first channel stopper region 66a may traverse the third region 43 and the fourth region 44. The first channel stopper region 66a may traverse the first region 41 and the second region 42.

[0049] Figure 3 is a schematic longitudinal cross-sectional view along the line III-III in Figure 2. As shown in Figure 3, the first peripheral region OR1 has a first termination layer 56. The first termination layer 56 has a fifth region 45 and a sixth region 46. The second peripheral region OR2 has a second termination layer 55. The second termination layer 55 has a seventh region 47 and an eighth region 48. The seventh region 47 corresponds to the third region 43, and the eighth region 48 corresponds to the fourth region 44. The seventh region 47 is in contact with the third region 43. The eighth region 48 is in contact with the fourth region 44. The insulating layer 7 is in contact with, for example, the first termination layer 56, the second termination layer 55, and the channel stopper 66.

[0050] The impurity concentration in the second termination layer 55 may be lower than that of the first termination layer 56. Specifically, the impurity concentration in the seventh region 47 may be lower than that of the fifth region 45. Similarly, the impurity concentration in the eighth region 48 may be lower than that of the sixth region 46. In the above, a two-stage JTE (Junction Termination Extension) having two termination layers has been described, but a three-stage JTE having three termination layers may also be adopted.

[0051] As shown in Figure 3, in a cross-section traversing the first region 41 and the second region 42, the height of the first region 41 in the third direction 103 may be greater than the width of the first region 41 in the first direction 101. Similarly, in a cross-section traversing the first region 41 and the second region 42, the height of the second region 42 in the third direction 103 may be greater than the width of the second region 42 in the first direction 101. The third direction 103 is a direction perpendicular to each of the first direction 101 and the second direction 102. The third direction 103 is, for example, <0001> It is a direction. The third direction 103 is, for example, <0001> The direction may be inclined with respect to the direction.

[0052] As shown in Figure 3, in a cross-section traversing the third region 43 and the fourth region 44, the height of the third region 43 in the third direction 103 may be greater than the width of the third region 43 in the first direction 101. Similarly, in a cross-section traversing the third region 43 and the fourth region 44, the height of the fourth region 44 in the third direction 103 may be greater than the width of the fourth region 44 in the first direction 101.

[0053] In a cross-section traversing the first region 41 and the third region 43, the height of the third region 43 in the third direction 103 may be greater than the height of the first region 41 in the third direction 103. Similarly, in a cross-section traversing the second region 42 and the fourth region 44, the height of the fourth region 44 in the third direction 103 may be greater than the height of the second region 42 in the third direction 103.

[0054] As shown in Figure 3, in a cross-sectional view, multiple gate electrodes 63 may be arranged along the first direction 101. Similarly, multiple first impurity regions 14, 23, 30, and 4th impurity regions 24 may be arranged along the first direction 101. The 4th impurity region 24 may penetrate the 3rd impurity region 30 and be in contact with the 1st region 41.

[0055] Figure 4 is a schematic longitudinal section along the line IV-IV in Figure 2. As shown in Figure 4, the peripheral region OR has multiple JTE regions. The first peripheral region OR1 has a first JTE region 53. The second peripheral region OR2 has a second JTE region 54. The second JTE region 54 is connected to the first JTE region 53. Each of the first JTE region 53 and the second JTE region 54 has, for example, a p-type impurity. The impurity concentration of the second JTE region 54 is, for example, smaller than the impurity concentration of the first JTE region 53. The value obtained by dividing the impurity concentration of the second JTE region 54 by the impurity concentration of the first JTE region 53 is, for example, 0.5.

[0056] As shown in Figure 4, the first region 41 may extend into the peripheral region OR along the second direction 102. In the peripheral region OR, the first region 41 may be in contact with the first JTE region 53, the second JTE region 54, and the channel stopper 66. In this embodiment, the case in which the peripheral region OR has two JTE regions has been described, but the number of JTE regions is not limited to two. For example, the peripheral region OR may have three or more JTE regions. In this case, the impurity concentration in the JTE region may decrease as it moves outward from the active region IR.

[0057] (Third embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the third embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the third embodiment differs from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment mainly in that the active region IR is a trench-type MOSFET, while other aspects are the same as the configuration of the silicon carbide semiconductor device 100 according to the first embodiment. The following description will focus on the configurations that differ from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0058] Figure 5 is a schematic longitudinal cross-sectional view showing the configuration of a silicon carbide semiconductor device 100 according to the third embodiment. As shown in Figure 5, a trench 5 is provided in the element layer 40. The shape of the trench 5 is, for example, V-shaped. The trench 5 is defined by a side surface 8 and a bottom surface 9. The side surface 8 is composed of a first impurity region 14, a second impurity region 23, and a third impurity region 30, respectively. The bottom surface 9 is connected to the side surface 8. The bottom surface 9 is composed of the first impurity region 14.

[0059] At least a portion of the gate insulating film 6 is provided, for example, inside the trench 5. The gate insulating film 6 is in contact with the first impurity region 14, the second impurity region 23, and the third impurity region 30 at its side surface 8. The gate insulating film 6 is in contact with the first impurity region 14 at its bottom 9. At least a portion of the gate electrode 63 is provided, for example, inside the trench 5.

[0060] (Fourth Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment differs from the configuration of the silicon carbide semiconductor device 100 according to the second embodiment mainly in that the active region IR is a trench-type MOSFET, while other aspects are the same as the configuration of the silicon carbide semiconductor device 100 according to the second embodiment. The following description will focus on the configurations that differ from the configuration of the silicon carbide semiconductor device 100 according to the second embodiment.

[0061] Figure 6 is a schematic partial cross-sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the fourth embodiment. As shown in Figure 6, in a plan view, the peripheral region OR surrounds the active region IR. The peripheral region OR has a first peripheral region OR1, a second peripheral region OR2, and a third peripheral region OR3. The channel stopper 66 has a first channel stopper region 66a extending along the first direction 101 and a second channel stopper region 66b extending along the second direction 102. The second channel stopper region 66b may be provided along the fourth region 44. The first channel stopper region 66a may traverse the third region 43 and the fourth region 44. The first channel stopper region 66a may traverse the first region 41 and the second region 42.

[0062] Figure 7 is a schematic longitudinal cross-sectional view along the line VII-VII in Figure 6. As shown in Figure 7, a trench 5 is provided in the element layer 40. The trench 5 is defined by a side surface 8 and a bottom surface 9. The side surface 8 is composed of a first impurity region 14, a second impurity region 23, and a third impurity region 30, respectively. The bottom surface 9 is connected to the side surface 8. The bottom surface 9 is composed of the first impurity region 14.

[0063] At least a portion of the gate insulating film 6 is provided, for example, inside the trench 5. The gate insulating film 6 is in contact with the first impurity region 14, the second impurity region 23, and the third impurity region 30 at its side surface 8. The gate insulating film 6 is in contact with the first impurity region at its bottom 9. At least a portion of the gate electrode 63 is provided, for example, inside the trench 5. At least a portion of the isolation insulating film 64 is provided, for example, inside the trench 5.

[0064] The active region IR may, for example, have a sixth impurity region 67. The sixth impurity region 67 may, for example, be p-type (second conductivity type). The sixth impurity region 67 faces the bottom 9 of the trench 5. The sixth impurity region 67 is in contact with, for example, the first region 41, the second region 42, and the first impurity region 14. In the third direction 103, the sixth impurity region 67 is located between the second region 42 and the first impurity region 14. In the first direction 101, the width of the sixth impurity region 67 may be greater than the width of the second region 42. In the first direction 101, the width of the sixth impurity region 67 may be greater than the width of the bottom 9 of the trench 5.

[0065] Figure 8 is a schematic longitudinal section along the line VIII-VIII in Figure 6. As shown in Figure 8, the sixth impurity region 67 may extend along the second direction 102. The width of the sixth impurity region 67 in the second direction 102 may be greater than the width of the sixth impurity region 67 in the first direction 101. Similarly, the first impurity region 14 may extend along the second direction 102. The width of the first impurity region 14 in the second direction 102 may be greater than the width of the first impurity region 14 in the first direction 101.

[0066] As shown in Figure 8, the second region 42 may extend into the peripheral region OR along the second direction 102. In the peripheral region OR, the second region 42 may be in contact with the first JTE region 53, the second JTE region 54, and the channel stopper 66.

[0067] (Fifth embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment differs from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment mainly in that the active region IR is a PN diode, and in other respects it is the same as the configuration of the silicon carbide semiconductor device 100 according to the first embodiment. The following description will focus on the configuration that differs from the configuration of the silicon carbide semiconductor device 100 according to the first embodiment.

[0068] Figure 9 is a schematic longitudinal cross-sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the fifth embodiment. As shown in Figure 9, the element layer 40 may be, for example, a rectifier element. The element layer 40 has, for example, a p-type (second conductivity type). The second electrode 62 is in contact with the element layer 40. The second electrode 62 is provided on the element layer 40. The element layer 40 is provided on the first superjunction layer 10. The element layer 40 is in contact with, for example, the first region 41 and the second region 42, respectively. The first electrode 61 is, for example, a cathode electrode. The second electrode 62 is, for example, an anode electrode.

[0069] (Sixth Embodiment) Next, the configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment will be described. The configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment differs from the configuration of the silicon carbide semiconductor device 100 according to the third embodiment mainly in that each of the first region 41 and the third region 43 has a first portion 71 and a second portion 72, and each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74. In other respects, it is the same as the configuration of the silicon carbide semiconductor device 100 according to the third embodiment. The following description will focus on the configuration that differs from the configuration of the silicon carbide semiconductor device 100 according to the third embodiment.

[0070] Figure 10 is a schematic longitudinal cross-sectional view showing the configuration of the silicon carbide semiconductor device 100 according to the sixth embodiment. As shown in Figure 10, each of the first region 41 and the third region 43 has a first portion 71 and a second portion 72. The second portion 72 is connected to the first portion 71. The second portion 72 is located between the first portion 71 and the substrate 90. The first portion 71 may be in contact with the first impurity region 14. The first portion 71 may be in contact with the fifth region 45. The second portion 72 may be in contact with the first buffer layer 12. The second portion 72 may be in contact with the second buffer layer 52.

[0071] As shown in Figure 10, each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74. The third portion 73 is in contact with the first portion 71. The fourth portion 74 is in contact with the second portion 72. The fourth portion 74 is connected to the third portion 73. The fourth portion 74 is located between the third portion 73 and the substrate 90. The third portion 73 may be in contact with the first impurity region 14. The third portion 73 may be in contact with the sixth region 46. The fourth portion 74 may be in contact with the first buffer layer 12. The fourth portion 74 may be in contact with the second buffer layer 52.

[0072] The third part 73 and the first part 71 are adjacent in the first direction 101. The third part 73 and the first part 71 are arranged alternately in the first direction 101. The fourth part 74 and the second part 72 are adjacent in the first direction 101. The fourth part 74 and the second part 72 are arranged alternately in the first direction 101.

[0073] The impurity concentration in Part 3 73 may be higher than the impurity concentration in Part 4 74. The impurity concentration in Part 1 71 is substantially the same as the impurity concentration in Part 2 72. The impurity concentration in Part 1 71 is substantially the same as the impurity concentration in Part 3 73. The impurity concentration in Part 4 74 may be lower than the impurity concentration in Part 2 72.

[0074] The impurity concentrations of the first part 71 and the third part 73 are, for example, 3 × 10 16 cm -3 The above 5 x 10 17 cm -3 The following may also be true: The lower limit of the impurity concentration in each of the first part 71 and the third part 73 is not particularly limited, but for example, 4 × 10 16 cm -3 It may be more than that, or 5 x 10 16 cm -3 The above may also be the case. The upper limits of the impurity concentrations in the first part 71 and the third part 73 are not particularly limited, but for example, 4 × 10 17 cm -3The following is also acceptable, or 3 x 10 17 cm -3 The following is also acceptable.

[0075] As shown in Figure 10, in a cross-section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the second portion 72 is greater than the width of the first portion 71 (first width W1). The width of the second portion 72 may increase monotonically as one moves from the first portion 71 toward the first main surface 1. The width of the second portion 72 in contact with the buffer layer 49 (second width W2) is greater than the first width W1.

[0076] As shown in Figure 10, in a cross-section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the fourth portion 74 is smaller than the width of the third portion 73 (third width W3). The width of the fourth portion 74 may decrease monotonically as one moves from the third portion 73 toward the first main surface 1. The width of the fourth portion 74 in contact with the buffer layer 49 (fourth width W4) is smaller than the third width W3.

[0077] As shown in Figure 10, the sum of the widths of the first section 71 (first width W1) and the third section 73 (third width W3) is, for example, between 0.5 μm and 4 μm. The sum of the widths of the first section 71 (first width W1) and the third section 73 (third width W3) is the respective pitch P of the first superjunction layer 10 and the second superjunction layer 20. The respective heights of the first region 41 and the second region 42 (third height) are, for example, 2 μm or more.

[0078] As shown in Figure 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the first portion 71 (first width W1) may be less than the height of the first portion 71 (first height T1). The height of the first portion 71 (first height T1) may be greater than the height of the second portion 72 (second height T2).

[0079] As shown in Figure 10, in a cross section perpendicular to the second main surface 2 and parallel to the direction from the first region 41 to the second region 42, the width of the third portion 73 (third width W3) may be smaller than the height of the third portion 73 (first height T1). The height of the third portion 73 (first height T1) may be larger than the height of the fourth portion 74 (second height T2).

[0080] Next, we will explain the method for forming the superjunction layer. First, a buffer layer 49 is formed on the substrate 90. The buffer layer 49 is formed, for example, by epitaxial growth. Next, a first region 41 and a third region 43 are formed on the buffer layer 49. The first region 41 and the third region 43 are formed, for example, by epitaxial growth. Each of the buffer layer 49, the first region 41, and the third region 43 has an n-type (first conductivity type). The impurity concentration of the buffer layer 49 may be the same as the impurity concentration of each of the first region 41 and the third region 43, or it may be lower than the impurity concentration of each of the first region 41 and the third region 43. Next, a mask layer (not shown) is formed on the first region 41 and the third region 43.

[0081] Next, a channeling ion implantation process is performed. Specifically, with a mask layer placed on the first region 41 and the third region 43, impurity ions capable of imparting p-type (second conductivity type), such as aluminum, are implanted into the first region 41 and the third region 43. The implantation energy is, for example, 960 keV. The implantation temperature is, for example, room temperature. As a result, a second region 42 is formed in a part of the first region 41. The second region 42 is spaced apart in the first direction 101. Similarly, a fourth region 44 is formed in a part of the third region 43. The fourth region 44 is spaced apart in the first direction 101. Thus, a first superjunction layer 10 in which the first region 41 and the second region 42 are alternately arranged, and a second superjunction layer 20 in which the third region 43 and the fourth region 44 are alternately arranged are formed (see Figure 10).

[0082] In the channeling ion implantation process, the crystal axis of silicon carbide is <0001> Impurity ions are implanted in a direction substantially parallel to the direction. The direction of impurity ion implantation is, <0001> The direction may be inclined by an angle of, for example, 0.5° or less. Specifically, the direction of impurity ion implantation may be a direction in which the third direction 103 is inclined in the off direction. The off direction may be, for example, the first direction 101 or the second direction 102. This reduces scattering between impurity ions and silicon carbide, allowing impurity ions to be implanted to greater depths. As a result, a second region 42 and a fourth region 44 are formed (see Figure 10). Each of the second region 42 and the fourth region 44 has a third portion 73 and a fourth portion 74. The width of the fourth portion 74 is formed to be smaller than the width of the third portion 73.

[0083] Next, we will explain how to measure the concentrations of p-type and n-type impurities in each impurity region.

[0084] The concentrations of p-type and n-type impurities in each impurity region can be measured using SIMS (Secondary Ion Mass Spectrometry). The measuring instrument is, for example, a Cameca secondary ion mass spectrometer. The measurement pitch is, for example, 0.01 μm. When the n-type impurity to be detected is nitrogen, the primary ion beam is cesium (Cs). The primary ion energy is 14.5 keV. The secondary ion polarity is negative. When the p-type impurity to be detected is aluminum or boron, the primary ion beam is oxygen (O2). The primary ion energy is 8 keV. The secondary ion polarity is positive.

[0085] Next, we will explain how to distinguish between p-type and n-type regions. Scanning Capacitance Microscope (SCM) is used to distinguish between p-type and n-type regions. The measuring device is, for example, the NanoScope IV manufactured by Bruker AXS. SCM is a method for visualizing the carrier concentration distribution in a semiconductor. Specifically, a metal-coated silicon probe is used to scan the surface of the sample. A high-frequency voltage is applied to the sample during this process. This excites the majority carriers and modulates the capacitance of the system. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V. Scanning Nonlinear Dielectric Microscopy (SNDM) or Scanning Microwave Microscopy (SMM) may also be used to distinguish between p-type and n-type regions.

[0086] In the above explanation, it was assumed that the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type is n-type. The impurity concentration in the impurity region having n-type is the concentration of n-type impurities. The impurity concentration in the impurity region having p-type is the concentration of p-type impurities.

[0087] Next, the effects and advantages of the silicon carbide semiconductor device 100 according to the above embodiment will be described. Silicon has a lower dielectric breakdown strength than silicon dioxide. Therefore, in the case of Si-MOSFETs, reliability can be improved by designing the MOSFET so that the electric field strength in the peripheral region OR is higher than the electric field strength in the active region IR. On the other hand, silicon carbide has a higher dielectric breakdown strength than silicon dioxide. Therefore, in the case of SiC-MOSFETs, if the MOSFET is designed so that the electric field strength in the peripheral region OR is higher than the electric field strength in the active region IR, the insulating layer 7 will break down before the semiconductor layer, making it difficult to sufficiently improve reliability.

[0088] Therefore, the inventors conceived a design concept that suppresses the concentration of the electric field at the interface between the semiconductor layer and the insulating layer 7 by lowering the electric field strength of the peripheral region OR, and actively generates an avalanche in the active region IR by increasing the electric field strength of the active region IR.

[0089] The inventors diligently studied specific structures to realize the design concept described above. As a result, they found that by adopting the following structure for the silicon carbide semiconductor device 100, the reliability of the silicon carbide semiconductor device 100 can be improved compared to a structure that concentrates the electric field in the surrounding OR region.

[0090] Specifically, the silicon carbide semiconductor device 100 according to this disclosure comprises a substrate 90, an active region IR, a peripheral region OR, and a first electrode 61. The substrate 90 is made of a silicon carbide semiconductor of a first conductivity type. The active region IR is provided on a part of the first main surface 1 of the substrate 90. The peripheral region OR is provided on the substrate 90 and surrounds the active region IR in a plan view. The first electrode 61 is provided on the second main surface 2 of the substrate 90, which is opposite the first main surface 1. The active region IR includes a first superjunction layer 10, an element layer 40, and a second electrode 62. The first superjunction layer 10 is provided above the substrate 90 and alternately has a first region 41 of a first conductivity type and a second region 42 of a second conductivity type. The element layer 40 is provided above the first superjunction layer 10. The second electrode 62 is provided on the element layer 40. The peripheral region OR includes a second superjunction layer 20, a termination layer 50, and an insulating layer 7. The second superjunction layer 20 is provided above the substrate 90 and alternately has a third region 43 of the first conductivity type and a fourth region 44 of the second conductivity type. The termination layer 50 is provided in contact with the second superjunction layer 20 and alternately has a fifth region 45 of the second conductivity type and a sixth region 46 of the second conductivity type. The insulating layer 7 is in contact with the upper end surfaces of the fifth region 45 and the sixth region 46, respectively. The fifth region 45 is provided corresponding to the third region 43, and the sixth region 46 is provided corresponding to the fourth region 44. The impurity concentration of the sixth region 46 is greater than the impurity concentration of the fifth region 45, and is 68 times or less the impurity concentration of the fifth region 45. This improves the reliability of the silicon carbide semiconductor device 100. [Examples]

[0091] To investigate the relationship between the impurity concentration in the 6th region 46 relative to the impurity concentration in the 5th region 45 and the reliability of the silicon carbide semiconductor device 100, a breakdown voltage simulation was performed. First, simulation models with different impurity concentrations in the superjunction layer (1200V design elements) were created. As shown in Table 1, in the first simulation model (conditions 2 to 8), the impurity concentration in the superjunction layer (in other words, the impurity concentrations in the 3rd region 43 and the 4th region 44: see Figure 1) was 1 × 10⁻¹⁶. 17 cm -3 In the second simulation model (condition 1), the impurity concentration in the superjunction layer was 3 × 10⁻⁶. 16 cm -3 The thickness of the superjunction layer was set to 7.5 μm. The same concentration of p-type impurities was added to each of the third region 43 and the fourth region 44 to form the fifth region 45 and the sixth region 46, respectively.

[0092] [Table 1]

[0093] As shown in Table 1, in the first simulation model, the value obtained by dividing the impurity concentration in the sixth region 46 by the impurity concentration in the fifth region 45 was set to a range of 1.48 to 67.7. In the second simulation model, the value obtained by dividing the impurity concentration in the sixth region 46 by the impurity concentration in the fifth region 45 was set to 1.11.

[0094] Figure 11 shows the results of the withstand voltage simulation. As shown in Figure 11 and Table 1, it was shown that a high withstand voltage of approximately 1.2kV or more can be achieved when the impurity concentration in the sixth region 46 is in the range of 1.11 times to 67.7 times the impurity concentration in the fifth region 45. In particular, it was shown that an even higher withstand voltage can be achieved when the impurity concentration in the sixth region 46 is greater than 1.48 times and less than 33.3 times the impurity concentration in the fifth region 45.

[0095] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than the foregoing description and is intended to include the meaning of equivalents of the claims and all modifications within the scope. [Explanation of Symbols]

[0096] 1 First main surface, 2 Second main surface, 3 Third main surface, 3a First upper surface, 3b Second upper surface, 4 Fourth main surface, 5 Trench, 6 Gate insulating film, 7 Insulating layer, 8 Side surface, 9 Bottom, 10 First superjunction layer, 11 First substrate portion, 12 First buffer layer, 14 First impurity region, 20 Second superjunction layer, 23 Second impurity region, 24 Fourth impurity region, 30 Third impurity region, 40 Element layer, 41 First region, 42 Second region, 43 Third region, 44 Fourth region, 45 Fifth region, 46 Sixth region, 47 Seventh region, 48 Eighth region, 49 Buffer layer, 50 Termination layer, 51 Second substrate portion, 52 Second buffer layer, 53 First JTE region, 54 Second JTE region, 55 Second termination layer, 56 First termination layer, 61 First electrode, 62 63 Second electrode, 64 Gate electrode, 64 Separating insulating film, 66 Channel stopper, 66a First channel stopper region, 66b Second channel stopper region, 67 Sixth impurity region, 71 First part, 72 Second part, 73 Third part, 74 Fourth part, 81 First interface, 82 Second interface, 90 Substrate, 91 First area, 92 Second area, 93 Third area, 94 Fourth area, 100 Silicon carbide semiconductor device, 101 First direction, 102 Second direction, 103 Third direction, D1 First distance, D2 Second distance, IR Active region, OR Peripheral region, OR1 First peripheral region, OR2 Second peripheral region, OR3 Third peripheral region, P Pitch, T1 First height, T2 Second height, T3 Third thickness, T4 Fourth thickness, W1 First width, W2 Second width, W3 Third width, W4 Fourth width.

Claims

1. A substrate made of a first-conductivity type silicon carbide semiconductor, An active region provided in the first area of ​​the first main surface of the substrate, A peripheral region is provided in the second area of ​​the first main surface of the substrate, and surrounds the active region in a plan view, The substrate comprises a first electrode provided on a second main surface facing the first main surface, The active region is, A first superjunction layer is provided above the substrate and has alternating first regions of the first conductivity type and second regions of the second conductivity type, An element layer provided above the first superjunction layer, The element layer includes a second electrode provided on the element layer, The aforementioned peripheral region is A second superjunction layer is provided above the substrate and has alternating third regions of the first conductivity type and fourth regions of the second conductivity type, A termination layer provided in contact with the second superjunction layer, having alternating fifth regions and sixth regions of the second conductivity type, The insulating layer includes an insulating layer in contact with the upper end surface of the fifth region and the upper end surface of the sixth region, The fifth region is provided in correspondence with the third region, and the sixth region is provided in correspondence with the fourth region. Each of the first and third regions has a first portion and a second portion located between the first portion and the substrate. Each of the second and fourth regions has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the substrate. In a cross-section perpendicular to the second main surface and parallel to the direction from the first region toward the second region, The width of the second part is greater than the width of the first part. The width of the fourth portion is smaller than the width of the third portion. The width of the first part is less than the height of the first part. The width of the third portion is smaller than the height of the third portion. A silicon carbide semiconductor device wherein the impurity concentrations in the first and third parts are greater than the impurity concentrations in the second and fourth parts.

2. The silicon carbide semiconductor device according to claim 1, wherein the impurity concentration in the sixth region is greater than the impurity concentration in the fourth region.

3. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the absolute value of the difference between the effective impurity concentration of the fifth region and the effective impurity concentration of the sixth region, when divided by the sum of the effective impurity concentration of the third region and the effective impurity concentration of the fourth region, is 0.8 or more and 1.2 or less.

4. The impurity concentrations in the first and third regions are 3 × 10⁻⁶ 16 cm -3 The above 5 x 10 17 cm -3 The following: The impurity concentrations in the second and fourth regions are 3 × 10⁻⁶ 16 cm -3 The above 5 x 10 17 cm -3 The silicon carbide semiconductor device according to any one of claims 1 to 3, which is as follows:

5. A first buffer layer of the first conductivity type is provided between the first superjunction layer and the first region. A silicon carbide semiconductor device according to any one of claims 1 to 4, wherein a second buffer layer of the first conductivity type is provided between the second superjunction layer and the second region.

6. The element layer includes a first impurity region having the first conductivity type, a second impurity region in contact with the first impurity region and having the second conductivity type, and a third impurity region separated from the first impurity region by the second impurity region and having the first conductivity type. The element layer is provided with a trench having a side surface composed of the first impurity region, the second impurity region, and the third impurity region, and a bottom portion that is connected to the side surface and composed of the first impurity region. The first electrode is the drain electrode, and the second electrode is the source electrode. A silicon carbide semiconductor device according to any one of claims 1 to 5, wherein a gate electrode is provided inside the trench.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the first main surface is a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane.

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