Semiconductor equipment

Abstract

To provide a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics), and also to provide the semiconductor device including the transistor with high reliability.SOLUTION: A semiconductor device includes a dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a channel width direction of the transistor, a side surface of each of the first and second gate electrodes is at an outer side of a side surface of the oxide semiconductor film. The first or second gate electrode faces the side surface of the oxide semiconductor film via a gate insulating film provided between the first or second gate electrode and the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device equipped with a transistor having an oxide semiconductor film and a method for manufacturing the same. [Background technology]

[0002] A transistor (thin film transistor (TFT)) is made using a semiconductor thin film formed on a substrate. The technology that makes up (also known as) is attracting attention. This transistor is used in integrated circuits (ICs) and graphics. It is widely applied in electronic devices such as image display devices (display devices). Suitable for transistors. Silicon-based semiconductor materials are widely known as usable semiconductor thin films, but other materials Oxide semiconductors are attracting attention as a result.

[0003] For example, indium (In), gallium (Ga), and sub-dioxide are used as the active layer of a transistor. A transistor using an oxide semiconductor containing lead (Zn) has been disclosed (see Patent Document 1). . ) .

[0004] Furthermore, a technology that improves carrier mobility by creating a stacked structure for oxide semiconductor layers. This has been disclosed (see Patent Documents 2 and 3). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Patent Document 2] Japanese Patent Publication No. 2011-138934 [Patent Document 3] Japanese Patent Publication No. 2011-124360 [Overview of the project] [Problems that the invention aims to solve]

[0006] One aspect of the present invention relates to electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.) To provide a semiconductor device having excellent transistors. Or, a highly reliable transistor. To provide a semiconductor device that is tightly bound. [Means for solving the problem]

[0007] One aspect of the present invention is a configuration in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. A dual-gate transistor that can be operated in the channel width direction of the transistor. In this configuration, the sides of the first gate electrode and the second gate electrode are, respectively, the sides of the oxide semiconductor film. This is a semiconductor device located outside the surface.

[0008] One aspect of the present invention is a configuration in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. A dual-gate transistor that can be subjected to stress time In a log-log graph showing the fluctuation amount of the threshold voltage, the interval between the logarithmic scales of the horizontal and vertical axes is Equally, the power approximation line of the variation in threshold voltage with respect to stress time, and the variation in threshold voltage The angle between the velocity and the straight line at 0V is less than 30°, and the stress time is 0.1 hours. This semiconductor device has a threshold voltage fluctuation of less than 0.2V. This refers to the duration for which a load such as voltage or temperature is applied to a transistor.

[0009] One aspect of the present invention is a configuration in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. A dual-gate transistor that can be subjected to stress time In a log-log graph showing the fluctuation amount of the threshold voltage, the interval between the logarithmic scales of the horizontal and vertical axes is Equally, the slope of the power approximation line of the threshold voltage fluctuation is 0.5 or less, and the stress time This semiconductor device has a threshold voltage fluctuation of less than 0.2V over a period of 0.1 hours.

[0010] Note that the first gate electrode or the second gate electrode is the first gate electrode or the second gate electrode The gate insulating film provided between the gate electrode and the oxide semiconductor film allows the oxide semiconductor film to penetrate. It may also face the side.

[0011] Furthermore, the first gate electrode and the second gate electrode are connected via an insulating film on the outside of the oxide semiconductor film. You may then face them.

[0012] Furthermore, the above transistor can be a channel etch structure transistor. Furthermore, the distance between a pair of electrodes on the oxide semiconductor film shall be 1 μm or more and less than 4 μm. It is possible.

[0013] Oxide semiconductor films are made of In, M (where M is Al, Ga, Y, Zr, La, Ce, or Nd ), and an oxide having Zn, wherein the atomic ratio of In is greater than or equal to the atomic ratio of M. It can be formed with a taring target. [Effects of the Invention]

[0014] According to one aspect of the present invention, electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.) are obtained. ) can provide a semiconductor device having excellent transistors. Or, the present invention In one embodiment, a semiconductor device having a highly reliable transistor can be provided. [Brief explanation of the drawing]

[0015] [Figure 1] This is a diagram illustrating the reliability of transistors. [Figure 2] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 3] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 4] This is a cross-sectional view illustrating one method for fabricating transistors. [Figure 5] This is a cross-sectional view illustrating one form of transistor. [Figure 6] This is a cross-sectional view illustrating one form of transistor. [Figure 7] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 8] This is a diagram illustrating the band structure of a transistor. [Figure 9] These are block diagrams and circuit diagrams illustrating one form of a semiconductor device. [Figure 10] This is a top view illustrating one form of a semiconductor device. [Figure 11] This is a cross-sectional view illustrating one form of a semiconductor device. [Figure 12] This is a cross-sectional view illustrating one form of a method for manufacturing semiconductor devices. [Figure 13] This is a cross-sectional view illustrating one form of a method for manufacturing semiconductor devices. [Figure 14] This is a cross-sectional view illustrating one form of a method for manufacturing semiconductor devices. [Figure 15] This is a cross-sectional view illustrating one form of a method for manufacturing semiconductor devices. [Figure 16] This is a cross-sectional view illustrating one form of a method for manufacturing semiconductor devices. [Figure 17] This figure shows the micro-electron diffraction pattern of an oxide semiconductor. [Figure 18] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 19] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 20] This is a diagram illustrating the Vg-Id characteristics of a transistor. [Figure 21]This diagram illustrates the Vg-Id characteristics of a transistor after GBT testing. [Figure 22] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 23] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 24] These are a top view and a cross-sectional view illustrating one form of transistor. [Figure 25] This diagram illustrates the ΔVth of a transistor as a function of stress time. [Figure 26] This is a cross-sectional view illustrating the structure of a transistor. [Figure 27] This diagram illustrates the results of the current-voltage curve calculation. [Figure 28] This diagram illustrates the results of calculating the potential of a transistor. [Figure 29] This is a diagram illustrating the model. [Figure 30] This is a diagram illustrating the model. [Figure 31] This diagram illustrates the results of the current-voltage curve calculation. [Figure 32] This is a cross-sectional view illustrating the structure of a transistor. [Modes for carrying out the invention]

[0016] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The present invention is not limited to the following description, and its form and scope may not depart from the spirit and scope of the present invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention The following embodiments and examples are not to be interpreted as being limited to their descriptions. In the embodiments and examples described below, parts that are the same or have similar functions In some cases, the same reference numeral or hatch pattern is used in common across different drawings, and the repetition of this pattern is used. I will omit the explanation of the counter-argument.

[0017] In each figure described herein, the size, film thickness, or region of each component is as follows: It may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. stomach.

[0018] Furthermore, the terms "first," "second," "third," etc. used in this specification are used to avoid confusion of constituent elements. This is a selection and not a numerical limit. Therefore, for example, "the first" This can be explained by substituting "the second" or "the third" as appropriate.

[0019] Furthermore, the functions of "source" and "drain" are used in situations where the direction of current changes during circuit operation. In this specification, "sauce" and "dressing" may be used interchangeably. The term "in" may be used interchangeably.

[0020] Furthermore, voltage refers to the potential difference between two points, while electric potential refers to the electrostatic field at a given point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge within a given object. Furthermore, generally speaking, the potential difference between the potential at a certain point and a reference potential (for example, the ground potential) This is simply called electric potential or voltage, and the terms electric potential and voltage are often used as synonyms. Therefore, unless otherwise specified in this specification, potential may be read as voltage. You may substitute "voltage" with "potential."

[0021] In this specification, when an etching process is performed after a photolithography process: The mask formed during the photolithography process shall be removed.

[0022] (Embodiment 1) In this embodiment, drawings illustrate a semiconductor device and a method for manufacturing the same, which are aspects of the present invention. Refer to the explanation.

[0023] Figures 2(A) to 2(C) show a top view and a cross-section of the transistor 50 of the semiconductor device. The diagram is shown. Transistor 50 shown in Figure 2 is a channel etch type transistor. Figure 2(A) is a top view of transistor 50, and Figure 2(B) is a top view of Figure 2(A) along the dashed line A- Figure 2(C) is a cross-sectional view between points B and C, and Figure 2(A) is a cross-sectional view between points C and D shown by the dashed line. Oh, in Figure 2(A), for clarity, the substrate 11, gate insulating film 17, oxide insulating film 23, The oxide insulating film 24, nitride insulating film 25, etc., have been omitted.

[0024] The transistor 50 shown in Figures 2(B) and 2(C) is a gate provided on the substrate 11. The electrode 15, the gate insulating film 17 formed on the substrate 11 and the gate electrode 15, and the gate insulating film A border film 17 is used to connect the oxide semiconductor film 18 that overlaps with the gate electrode 15, and the oxide semiconductor film 18 A pair of electrodes 21 and 22 in contact with the gate, a gate insulating film 17, an oxide semiconductor film 18, and a pair A protective film 26 on electrodes 21 and 22, and a gate that overlaps with the oxide semiconductor film 18 via the protective film 26. It has an electrode 29. The protective film 26 consists of an oxide insulating film 23, an oxide insulating film 24, and It has a nitride insulating film 25.

[0025] The transistor 50 shown in this embodiment has multiple gate electrodes, and between the gate electrodes This is a dual-gate transistor having an oxide semiconductor film 18. Figure 2(C) shows In the channel width direction shown, the end of the gate electrode 29 is located outside the oxide semiconductor film 18. Alternatively, in the channel width direction, the gate electrode 29 is oxide via the protective film 26. Facing the side surface of the semiconductor film 18, or in the channel width direction, the oxide semiconductor film 18 On the outside, gate electrodes 15 and 29 are connected to a gate insulating film 17 and a protective film 26. They face each other through this.

[0026] Figure 2(D) is an enlarged view of the dashed line 30 in Figure 2(C). Using Figure 2(D), the gate electric The positions of the electrode 15, the oxide semiconductor film 18, and the edges of the gate electrode 29 will be explained.

[0027] Here, as shown in Figure 2(D), the edges of the oxide semiconductor film 18 and the edges of the gate electrode 29 If the distance between the parts is d and the thickness of the protective film 26 is t, then the edges and the gate of the oxide semiconductor film 18 It is preferable that the distance d at the end of the electrode 29 is less than or equal to the thickness t of the protective film 26. The distance d between the end of the conductive film 18 and the end of the gate electrode 29 shall be less than or equal to the thickness t of the protective film 26. This makes it possible to influence the edge of the oxide semiconductor film 18 with the electric field of the gate electrode 29. Yes, the entire oxide semiconductor film 18, including its edges, can function as a channel.

[0028] At the edges of oxide semiconductor films processed by etching, etc., damage during processing occurs. As more defects are formed, the area becomes contaminated with impurities and other contaminants. Therefore, electric fields and other elements When a trace is applied, the edges of the oxide semiconductor film become more easily activated, and n-type (Low resistance) is likely to occur. Therefore, in this embodiment, the oxide semiconductor overlaps with the gate electrode 15. The ends of the conductive film 18 are more likely to become n-shaped. These n-shaped ends become a pair of electrodes. If it is placed between 21 and 22, that region becomes a carrier path, a parasitic channel. A layer is formed. However, as shown in Figure 2(C), a layer forms on the outside of the oxide semiconductor film 18. The end of the electrode 29 is located there, and due to the influence of the electric field of the tetrahydroelectrode 29, the oxide semiconductor The development of parasitic channels on or near the side of the body membrane 18 is suppressed. As a result, A transistor with excellent electrical characteristics exhibits a steep rise in drain current at key voltages. Yes.

[0029] Furthermore, by providing gate electrode 15 and gate electrode 29, the gate electrode 15 and By setting the gate electrode 29 to the same potential, the carrier flow region in the oxide semiconductor film 18 As the region becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, As the on-current of the transistor 50 increases, the field-effect mobility also increases.

[0030] Furthermore, by having gate electrodes 15 and 29, each of them is protected from the external electric field. Because it has the function of shielding, it is installed between the substrate 11 and the gate electrode 15, on the gate electrode 29. The charge of the charged particles, etc., does not affect the oxide semiconductor film 18. As a result, stress testing (For example, applying a negative charge to the gate - GBT (Gate Bias - Tempera The degradation of the stress test is suppressed, and the on-voltage at different drain voltages is also suppressed. This can suppress fluctuations in the rising voltage of the current. This effect is due to the gate electrode 1 This occurs when 5 and the gate electrode 29 are at the same potential or different potentials.

[0031] Note that the BT stress test is a type of accelerated test that shows the effects of long-term use. The characteristic changes (i.e., changes over time) of the ZISTA can be evaluated in a short time. In particular, BT S The change in the transistor's threshold voltage before and after the Tress test is used to examine reliability. This is an important indicator. The smaller the fluctuation in threshold voltage before and after the BT stress test, the better. Therefore, it can be said that it is a highly reliable transistor.

[0032] Furthermore, it has gate electrodes 15 and 29, and gate electrodes 15 and 29 By setting point 29 to the same potential, the amount of fluctuation in the threshold voltage is reduced. Therefore, multiple traps The variation in electrical characteristics in the inverter is also reduced at the same time.

[0033] Furthermore, transistor 50 is subjected to a positive charge applied to its gate before and after the +GBT stress test. The fluctuation amount of the threshold voltage is small.

[0034] In the transistor 50 shown in this embodiment, a positive charge is applied to the gate B The amount of change in threshold voltage (ΔVth) with respect to stress time before and after the T stress test. Figure 1 shows the power approximation line L1 representing the test time (stress time) and threshold voltage. When the fluctuations are plotted on a graph, the plotted values ​​can be approximated by a power approximation line. And that power approximation line becomes a straight line on a log-log graph. In Figure 1, Figure 1 is a log-log graph. The horizontal axis represents the logarithm of stress time, and the vertical axis represents the logarithm of the threshold voltage fluctuation. Furthermore, the stress test conditions included setting the substrate temperature to 60°C and the measurement environment to a darkroom (da). In an rk environment, apply +30V to the gate voltage and run for any time, for example, 1 hour. These are the conditions that apply stress to a transistor.

[0035] In Figure 1, on a log-log graph, the power approximation line L1 is a straight line, so the horizontal and vertical axes... When the intervals between several scale divisions are equal, the power approximation line L in the transistor 50 shown in this embodiment 1. A straight line when there is no change in threshold voltage with respect to stress time (ΔVth is 0V) That is, the angle θ with the straight line L2, which has a slope of 0 and is shown by the dashed line in Figure 1, is less than 30 degrees, or 25 degrees. It is less than 1 degree. Note that the intervals between the logarithmic scales of the horizontal and vertical axes are equal, for example, on the horizontal axis The interval between 0.01 hours and 0.1 hours, where the stress time increases tenfold, and ΔV on the vertical axis. This means that the intervals between 0.01V (where th is 10 times greater) and 0.1V are equal.

[0036] Furthermore, the smaller the angle θ, the smaller the fluctuation in threshold voltage due to aging. It is a highly reliable transistor.

[0037] Furthermore, in Figure 1, if the horizontal axis is x and the vertical axis is y, the power approximation line is shown by Equation 1. This is possible. Note that b and C are constants, and b corresponds to the slope of the power approximation line.

[0038]

number

[0039] The slope b of the power approximation line L1 in the transistor 50 shown in this embodiment is 0.5V / Δ when the stress duration is less than or equal to 0.4V / hr, or less than or equal to 0.1 hours. Vth is less than 0.2V or less than 0.5V.

[0040] The smaller the slope b of the power approximation line L1, the smaller the fluctuation in threshold voltage due to aging. It is a highly reliable transistor. Also, ΔVth at a stress time of 0.1 hours is The smaller the value, the more reliable the transistor is during the initial stages of operation. As a result, the power approximation line... The slope b of L1 is 0.5V / hr or less, or 0.4V / hr or less, and the stress Transitions where ΔVth is less than 0.2V or less than 0.5V at a time of 0.1 hours Sta is highly reliable.

[0041] Note that in Figure 2(A), the width of the gate electrode 15 per channel length is greater than the oxidation Although the width of the monocrystalline semiconductor film 18 is large, as shown in the transistor 51 in Figure 3(A), a channel The width of the gate electrode 15 can be made larger than the width of the oxide semiconductor film 18 in the longitudinal direction. This makes it possible to block light irradiation from the substrate 11 side with the gate electrode 15. Therefore, fluctuations in the electrical characteristics of transistor 51 can be suppressed. (See Figure 3(A)) Figure 3(B) is a top view of transistor 51, and Figure 3(A) shows the area between A and B indicated by the dashed line. This is a cross-sectional view; Figure 3(C) is a cross-sectional view between the dashed lines C and D in Figure 3(A).

[0042] In this embodiment, gate electrode 15 and gate electrode 29 are connected, and the same power However, gate electrode 15 and gate electrode 29 are not connected, and different potentials are indicated. It may be added.

[0043] The following describes the other configurations of transistor 50.

[0044] There are no major restrictions on the material of the substrate 11, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, saffron A wire substrate or the like may be used as the substrate 11. Alternatively, a simple silicon or silicon carbide may be used. Crystalline semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SO It is also possible to apply substrates such as I, and semiconductor elements are provided on these substrates. It may also be used as substrate 11. Note that if a glass substrate is used as substrate 11, the sixth Generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th generation Generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), 1st By using large-area substrates such as the 0th generation (2950mm x 3400mm), large-scale display devices can be created. It is possible to produce this.

[0045] Furthermore, a flexible substrate is used as the substrate 11, and the transistor 50 is directly mounted on the flexible substrate. It may be formed. Alternatively, a release layer may be provided between the substrate 11 and the transistor 50. The abscission layer separates from the substrate 11 after partially or completely completing the semiconductor device on it, and It can be used to transfer the image onto a substrate. In this case, the transistor 50 is a substrate with poor heat resistance. It can also be transferred to boards and flexible substrates.

[0046] The gate electrode 15 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tan. A metal element selected from gusten, or an alloy containing the aforementioned metal elements, or the aforementioned It can be formed using alloys that combine metallic elements. Also, manganese, zirconium, etc. A metallic element selected from one or more of the nium species may be used. Also, the gate electric element Pole 15 may be a single-layer structure or a multi-layer structure of two or more layers. For example, a silicon-containing Single-layer structure of luminium film, double-layer structure of aluminum film laminated on titanium film, titanium nitride A two-layer structure in which a titanium film is laminated on a film, and a two-layer structure in which a tungsten film is laminated on a titanium nitride film. A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. A two-layer structure in which a copper film is laminated on a titanium film, and an aluminum film on top of the titanium film. There are also three-layer structures, such as one in which layers are stacked and then a titanium film is formed on top of them. Furthermore, with aluminum, Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. A film of the extracted element, an alloy film combining multiple elements, or a nitride film may be used.

[0047] Furthermore, the gate electrode 15 contains indium tin oxide and indium acid containing tungsten oxide. Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide The substance contains titanium dioxide, indium tin oxide, indium zinc oxide, and silicon oxide. Transparent conductive materials such as indium tin oxide can also be applied. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can also be used.

[0048] The gate insulating film 17 is, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, and nitrogen Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn metals Oxides, silicon nitride, etc., can be used, and they can be provided in a laminated or single layer configuration.

[0049] Furthermore, as the gate insulating film 17, hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), Nitrogen-added hafnium Minate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. Using k-materials can reduce gate leakage in transistors.

[0050] The thickness of the gate insulating film 17 is 5 nm to 400 nm, or 10 nm to 300 nm. Alternatively, a wavelength between 50nm and 250nm is preferable.

[0051] The oxide semiconductor film 18 is typically an In-Ga oxide film, an In-Zn oxide film, or an In -M-Zn oxide film (where M is Al, Ga, Y, Zr, La, Ce, or Nd).

[0052] Furthermore, when the oxide semiconductor film 18 is an In-M-Zn oxide film, the sum of In and M is When assumed to be 100 atomic%, the atomic ratio of In to M is 25 atomic% for In. The above and M is less than 75 atomic%, or In is 34 atomic or more and M is 6 The percentage should be less than 6 atomic%.

[0053] The oxide semiconductor film 18 has an energy gap of 2 eV or more, 2.5 eV or more, or 3 eV. It is above eV. In this way, by using oxide semiconductors with a wide energy gap, The off-current of transistor 50 can be reduced.

[0054] The thickness of the oxide semiconductor film 18 is between 3 nm and 200 nm, or between 3 nm and 100 nm. or 3nm to 50nm.

[0055] The oxide semiconductor film 18 is an In-M-Zn oxide film (where M is Al, Ga, Y, Zr, La, C). e) or Nd), sputtering used to deposit In-M-Zn oxide film The atomic ratio of the target metal elements is preferably such that In ≥ M and Zn ≥ M. For a sputtering target, the atomic ratio of metal elements is In:M:Zn = 1:1. :1, In:M:Zn=3:1:2 is preferred. Note that the oxide semiconductor film 18 to be formed The atomic ratio includes, as an error, plus or minus 40% variation in the atomic ratio of the metal elements contained in the above sputtering target. Note that when the content of In in the oxide semiconductor film 18 is high, the on-current of the transistor increases and the field-effect mobility increases. For this reason, by forming the oxide semiconductor film 18 using a sputtering target of In-M-Zn oxide with an atomic ratio of metal elements of In:M:Zn = 3:1:2, transistors with excellent electrical characteristics can be fabricated. As the oxide semiconductor film 18, an oxide semiconductor film with a low carrier density is used. For example, the oxide semiconductor film 18 has a carrier density of 1×10 per cm or less, 1×10

[0056] per cm or less, 1×10 17 per cm 3 or less, or an oxide semiconductor film with 1×10 15 per cm 3 or less is used. 13 Note that it is not limited to these, and those with an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor. Also, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal elements and oxygen, interatomic distance, density, etc. of the oxide semiconductor film 18 appropriate. 3 Note that by using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor film 18, transistors with even more excellent electrical characteristics can be fabricated. 11 3

[0057]

[0058] ​​​​​​​​​​This is preferable. Here, the impurity concentration is low and the defect level density is low (few oxygen vacancies). This is called high-purity intrinsic or substantially high-purity intrinsic. Some oxide semiconductors have few carrier sources, which allows for a low carrier density. In some cases, this may occur. Therefore, transistors in which a channel region is formed in the oxide semiconductor film are The electrical characteristics (also called normally-on) where the threshold voltage is negative are less common. No. Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic are defect-level dense. Because the degree is low, the trap level density may also be low. Also, high purity true or substantial Furthermore, the highly pure and intrinsic oxide semiconductor film exhibits remarkably low off-current and a channel width of 1 × 10⁻⁶ 6 Even with a μm element and a channel length L of 10 μm, the voltage between the source electrode and the drain electrode When the drain voltage is in the range of 1V to 10V, the off-current is measured by the semiconductor parameter analyzer. Below the measurement limit of the riser, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. Therefore, transistors in which a channel region is formed in the oxide semiconductor film exhibit changes in electrical characteristics. This can result in transistors with low dynamics and high reliability. Charges trapped in the top level take a long time to disappear, much like fixed charges. They sometimes behave like sea urchins. Therefore, channels are formed in oxide semiconductor films with a high trap level density. Transistors in which regions are formed may have unstable electrical properties. Impurities include... These include hydrogen, nitrogen, alkali metals, or alkaline earth metals.

[0059] The hydrogen contained in the oxide semiconductor film reacts with the oxygen bonded to the metal atom to form water, An oxygen vacancy is formed in the lattice (or the area where oxygen has been removed) where oxygen has been removed. When hydrogen enters, electrons, which act as carriers, are sometimes generated. Also, some of the hydrogen In some cases, by bonding with oxygen atoms that bond with metal atoms, electrons, which act as carriers, can be generated. Therefore, transistors using oxide semiconductors containing hydrogen exhibit normally-on characteristics. It's easy to get it.

[0060] Therefore, it is preferable that the oxide semiconductor film 18 has as little hydrogen as possible. Specifically, in the oxide semiconductor film 18, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) was performed. The hydrogen concentration obtained by (daily Ion Mass Spectrometry) 5 x 10 19 atoms / cm 3 Below, 1 x 10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Below, 1 x 10 18 atoms / cm 3 Below, 5 x 10 17 at oms / cm 3 The following, or 1 × 10 16 atoms / cm 3 The following applies:

[0061] In the oxide semiconductor film 18, if silicon or carbon, which are among the Group 14 elements, are included... Therefore, oxygen vacancies increase in the oxide semiconductor film 18, causing it to become n-type. Concentrations of silicon and carbon in semiconductor film 18 (concentrations obtained by secondary ion mass spectrometry) ) to 2 × 10 18 atoms / cm 3 The following, or 2 × 10 17 atoms / cm 3 Below It will be below.

[0062] Furthermore, in the oxide semiconductor film 18, alkali gold obtained by secondary ion mass spectrometry The concentration of the genus or alkaline earth metal is 1 × 10⁻⁶. 18 atoms / cm 3 The following, or 2x 10 16 atoms / cm 3 The following applies: Alkali metals and alkaline earth metals are oxides. When coupled with a semiconductor, it can generate carriers, increasing the transistor's off-current. This can happen. For this reason, alkali metal or alkaline earth metal of the oxide semiconductor film 18 It is preferable to reduce the concentration of the genus.

[0063] Furthermore, if nitrogen is present in the oxide semiconductor film 18, electrons, which are carriers, are generated, The rear density increases, making it easier to convert to n-type. As a result, using an oxide semiconductor containing nitrogen... Transistors tend to exhibit normally-on characteristics. Therefore, in the oxide semiconductor film, Therefore, it is preferable that nitrogen is reduced as much as possible, for example, in secondary ion mass spectrometry. The nitrogen concentration obtained is 5 × 10 18 atoms / cm 3 The following is preferable:

[0064] Furthermore, the oxide semiconductor film 18 may have a non-single-crystal structure, for example. CAAC-OS (C Axis Aligned Crystalline), as described later. Oxide Semiconductor), polycrystalline structure, microcrystalline structure described later, or It includes amorphous structures. In non-single crystal structures, amorphous structures have the highest defect level density, CA AC-OS has the lowest defect level density.

[0065] The oxide semiconductor film 18 may have an amorphous structure, for example. An oxide semiconductor film with an amorphous structure is For example, an oxide film with a disordered atomic arrangement and no crystalline components, or an amorphous structure. For example, it has a completely amorphous structure and does not contain any crystalline parts.

[0066] Furthermore, the oxide semiconductor film 18 has regions of amorphous structure, regions of microcrystalline structure, and regions of polycrystalline structure. A mixed film having two or more regions: a region of CAAC-OS and a region of single crystal structure. The mixed film, for example, has regions with an amorphous structure, regions with a microcrystalline structure, regions with a polycrystalline structure, CAA It may have two or more regions, either C-OS regions or single-crystal structure regions. The mixed film, for example, has regions with an amorphous structure, regions with a microcrystalline structure, regions with a polycrystalline structure, CAA In cases where the stacked structure has two or more regions, either C-OS regions or single-crystal structures, be.

[0067] The pair of electrodes 21 and 22 are made of aluminum, titanium, chromium, nickel, copper, and yttrium. A single elemental metal consisting of zirconium, molybdenum, silver, tantalum, or tungsten. Alternatively, an alloy with this as the main component is used as a single-layer or multi-layer structure. For example, silico A single-layer structure of an aluminum film containing , a double-layer structure in which an aluminum film is laminated on a titanium film, A two-layer structure consisting of an aluminum film laminated on a tungsten film, copper-magnesium-aluminium A two-layer structure in which a copper film is laminated on an alloy film, a two-layer structure in which a copper film is laminated on a titanium film, tungsten A two-layer structure in which a copper film is laminated on a titanium film, a titanium film or a titanium nitride film, and the titanium film This involves layering an aluminum film or a copper film on top of a titanium nitride film, and then layering a titanium film on top of that. Alternatively, a three-layer structure forming a titanium nitride film, a molybdenum film or a molybdenum nitride film, and An aluminum film or copper film is laminated on top of a molybdenum film or molybdenum nitride film, Furthermore, there are three-layer structures in which a molybdenum film or molybdenum nitride film is formed on top of it. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may also be used.

[0068] The oxide insulating film 23 is an oxide insulating film that permeates oxygen. This helps to mitigate damage to the oxide semiconductor film 18 when forming the oxide insulating film 24 that will be formed later. It also functions as a membrane.

[0069] The oxide insulating film 23 has a thickness of 5 nm or more and 150 nm or less, or 5 nm or more and 50 nm Silicon oxide films, silicon oxynitride films, etc., with a minimum size of nm can be used. In the book, silicon oxidizride film is described as having a composition in which oxygen content is higher than nitrogen content. This refers to a film, and a silicon nitride film is a film whose composition contains more nitrogen than oxygen. It refers to a membrane.

[0070] Furthermore, the oxide insulating film 23 preferably has a low defect count, and typically, ESR measurement... This results in the spin of the signal appearing at g=2.001, which originates from the silicon dangling bond. Density is 3 × 10 17 spins / cm 3 The following is preferable. This is an oxide insulation. If the defect density in the film 23 is high, oxygen will bind to the defects, and the oxide insulating film 2 This is because the amount of oxygen permeable in point 3 decreases.

[0071] Furthermore, the low number of defects at the interface between the oxide insulating film 23 and the oxide semiconductor film 18 is a positive factor. Preferably, and typically, g=1 originating from defects in the oxide semiconductor film 18, as determined by ESR measurement. The spin density of the signal appearing at 0.93 is 1 × 10⁻⁶ 17 spins / cm 3 Further detection It is preferable that it be below the lower limit.

[0072] Furthermore, in the oxide insulating film 23, all of the oxygen that enters the oxide insulating film 23 from the outside is acid Some oxygen remains in the oxide insulating film 23 without moving to the outside of the oxide insulating film 23. As oxygen enters the material insulating film 23, the oxygen contained in the oxide insulating film 23 Movement to the outside may also cause oxygen to move within the oxide insulating film 23.

[0073] When an oxide insulating film that permeates oxygen is formed as the oxide insulating film 23, the oxide insulating film 23 Oxygen that desorbs from the oxide insulating film 24 provided above is absorbed through the oxide insulating film 23. It can be moved to the semiconductor film 18.

[0074] The oxide insulating film 24 is formed so as to be in contact with the oxide insulating film 23. 4 is formed using an oxide insulating film containing more oxygen than satisfactorily satisfying the stoichiometric composition. Oxide insulating films containing more oxygen than that satisfying the stoichiometric composition will become acidic when heated. Some of the elements are eliminated. Oxide insulating film contains more oxygen than satisfactorily required to satisfy the stoichiometric composition. In TDS analysis, the amount of oxygen removed, converted to oxygen atoms, was 1.0 × 10⁻⁶. 18 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The above is an oxide insulating film. ru.

[0075] The oxide insulating film 24 has a thickness of 30 nm to 500 nm, or 50 nm or more. Silicon oxide films, silicon oxide nitride films, etc., with a wavelength of 400 nm or less can be used.

[0076] Furthermore, the oxide insulating film 24 preferably has a low defect count, and typically, ESR measurement... This results in the spin of the signal appearing at g=2.001, which originates from the silicon dangling bond. Density is 1.5 × 10 18 spins / cm 3 Less than, and even 1 x 10 18 spins / cm 3 The following is preferable. Note that the oxide insulating film 24 is compared with the oxide insulating film 23. Because it is far from the oxide semiconductor film 18, even if the defect density is higher than that of the oxide insulating film 23... stomach.

[0077] Furthermore, oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. are added to the oxide insulating film 24. By providing a nitride insulating film 25 having a blocking effect, the oxide semiconductor film 18 can be blocked. To prevent the diffusion of oxygen to the outside and the intrusion of hydrogen, water, etc. into the oxide semiconductor film 18 from the outside. This can be done. Examples of nitride insulating films include silicon nitride film, silicon nitride oxide film, and aluminum nitride film. Examples include aluminum film, aluminum nitride film, etc. Note that oxygen, hydrogen, water, alkali metals, aluminum Instead of a nitride insulating film having a blocking effect such as potassium earth metals, use oxygen, hydrogen, water, etc. An oxide insulating film having a blocking effect may be provided. Blocking of oxygen, hydrogen, water, etc. Examples of oxide insulating films having a rubbing effect include aluminum oxide films and aluminum oxide nitride films. , gallium oxide film, gallium oxide nitride film, yttrium oxide film, yttrium oxide nitride film Examples include hafnium oxide films and hafnium oxide nitride films.

[0078] The configuration of the protective film 26 is not limited to the above configuration, and an oxide insulating film or nitride insulating film may be used as appropriate. The film can be a single layer or a multilayer structure. Alternatively, a multilayer structure of two, four, or other layers can be used as appropriate. It is possible.

[0079] Next, the method for fabricating the transistor 50 shown in Figure 2 will be explained using Figure 4.

[0080] As shown in Figure 4(A), a gate electrode 15 is formed on the substrate 11, and on the gate electrode 15 A gate insulating film 17 is formed.

[0081] Here, a glass substrate is used as the substrate 11.

[0082] The method for forming the gate electrode 15 is shown below. First, sputtering, CVD, and vapor deposition are described. A conductive film is formed by a coating method, and a photolithograph is performed on the conductive film using a first photomask. A mask is formed by the following process. Next, a portion of the conductive film is etched using the mask. Then, the gate electrode 15 is formed. After this, the mask is removed.

[0083] The gate electrode 15 may be formed by electroplating, printing, or inkjet instead of the above formation method. It may also be formed by the jet method or other methods.

[0084] Here, a tungsten film with a thickness of 200 nm is formed by sputtering. Next A mask is formed by a photolithography process, and a tungsten film is made using this mask. Dry etching is performed to form the gate electrode 15.

[0085] The gate insulating film 17 is formed by sputtering, CVD, vapor deposition, or the like.

[0086] The gate insulating film 17 is a silicon oxide film, a silicon oxide nitride film, or silicon oxide nitride film. When forming a film, depositing gases containing silicon and oxidizing gases are used as raw material gases. It is preferable that it be present. Typical examples of silicon-containing sedimentary gases include silane, disilane, Examples include trisilane and silane fluoride. Oxidizing gases include oxygen, ozone, and nitrous oxide. Examples include nitrogen dioxide, etc.

[0087] Furthermore, when forming a gallium oxide film as the gate insulating film 17, MOCVD (Meta Using the Organic Chemical Vapor Deposition method It can be formed by [doing something].

[0088] Here, the gate insulating film 17 is a silicon nitride film with a thickness of 400 nm and a film with a thickness of 50 nm. It is formed by laminating a silicon oxidizide film of m. The silicon nitride film is composed of silane, nitrogen, and a It is formed by plasma CVD using monoxide as the raw material gas. The silicon oxidizride film is formed by It is formed by plasma CVD using ranum and nitrous oxide as raw material gases.

[0089] Next, as shown in Figure 4(B), an oxide semiconductor film 18 is formed on the gate insulating film 17. .

[0090] The method for forming the oxide semiconductor film 18 is described below. On the gate insulating film 17, acid An oxide semiconductor film is formed to become the oxide semiconductor film 18. Next, a second film is formed on the oxide semiconductor film. After forming a mask using a photomask in a photolithography process, the mask is used By etching a portion of the oxide semiconductor film, device isolation can be achieved as shown in Figure 4(B). A modified oxide semiconductor film 18 is formed. After this, the mask is removed.

[0091] The oxide semiconductor film that would later become the oxide semiconductor film 18 was produced by sputtering, coating, and pulsed It can be formed using methods such as laser deposition and laser ablation.

[0092] When forming an oxide semiconductor film by sputtering, a power supply is required to generate the plasma. The device can use an RF power supply, AC power supply, DC power supply, etc., as appropriate.

[0093] Sputtering gases include a mixture of noble gases and oxygen, and noble gases (typically argon). Use oxygen as appropriate. In the case of a mixture of noble gas and oxygen, use oxygen relative to the noble gas. It is preferable to increase the ratio.

[0094] Furthermore, the target should be appropriately selected according to the composition of the oxide semiconductor film to be formed. .

[0095] To obtain an oxide semiconductor film that is of high purity intrinsic or substantially high purity intrinsic, a chamber - In addition to evacuating the inside to a high vacuum, it is also necessary to purify the sputtering gas. The oxygen and argon gases used have dew points of -40°C or lower, -80°C or lower, and -100°C. By using the following methods, or by using gas purified to below -120°C, water can be added to the oxide semiconductor film. This can prevent, as much as possible, the inclusion of fractions and other elements.

[0096] Here, we have an In-Ga-Zn oxide target (In:Ga:Zn=3:1:2), By using an oxygen sputtering gas, an oxide semiconductor film is produced. A 35nm thick In-Ga-Zn oxide film is formed. Next, a mask is placed on the oxide semiconductor film. By forming and selectively etching a portion of the oxide semiconductor film, the oxide semiconductor film 18 It forms.

[0097] Next, as shown in Figure 4(C), a pair of electrodes 21 and 22 are formed.

[0098] The methods for forming the pair of electrodes 21 and 22 are shown below. First, sputtering and CVD. A conductive film is formed using methods such as vapor deposition. Next, a third photomask is used to form a conductive film on the conductive film. A mask is formed by a trisography process. Next, the conductive film is etched using the mask. Then, a pair of electrodes 21 and 22 are formed. After this, the mask is removed.

[0099] Here, a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a thick Two 200 nm thick titanium films are sequentially stacked using the sputtering method. Next, a fu... A mask is formed by a photolithography process, and a tungsten film is formed using this mask. A pair of electrodes 21 and 22 are formed by dry etching a titanium film and a titanium film.

[0100] Next, as shown in Figure 4(D), on the oxide semiconductor film 18 and the pair of electrodes 21 and 22, An oxide insulating film 23 is formed. Next, an oxide insulating film 24 is formed on the oxide insulating film 23. .

[0101] Furthermore, after forming the oxide insulating film 23, the oxide insulating film 2 is continuously processed without exposure to the atmosphere. It is preferable to form 4. After forming the oxide insulating film 23, do not open it to the atmosphere and the raw material gas By adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature, the oxide insulating film 24 is continuously... By forming it in this way, the atmospheric components at the interface between oxide insulating film 23 and oxide insulating film 24 This can reduce the concentration of impurities, and also remove the oxygen contained in the oxide insulating film 24. It is possible to transfer oxygen to the semiconductor film 18, thereby reducing the amount of oxygen vacancies in the oxide semiconductor film 18. It is possible.

[0102] A substrate placed in the vacuum-evacuated processing chamber of a plasma CVD apparatus is subjected to temperatures of 280°C or higher and 400°C. Maintain the temperature below ℃, introduce the raw material gas into the processing chamber, and maintain the pressure inside the processing chamber at 20 Pa or higher. The pressure shall be 0 Pa or less, or 100 Pa to 250 Pa, and the electrodes installed in the processing chamber shall be high Depending on the conditions under which frequency power is supplied, the oxide insulating film 23 can be a silicon oxide film or an oxidative nitride film. A silicon film can be formed.

[0103] As the raw material gas for the oxide insulating film 23, a depositing gas containing silicon and an oxidizing gas are used. It is preferable that it be present. Typical examples of silicon-containing sedimentary gases include silane, disilane, Examples include trisilane and silane fluoride. Oxidizing gases include oxygen, ozone, and nitrous oxide. Examples include nitrogen dioxide, etc.

[0104] By using the above conditions, an oxide insulating film that permeates oxygen is formed as the oxide insulating film 23. This is possible. In addition, by providing the oxide insulating film 23, the oxide insulating film that is formed later can be made In the formation process 24, damage to the oxide semiconductor film 18 can be reduced.

[0105] The oxide insulating film 23 is placed in the vacuum-evacuated processing chamber of the plasma CVD apparatus. The substrate is kept at a temperature between 280°C and 400°C, and the raw material gas is introduced into the processing chamber. The pressure applied is set to 100 Pa or more and 250 Pa or less, and high-frequency power is applied to the electrodes installed in the processing chamber. Under the condition of supply, as the oxide insulating film 23, a silicon oxide film or a silicon oxynitride film can be formed. The film can be formed.

[0106] Under the film formation condition, by setting the substrate temperature to the above temperature, the binding force between silicon and oxygen becomes stronger. As a result, as the oxide insulating film 23, an oxide insulating film through which oxygen permeates, is dense, and is hard can be formed. Typically, a silicon oxide film or a silicon oxynitride film having an etching rate of 10 nm / min or less, or 8 nm / min or less with respect to 0.5 wt% hydrofluoric acid at 25°C can be formed. Moreover, in order to form the oxide insulating film 23 while heating, hydrogen, water, etc. contained in the oxide semiconductor film 18 can be desorbed in this process. The hydrogen contained in the oxide semiconductor film 18 combines with oxygen radicals generated in the plasma to become water. Since the substrate is heated in the film formation process of the oxide insulating film 23, the water generated by the combination of oxygen and hydrogen desorbs from the oxide semiconductor film. That is, by forming the oxide insulating film 23 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. The film can be formed.

[0107] In addition, since the oxide insulating film 23 is formed while heating, the heating time in the state where the oxide semiconductor film 18 is exposed is short, and the amount of oxygen desorbed from the oxide semiconductor film due to the heat treatment can be reduced. That is, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced. The film can be formed.

[0108] Furthermore, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film The film can be formed.

[0109] Moreover, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film ​​​​​​​​Because the water content in 23 decreases, the variation in the electrical characteristics of transistor 50 This reduces the threshold voltage and suppresses fluctuations in the threshold voltage.

[0110] Furthermore, by setting the pressure in the processing chamber to between 100 Pa and 250 Pa, the oxide insulating film 23 When forming the film, it is possible to reduce damage to the oxide semiconductor film 18, The amount of oxygen vacancies in the semiconductor film 18 can be reduced. In particular, the oxide insulating film 23 Alternatively, the deposition temperature of the oxide insulating film 24 that is formed later can be increased, typically above 220°C. By raising the temperature, some of the oxygen contained in the oxide semiconductor film 18 is desorbed, and oxygen vacancies form It is easily achieved. Also, in order to improve the reliability of the transistor, the oxide insulating film 2 that is formed later Using film deposition conditions that reduce the amount of defects in step 4 makes it easier to reduce oxygen desorption. As a result, it can be difficult to reduce oxygen vacancies in the oxide semiconductor film 18. However, The pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, and during the deposition of the oxide insulating film 23... By reducing damage to the oxide semiconductor film 18, less acid is released from the oxide insulating film 24. Even with minimal desorption, it is possible to reduce oxygen vacancies in the oxide semiconductor film 18.

[0111] Furthermore, by increasing the amount of oxidizing gas relative to the silicon-containing sedimentary gas to more than 100 times, It is possible to reduce the hydrogen content contained in the oxide insulating film 23. As a result, the oxide Since the amount of hydrogen mixed into the semiconductor film 18 can be reduced, the threshold voltage of the transistor becomes negative. This can suppress shift.

[0112] Here, as the oxide insulating film 23, silane and nitrous oxide are used as source gases. A silicon oxynitride film with a thickness of 50 nm is formed by the plasma CVD method. Under these conditions, a silicon oxynitride film through which oxygen can permeate can be formed.

[0113] As the oxide insulating film 24, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is held at 180°C or higher and 280°C or lower, or 200°C or higher and 240°C or lower. A raw material gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 100 Pa or higher and 250 Pa or lower, or 100 Pa or higher and 200 Pa or lower. High-frequency power of 0.17 W / cm or higher and 0.5 W / cm or lower, or 0.25 W / cm or higher and 0.35 W / cm or lower is supplied to the electrode provided in the processing chamber. Under these conditions, a silicon oxide film or a silicon oxynitride film is formed. 2 2 2 2

[0114] As the raw material gas for the oxide insulating film 24, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0115] As the film formation conditions for the oxide insulating film 24, by supplying high-frequency power with the above power density in the processing chamber with the above pressure, the decomposition efficiency of the raw material gas in the plasma increases, the oxygen radicals increase, and the oxidation of the raw material gas proceeds. Therefore, the oxygen content in the oxide insulating film 24 becomes more than the stoichiometric composition. On the other hand, in the film formed at the above temperature, since the binding force between silicon and oxygen is weak, a part of the oxygen in the film desorbs due to the heat treatment in the subsequent process. As a result It contains more oxygen than satisfactorily satisfactorily, and some of the oxygen is removed upon heating. An oxide insulating film can be formed on the oxide semiconductor film 18. 3 is provided. For this reason, in the process of forming the oxide insulating film 2, Layer 3 acts as a protective layer for the oxide semiconductor film 18. As a result, damage to the oxide semiconductor film 18 is reduced. While reducing power density, it is possible to form the oxide insulating film 24 using high-frequency power. Cut.

[0116] Furthermore, in the deposition conditions for the oxide insulating film 24, silicon-containing deposition in an oxidizing gas... By increasing the flow rate of the volatile gas, it is possible to reduce the amount of defects in the oxide insulating film 24. Typically, ESR measurements show that g = 2.0 originates from dangling bonds in silicon. The spin density of the signal appearing at 01 is 6 × 10 17 spins / cm 3 Less than 3 x 10 17 s pins / cm 3 The following, or 1.5 × 10 17 spins / cm 3 The amount of defects is as follows: This allows for the formation of a smaller oxide insulating film. As a result, the reliability of the transistor is improved. It is possible.

[0117] Here, as the oxide insulating film 24, silane and nitrous oxide are used as source gases. A silicon oxide nitride film with a thickness of 400 nm is formed using the CVD method.

[0118] Next, a heat treatment is performed. The temperature for this heat treatment is typically between 150°C and 400°C. The temperature shall be between 300°C and 400°C, or between 320°C and 370°C.

[0119] The heat treatment can be carried out using an electric furnace, an RTA device, etc. Therefore, heat treatment can be performed at a temperature above the strain point of the substrate for a short period of time. Processing time can be reduced.

[0120] Heat treatment involves nitrogen, oxygen, and ultra-dry air (with water content of 20 ppm or less, 1 ppm or less). The test is performed in an atmosphere of air (or air with a ppb of less than 10 ppb) or a noble gas (argon, helium, etc.). That's fine. Note that the above nitrogen, oxygen, ultra-dry air, or noble gases do not contain hydrogen, water, etc. It is preferable.

[0121] This heat treatment converts some of the oxygen contained in the oxide insulating film 24 into the oxide semiconductor film 18. By moving the oxygen, the amount of oxygen vacancies contained in the oxide semiconductor film 18 can be further reduced.

[0122] Furthermore, if the oxide insulating film 23 and the oxide insulating film 24 contain water, hydrogen, etc., A nitride insulating film 25 having the function of blocking such substances is subsequently formed and then subjected to heat treatment. Water, hydrogen, etc. contained in the oxide insulating film 23 and oxide insulating film 24 are absorbed into the oxide semiconductor film 18. The acid moves, causing defects in the oxide semiconductor film 18. However, this heating process causes the acid It is possible to remove water, hydrogen, etc. contained in the oxide insulating film 23 and the oxide insulating film 24. This reduces variations in the electrical characteristics of transistor 50 and suppresses fluctuations in the threshold voltage. It can be controlled.

[0123] Furthermore, by forming the oxide insulating film 24 on the oxide insulating film 23 while heating, oxidation By transferring oxygen to the material semiconductor film 18, the oxygen vacancies contained in the oxide semiconductor film 18 are reduced. Since this is possible, the heat treatment does not need to be performed.

[0124] Here, the material is heated at 350°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

[0125] Furthermore, when forming the pair of electrodes 21 and 22, the conductive film is etched, resulting in an oxide semiconductor The body membrane 18 is damaged, and the back channel of the oxide semiconductor film 18 (oxide semiconductor film 18 In this case, an oxygen deficiency occurs on the side opposite to the side facing the gate electrode 15. However, The oxide insulating film 24 contains more oxygen than satisfies the stoichiometric composition. By applying this, the oxygen deficiency that occurs on the back channel side due to heat treatment is repaired. This makes it possible to reduce defects contained in the oxide semiconductor film 18. Therefore, the reliability of transistor 50 can be improved.

[0126] Next, a nitride insulating film 25 is formed by sputtering, CVD, or the like.

[0127] Furthermore, when forming the nitride insulating film 25 by plasma CVD, the true The substrate placed in the ventilated processing chamber is subjected to temperatures between 300°C and 400°C, or between 320°C and 320°C. Maintaining a temperature of 370°C or lower is preferable because it allows for the formation of a dense nitride insulating film.

[0128] When forming a silicon nitride film as the nitride insulating film 25 by plasma CVD, It is preferable to use depositing gases containing condensate, nitrogen, and ammonia as raw material gases. By using a small amount of ammonia as a raw material gas compared to nitrogen, ammonia can be produced in the plasma. The nitrate dissociates, generating an active species. This active species is contained in the silicon-containing sedimentary gas. The bonds between silicon and hydrogen, and the triple bond of nitrogen are broken. As a result, silicon and nitrogen The bonding is promoted, resulting in fewer silicon and hydrogen bonds, fewer defects, and a dense silicon nitride. A film can be formed. On the other hand, in the raw material gas, the amount of ammonia relative to nitrogen If the levels are high, the decomposition of silicon-containing sedimentary gases and nitrogen will not proceed, and silicon and hydrogen will not decompose. The bonds remain intact, leading to an increase in defects and the formation of a rough silicon nitride film. For these reasons, the flow rate ratio of nitrogen to ammonia in the raw gas should be between 5 and 50. Alternatively, it is preferable to have a value between 10 and 50.

[0129] Here, using plasma CVD with silane, nitrogen, and ammonia as raw material gases, A silicon nitride film with a thickness of 100 nm is formed.

[0130] Through the above process, the oxide insulating film 23, oxide insulating film 24, and nitride insulating film 25 are formed A protective film 26 can be formed.

[0131] Next, a heat treatment may be performed. The temperature of this heat treatment is typically 150°C or higher. The temperature range shall be below 0°C, between 300°C and 400°C, or between 320°C and 370°C.

[0132] If the gate electrode 15 and the gate electrode 29 to be formed later are to be connected, then the gate Openings are formed in the insulating film 17, oxide insulating film 23, oxide insulating film 24, and nitride insulating film 25. To accomplish.

[0133] Next, as shown in Figure 4(E), the gate electrode 29 is formed. The procedure is as follows: First, a conductive film is formed by sputtering, CVD, vapor deposition, etc. Then, a mask is formed on the conductive film by a photolithography process using a fourth photomask. Next, a portion of the conductive film is etched using the mask to form the gate electrode 29. Then, remove the mask.

[0134] Furthermore, as shown in Figure 3(C), in the channel width direction, the outer side of the oxide semiconductor film 18 The gate electrode 29 is formed such that its end is located at [location].

[0135] Here, indium tin oxide (hereinafter referred to as ITO) having silicon oxide with a thickness of 100 nm is used. The film is formed by sputtering. Next, by a photolithography process A mask is formed, and an ITO film containing silicon oxide is wet-etched using the mask. Then, the gate electrode 29 is formed. After this, heat treatment may be performed.

[0136] By following the above steps, transistor 50 can be manufactured.

[0137] A dual gate electrode is provided with an oxide semiconductor film between the first gate electrode and the second gate electrode. A transistor having a gate structure, wherein in the channel width direction of the transistor, a first gate The sides of the first electrode and the second gate electrode are each located outside the side surface of the oxide semiconductor film. This makes it possible to influence the edge of the oxide semiconductor film 18 with the electric field of the gate electrode 29. Thus, the entire oxide semiconductor film 18, including its edges, can function as a channel. As a result, the on-current of the transistor is increased, and the field-effect mobility is also increased. It is possible.

[0138] Furthermore, the transistor shown in this embodiment has a first gate electrode and a second gate electrode. Therefore, each gate electrode can shield against an external electric field. As a result, the degradation of stress tests is suppressed, and the on-current at different drain voltages is also reduced. This can suppress fluctuations in the rise voltage. As a result, transistors with excellent electrical characteristics... A semiconductor device having a tactile function can be obtained. Furthermore, a highly reliable semiconductor device can be obtained. can.

[0139] <Example 1: Regarding the undercoat insulating film> In the transistor 50 shown in this embodiment, the substrate 11 and gate electric current may be used as needed. A base insulating film can be provided between the poles 15. The material for the base insulating film is silicon dioxide. N, silicon oxide nitride, silicon nitride, silicon oxide nitride, gallium oxide, hafnium oxide Examples include aluminum oxide, yttrium oxide, aluminum oxide, and aluminum nitride oxide. Materials used for insulating films include silicon nitride, gallium oxide, hafnium oxide, and yttrium oxide. By using aluminum oxide, etc., impurities, typically alkali metals, can be removed from the substrate 11. This can suppress the diffusion of water, hydrogen, and other elements into the oxide semiconductor film 18.

[0140] The underlying insulating film can be formed by sputtering, CVD, or other methods.

[0141] <Modification Example 2: Regarding the gate insulating film> In the transistor 50 shown in this embodiment, the gate insulating film 17 may be added if necessary. A layered structure can be used. Here, the configuration of the gate insulating film 17 is shown using Figure 5. explain.

[0142] As shown in Figure 5(A), the gate insulating film 17 consists of a nitride insulating film 17a and an oxide insulating film. 17b can be arranged in a stacked structure in which it is stacked sequentially from the gate electrode 15 side. By providing a nitride insulating film 17a on the electrode 15 side, impurities from the gate electrode 15 are typically... This involves the movement of hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc., to the oxide semiconductor film 18. This can prevent that from happening.

[0143] Furthermore, by providing an oxide insulating film 17b on the oxide semiconductor film 18 side, the gate insulating film 17 Furthermore, it is possible to reduce the defect level density at the interface of the oxide semiconductor film 18. As a result, transistors with less degradation of electrical characteristics can be obtained. As b, similar to the oxide insulating film 24, more oxygen than satisfies the stoichiometric composition. When formed using an oxide insulating film containing oxide film, the interface between the gate insulating film 17 and the oxide semiconductor film 18 This is even more preferable because it allows for a further reduction in the defect level density.

[0144] As shown in Figure 5(B), the gate insulating film 17 is made of a nitride insulating film 17c with few defects, A nitride insulating film 17d with high hydrogen blocking properties and an oxide insulating film 17b form a gate electrode. A stacked structure can be formed in which layers are stacked sequentially from the 15 side. The gate insulating film 17 can be a defect By providing a nitride insulating film 17c with a low concentration, the dielectric breakdown voltage of the gate insulating film 17 is improved. This is possible. In addition, by providing a nitride insulating film 17d with high hydrogen blocking properties, Hydrogen from the electrode 15 and the nitride insulating film 17c moves to the oxide semiconductor film 18. It can be prevented.

[0145] An example of the fabrication method for the nitride insulating films 17c and 17d shown in Figure 5(B) is described below. Plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as the raw material gas. This forms a silicon nitride film with few defects as a nitride insulating film 17c. Next, the raw materials The gas is switched to a mixture of silane and nitrogen, resulting in a lower hydrogen concentration and blocking hydrogen. A silicon nitride film capable of being fired is formed as a nitride insulating film 17d. By using this formation method, a nitride insulating film with few defects and hydrogen blocking properties is formed. A layered gate insulating film 17 can be formed.

[0146] As shown in Figure 5(C), the gate insulating film 17 is made of nitride with high impurity blocking properties. Insulating film 17e, a nitride insulating film 17c with few defects, and a nitride with high hydrogen blocking properties A laminated structure in which insulating film 17d and oxide insulating film 17b are stacked in order from the gate electrode 15 side. It can be constructed as follows: As the gate insulating film 17, a nitride with high impurity blocking properties By providing the insulating film 17e, impurities from the gate electrode 15, typically hydrogen, nitrogen, This prevents alkali metals or alkaline earth metals from migrating to the oxide semiconductor film 18. It is possible.

[0147] An example of the method for fabricating the nitride insulating films 17e, 17c, and 17d shown in Figure 5(C) is described below. First, a plasma was created using a mixed gas of silane, nitrogen, and ammonia as the source gas. By the CVD method, a silicon nitride film with high impurity blocking properties is formed with a nitride insulating film 17e. This is how it is formed. Next, by increasing the flow rate of ammonia, a silicon nitride with fewer defects is formed. The film is formed as a nitride insulating film 17c. Next, the source gas is a mixed gas of silane and nitrogen. Switching to a silicon nitride with a low hydrogen concentration and capable of blocking hydrogen The film is formed as a nitride insulating film 17d. This formation method results in fewer defects. Furthermore, a gate insulating film 17 is formed by stacking nitride insulating films that have impurity-blocking properties. It is possible.

[0148] <Modification 3: Regarding a pair of electrodes> As a pair of electrodes 21 and 22 provided in the transistor 50 shown in this embodiment, Gusten, titanium, aluminum, copper, molybdenum, chromium, or tantalum in elemental form This allows the use of conductive materials that readily bond with oxygen, such as alloys. As a result, oxide semiconductors can be used. The oxygen contained in the film 18 combines with the conductive material contained in the pair of electrodes 21 and 22, forming an oxide semi-oxide. In the conductive film 18, an oxygen-deficient region is formed. Also, a pair of electrodes are placed in the oxide semiconductor film 18. In some cases, some of the constituent elements of the conductive material forming poles 21 and 22 may be mixed in. As shown in Figure 6, in the oxide semiconductor film 18, the region in contact with the pair of electrodes 21 and 22 Low-resistance regions 20a and 20b are formed in the vicinity. The low-resistance regions 20a and 20b are a pair It is in contact with electrodes 21 and 22 and is formed between the gate insulating film 17 and the pair of electrodes 21 and 22. The low-resistance regions 20a and 20b have high conductivity, so the oxide semiconductor film 18 and the pair of electrodes... It is possible to reduce the contact resistance with 21 and 22, and increase the on-current of the transistor. It is possible to do so.

[0149] Furthermore, the pair of electrodes 21 and 22 are made of a conductive material that readily bonds with oxygen, titanium nitride, and nitrogen. A laminated structure with conductive materials that do not readily bond with oxygen, such as tantalum or ruthenium, may also be used. By using such a layered structure, at the interface between the pair of electrodes 21 and 22 and the oxide insulating film 23 This makes it possible to prevent oxidation of the pair of electrodes 21 and 22, and the high temperature of the pair of electrodes 21 and 22 It is possible to suppress the development of resistance.

[0150] <Modification 4: Regarding oxide semiconductor films> In the method for manufacturing the transistor 50 shown in this embodiment, a pair of electrodes 21 and 22 are formed After this, the oxide semiconductor film 18 is exposed to plasma generated in an oxygen atmosphere, and the oxide semiconductor Oxygen can be supplied to the membrane 18. The oxidizing atmosphere can be oxygen, ozone, or dinitrate monoxide. There is an atmosphere containing elements such as nitrogen dioxide. Furthermore, in the plasma treatment, the substrate 11 side is It is preferable to expose the oxide semiconductor film 18 to the plasma generated without applying IAS. As a result, it is possible to supply oxygen without damaging the oxide semiconductor film 18. Yes, and the amount of oxygen vacancies contained in the oxide semiconductor film 18 can be reduced. Also, etch Impurities remaining on the surface of the oxide semiconductor film 18 after polishing, such as fluorine and chlorine It can remove halogens and other substances. Furthermore, the plasma treatment is performed by heating it to 300°C or higher. It is preferable to carry this out. The oxygen in the plasma and the hydrogen contained in the oxide semiconductor film 18 combine. It then turns into water. Because the substrate is heated, the water detaches from the oxide semiconductor film 18. As a result, the hydrogen and water content in the oxide semiconductor film 18 can be reduced.

[0151] <Modification 5> The transistor 50 shown in this embodiment maintains the substrate at a temperature of 280°C to 400°C. By forming the oxide insulating film 23, hydrogen, water, etc. contained in the oxide semiconductor film 18 are removed. It can be separated. On the other hand, after forming the oxide semiconductor film 18 shown in Figure 4(B), 15 Above 0°C and below the substrate strain point, between 200°C and 450°C, or between 300°C and 450°C. After the heat treatment, the substrate is kept at 180°C to 260°C while the oxide insulating film is applied. 23 may be formed. As a result, the hydrogen, water, etc. content contained in the oxide semiconductor film 18 is Further reduction is possible, and transistors with even better electrical characteristics can be fabricated. It is possible.

[0152] Note that the configuration and methods shown in this embodiment are different from those shown in other embodiments and examples. It can be used in appropriate combination with methods and other techniques.

[0153] (Embodiment 2) In this embodiment, the number of defects in the oxide semiconductor film is further reduced compared to Embodiment 1. A semiconductor device having a transistor capable of performing this function will be described with reference to the drawings. The transistor described in the embodiment has an oxide semiconductor film stacked in comparison with Embodiment 1. It differs in that it has a multilayer film.

[0154] Figure 7 shows a top view and a cross-sectional view of the transistor 60 of the semiconductor device. Figure 7(A) Figure 7(B) is a top view of transistor 60, and Figure 7(A) shows the cross section between the dashed line A and B in Figure 7(A). This is a top view, and Figure 7(C) is a cross-sectional view between the dashed lines C and D in Figure 7(A). Note that Figure 7 (A) For clarity, the substrate 11, gate insulating film 17, oxide insulating film 23, oxide insulating film The edge film 24, nitride insulating film 25, etc., have been omitted.

[0155] The transistor 60 shown in Figures 7(A) to 7(C) is a gate provided on the substrate 11. The electrode 15, the gate insulating film 17, and the gate electrode 15 overlapping via the gate insulating film 17 A multilayer film 20, a pair of electrodes 21 and 22 in contact with the multilayer film 20, a gate insulating film 17, and a multilayer film 20, and a protective film 26 on a pair of electrodes 21, 22, and a gate electrode 29 on the protective film 26, The protective film 26 has an oxide insulating film 23, an oxide insulating film 24, and a nitride insulating film 25 The protective film 26 functions as a gate insulating film.

[0156] In the transistor 60 shown in this embodiment, the multilayer film 20 comprises an oxide semiconductor film 18 and It has an oxide semiconductor film 19. That is, the multilayer film 20 has a two-layer structure. A portion of the body membrane 18 functions as a channel region. Also, in contact with the multilayer film 20, oxidation A material insulating film 23 is formed. Between the oxide semiconductor film 18 and the oxide insulating film 23, A semiconductor film 19 is provided. Furthermore, an oxide insulating film is provided so as to be in contact with the oxide insulating film 23. 24 is formed.

[0157] The oxide semiconductor film 19 is composed of one or more of the elements that make up the oxide semiconductor film 18. It is an oxide film. Therefore, at the interface between the oxide semiconductor film 18 and the oxide semiconductor film 19 Therefore, interfacial scattering is less likely to occur. Consequently, carrier movement is not hindered at the interface. Therefore, the field-effect mobility of the transistor increases.

[0158] The oxide semiconductor film 19 is typically an In-Ga oxide film, an In-Zn oxide film, or an In -M-Zn oxide film (where M is Al, Ga, Y, Zr, La, Ce, or Nd), and The energy at the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 18, and typically, The energy at the lower end of the conduction band of the oxide semiconductor film 19 and the energy at the lower end of the conduction band of the oxide semiconductor film 18 The difference from the energy is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or higher, and 2 eV or lower, 1 eV or lower, 0.5 eV or lower, or 0.4 eV or lower Below. That is, the electron affinity of the oxide semiconductor film 19 and the electron affinity of the oxide semiconductor film 18. The difference is 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0.15eV The values ​​are above the specified threshold, and also below 2 eV, below 1 eV, below 0.5 eV, or below 0.4 eV.

[0159] The oxide semiconductor film 19 has increased carrier mobility (electron mobility) due to the presence of In. Therefore, it is preferable.

[0160] As the oxide semiconductor film 19, Al, Ga, Y, Zr, La, Ce, or Nd is used in In Having a high atomic ratio may have the following effects: (1) Oxide semiconductor film (1) Increase the energy gap of 19. (2) Decrease the electron affinity of the oxide semiconductor film 19. (3) To shield against external impurities. (4) Compared to the oxide semiconductor film 18, it is extremely The affinity for oxygen increases. (5) Al, Ga, Y, Zr, La, Ce, or Nd have a high affinity for oxygen. Because it is a metallic element with a strong resultant force, oxygen deficiency is less likely to occur.

[0161] When the oxide semiconductor film 19 is an In-M-Zn oxide film, the sum of In and M is 100. When expressed as atomic%, the atomic ratio of In to M is such that In is less than 50 atomic%. If M is 50 atomic% or more, or if In is less than 25 atomic% and M is 75a The tomic percentage must be greater than or equal to %.

[0162] Furthermore, the oxide semiconductor film 18 and the oxide semiconductor film 19 are In-M-Zn oxide films (M is In the case of Al, Ga, Y, Zr, La, Ce, or Nd, compared with oxide semiconductor film 18 The oxide semiconductor film 19 contains M(Al, Ga, Y, Zr, La, Ce, or Nd The atomic ratio of ) is large, and typically compared to the above atoms contained in the oxide semiconductor film 18 This represents an atomic ratio that is 1.5 times, 2 times, or 3 times higher.

[0163] Furthermore, the oxide semiconductor film 18 and the oxide semiconductor film 19 are In-M-Zn oxide films (M is In the case of Al, Ga, Y, Zr, La, Ce, or Nd, the oxide semiconductor film 19 is In: M:Zn=x1:y1:z1 [atomic ratio], oxide semiconductor film 18 In:M:Zn=x2 If we set y2:z2 [atomic ratio], then y1 / x1 is greater than y2 / x2, or y 1 / x1 is 1.5 times or more than y2 / x2. Or, y1 / x1 is greater than y2 / x2. It is more than twice as large, or y1 / x1 is more than three times larger than y2 / x2. In this case, In an oxide semiconductor film, if y2 is greater than or equal to x2, the transistor using the oxide semiconductor film This is preferable because it allows for stable electrical characteristics to be imparted to the zista.

[0164] The oxide semiconductor film 18 is an In-M-Zn oxide film (where M is Al, Ga, Y, Zr, La, In the case of Ce or Nd, the target used to deposit the oxide semiconductor film 18 is If we assume that the atomic ratio of the metal elements is In:M:Zn=x1:y1:z1, then 、 x1 / y1 is , 1 / 3 or more and 6 or less, and furthermore 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less Furthermore, it is preferable that it be between 1 and 6. This facilitates the formation of the CAAC-OS film as the oxide semiconductor film 18. Typical examples of atomic ratios of metal elements include In:M:Zn = 1:1:1 and In:M:Zn Examples include =1:1:1.2 and In:M:Zn=3:1:2.

[0165] The oxide semiconductor film 19 is an In-M-Zn oxide film (where M is Al, Ga, Y, Zr, La, In the case of Ce or Nd, the target used to deposit the oxide semiconductor film 19 is If we assume that the atomic ratio of the metal elements is In:M:Zn = x²:y²:z², then 、 x2 / y2< x1 / y1 is such that z2 / y2 is between 1 / 3 and 6, and moreover, between 1 and 6. This is preferable. Furthermore, by setting z2 / y2 to 1 or more and 6 or less, the oxide semiconductor film 19 is formed. This facilitates the formation of CAAC-OS films. Typical examples of atomic ratios of target metal elements are as follows: Therefore, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn= Examples include 1:3:6 and In:M:Zn=1:3:8.

[0166] Furthermore, the atomic ratios of oxide semiconductor film 18 and oxide semiconductor film 19 are, respectively, considered to be within the margin of error. This includes a variation of plus or minus 40% in the above atomic ratio.

[0167] The oxide semiconductor film 19 is used when forming the oxide insulating film 24 that will be formed later. It also functions as a damage-mitigating membrane for membrane 18.

[0168] The thickness of the oxide semiconductor film 19 is 3 nm to 100 nm, or 3 nm to 50 nm. Let's assume that.

[0169] Furthermore, the oxide semiconductor film 19, like the oxide semiconductor film 18, can also have, for example, a non-single crystal structure. Good. Non-single-crystal structures include, for example, CAAC-OS (described later), polycrystalline structures, and microcrystals (described later). Includes a structure, or amorphous structure.

[0170] The oxide semiconductor film 19 may have an amorphous structure, for example. An amorphous oxide semiconductor film is For example, an oxide film with a disordered atomic arrangement and no crystalline components, or an amorphous structure. For example, it has a completely amorphous structure and does not contain any crystalline parts.

[0171] Furthermore, in the oxide semiconductor film 18 and the oxide semiconductor film 19, the amorphous structure is Regions of microcrystalline structure, polycrystalline structure, CAAC-OS, and single-crystal structure A mixed film having two or more regions may be constructed. The mixed film may, for example, have regions with an amorphous structure. The regions of microcrystalline structure, polycrystalline structure, CAAC-OS, and single crystal structure It may be a single-layer structure having two or more of the following regions. Also, the mixed film may have an amorphous structure, for example. Region of structure, region of microcrystalline structure, region of polycrystalline structure, region of CAAC-OS, region of single crystal structure It may have a layered structure in which two or more of the regions are stacked on top of each other.

[0172] Here, an oxide semiconductor film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, impurities are present between the oxide semiconductor film 19 and the oxide insulating film 23. And even if a trap level is formed due to a defect, the trap level and the oxide semiconductor film 18 There is a gap between them. As a result, electrons flowing through the oxide semiconductor film 18 get trapped at the trap level. It is difficult to capture, and it is possible to increase the on-current of the transistor, as well as the field effect Mobility can be increased. Also, when an electron is trapped at a trap level, that electron becomes This results in a fixed charge on the eggplant. As a result, the transistor's threshold voltage fluctuates. However, because there is a gap between the oxide semiconductor film 18 and the trap level, It is possible to reduce electron trapping at the top level and reduce fluctuations in the threshold voltage. It is possible.

[0173] Furthermore, the oxide semiconductor film 19 can shield against external impurities, It is possible to reduce the amount of impurities that move from the part to the oxide semiconductor film 18. The material semiconductor film 19 is less likely to form oxygen vacancies. For these reasons, in the oxide semiconductor film 18 It is possible to reduce the concentration of impurities and the amount of oxygen deficiency.

[0174] Furthermore, the oxide semiconductor film 18 and the oxide semiconductor film 19 are not simply stacked on top of each other. A continuous junction (in this context, a structure in which the energy at the lower end of the conduction band changes continuously between each film). The film is fabricated so that trap centers and recombination centers are formed at the interface of each film. The layered structure is designed so that no impurities that form defect levels exist. If impurities are present between the material semiconductor film 18 and the oxide semiconductor film 19, energy bands may form. The continuity of the carriers is lost, and carriers are trapped or recombine at the interface and disappear. Mau.

[0175] To form continuous bonding, a multi-chamber type film deposition system equipped with a load lock chamber is required. By using a sputtering device, each film is continuously layered without being exposed to the atmosphere. This is necessary. Each chamber in the sputtering apparatus is for the oxide semiconductor film To remove impurities such as water as much as possible, an adsorption-type vacuum pump such as a cryopump is used. Using a pump to perform high vacuum evacuation (5×10 -7 Pa~1×10 -4It is preferable to do so (up to about Pa). It seems so. Alternatively, you can combine a turbomolecular pump and a cold trap to remove air from the exhaust system. It is preferable to prevent gases, especially those containing carbon or hydrogen, from flowing back into the bar. stomach.

[0176] Note that instead of the multilayer film 20, a multilayer film 3 can be used, as shown in the transistor 65 in Figure 7(D). It may have 4.

[0177] The multilayer film 34 comprises an oxide semiconductor film 31, an oxide semiconductor film 18, and an oxide semiconductor film 19. It has. That is, the multilayer film 34 has a three-layer structure. Also, the oxide semiconductor film 18 has a channel region. It functions as such.

[0178] Furthermore, the gate insulating film 17 and the oxide semiconductor film 31 are in contact. That is, the gate insulating film 17 and An oxide semiconductor film 31 is provided between the oxide semiconductor film 18 and the oxide semiconductor film 31.

[0179] Furthermore, the multilayer film 34 and the oxide insulating film 23 are in contact. Also, the oxide semiconductor film 19 and the oxide The oxide insulating film 23 is in contact with the oxide semiconductor film 18. That is, between the oxide semiconductor film 18 and the oxide insulating film 23, A semiconductor film 19 is provided.

[0180] The oxide semiconductor film 31 is formed using the same materials and formation methods as the oxide semiconductor film 19, as appropriate. It is possible.

[0181] Preferably, the oxide semiconductor film 31 has a thinner film thickness than the oxide semiconductor film 18. By making the thickness of the body membrane 31 between 1 nm and 5 nm, or between 1 nm and 3 nm, It is possible to reduce the fluctuation in the threshold voltage of the transistor.

[0182] The transistor shown in this embodiment has a layer between the oxide semiconductor film 18 and the oxide insulating film 23. An oxide semiconductor film 19 is provided. Therefore, the oxide semiconductor film 19 and the oxide insulating film are provided. Even if a trap level is formed due to impurities and defects during 23, the trap level There is a gap between the position and the oxide semiconductor film 18. As a result, the flow through the oxide semiconductor film 18 Electrons are less likely to be trapped at the trap level, and the on-current of the transistor can be increased. It is capable of increasing field-effect mobility. Furthermore, electrons can be trapped in the trap level. When captured, the electron becomes a negative fixed charge. As a result, the transistor The key voltage fluctuates. However, between the oxide semiconductor film 18 and the trap level Because there is a gap, it is possible to reduce electron trapping at the trap level, This can reduce fluctuations in the key voltage.

[0183] Furthermore, the oxide semiconductor film 19 can shield against external impurities, It is possible to reduce the amount of impurities that move from the part to the oxide semiconductor film 18. The material semiconductor film 19 is less likely to form oxygen vacancies. For these reasons, in the oxide semiconductor film 18 It is possible to reduce the concentration of impurities and the amount of oxygen deficiency.

[0184] Furthermore, an oxide semiconductor film 31 is provided between the gate insulating film 17 and the oxide semiconductor film 18. An oxide semiconductor film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, near the interface between the oxide semiconductor film 31 and the oxide semiconductor film 18, silicon The concentration of silicon and carbon, the concentration of silicon and carbon in the oxide semiconductor film 18, or the oxide semiconductor To reduce the concentration of silicon and carbon near the interface between the body film 19 and the oxide semiconductor film 18. This can be achieved. As a result, in the multilayer film 34, the absorption ratio derived by the constant photocurrent measurement method is The number is 1 × 10 -3 Less than / cm, or 1 × 10 -4 It becomes less than / cm, and the localization level is extremely low. There are very few.

[0185] The transistor 65 having such a structure is a multilayer film 34 including an oxide semiconductor film 18. Because it has very few defects, it is possible to improve the electrical characteristics of the transistor. Typically, this allows for an increase in on-current and an improvement in field-effect mobility. Also, stress Fluctuation of threshold voltage in BT stress tests and photo-BT stress tests, which are examples of tests. It is small in quantity and highly reliable.

[0186] <Transistor Band Structure> Next, the multilayer film 20 provided on the transistor 60 shown in Figure 7(A), and Figure 7(D) The band structure of the multilayer film 34 provided on the transistor 65 shown will be explained using Figure 8. do.

[0187] Here, as an example, the oxide semiconductor film 18 has an energy gap of 3.15 eV. Using a certain InGa-Zn oxide, the oxide semiconductor film 19 has an energy gap of 3 An In-Ga-Zn oxide with an energy gap of 0.5 eV is used. The energy gap is measured using a spectroscopic ellipsoid. Measurement should be performed using a meter (HORIBA JOBIN YVON UT-300). It is possible.

[0188] Energy difference between the vacuum level and the upper edge of the valence band of oxide semiconductor film 18 and oxide semiconductor film 19 The ionization potentials (also called ionization potentials) were 8 eV and 8.2 eV, respectively. The energy difference between the vacuum level and the upper end of the valence band is determined by ultraviolet photoelectron spectroscopy (UPS: Ultr Aviolet Photoelectron Spectroscopy (PH) apparatus Measurements can be taken using Company I's VersaProbe.

[0189] Therefore, the vacuum level of the oxide semiconductor film 18 and the oxide semiconductor film 19 and the lower edge of the conduction band The energy differences (also called electron affinity) are 4.85 eV and 4.7 eV, respectively.

[0190] Figure 8(A) schematically shows a part of the band structure of the multilayer film 20. Here, multilayer The case in which a silicon oxide film is provided in contact with film 20 will be explained. Note that this is shown in Figure 8(A). EcI1 represents the energy at the lower end of the conduction band of a silicon oxide film, and EcS1 represents the energy of an oxide semiconductor film. 18 shows the energy at the lower end of the conduction band, and EcS2 is the energy at the lower end of the conduction band of the oxide semiconductor film 19. EcI2 represents energy, and EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. cI1 corresponds to the gate insulating film 17 in Figure 7(B), and EcI2 corresponds to the gate insulating film 17 in Figure 7(B). In this context, it corresponds to the oxide insulating film 23.

[0191] As shown in Figure 8(A), in oxide semiconductor film 18 and oxide semiconductor film 19, conduction The energy at the bottom of the belt changes smoothly without any barriers. In other words, it changes continuously. It can also be said that the multilayer film 20 contains elements common to the oxide semiconductor film 18, Between the oxide semiconductor film 18 and the oxide semiconductor film 19, oxygen moves toward each other, forming a mixed layer. It can be said that this is because it is formed.

[0192] From Figure 8(A), the oxide semiconductor film 18 of the multilayer film 20 becomes a well, and the multilayer film 2 In a transistor using 0, the channel region is formed in the oxide semiconductor film 18. This can be understood. Furthermore, since the energy at the lower end of the conduction band of the multilayer film 20 changes continuously, It can also be said that the oxide semiconductor film 18 and the oxide semiconductor film 19 are continuously bonded together.

[0193] Furthermore, as shown in Figure 8(A), near the interface between the oxide semiconductor film 19 and the oxide insulating film 23 Nearby, trap levels may form due to impurities and defects, but oxide semiconductor film 1 The provision of 9 allows the oxide semiconductor film 18 and the trap level to be kept apart. Yes. However, if the energy difference between EcS1 and EcS2 is small, the oxide semiconductor film 18 Electrons may exceed the energy difference and reach the trap level. When these particles are trapped, a negative charge is generated at the oxide insulating film interface, which is the threshold of the transistor. The voltage value shifts in the positive direction. Therefore, the energy between EcS1 and EcS2 - If the difference is 0.1 eV or more, or 0.15 eV or more, the threshold voltage of the transistor... This is preferable because it reduces pressure fluctuations and results in stable electrical characteristics.

[0194] Furthermore, Figure 8(B) schematically shows a part of the band structure of the multilayer film 20, as shown in Figure 8(A). This is a modified example of a band structure. Here, a silicon oxide film is provided in contact with the multilayer film 20. Let's explain the relationship. Note that EcI1 shown in Figure 8(B) is the lower end of the conduction band of the silicon oxide film. EcS1 indicates the energy at the lower end of the conduction band of the oxide semiconductor film 18. cI2 represents the energy at the lower end of the conduction band of the silicon oxide film. EcI1 is shown in Figure 7(B). In Figure 7(B), EcI2 corresponds to the gate insulating film 17, and in Figure 7(B), it is an oxide insulating film. This corresponds to membrane 23.

[0195] In the transistor shown in Figure 7(B), when the pair of electrodes 21 and 22 are formed, the multilayer film 20 In some cases, the oxide semiconductor film 19 may be etched above it. The upper surface of the body film 18 is formed when the oxide semiconductor film 19 is deposited between the oxide semiconductor film 18 and the oxide semiconductor film 19 mixed layers may be formed.

[0196] For example, the oxide semiconductor film 18 has an In:Ga:Zn=1:1:1 [atomic ratio] In- Ga-Zn oxide, or In-Ga-Zn with an atomic ratio of In:Ga:Zn=3:1:2 This is an oxide semiconductor film deposited using an oxide as a sputtering target, The semiconductor film 19 is an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2. In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:4, or In: In-Ga-Zn oxide with a Ga:Zn = 1:3:6 [atomic ratio] is used as a sputtering target. In the case of an oxide semiconductor film formed using a net, the oxide semiconductor film 18 is larger than the oxide semiconductor film 18. Because the conductive film 19 has a high Ga content, a GaOx layer is formed on the upper surface of the oxide semiconductor film 18. A mixed layer containing more Ga than the oxide semiconductor film 18 can be formed.

[0197] Therefore, even when the oxide semiconductor film 19 is etched, the Ec of EcS1 The energy at the lower end of the conduction band on the I2 side increases, resulting in the band structure shown in Figure 8(B). There are cases where this is the case.

[0198] When the band structure is as shown in Figure 8(B), when observing the cross-section of the channel region, The multilayer film 20 may appear to be only the oxide semiconductor film 18. However, In essence, the oxide semiconductor film 18 contains a mixture that has more Ga than the oxide semiconductor film 18. Since a composite layer is formed, the mixed layer can be considered as layer 1.5. When the elements contained in the multilayer film 20 are measured, for example by EDX analysis, the mixed layer is... This can be confirmed by analyzing the composition of the upper part of the oxide semiconductor film 18. For example, The composition of the upper part of the material semiconductor film 18 has a higher Ga content than the composition within the oxide semiconductor film 18. This can be confirmed by looking at the configuration.

[0199] Figure 8(C) schematically shows a portion of the band structure of the multilayer film 34. Here, multilayer The case in which a silicon oxide film is provided in contact with film 34 will be explained. EcI1 represents the energy at the lower end of the conduction band of a silicon oxide film, and EcS1 represents the energy of an oxide semiconductor film. 18 shows the energy at the lower end of the conduction band, and EcS2 is the energy at the lower end of the conduction band of the oxide semiconductor film 19. EcS3 indicates the energy, and EcS3 indicates the energy at the lower end of the conduction band of the oxide semiconductor film 31. I2 represents the energy at the lower end of the conduction band of the silicon oxide film. EcI1 is shown in Figure 7(D). In this case, it corresponds to the gate insulating film 17, and EcI2 is, in Figure 7(D), an oxide insulating film. It corresponds to 23.

[0200] As shown in Figure 8(C), oxide semiconductor film 31, oxide semiconductor film 18, and oxide semiconductor In the body membrane 19, the energy at the lower end of the conduction band changes smoothly without barriers. In other words... It can also be said that it changes continuously. This is because the multilayer film 34 is an oxide semiconductor film 1 It contains elements common to 8, and between the oxide semiconductor film 18 and the oxide semiconductor film 31, A mixed layer is formed between the body film 18 and the oxide semiconductor film 19 by the mutual movement of oxygen. It can be said that this is for that purpose.

[0201] From Figure 8(C), the oxide semiconductor film 18 of the multilayer film 34 becomes a well, and the multilayer film 3 In a transistor using 4, the channel region is formed in the oxide semiconductor film 18. This can be understood. Furthermore, in the multilayer film 34, the energy at the lower end of the conduction band changes continuously, The oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor film 19 are continuously bonded together. It could also be said that...

[0202] Furthermore, near the interface between the oxide semiconductor film 18 and the oxide insulating film 23, the oxide semiconductor film 18 and In the vicinity of the interface with the gate insulating film 17, trap levels are formed due to impurities and defects. However, as shown in Figure 8(C), the oxide semiconductor films 19 and 31 are provided. This allows the oxide semiconductor film 18 and the trap level to be kept apart. However, EcS1 When the energy difference between EcS2 and EcS1 and EcS3 is small, Electrons in the oxide semiconductor film 18 may exceed the energy difference and reach the trap level. When electrons are trapped in the trap level, a negative charge is generated at the oxide insulating film interface, The threshold voltage of the transistor shifts in the positive direction. Therefore, EcS1 and E The energy difference with cS2, and the energy difference between EcS1 and EcS3, must be 0.1 eV or greater. Setting it to 0.15eV or higher reduces the fluctuation in the transistor's threshold voltage, making it safer. It is suitable because it provides stable electrical characteristics.

[0203] Note that the configurations and methods shown in this embodiment may differ from those shown in other embodiments. It can be used in appropriate combinations.

[0204] (Embodiment 3) In this embodiment, in the dual-gate transistor shown in Embodiment 2, Figure 7 shows the electrical characteristics of a transistor when different gate electrodes are connected and brought to the same potential. This will be explained using Figures 26 to 31.

[0205] In this case, the gate electrode 15 and gate electrode 29 shown in Figure 7 are electrically short-circuited. A driving method that applies a gate voltage in addition to the gate voltage is called Dual Gate driving. In an all-gate drive, the voltage of gate electrode 15 and the voltage of gate electrode 29 are always equal. It will get worse.

[0206] Here, we calculated the electrical characteristics of the transistor. Figure 26 shows the transistor used in the calculation. The structure of the device is shown. Note that the calculations were performed using the device simulation software Atlas(Sil). (Vaco Corporation) was used.

[0207] The transistor of structure 1 shown in Figure 26(A) is a dual-gate transistor. ru.

[0208] In the transistor of structure 1, an insulating film 203 is formed on the gate electrode 201, and insulating film 20 An oxide semiconductor film 205 is formed on 3. On the insulating film 203 and the oxide semiconductor film 205 A pair of electrodes 207, 208 are formed, and an oxide semiconductor film 205 and a pair of electrodes 207, 2 An insulating film 209 is formed on 08. A gate electrode 213 is formed on the insulating film 209. Furthermore, the gate electrodes 201 and 213 are formed in the insulating film 203 and 209. It is connected at the opening (not shown).

[0209] The transistor in structure 2 shown in Figure 26(B) is a single-gate transistor. .

[0210] In the transistor of structure 2, an insulating film 203 is formed on the gate electrode 201, and the insulating film 20 An oxide semiconductor film 205 is formed on 3. On the insulating film 203 and the oxide semiconductor film 205 A pair of electrodes 207, 208 are formed, and an oxide semiconductor film 205 and a pair of electrodes 207, 2 An insulating film 209 is formed on 08.

[0211] Note that in the calculation, the work function φ of gate 201 is used. M The voltage was set to 5.0eV. Film 203 was defined as a film with a dielectric constant of 4.1 and a thickness of 100 nm. Oxide semiconductor film 20 For option 5, we assume a single layer of In-Ga-Zn oxide film (In:Ga:Zn=1:1:1). Bandgap E of In-Ga-Zn oxide film g 3.15 eV, electron affinity χ = 4.6 eV, relative permittivity of 15, electron mobility of 10 cm 2 Let / Vs be the donor density N d 3 x 10 17 atoms / cm 3 The work function φ of the pair of electrodes 207 and 208 was set as follows. sd 4. The dielectric constant was set to 6 eV, and an ohmic junction was established with the oxide semiconductor film 205. The ratio was set to 4.1 and the thickness to 100 nm. Models such as depression levels and surface scattering are not considered. Also, the transistor channel length and The channel widths were set to 10 μm and 100 μm, respectively.

[0212] <Reducing initial characteristic variation> By using dual gate drive as shown in the transistor in Structure 1, the initial characteristics are Variation can be reduced. This is achieved by using Dual Gate drive, Id -Threshold voltage V of Vg characteristic th The amount of variation is smaller compared to the transistor shown in Structure 2. It results from becoming.

[0213] Here, as an example, the negative shift in Id-Vg characteristics due to the n-type semiconductor film Let me explain.

[0214] Let Q(C) be the total charge of the donor ions, and the gate electrode 201, insulating film 203, and The capacitance formed by the oxide semiconductor film 205 is C Bottom The oxide semiconductor film 205, The capacitance formed by the insulating film 209 and the gate electrode 213 is C Top Let it be so. At this time, The V of the transistor shown in Structure 1 th The variation ΔV is shown in equation (2). Also, as shown in structure 2. Transistor V th The variation ΔV is shown in equation (3).

[0215]

number

[0216]

number

[0217] As shown in equation (2), a dual-gate drive like the transistor shown in structure 1. So, the capacitance between the donor ion and the gate electrode is C Bottom、and C Top The sum of Therefore, the fluctuation amount of the threshold voltage becomes smaller.

[0218] Furthermore, in the transistors of structure 1 and structure 2, the drain voltage is 0.1V. Figure 27 shows the calculated current-voltage curve when the voltage is 1V. Note that Figure 27(A) is a structure Figure 27(B) shows the current-voltage curve of the transistor shown in Structure 1, and the transistor shown in Structure 2 This is the current-voltage curve of the transistor. When the drain voltage Vd is 0.1V, the transient shown in Structure 1 The threshold voltage of the transistor is -2.26V, and the threshold voltage of the transistor shown in Structure 2 is The voltage was -4.73V.

[0219] When dual gate drive is adopted, as in the transistor shown in Structure 1, the threshold Voltage fluctuations are reduced. Therefore, variations in the electrical characteristics of multiple transistors This is also reduced at the same time.

[0220] Note that here we considered the negative shift in threshold voltage due to donor ions, but isolation Fixed charges, mobile charges, or negative charges (acceptors) in film 203 and insulating film 209 The positive shift in threshold voltage caused by electrons trapped in certain energy levels is similarly suppressed. Therefore, it is thought that the variability will be reduced.

[0221] <- Suppression of degradation in GBT stress tests> Furthermore, by using dual gate drive as shown in the transistor in Structure 1, -G Degradation of BT stress tests can be reduced. Below is the degradation of GBT stress tests. We will explain why it can be reduced.

[0222] The first reason is that by using dual gate drive, electrostatic stress is avoided. There is a point to note. In Figure 28(A), in the transistor of structure 1, the gate electrode 201 and the gate The potential contour lines were plotted when -30V was applied to each of the electrode 213. The figure is shown. Also, in Figure 28(B), the potential at the AB section of Figure 28(A) is shown. show.

[0223] The oxide semiconductor film 205 is an intrinsic semiconductor, and a negative voltage is applied to the gate electrodes 201 and 213. When charged and completely depleted, no charge exists between gate electrodes 201 and 213. No. In this state, if gate electrode 201 and gate electrode 213 are made to the same potential, Figure 28( As shown in B), the potentials between gate electrode 201 and gate electrode 213 are perfectly equipotential. Because the potentials are equal, electrostatic discharge occurs between the insulating film 203, the oxide semiconductor film 205, and the insulating film 209. No response occurs. As a result, mobile ions and the film in insulating film 203 and insulating film 209 are not affected. Phenomena that cause degradation in the GBT stress test, such as rear trapping and detrapping, occur. do not.

[0224] The second reason is that by using dual gate drive, the power from the outside of the FET is reduced. The field is shielded. Here, the transistor of structure 1 shown in Figure 26(A), and In each transistor of structure 2 shown in Figure 26(B), the insulating film 209 or the gate Figure 29 shows a model in which charged particles from the air are adsorbed onto electrode 213.

[0225] As shown in Figure 29(B), in the transistor shown in structure 2, the insulating film 209 surface Positively charged particles from the air are attracted to it. When a negative voltage is applied to the gate electrode 201, positive Charged particles are adsorbed onto the insulating film 209. As a result, as shown by the arrow in Figure 29(B), The electric field of the charged particles affects the interface of the oxide semiconductor film 205 to the insulating film 209, and is substantially positive. This results in a bias being applied. As a result, the threshold voltage is thought to shift negative. It can be done.

[0226] On the other hand, as shown in Figure 29(A), in the transistor shown in structure 1, the gate electrode Even if positively charged particles adhere to the surface of 213, as shown by the arrow in Figure 29(A), The electrode 213 shields the electric field of positively charged particles, thus affecting the electrical characteristics of the transistor. Electric particles do not have an effect. That is, if the gate electrode 213 is present, the transistor will not be affected by external charges. The DISTA can be electrically protected, and degradation during GBT stress testing is suppressed. .

[0227] For the two reasons mentioned above, in dual-gate driven transistors, -GBT The degradation of the trace test is suppressed.

[0228] <Suppression of fluctuations in the on-current rise voltage at different drain voltages> Here, in the case of structure 2, the rise voltage of the on-current at different drain voltages. This section explains the fluctuations and their causes.

[0229] The transistor shown in Figure 30 has a gate insulating film 233 provided on the gate electrode 231. An oxide semiconductor film 235 is provided on the gate insulating film 233. A pair of electrodes 237 and 238 are provided, along with a gate insulating film 233, an oxide semiconductor film 235, and An insulating film 239 is provided on a pair of electrodes 237 and 238.

[0230] Note that in the calculation, the work function φ of gate electrode 231 is used. M I set it to 5.0eV. The insulating film 233 consists of a film with a dielectric constant of 7.5 and a thickness of 400 nm, and a film with a dielectric constant of 4.1. The structure was set to a stacked film with a thickness of 50 nm. The oxide semiconductor film 235 is In-Ga-Z Assuming a single layer of n oxide film (In:Ga:Zn=1:1:1), the In-Ga-Zn oxide film Band gap E g With a dielectric constant of 3.15 eV, electron affinity χ of 4.6 eV, relative permittivity of 15, and electric charge Child movement range 10cm 2 Let / Vs be the donor density N d is 1 x 10 13 / cm 3 I set it to that. Work function φ of the pair of electrodes 237 and 238 sd With a voltage of 4.6 eV, the oxide semiconductor film 235 and An ohmic junction was set. The dielectric constant of insulating film 239 was set to 3.9, and its thickness to 550 nm. The settings have been configured. Note that models for defect levels and surface scattering in the oxide semiconductor film 235 have been considered. It has not been done. Also, the channel length and channel width of the transistor are 3 μm and 50 μm, respectively. The unit was expressed as μm.

[0231] Next, in the transistor shown in Figure 30(A), positively charged particles are present on the surface of the insulating film 239. Models of the adsorbed transistors are shown in Figures 30(B) and 30(C). Note that Figure 30( In B), a structure is assumed in which a uniform positive fixed charge is assumed on the surface of the insulating film 239, as shown in Figure 3. At 0(C), the structure partially assumes a positive fixed charge on the surface of the insulating film 239. .

[0232] Figure 31 shows the results of calculating the electrical characteristics of the transistors shown in Figures 30(A) to 30(C). (A) to Figure 31(C) are shown.

[0233] As shown in Figure 31(A), the insulating film 239 of the transistor shown in Figure 30(A) has a positive solid When a constant charge is not assumed, the drain voltage (Vd) is 1V and 10V, respectively The rise voltages are almost identical.

[0234] On the other hand, as shown in Figure 31(B), the insulating film 239 of the transistor shown in Figure 30(B) Assuming a uniform positive fixed charge, the threshold voltage is shifted negatively. On the other hand, The drain voltages (Vd) are 1V and 10V, and their respective rise voltages are approximately the same.

[0235] Furthermore, as shown in Figure 31(C), the insulating film 239 of the transistor shown in Figure 30(C) If we partially assume a positive fixed charge, the drain voltage (Vd) is 1V and 10V, Their rise voltages are different.

[0236] On the other hand, in the transistor shown in structure 1, the gate electrode 213 is provided. As explained above in <<Suppression of Degradation in GBT Stress Test>, the gate electrode 213 is external Because the electric field of the charged particles in the region is shielded, the charged particles do not affect the electrical characteristics of the transistor. In other words, having a gate electrode 213 electrically protects the transistor from external charges. It is possible to control the variation in the on-current rise voltage at different drain voltages. It can be suppressed.

[0237] Based on the above, a dual-gate structure is adopted, and an arbitrary voltage is applied to each gate electrode. Therefore, the degradation of the GBT stress test and the rise of the on-current at different drain voltages are suppressed. It is possible to suppress fluctuations in the rising voltage. In addition, a dual gate structure is used, and each gate electrode By applying a voltage of the same potential, reduction of initial characteristic variations, suppression of deterioration in the GBT stress test, and suppression of variations in the rise voltage of the on-current at different drain voltages are possible. and there is.

[0238] <Regarding the distance between the end of the gate electrode and the end of the oxide semiconductor film in the channel width direction and the variation amount of the threshold voltage> Fig. 32 shows a schematic cross-sectional view in the channel width direction of the transistor shown in Structure 1. Note that each configuration in the schematic cross-sectional view of the transistor shown in Fig. 32 has a different scale from each configuration of Structure 1 shown in Fig. 26(A).

[0239] Here, in the channel width direction of the transistor shown in Structure 1, although the gate electrode 201 and the gate electrode 213 protrude by t2 in the channel width direction from the oxide semiconductor film 205, a structure in which there is no gate electrode facing the side surface of the oxide semiconductor film 205 is defined as Structure 3 (see Fig. 32(A)).

[0240] At this time, when the transistor shown in Structure 3 is driven by Dual Gate, the variation amount ΔV4 of V due to the charge amount Q (C / m ) is as shown in Equation (4). 2 th

[0241]

Equation

[0242] Note that the situation where the variation amount of V in the transistor can be expressed by Equation (4) is limited to the case where the charge on the side surface of the oxide semiconductor film 205 is the main factor causing the shift of V. th [[ID=****]] th For example, the gate electrode 201 or the gate electrode 213 is from the oxide semiconductor film 205 to the channel When not protruding in the channel width direction, parasitic channels may be formed by the charges of donor ions on the side surfaces of the oxide semiconductor film 205. In contrast, in the case of Structure 3, according to Equation ( 4), the influence of charges is suppressed.

[0243] As described above, as the origin of charges, donor ions on the side surfaces of the oxide semiconductor film 205 are assumed. However, even if they are fixed charges in the insulating film, the insulating film interface, or the oxide semiconductor film, or electrons or holes trapped in trap levels, the same discussion holds when they are the main factors causing the shift of V th .

[0244] As a more generalized case of Structure 3, consider Structure 4 in which the gate electrode 201 and the gate electrode 213 each protrude by X and X B in the channel width direction more than the oxide semiconductor film T 205 (see Fig. 32(B)). At this time, C and C Bottom and C Top can be rewritten as in Equation (5) and Equation (6), respectively.

[0245]

Equation

[0246]

Equation

[0247] When X B and X T are changed, Equation (5) and Equation (6) become X B = t1 + t os and X T = t3 + t os ​The maximum value C shown in equation (7) is shown by equation (7). Bottom Max and formula (8) C shown Top Max Take it.

[0248]

number

[0249]

number

[0250] Therefore, based on equation (4), V th To minimize the variation of X, B =t1 +t os , X T = t³ + t os That would be fine.

[0251] Note that the configurations and methods shown in this embodiment may differ from those shown in other embodiments. It can be used in appropriate combinations.

[0252] (Embodiment 4) In this embodiment, a semiconductor device, which is one aspect of the present invention, will be described with reference to the drawings. In this embodiment, a semiconductor device, which is one aspect of the present invention, will be described using a display device as an example. do.

[0253] Figure 9(A) shows an example of a semiconductor device. The semiconductor device shown in Figure 9(A) has a pixel section 10 1, the scan line drive circuit 104, and the signal line drive circuit 106 are arranged in parallel or approximately parallel to each other. m scan lines 107 are provided and whose potential is controlled by the scan line drive circuit 104, and each They are arranged in parallel or nearly parallel, and their potential is controlled by the signal line drive circuit 106. It has n signal lines 109 and, furthermore, the pixel section 101 is arranged in a matrix. It has 100 pixels. Furthermore, each is arranged parallel or nearly parallel to the signal line 109. It has capacitance lines 115. The capacitance lines 115 are arranged along the scan lines 107, and each is flat They may be arranged in rows or approximately parallel. Also, the scan line drive circuit 104 and the signal line drive circuit Sometimes, the entire section 106 is referred to as the drive circuit section.

[0254] Each scan line 107 is among the pixels 100 arranged in m rows and n columns in the pixel section 101. It is electrically connected to n pixels 100 arranged in any row. Also, each signal line 109 This refers to m pixels 10 arranged in m rows and n columns, where m pixels 10 are located in any of the columns. It is electrically connected to 0. m and n are both integers greater than or equal to 1. Also, each capacitance line 115 This refers to n pixels 10 located in any row among the m rows and n columns of pixels 100. It is electrically connected to 0. Note that the capacitance line 115 runs parallel to the signal line 109. Or, if they are arranged in roughly parallel directions, any of the pixels 100 arranged in m rows and n columns m pixels 100 arranged in a row are electrically connected.

[0255] Figures 9(B) and (C) can be used for pixel 100 of the display device shown in Figure 9(A). An example of a circuit configuration is shown.

[0256] The pixel 100 shown in Figure 9(B) consists of a liquid crystal element 121, a transistor 103, and a capacitive element. It has 105 and

[0257] The potential of one of the pair of electrodes of the liquid crystal element 121 is set appropriately according to the specifications of the pixel 100. The orientation state of the liquid crystal element 121 is set according to the data being written to it. A common potential (common) is applied to one of the pair of electrodes of the liquid crystal element 121 that each pixel 100 possesses. A potential may be applied. Also, one of the pair of electrodes of the liquid crystal element 121 for every 100 pixels in each row. You may apply different potentials to them.

[0258] Furthermore, the liquid crystal element 121 controls the transmission or non-transmission of light through the optical modulation effect of the liquid crystal. It is an element that does this. Furthermore, the optical modulation effect of liquid crystals is due to the electric field (horizontal electric field, vertical electric field) applied to the liquid crystal. It is controlled by an electric field in the direction or an electric field in the oblique direction. Note that the liquid crystal element 121 is For example, nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, and thermotropic liquid crystals. Examples include liotropic liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals.

[0259] The driving method for the display device having the liquid crystal element 121 is, for example, TN mode, VA mode ASM (Axially Symmetric Aligned Micro-ce) ll) mode, OCB (Optically Compensated Birefringence) PVA mode, MVA mode, PVA (Patterned Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transfer) You may also use modes such as (Sverse Bend Alignment). However, However, various liquid crystal elements and their driving methods can be used.

[0260] Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element may be constructed in this manner. The liquid crystal exhibiting the blue phase has a response speed of 1 msec or less. Because it is short and optically isotropic, orientation processing is unnecessary and it has low dependence on the viewing angle.

[0261] In the configuration of the pixel 100 shown in Figure 9(B), the source electrode and the d One end of the rain electrode is electrically connected to the signal line 109, and the other end is connected to a pair of liquid crystal elements 121. It is electrically connected to the other electrode. Also, the gate electrode of transistor 103 is connected to scan line 1 It is electrically connected to 07. Transistor 103 can be in an on or off state. This provides a function to control the writing of data to the data signal.

[0262] In the configuration of the pixel 100 shown in Figure 9(B), one of the pair of electrodes of the capacitive element 105 is It is electrically connected to the capacitance line 115 to which the potential is supplied, and the other end is a pair of electrical connections to the liquid crystal element 121. It is electrically connected to the other pole. Note that the potential value of capacitance line 115 is specified in the specifications of pixel 100. It is set appropriately accordingly. The capacitive element 105 is a retaining capacitance that holds the written data. It has the function of being functional.

[0263] For example, in the display device having pixel 100 as shown in Figure 9(B), the scan line drive circuit 104 Each row of pixels 100 is selected sequentially, and transistor 103 is turned on to set the data signal. Write "Ta".

[0264] The pixel 100 on which data has been written is retained when transistor 103 is turned off. This is the state it enters. By doing this sequentially for each row, the image can be displayed.

[0265] Furthermore, the pixel 100 shown in Figure 9(C) is a transistor 1 that performs switching of the display element. 33, transistor 103 which controls the driving of the pixels, transistor 135, and capacitive element It has 105 and a light-emitting element 131.

[0266] One of the source and drain electrodes of transistor 133 is supplied with a data signal. It is electrically connected to signal line 109. Furthermore, the gate electrode of transistor 103 is connected to the gate The scan line 107 to which the signal is applied is electrically connected.

[0267] Transistor 133, by being in an ON or OFF state, controls the data signal. It has a function to control the writing of data.

[0268] One of the source and drain electrodes of transistor 103 functions as the anode wire. The wiring 137 is electrically connected to the source and drain electrodes of transistor 103. The other end is electrically connected to one electrode of the light-emitting element 131. Furthermore, transistor 10 The gate electrode of 3 is the source electrode and the other drain electrode of transistor 133, and the capacitance It is electrically connected to one electrode of element 105.

[0269] Transistor 103, by being in an ON or OFF state, affects the light-emitting element 131. It has the function of controlling the flow of electric current.

[0270] The source electrode and drain electrode of transistor 135 are given a data reference potential. The wiring 139 is connected, and the source electrode and the other drain electrode of transistor 135 are The light-emitting element 131 is electrically connected to one electrode, and the capacitive element 105 is electrically connected to the other electrode. Furthermore, the gate electrode of transistor 135 is connected to scan line 107 to which the gate signal is applied. It is electrically connected.

[0271] Transistor 135 has the function of adjusting the current flowing to the light-emitting element 131. For example If the internal resistance of the light-emitting element 131 increases due to deterioration or other reasons, the transient The current flowing through wiring 139 to which one of the source and drain electrodes of station 135 is connected is By monitoring, the current flowing through the light-emitting element 131 can be corrected. Wiring 1 The potential applied to 39 can be, for example, 0V.

[0272] One of the pair of electrodes of the capacitive element 105 is connected to the source electrode and drain of the transistor 103. The other electrode and the gate electrode of transistor 133 are electrically connected, and the capacitive element 105 The other of the pair of electrodes is the other of the source electrode and drain electrode of transistor 135, and It is electrically connected to one electrode of the light-emitting element 131.

[0273] In the pixel 100 configuration shown in Figure 9(C), the capacitive element 105 receives the written data. It functions as a holding capacity for retaining [something].

[0274] One of the pair of electrodes of the light-emitting element 131 is the source electrode and drain electrode of the transistor 135. The other electrode, the other electrode of the capacitive element 105, and the source electrode and the drive of the transistor 103. It is electrically connected to the other electrode of the rain electrode. Also, the other electrode of the pair of electrodes of the light-emitting element 131 is It is electrically connected to wiring 141, which functions as a cathode.

[0275] The light-emitting element 131 can be, for example, an organic electroluminescent element (also known as an organic EL element). (These can be used.) However, the light-emitting element 131 is not limited to these. Inorganic EL elements made of inorganic materials may also be used.

[0276] Furthermore, a high power supply potential VDD is applied to one of the wires 137 and 141, and the other is A low power supply potential VSS is applied. In the configuration shown in Figure 9(C), a high power supply is supplied to wiring 137. The configuration provides the source potential VDD to the wiring 141 and the low power supply potential VSS to the wiring 141.

[0277] In the display device having pixels 100 as shown in Figure 9(C), the scanning line driving circuit 104 drives each row of pixels Select element 100 sequentially, turn on transistor 102, and write the data signal. It gets crowded.

[0278] The pixel 100 on which data has been written is retained when transistor 103 is turned off. This is the state. Furthermore, since transistor 103 is connected to capacitive element 105, writing It becomes possible to retain the entered data for a long time. Also, thanks to transistor 133, The amount of current flowing between the source electrode and the drain electrode is controlled, and the light-emitting element 131 is controlled by the flow of current. It emits light with brightness corresponding to the flow rate. By performing this sequentially for each row, an image can be displayed.

[0279] Next, a specific example of a liquid crystal display device using liquid crystal elements in pixel 100 will be described. Here, Figure 10 shows a top view of pixel 100, which is shown in Figure 9(B). Note that in Figure 10... This omits the counter electrode and liquid crystal element.

[0280] In Figure 10, the conductive film 304c, which functions as a scan line, is oriented in a direction approximately perpendicular to the signal line. It is provided extending in the left-right direction in the diagram. The conductive film 310d, which functions as a signal line, It is provided extending in a direction approximately perpendicular to the inspection line (up and down in the diagram). It functions as a capacity line. The conductive film 310f is provided extending in a direction parallel to the signal line. The functional conductive film 304c is electrically connected to the scan line drive circuit 104 (see Figure 9(A)). It is connected to a conductive film 310d that functions as a signal line and a conductive film 3 that functions as a capacitance line. 10f is electrically connected to the signal line drive circuit 106 (see Figure 9(A)).

[0281] Transistor 103 is located in the region where the scan line and signal line intersect. STA 103 is a conductive film 304c that functions as a gate electrode, and a gate insulating film (shown in Figure 10). (Not done.) A channel region is formed on the gate insulating film of the oxide semiconductor film 308. b. Conductive films 310d and 310e that function as source and drain electrodes, and oxide semiconductors. A protective film (not shown in Figure 10) formed on the body membrane 308b, and functions as a gate electrode. It is composed of conductive film 316c. The conductive film 304c also functions as a scanning line. The region superimposed with the oxide semiconductor film 308b functions as the gate electrode of transistor 102. Furthermore, the conductive film 310d also functions as a signal line and is superimposed on the oxide semiconductor film 308b. The region functions as the source or drain electrode of transistor 102. In Figure 10, the scan lines are such that the ends of the top surface shape are further from the edges of the oxide semiconductor film 308b. It is located on the outside. Therefore, the scan lines are made of a light-shielding film that blocks light from light sources such as backlights. And it functions. As a result, light is irradiated onto the oxide semiconductor film 308b contained in the transistor. Furthermore, it is possible to suppress fluctuations in the electrical characteristics of the transistor. Also, as a gate electrode, The conductive film 304c that can perform functions and the conductive film 316c that functions as a gate electrode are located at the opening 364c Connect at [location].

[0282] Furthermore, the conductive film 310e has light-transmitting properties that function as a pixel electrode in the aperture 364c. It is electrically connected to the conductive film 316b.

[0283] The capacitive element 105 is connected to the conductive film 310f, which functions as a capacitance line in the aperture 362. Furthermore, the capacitive element 105 has a conductive film 3 formed on the gate insulating film. 08c, a dielectric film formed of a nitride insulating film provided on transistor 103, and It is composed of a transparent conductive film 316c that functions as an elementary electrode, and has conductivity. Since the film 308c is light-transmitting, the capacitive element 105 is also light-transmitting.

[0284] Since the capacitive element 105 is light-transmitting, the capacitive element 105 is large within the pixel 100. It can be formed over a large area. Therefore, while increasing the opening ratio, typically 50% In addition, it is possible to achieve a value of 55% or more, or 60% or more, and to increase the charge capacity. A semiconductor device can be obtained. For example, a semiconductor device with high resolution, such as a liquid crystal display. In the device, the pixel area becomes smaller, and the area of ​​the capacitive element also becomes smaller. Therefore, In semiconductor devices with high image resolution, the charge capacitance accumulated in capacitive elements becomes smaller. However, However, since the capacitive element 105 shown in this embodiment is light-transmitting, the capacitive element is used in the pixel. By providing this feature, it is possible to increase the aperture ratio while obtaining sufficient charge capacitance in each pixel. Typically, pixel densities of 200 ppi or higher, even 300 ppi or higher, and even 500 ppi or higher. It can be suitably used in high-resolution semiconductor devices with a resolution of pi or higher.

[0285] Furthermore, the pixel 100 shown in Figure 10 has sides parallel to the conductive film 310d which functions as a signal line. In comparison, the conductive film 304c, which functions as a scanning line, has a longer side parallel to it, and The conductive film 310f, which functions as a quantity line, is parallel to the conductive film 310d, which functions as a signal line. It is provided with an extended shape. As a result, the area of ​​the conductive film 310f in relation to the pixel 100 is reduced. Because it can be reduced, the aperture ratio can be increased. Also, it functions as a capacitance line. Since the conductive film 310f comes into direct contact with the conductive film 308c without using a connecting electrode, Furthermore, the aperture ratio can be increased.

[0286] Furthermore, one aspect of the present invention allows for an increase in the aperture ratio even in high-resolution display devices. Therefore, it is possible to efficiently utilize the light from light sources such as backlights, and the power consumption of the display device is reduced. The force can be reduced.

[0287] Next, Figure 11 shows a cross-sectional view between the dashed lines C and D in Figure 10. The drive circuit section includes the scan line drive circuit 104 and the signal line drive circuit 106 (top view omitted). A cross-sectional view of the device is shown at AB. In this embodiment, a vertical electric field type liquid crystal display device is used. I will explain this.

[0288] The display device shown in this embodiment has liquid crystal elements between a pair of substrates (substrate 302 and substrate 342). 322 is being held in place.

[0289] The liquid crystal element 322 has a translucent conductive film 316b above the substrate 302 and controls the orientation. The control film (hereinafter referred to as alignment films 318 and 352), the liquid crystal layer 320, and the conductive film 350, It has the following characteristics. The light-transmitting conductive film 316b is used as one electrode of the liquid crystal element 322. The conductive film 350 functions as the other electrode of the liquid crystal element 322.

[0290] Thus, a liquid crystal display device refers to a device that has liquid crystal elements. The device includes a drive circuit for driving multiple pixels, etc. Furthermore, the liquid crystal display device is mounted on a separate substrate. This includes a control circuit, power supply circuit, signal generation circuit, and backlight module, etc., located in the same area. It is sometimes called a liquid crystal module.

[0291] In the drive circuit section, a conductive film 304a functions as a gate electrode, and as a gate insulating film Functional insulating film 305 and insulating film 306, oxide semiconductor film 30 in which a channel region is formed 8a, conductive films 310a and 310b, which function as source and drain electrodes, provide traction The oxide semiconductor film 308a constitutes the inverter 102. The oxide semiconductor film 308a is provided on the gate insulating film.

[0292] In the pixel area, the conductive film 304c functions as a gate electrode, and the gate insulating film functions as a gate insulating film. Insulating film 305 and insulating film 306, and a channel region formed on the gate insulating film. A conductive film 310 functions as a source electrode and a drain electrode, and the oxide semiconductor film 308b is formed. d, 310e, insulating film 312, insulating film 314, and conductive film 31 which functions as a gate electrode. 6c constitutes transistor 103. The oxide semiconductor film 308b is on the gate insulating film. It is provided there. In addition, insulating film 312 and insulating film 314 are provided on the conductive films 310d and 310e. It is provided as a protective layer.

[0293] Furthermore, the light-transmitting conductive film 316b, which functions as a pixel electrode, is insulated from the insulating film 312 and an insulating film. The conductive film 310e is connected at an opening provided in the edge film 314.

[0294] Furthermore, one of the electrodes is a conductive film 308c, and the other is a dielectric film. A capacitive element is formed by an insulating film 314 and a light-transmitting conductive film 316b that functions as the other electrode. 105 is formed. The conductive film 308c is provided on the gate insulating film.

[0295] Furthermore, in the drive circuit section, the conductive film 30 formed simultaneously with the conductive films 304a and 304c 4b and conductive film 31 formed simultaneously with conductive films 310a, 310b, 310d, and 310e 0c refers to the transparent conductive film 31 that was formed simultaneously with the transparent conductive film 316b. It will be connected via 6a.

[0296] The conductive film 304b and the light-transmitting conductive film 316a are insulating film 306 and insulating film 312 The connection is made at the opening provided therein. Also, the conductive film 310c and the light-transmitting conductive film 3 16a is connected at the openings provided in the insulating film 312 and the insulating film 314.

[0297] The components of the display device shown in Figure 11 will be described below.

[0298] Conductive films 304a, 304b, and 304c are formed on the substrate 302. 04a functions as the gate electrode of the transistor in the drive circuit section. Also, the conductive film... 304c is formed in the pixel portion 101 and functions as the gate electrode of the transistor in the pixel portion. Furthermore, the conductive film 304b is formed on the scan line drive circuit 104 and is connected to the conductive film 310c. do.

[0299] The substrate 302 can be made from the same material as the substrate 11 shown in Embodiment 1.

[0300] The conductive films 304a, 304b, and 304c are the same as those of the gate electrode 15 shown in Embodiment 1. Materials and manufacturing methods can be used as appropriate.

[0301] On the substrate 302 and the conductive films 304a, 304c, and 304b, there is an insulating film 305, an insulating film 306 is formed. The insulating film 305 and insulating film 306 are the transistor of the drive circuit section. It functions as a gate insulating film and as a gate insulating film for the transistor of the pixel portion 101.

[0302] The insulating film 305 is a nitride insulating film as described in the gate insulating film 17 shown in Embodiment 1. It is preferable to form it using the gate insulating film shown in Embodiment 1. It is preferable to form it using the oxide insulating film described in edge film 17.

[0303] On the insulating film 306 are oxide semiconductor films 308a and 308b, and a conductive film 308c. A film is formed. The oxide semiconductor film 308a is formed in a position where it overlaps with the conductive film 304a. It functions as the channel region of the transistor in the drive circuit section. Also, the oxide semiconductor film 3 08b is formed in a position superimposed on the conductive film 304c, and is the channel of the transistor in the pixel area. It functions as a region. The conductive film 308c serves as one electrode of the capacitive element 105. It works.

[0304] The oxide semiconductor films 308a, 308b, and the conductive film 308c are as described in Embodiment 1. The materials and methods for producing the oxide semiconductor film 18 shown can be used as appropriate.

[0305] The conductive film 308c is similar to the oxide semiconductor films 308a and 308b, and is made of oxide semiconductor material. It is characterized by being a conductive film and containing impurities. The impurities include hydrogen. In addition, boron, phosphorus, tin, antimony, and noble gas elements are used as impurities instead of hydrogen. It may also contain alkali metals, alkaline earth metals, etc.

[0306] The oxide semiconductor films 308a and 308b, and the conductive film 308c are all gate insulating films. They are formed on the edge film, but the impurity concentrations differ. Specifically, oxide semiconductor films 308a and 3 Compared to 08b, the impurity concentration of the conductive film 308c is higher. For example, oxide semiconductors The hydrogen concentration in body membranes 308a and 308b is 5 × 10⁻⁶. 19 atoms / cm 3 below, 5 x 10 18 atoms / cm 3 Below, 1 x 10 18 atoms / cm 3 Below, 5 x 10 17 atoms / cm 3 The following, or 1 × 10 16 atoms / cm 3 The following is conductive The hydrogen concentration contained in the membrane 308c, which has properties, is 8 × 10 19 atoms / cm 3 That's all. ×10 20 atoms / cm 3 Above, or 5 x 10 20 atoms / cm 3 That's all. Furthermore, compared to oxide semiconductor films 308a and 308b, the conductive film 308c contains The hydrogen concentration produced is twice, or more than ten times, higher.

[0307] Furthermore, the conductive film 308c has a lower resistivity than the oxide semiconductor films 308a and 308b. Low. The resistivity of the conductive film 308c is lower than that of the oxide semiconductor films 308a and 308b. The rate is 1 × 10 -8 1×10 times more -1 It is preferable that it is less than or equal to a multiple, typically 1 × 10⁻⁶. -3 Ωcm or more, 1 × 104 Resistivity less than Ωcm, or resistivity of 1 × 10⁻⁶ -3 Ωcm or larger 1×1 0 -1 It should be less than Ωcm.

[0308] The oxide semiconductor films 308a and 308b are made of oxide semiconductors such as insulating film 306 and insulating film 312. Because it is in contact with a film formed of a material that can improve the interfacial properties with the conductive film, acid The oxide semiconductor films 308a and 308b function as semiconductors, and the oxide semiconductor films 308a and 3 Transistors containing 08b have excellent electrical properties.

[0309] On the other hand, the conductive film 308c is an insulating film at the opening 362 (see Figure 14(A)). It is in contact with the edge film 314. The insulating film 314 is protected from external impurities, such as water, alkali metals, This film is formed from a material that prevents alkaline earth metals, etc., from diffusing into the oxide semiconductor film. Furthermore, it contains hydrogen. Therefore, the hydrogen in the insulating film 314 is absorbed by the oxide semiconductor films 308a and 308b. Simultaneously, when hydrogen diffuses into the oxide semiconductor film formed at the same time, hydrogen in the oxide semiconductor film becomes oxygen It combines with and generates electrons, which are carriers. In addition, the insulating film 314 is subjected to plasma CVD. Alternatively, when a film is deposited by sputtering, the oxide semiconductor film is exposed to plasma, creating oxygen vacancies. This is achieved when hydrogen contained in the insulating film 314 enters the oxygen vacancy, thereby allowing the carrier electrons to be deposited. Subatoms are generated. As a result, the oxide semiconductor film becomes highly conductive and functions as a conductor. In other words, it can be described as a highly conductive oxide semiconductor film. Here, oxide semiconductor film 308a , which has the same material as 308b as its main component, and the hydrogen concentration is the same as oxide semiconductor film 308a, 308 Because it is higher than b, the metal oxide has increased conductivity, and the conductive film 308c Call.

[0310] However, one embodiment of the present invention is not limited thereto, and includes a conductive film 308c In some cases, it is possible that it is not in contact with the insulating film 314.

[0311] Furthermore, one embodiment of the present invention is not limited thereto, and the conductive film 308c is In some cases, the oxide semiconductor film 308a or 308b may be formed in separate processes. It is also possible. In that case, the conductive film 308c is the oxide semiconductor film 308a, 30 8b may have a different material. For example, the conductive film 308c may be ITO Alternatively, it may be formed using indium zinc oxide or the like.

[0312] The semiconductor device shown in this embodiment simultaneously forms an oxide semiconductor film of a transistor and a capacitive element One electrode is formed. In addition, a light-transmitting conductive film that functions as a pixel electrode is provided. It is used as the other electrode of the capacitance element. For these reasons, in order to form a capacitance element, a new conductive element is used. The process of forming an electrical film is unnecessary, and the manufacturing process for semiconductor devices can be reduced. This is because the pair of electrodes are formed of a light-transmitting conductive film, and therefore it is light-transmitting. As a result, it is possible to increase the area occupied by the capacitive element while increasing the aperture ratio of the pixels.

[0313] The conductive films 310a, 310b, 310c, 310d, and 310e are as shown in Embodiment 1. The materials and manufacturing methods for the pair of electrodes 21 and 22 can be used as appropriate.

[0314] insulating film 306, oxide semiconductor films 308a, 308b, conductive film 308c, and On the conductive films 310a, 310b, 310c, 310d, and 310e, there is an insulating film 312, an insulating film A film 314 is formed. The insulating film 312, like the insulating film 306, is made of an oxide semiconductor film. It is preferable to use a material capable of improving the interfacial properties, at least in an embodiment The same materials and manufacturing methods as those used for the oxide insulating film 24 shown in Form 1 can be used as appropriate. As shown in Embodiment 1, even if the oxide insulating film 23 and the oxide insulating film are laminated together, good.

[0315] The insulating film 314, like the insulating film 305, is resistant to external impurities such as water and alkali gold. It is preferable to use materials that prevent the diffusion of minerals, alkaline earth metals, etc., into oxide semiconductor films. Furthermore, the materials and manufacturing methods for the nitride insulating film 25 shown in Embodiment 1 can be used as appropriate. ru.

[0316] Furthermore, the insulating film 314 has transparent conductive films 316a and 316b, and the gate electrode has a transparent conductive film 316a, 316b, and A conductive film 316c is formed which functions as a conductive film 316a. The transparent conductive film 316a is open At the opening 364a (see Figure 14(C)), it is electrically connected to the conductive film 304b, and the opening In section 364b (see Figure 14(C)), it is electrically connected to the conductive film 310c. It functions as a connecting electrode that connects conductive film 304b and conductive film 310c. It is light-transmitting. The conductive film 316b is connected to the conductive film 310e at the opening 364c (see Figure 14(C)). It is electrically connected and functions as a pixel electrode for the pixel. It is also a transparent conductive film. 316b can function as one of a pair of electrodes in a capacitive element. Conductive film 316c It is electrically connected to the conductive film 304c at the opening 364c (see Figure 10).

[0317] In order to create a connection structure in which conductive film 304b and conductive film 310c are in direct contact, conductive film 3 Before forming 10c, a patina is used to form openings in insulating film 305 and insulating film 306. It is necessary to perform a photomask to form a mask, but the connection structure in Figure 11 is the photomask. This is unnecessary. However, as shown in Figure 11, the transparent conductive film 316b allows for By connecting conductive film 304b and conductive film 310c, conductive film 304b and conductive film 310 This eliminates the need to create a connection point where c directly touches, thus reducing the number of photomasks by one. Yes, it is possible. In other words, it is possible to reduce the manufacturing process for semiconductor devices.

[0318] The transparent conductive films 316a, 316b, and conductive film 316c are tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium tin oxide Translucent conductive materials such as lead oxide and indium tin oxide with added silicon oxide It can be used.

[0319] Furthermore, a colored film (hereinafter referred to as the colored film 346) is formed on the substrate 342. The colored film 346 functions as a color filter. A light-shielding film 344 adjacent to it is formed on the substrate 342. The light-shielding film 344 is a black matrix It functions as a display. Also, the colored film 346 is not necessarily required; for example, it can be used as a display. In cases where the device is monochrome, for example, the colored film 346 may be omitted.

[0320] The colored film 346 can be any colored film that transmits light in a specific wavelength range, for example, A red (R) color filter that transmits light in the red wavelength range, and a filter that transmits light in the green wavelength range. A green (G) color filter that transmits light in the blue wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range. Filters and the like can be used.

[0321] The light-shielding film 344 only needs to have the function of blocking light in a specific wavelength band, and is made of metal. An organic insulating film containing a film or black pigment can be used.

[0322] Furthermore, an insulating film 348 is formed on the colored film 346. The insulating film 348 is planarized It functions as a layer, or it suppresses the diffusion of impurities that the colored film 346 may contain to the liquid crystal element. It has the function of controlling.

[0323] Furthermore, a conductive film 350 is formed on the insulating film 348. The conductive film 350 is formed on the pixel portion It functions as the other electrode of the pair of electrodes that the liquid crystal element has. An insulating film having the function of an alignment film is provided on films 316a, 316b, and the conductive film 350. They may be formed separately.

[0324] Furthermore, the conductive films 316a, 316b, 316c, and 350, which are transparent conductive films, are also connected. A liquid crystal layer 320 is formed in between. The liquid crystal layer 320 is also a sealing material (not shown). It is sealed between substrate 302 and substrate 342 using [a specific material]. Note that the sealing material is not exposed to the outside To suppress the intrusion of moisture and other substances, a configuration in which it comes into contact with an inorganic material is preferred.

[0325] Furthermore, the conductive films 316a, 316b, 316c, and 350, which are transparent conductive films, are also connected. A spacer may be provided in between to maintain the thickness of the liquid crystal layer 320 (also called the cell gap).

[0326] Regarding the method for manufacturing an element portion provided on a substrate 302 as shown in the semiconductor device in Figure 11, This will be explained using Figures 12 to 15.

[0327] First, prepare the substrate 302. Here, a glass substrate is used as the substrate 302.

[0328] Next, a conductive film is formed on the substrate 302, and the conductive film is processed to a desired region, thereby enabling conductivity Films 304a, 304b, and 304c are formed. Note that conductive films 304a, 304b, and 304 The formation of c involves forming a mask in the desired region by first patterning, and covering the mask. It can be formed by etching the areas that have not been cracked. (See Figure 12(A)) .

[0329] Furthermore, conductive films 304a, 304b, and 304c are typically produced by vapor deposition and CVD methods. They can be formed using methods such as sputtering and spin coating.

[0330] Next, an insulating film 305 is formed on the substrate 302 and the conductive films 304a, 304b, and 304c. Then, an insulating film 306 is formed on the insulating film 305 (see Figure 12(A)).

[0331] The insulating film 305 and insulating film 306 are formed by sputtering, CVD, or the like. This can be achieved. Note that if insulating film 305 and insulating film 306 are formed continuously in a vacuum, impurities will be produced. The inclusion of [unspecified substance] is suppressed, which is preferable.

[0332] Next, an oxide semiconductor film 307 is formed on the insulating film 306 (see Figure 12(B)).

[0333] Oxide semiconductor film 307 is produced by sputtering, coating, pulsed laser deposition, and laser - It can be formed using methods such as ablation.

[0334] Next, the oxide semiconductor film 307 is processed into a desired region, thereby creating an island-shaped oxide semiconductor film 3 Form 08a, 308b, and 308d. Note that oxide semiconductor films 308a, 308b, 3 Formation of 08d involves forming a mask in the desired region by a second patterning, and the mask It can be formed by etching the areas not covered by the material. This involves using dry etching, wet etching, or a combination of both. They can be there (see Figure 12(C)).

[0335] Next, conductive film 3 is applied to the insulating film 306 and the oxide semiconductor films 308a, 308b, and 308d. It forms 09 (see Figure 13(A)).

[0336] The conductive film 309 can be formed, for example, by a sputtering method.

[0337] Next, the conductive film 309 is processed into the desired region, thereby creating conductive films 310a, 310b, 31 0c, 310d, and 310e are formed. Note that conductive films 310a, 310b, 310c, and 3 Formation of 10d and 310e involves creating a mask in the desired region by third patterning. This can be formed by etching the areas not covered by the mask (Figure 1). 3(B)).

[0338] Next, insulating film 306, oxide semiconductor films 308a, 308b, 308d, and conductive film 31 An insulating film 311 is formed so as to cover 0a, 310b, 310c, 310d, and 310e. (See Figure 13(C)).

[0339] The insulating film 311 is the oxide insulating film 23 and oxide insulating film 24 shown in Embodiment 1. It can be formed by lamination using similar conditions. As shown in Embodiment 1, oxide By forming the insulating film 23 while heating, oxide semiconductor films 308a, 308b, and 308 d. By removing hydrogen, water, etc. contained in, a highly purified oxide semiconductor film can be formed. can.

[0340] Next, the insulating film 311 is processed into a desired area to form the insulating film 312 and the opening 362 The insulating film 311 and the opening 362 are formed by creating a fourth pattern in the desired region. A mask is formed by etching, and the areas not covered by the mask are etched. This can be formed. (See Figure 14(A)).

[0341] The opening 362 is formed so that the surface of the oxide semiconductor film 308d is exposed. For example, a dry etching method can be used to form the opening 362. Furthermore, the method for forming the opening 362 is not limited to this, and includes wet etching, Alternatively, a formation method combining dry etching and wet etching may be used.

[0342] After this, a heat treatment is performed in the same manner as in Embodiment 1 to remove the oxygen contained in the insulating film 311. A portion of the oxygen is transferred to the oxide semiconductor films 308a and 308b, and the oxide semiconductor film 308a, The amount of oxygen deficiency in 308b can be reduced.

[0343] Next, an insulating film 313 is formed on the insulating film 312 and the oxide semiconductor film 308d (Figure 14). (See (B)).

[0344] The insulating film 313 is a barrier against external impurities, such as oxygen, hydrogen, water, alkali metals, It is preferable to use a material that prevents alkaline earth metals, etc., from diffusing into the oxide semiconductor film. Furthermore, it is preferable that the material contains hydrogen, and typically an inorganic insulating material containing nitrogen, such as a nitride. An insulating film can be used. For example, the insulating film 313 can be formed using the CVD method. It is possible.

[0345] The insulating film 314 is protected from external impurities, such as water, alkali metals, alkaline earth metals, etc. However, it is a film formed of a material that prevents diffusion into the oxide semiconductor film, and furthermore, it contains hydrogen. Therefore, when hydrogen from the insulating film 314 diffuses into the oxide semiconductor film 308d, the oxide semiconductor In film 308d, hydrogen combines with oxygen, generating electrons, which act as carriers. As a result, The oxide semiconductor film 308d becomes highly conductive, transforming into a conductive film 308c.

[0346] Furthermore, the silicon nitride film is preferably deposited at a high temperature to enhance its blocking properties. For example, substrate temperatures between 100°C and 400°C, or between 300°C and 400°C. It is preferable to form the film by heating at a certain temperature. Furthermore, when forming the film at a high temperature, an oxide semiconductor film 3 Oxygen is desorbed from the oxide semiconductor used as 08a and 308b, and the carrier concentration increases. Since this phenomenon may occur, the temperature should be set so that this phenomenon does not occur.

[0347] Next, the insulating film 313 is processed into a desired region to form the insulating film 314 and the opening 364. a, 364b, 364c, 364d (see Figure 10) are formed. Note that insulating film 314 , and the openings 364a, 364b, 364c are made by a fifth patterning in the desired area This is achieved by forming a mask and then etching the areas not covered by the mask. This can be done (see Figure 14(C)).

[0348] Furthermore, the opening 364a is formed so that the surface of the conductive film 304b is exposed. The opening 364b is formed so that the conductive film 310c is exposed. Also, the opening 364c is The conductive film 310e is formed to be exposed. Also, the opening 364d is formed so that the conductive film 304c Form it so that it is exposed.

[0349] For example, the method for forming the openings 364a, 364b, 364c, and 364d is as follows: Dry etching can be used. However, for openings 364a, 364b, and 364 The formation method for c, 364d is not limited to this, but may include wet etching or A formation method combining the dry etching method and the wet etching method may also be used.

[0350] Next, the insulating film 314 is placed over the openings 364a, 364b, 364c, and 364d. A conductive film 315 is formed (see Figure 15(A)).

[0351] The conductive film 315 can be formed, for example, by sputtering.

[0352] Next, by processing the conductive film 315 into a desired region, a light-transmitting conductive film 316a is obtained. 316b and conductive film 316c are formed. Note that the conductive films 316a and 316b are translucent. The formation of the conductive film 316c is performed by forming a mask in the desired region by a sixth patterning. This can be formed by etching the areas not covered by the mask (Figure 15). (See (B)).

[0353] In the above steps, a pixel section having a transistor and a drive circuit section are formed on the substrate 302. This is possible. In addition, in the manufacturing process shown in this embodiment, the first to sixth patterns This means that transistors and capacitive elements can be formed simultaneously using six masks. ru.

[0354] In this embodiment, hydrogen contained in the insulating film 314 is expanded into the oxide semiconductor film 308d. The conductivity of the oxide semiconductor film 308d was increased by scattering, but the oxide semiconductor films 308a and 30 8b is covered with a mask, and impurities, typically hydrogen, boron, and lysate, are added to the oxide semiconductor film 308d. By adding tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., acid The conductivity of the oxide semiconductor film 308d may be increased. Hydrogen and boron may be added to the oxide semiconductor film 308d. Methods for adding phosphorus, tin, antimony, noble gas elements, etc. include ion doping. , ion implantation, etc. On the other hand, alkali metals and alkaline earth elements are used in oxide semiconductor films 308d. One method for adding metals, etc., involves exposing the oxide semiconductor film 308d to a solution containing the impurities. There is a law.

[0355] Next, regarding the structure formed on the substrate 342 which is provided opposite the substrate 302, the following applies: Give an explanation.

[0356] First, prepare substrate 342. The materials used for substrate 342 are the same as those used for substrate 302. This can be done. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (Figure 16( See A).

[0357] The light-shielding film 344 and the colored film 346 are produced using various materials by printing, inkjet, and These are formed at the desired locations using etching methods such as photolithography.

[0358] Next, an insulating film 348 is formed on the light-shielding film 344 and the colored film 346 (see Figure 16(B)). (see).

[0359] Examples of insulating film 348 include organic insulating films such as acrylic resin, epoxy resin, and polyimide. A border film can be used. By forming an insulating film 348, for example, a colored film 34 This can suppress the diffusion of impurities contained in 6 towards the liquid crystal layer 320. Furthermore, the insulating film 348 is not necessarily required, and a structure without the insulating film 348 can be formed. That's good too.

[0360] Next, a conductive film 350 is formed on the insulating film 348 (see Figure 16(C)). Conductive film 350 For this purpose, the material shown in conductive film 315 can be used.

[0361] The structure to be formed on the substrate 342 can be created through the above process.

[0362] Next, the insulating film 31 formed on substrate 302 and substrate 342, more specifically on substrate 302 4. Transparent conductive films 316a, 316b and conductive film 35 formed on the substrate 342 Alignment film 318 and alignment film 352 are formed on the 0, respectively. Alignment film 318, Alignment film 352 These can be formed using methods such as rubbing and photo-alignment. Subsequently, the substrate 302 and the base A liquid crystal layer 320 is formed between the plate 342 and the liquid crystal layer 320. The method for forming the liquid crystal layer 320 is to disperse The drip method (dropping method) or the method of bonding substrate 302 and substrate 342 together and then using capillary action An injection method for injecting liquid crystal can be used.

[0363] By following the above steps, the display device shown in Figure 11 can be manufactured.

[0364] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0365] <Example 1> A modified example of a liquid crystal display device using liquid crystal elements in pixel 100 will be described. (See Figure 11) In a liquid crystal display device, the conductive film 308c is in contact with the insulating film 314, but it is an insulating film. The structure can be made to be in contact with the membrane 305. In this case, the opening 362 as shown in Figure 14 Since there is no need to provide a step, the step on the surface of the light-transmitting conductive films 316a and 316b is reduced. This makes it possible to reduce the orientation disorder of the liquid crystal material contained in the liquid crystal layer 320. This is possible. Furthermore, it is possible to fabricate semiconductor devices with high contrast.

[0366] In this structure, as shown in Figure 12(B), before forming the oxide semiconductor film 307, The edge film 306 can be selectively etched to expose a portion of the insulating film 305.

[0367] <Modification 2> In this embodiment and its modified form, the insulating film 314, the light-transmitting conductive films 316a, 316 b, or between the conductive film 316c and the alignment film 318, acrylic resin, epoxy resin, and An organic insulating film such as liimide may be provided. Organic insulating films such as acrylic resins have high flatness. Therefore, it is possible to reduce the step height on the surface of the light-transmitting conductive film 316b. Therefore, it is possible to reduce the orientation disorder of the liquid crystal material contained in the liquid crystal layer 320. It is possible to fabricate semiconductor devices with high traction.

[0368] (Embodiment 5) In this embodiment, the transistors included in the semiconductor device described in the above embodiment are used. In this context, one embodiment applicable to oxide semiconductor films will be described.

[0369] Oxide semiconductor films are oxide semiconductors with a single-crystal structure (hereinafter referred to as single-crystal oxide semiconductors). Polycrystalline oxide semiconductors (hereinafter referred to as polycrystalline oxide semiconductors), microcrystalline oxides Material semiconductors (hereinafter referred to as microcrystalline oxide semiconductors), and amorphous oxide semiconductors (hereinafter referred to as It may be composed of one or more of the following: , which is called an amorphous oxide semiconductor. Also, the oxide semiconductor film is It may also be composed of a CAAC-OS film. In addition, the oxide semiconductor film may be an amorphous oxide semiconductor film. It may be composed of an oxide semiconductor having conductors and crystal grains. Below, single-crystal oxide semiconductors Conductors, CAAC-OS, polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors Let's explain conductors.

[0370] <Single-crystal oxide semiconductor> Single-crystal oxide semiconductor films have low impurity concentrations and low defect level densities (few oxygen vacancies). It is an oxide semiconductor film. Therefore, the carrier density can be lowered. Transistors using crystalline oxide semiconductor films rarely exhibit normally-on electrical properties. No. Also, single-crystal oxide semiconductor films have a low impurity concentration and a low defect level density, so Carrier traps may be reduced. Therefore, using a single-crystal oxide semiconductor film ZISTA transistors exhibit less variation in electrical characteristics, resulting in highly reliable transistors.

[0371] Furthermore, oxide semiconductor films have higher density when they have fewer defects. Also, oxide semiconductor films Higher crystallinity results in higher density. Also, oxide semiconductor films have a low concentration of impurities such as hydrogen. The density increases. Single-crystal oxide semiconductor films have a higher density than CAAC-OS films. Furthermore, CAAC-OS films have a higher density than microcrystalline oxide semiconductor films. Conductive films have a higher density than microcrystalline oxide semiconductor films. Also, microcrystalline oxide semiconductor films are non It has a higher density than crystalline oxide semiconductor films.

[0372] <caac-os> CAAC-OS film is an oxide semiconductor film having multiple crystalline regions. The crystalline portion contained in the AC-OS film has c-axis orientation. In the planar TEM image, CAA The area of ​​the crystalline portion contained in the C-OS film is 2500 nm 2 Above 5μm 2 or more, or 100 0 μm 2 That is all. Furthermore, in the cross-sectional TEM image, the crystalline portion is 50% or more, 80% or more. Having 95% or more of this material results in a thin film with physical properties close to those of a single crystal.

[0373] CAAC-OS film is examined using a transmission electron microscope (TEM). When observed with a tron ​​microscope, clear boundaries between crystals, i.e., bonds, can be seen. The grain boundaries (also called crystal grain boundaries) cannot be identified. Therefore, CA AC-OS films are less susceptible to the decrease in electron mobility caused by grain boundaries.

[0374] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM view). (Inference) It can be confirmed that in the crystalline part, metal atoms are arranged in layers. Each of these layers has a concave surface on the surface (also called the surface to be formed) or upper surface that forms the CAAC-OS film. It has a convex shape and is arranged parallel to the surface or top surface of the CAAC-OS film. In this specification, "parallel" means that two straight lines are aligned at an angle of -10° or more and 10° or less. This refers to the state in which something is placed. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "vertical" "A straight line is a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, This also includes cases where the angle is between 85° and 95°.

[0375] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T). EM observation reveals that in the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. do not have.

[0376] Furthermore, when electron diffraction is performed on the CAAC-OS film, oriented spots (bright spots) are observed. This is observed.

[0377] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. It can be seen that this is the case.

[0378] X-ray diffraction (XRD) of CAAC-OS film Structural analysis using the instrument reveals that the CAAC-OS film can be analyzed by an out-of-plane method. In the analysis, a peak may appear near a diffraction angle (2θ) of 31°. This peak is I Since it is attributed to the (00x) plane (where x is an integer) of the nGaZn oxide crystal, CAAC- The crystals of the OS film have c-axis orientation, with the c-axis pointing in a direction approximately perpendicular to the surface to be formed or the upper surface. It can be confirmed that they are there.

[0379] On the other hand, in the CAAC-OS film, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-p In analysis using the lane method, a peak may appear when 2θ is around 56°. This is attributed to the (110) plane of the InGaZn oxide crystal. For a crystalline oxide semiconductor film, fix 2θ to around 56° and set the normal vector of the sample surface to axis (φ When the analysis (φ scan) is performed while rotating the sample as the axis, the (110) plane is equivalent to the (110) plane. Six peaks attributable to the crystal plane are observed. In contrast, in the case of the CAAC-OS film, 2 Even when θ is fixed near 56° and φ is scanned, no clear peak appears.

[0380] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis between different crystalline regions is Although irregular, it has c-axis orientation, and the c-axis is parallel to the normal vector of the formed surface or the upper surface. It can be seen that it is oriented in a specific direction. Therefore, the layered structure confirmed by the aforementioned cross-sectional TEM observation is Each layer of arranged metal atoms is a plane parallel to the ab-plane of the crystal.

[0381] The crystals are formed when the CAAC-OS film is deposited, or when crystallization treatments such as heat treatment are performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface.

[0382] Furthermore, the degree of crystallinity in the CAAC-OS film does not need to be uniform. For example, CAAC-OS When the crystalline portion of the film is formed by crystal growth from near the upper surface of the CAAC-OS film, The region near the surface may have a higher degree of crystallinity than the region near the surface being formed. Also, CA When impurities are added to an AC-OS film, the degree of crystallinity in the region where the impurities are added changes, and Regions with varying degrees of crystallinity may also be formed.

[0383] Furthermore, in the out-of-plane analysis of the CAAC-OS film, 2θ was 31° In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak indicates that a portion of the CAAC-OS film contains crystalline regions that do not exhibit c-axis orientation. This indicates that the CAAC-OS film shows a peak around 2θ = 31° and 2θ = 36°. It is preferable that no peaks appear in the vicinity.

[0384] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen and carbon. These are elements other than the main components of oxide semiconductor films, such as silicon and transition metal elements. In particular, silicon Elements such as condensate, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, are acidic. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a high atomic ratio. Because of its large diameter (or molecular radius), when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Pure substances can act as carrier traps or carrier sources.

[0385] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxidation Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. This can sometimes become a source of carrier transmission.

[0386] A low impurity concentration and low defect level density (few oxygen vacancies) are referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic. Because the membrane has fewer carrier sources, the carrier density can be lowered. Therefore, A transistor using this oxide semiconductor film exhibits electrical characteristics such as a negative threshold voltage ( - Also called Marieion.) It rarely becomes high purity genuine or substantially high purity. Intrinsic oxide semiconductor films have few carrier traps. Therefore, the oxide semiconductor... Transistors using film have small variations in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can last for a long time and behave as if it were a fixed charge. Therefore, when the impurity concentration is high... Furthermore, transistors using oxide semiconductor films with a high defect level density exhibit unstable electrical properties. There are cases where this occurs.

[0387] Furthermore, transistors using CAAC-OS films exhibit electrical properties when irradiated with visible light or ultraviolet light. Sexual variation is small.

[0388] <Polycrystalline oxide semiconductors> Polycrystalline oxide semiconductor films allow for the identification of crystal grains using TEM observation. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm or larger in TEM observation images. The particle size is less than 00 nm, between 3 nm and 100 nm, or between 5 nm and 50 nm. There are many such cases. Also, in polycrystalline oxide semiconductor films, grain boundaries can be confirmed by TEM observation. There are cases where this occurs.

[0389] A polycrystalline oxide semiconductor film has multiple crystal grains, and between these multiple crystal grains, the crystals The positions may differ. Also, polycrystalline oxide semiconductor films can be analyzed using, for example, an XRD device. When an out-of-plane analysis is performed, one or more peaks may appear. There is a correlation. For example, in polycrystalline IGZO films, the orientation-indicating 2θ peaks near 31°, and Multiple peaks showing different orientations may appear.

[0390] Polycrystalline oxide semiconductor films have high crystallinity, and therefore may have high electron mobility. Therefore, transistors using polycrystalline oxide semiconductor films have high field-effect mobility. However, polycrystalline oxide semiconductor films may have impurities segregated at grain boundaries. In crystalline oxide semiconductor films, grain boundaries become defect levels. In polycrystalline oxide semiconductor films, grain boundaries become carrier emission levels. Because it can become a source or trap level, transistors using polycrystalline oxide semiconductor films Compared to transistors using CAAC-OS film, it exhibits greater variation in electrical characteristics and reliability. This can result in a transistor with low performance.

[0391] <Microcrystalline oxide semiconductor> Microcrystalline oxide semiconductor films can be clearly observed using TEM. In some cases, this may not be possible. The crystalline portion contained in the microcrystalline oxide semiconductor film is between 1 nm and 100 nm. They are often smaller than 1 nm, or between 1 nm and 10 nm in size. In particular, between 1 nm and 10 nm Nanocrystals (nc: nanocrystals) are microcrystals of a size of 1 nm or less, or between 1 nm and 3 nm. An oxide semiconductor film having tal is made nc-OS (nanocrystalline O It is called an xide Semiconductor film. Also, an nc-OS film is, for example, T In some cases, grain boundaries may not be clearly visible in images obtained using EM (Electromagnetic Wave) imaging.

[0392] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region of 3 nm or less. In addition, the nc-OS film is different There is no regularity in the crystal orientation between the crystalline regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this occurs. For example, XRD using X-rays with a diameter larger than that of the crystalline region on an nc-OS film. When structural analysis is performed using the apparatus, the out-of-plane method analyzes the crystal planes. The peaks shown are not detected. Also, for the nc-OS film, a diameter larger than that of the crystalline region (for example) When electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or more, A diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films, crystal An electron beam with a diameter close to or smaller than the size of the crystal portion (for example, between 1 nm and 30 nm) is used. When electron diffraction (also called nanobeam electron diffraction) is performed, spots can be observed. Furthermore, when nanobeam electron diffraction is performed on an nc-OS film, it forms a circular (ring-shaped) pattern. )A region with high brightness may be observed. Also, when a nanobeam electron beam is used on the nc-OS film... When diffraction is performed, multiple spots may be observed within a ring-shaped region.

[0393] Figure 17 shows nanobeam electron diffraction at different measurement locations for a sample containing an nc-OS film. This is an example of the procedure performed. Here, the sample is cut in a direction perpendicular to the surface on which the nc-OS film is formed. The material is thinned to a thickness of 10 nm or less. Furthermore, an electron beam with a diameter of 1 nm is used. The sample is incident from a direction perpendicular to the cross-section. As shown in Figure 17, for a sample with an nc-OS film... Furthermore, when nanobeam electron diffraction is performed, a diffraction pattern showing crystal planes is obtained, but in a specific direction It was found that no orientation toward the crystal plane was observed.

[0394] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, Furthermore, the nc-OS film does not show any regularity in crystal orientation between different crystalline regions. Therefore, nc- OS films have a higher defect level density compared to CAAC-OS films.

[0395] Note that the configurations and methods shown in this embodiment may differ from those shown in other embodiments. It can be used in appropriate combinations.

[0396] (Embodiment 6) The oxide semiconductor film disclosed in the above embodiment can be formed by sputtering. However, it may also be formed by other methods, such as thermal CVD. An example of thermal CVD is M OCVD(Metal Organic Chemical Vapor Deposit) Using methods such as the tion method or ALD (Atomic Layer Deposition) That's good too.

[0397] Thermal CVD is a film deposition method that does not use plasma, so defects can occur due to plasma damage. It has the advantage of never being accomplished.

[0398] In the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the chamber is subjected to atmospheric pressure. Alternatively, by applying reduced pressure and reacting the film near or on the substrate, the film can be deposited on the substrate. You may go.

[0399] Furthermore, the ALD method maintains atmospheric pressure or reduced pressure inside the chamber, and the raw material gas for the reaction is The gases are introduced into the chamber sequentially, and film deposition can be performed by repeating this gas introduction sequence. For example, by switching between each switching valve (also called a high-speed valve), two types or less The above raw material gases are supplied to the chamber in order, and the first is supplied in order to prevent the mixing of multiple types of raw material gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the raw material gas. A second raw material gas is introduced. If an inert gas is introduced at the same time, the inert gas is... It acts as a carrier gas, and also when introducing a second raw material gas, an inert gas is introduced at the same time. Good. Also, instead of introducing an inert gas, the first source gas was removed by vacuum evacuation. Later, a second raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate and forms the first layer. A film is formed, and it reacts with a second raw material gas introduced later, so that the second layer is laminated on top of the first layer. A thin film is formed. This process is repeated multiple times while controlling the gas introduction sequence until the desired thickness is reached. By doing this, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the gas introduction. Because it can be adjusted by the number of times the sequence is repeated, precise film thickness adjustment is possible. It is suitable for fabricating miniature FETs.

[0400] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. Various films can be formed, such as metal films, oxide semiconductor films, and inorganic insulating films. For example, I When forming an nGaZnO film, trimethylindium, trimethylgallium, and Dimethylzinc is used. Note that the chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for lead is Zn(CH3)2. Furthermore, it is not limited to these combinations, but also includes tri Use triethylgallium (chemical formula Ga(C2H5)3) instead of methylgallium. It is also possible to use diethylzinc (chemical formula Zn(C2H5)2) instead of dimethylzinc. It's also possible.

[0401] For example, oxide semiconductor films, such as In-Ga-Zn-, can be deposited using an ALD-based film deposition system. When forming an O film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. - An O layer is formed, and then Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. After forming the layer, a ZnO layer is formed by simultaneously introducing Zn(CH3)2 and O3 gas. Note that the order of these layers is not limited to this example. Also, by mixing these gases, In-Ga- Mixed compound layers such as an O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. Even if you use H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas, It is good, but it is preferable to use O3 gas that does not contain H. Also, In(CH3)3 gas Alternatively, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Alternatively, In(CH3)3 gas can be used instead. C2H5)3 gas may be used. Alternatively, Zn(CH3)2 gas may be used.

[0402] Note that the configurations and methods shown in this embodiment may differ from those shown in other embodiments. It can be used in appropriate combinations. [Examples]

[0403] In this example, the Vg-Id characteristics of the transistor and the measurement results of the gate BT stress test are shown. I will explain this.

[0404] In this embodiment, samples 1 to 3, which represent one aspect of the present invention, and comparative samples 4 to 6 were prepared. First, the preparation process for Sample 1 will be explained. Samples 1 to 3 are one embodiment of the present invention. For details, please refer to Figure 18, and for comparative samples 4 to 6, please refer to Figure 19. I will explain each of them.

[0405] (Sample 1) Sample 1 consists of a substrate 511, a gate electrode 515 on the substrate 511, and the substrate 511 and gate A gate insulating film 517 on the electrode 515, and a gate insulating film 517 provided on the gate insulating film 517, and gate An oxide semiconductor film 518 provided in the region overlapping with pole 515, and a gate insulating film 517 and A pair of electrodes 521 and 522 on the oxide semiconductor film 518, and the oxide semiconductor film 518 and a pair A protective film 526 on electrodes 521 and 522, and a gate electrode provided on the protective film 526. It has a back gate electrode 527 provided in a region overlapping with 515 (see Figure 18). .

[0406] The protective film 526 consists of oxide insulating film 523, oxide insulating film 524, and nitride insulating film. It was formed with a three-layer stacked structure of 525. Furthermore, both ends of the back gate electrode 527 are shown in Figure 18. As shown in (B), it roughly coincides with both ends of the gate electrode 515. Also, the backgear As shown in Figure 18(C), the electrode 527 is connected to the oxide semiconductor film 51 via the protective film 526. It was formed to cover 8.

[0407] Next, the method for preparing sample 1 shown in Figure 18 is described below.

[0408] First, a glass substrate is used as the substrate 511, and a gate electrode 515 is formed on the substrate 511. Ta.

[0409] A 200 nm thick tungsten film was formed as the gate electrode 515 using the sputtering method. Then, a mask is formed on the tungsten film by a photolithography process, and the mask is used The tungsten film was then formed by etching a portion of it.

[0410] Next, a gate insulating film 517 was formed on the gate electrode 515.

[0411] As the gate insulating film 517, a silicon nitride film with a thickness of 400 nm and an oxide film with a thickness of 50 nm are used. It was formed by laminating silicon nitride films.

[0412] Furthermore, the silicon nitride film consists of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminated structure of silicon nitride film was adopted.

[0413] The first silicon nitride film is a silane at a flow rate of 200 sccm, and a silane at a flow rate of 2000 sccm. A plasma CVD apparatus uses nitrogen and ammonia gas at a flow rate of 100 sccm as raw material gases. It is supplied to the processing chamber, the pressure inside the processing chamber is controlled to 100 Pa, and a 27.12 MHz high-frequency electric current is used. Using a power source, 2000W of power was supplied, and the material was formed to a thickness of 50nm. Second For silicon nitride films, silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, And ammonia gas at a flow rate of 2000 sccm is used as the raw material gas for processing in a plasma CVD apparatus. A 27.12 MHz high-frequency power supply is used to supply power to the chamber, control the pressure inside the processing chamber to 100 Pa, and supply power to the chamber. Then, 2000W of power was supplied and it was formed to a thickness of 300nm. Third nitriding As for the silicon membrane, a flow rate of 200 sccm of silane and a flow rate of 5000 sccm of nitrogen were used. It is supplied as a raw material gas to the processing chamber of the plasma CVD apparatus, and the pressure inside the processing chamber is controlled to 100 Pa. It is controlled and supplied with 2000W of power using a 27.12MHz high-frequency power supply, and the thickness is 50 It was formed to have a size of nm. The first silicon nitride film, the second silicon nitride film, and The substrate temperature during the formation of the third silicon nitride film was set to 350°C.

[0414] As for the silicon oxidizride film, a silane flow rate of 20 sccm and a flow rate of 3000 sccm Dinitrogen oxide is supplied as a raw material gas to the processing chamber of the plasma CVD apparatus, and the pressure inside the processing chamber is set to 4 The pressure is controlled to 0 Pa, and 100 W of power is supplied using a 27.12 MHz high-frequency power supply, and the acid A silicon oxide nitride film was formed. The substrate temperature during the formation of the silicon oxide nitride film was 350°C. did.

[0415] Next, the oxide semiconductor film 518 overlapping the gate electrode 515 is connected via the gate insulating film 517. It was formed.

[0416] Here, a 35 nm thick oxide semiconductor film is applied to the gate insulating film 517 by sputtering. It was formed by [this method].

[0417] Oxide semiconductor films are sputtered using an In:Ga:Zn=3:1:2 (atomic) target. The target (numerical ratio) is oxygen at a flow rate of 100 sccm used as the sputtering gas. It is supplied to the processing chamber of the taring device, the pressure inside the processing chamber is controlled to 0.6 Pa, and a 5 kW DC power supply is used. The film was formed by supplying power. The substrate temperature during the formation of the oxide semiconductor film was set to 170°C. Ta.

[0418] Next, a pair of electrodes 521 and 522 were formed to contact the oxide semiconductor film 518.

[0419] Here, a conductive film was formed on the gate insulating film 517 and the oxide semiconductor film 518. As an electrical film, a 400 nm thick aluminum film is formed on a 50 nm thick tungsten film. Next, a titanium film with a thickness of 200 nm was formed on the aluminum film. A mask is formed on the conductive film by a process, and a portion of the conductive film is etched using the mask. A pair of electrodes 521 and 522 were formed by shaping.

[0420] Next, the substrate is moved to a depressurized processing chamber, heated to 350°C, and then placed in the processing chamber. A high-frequency power of 150W is supplied to the upper electrode using a 27.12MHz high-frequency power supply, The oxide semiconductor film 518 was exposed to oxygen plasma generated in a nitrogen oxide atmosphere.

[0421] Next, a protective film 526 is formed on the oxide semiconductor film 518 and the pair of electrodes 521 and 522. Here, the protective film 526 is made of oxide insulating film 523, oxide insulating film 524, and nitrogen A monoxide insulating film 525 was formed.

[0422] First, after the oxygen plasma treatment described above, the oxide insulating film 523 is continuously treated without exposure to the atmosphere. And an oxide insulating film 524 was formed. A 50 nm thick oxide nitride insulating film was used as the oxide insulating film 523. A silicon film is formed, and a silicon oxidoxide nitride film with a thickness of 400 nm is used as the oxide insulating film 524. It was formed.

[0423] The oxide insulating film 523 is treated with silane at a flow rate of 20 sccm and oxide monoxide at a flow rate of 3000 sccm. Using dinitrogen as the raw material gas, with a processing chamber pressure of 200 Pa, a substrate temperature of 350°C, and 100 W of power. It was formed by a plasma CVD method in which high-frequency power was supplied to parallel plate electrodes.

[0424] The oxide insulating film 524 is infused with silane at a flow rate of 160 sccm and monoacid at a flow rate of 4000 sccm. Using dinitrogen dioxide as the raw material gas, with a processing chamber pressure of 200 Pa and a substrate temperature of 220°C, 150 The material was formed by plasma CVD using a method in which 0W of high-frequency power was supplied to parallel plate electrodes. Therefore, it contains more oxygen than satisfactorily satisfying the oxygen composition, and some of the oxygen is released upon heating. It is possible to form a desorbable silicon oxidizride film.

[0425] Next, a heat treatment is performed, and water, nitrogen, and water are removed from the oxide insulating film 523 and the oxide insulating film 524. In addition to removing elements, some of the oxygen contained in the oxide insulating film 524 is removed from the oxide semiconductor film 5 It was supplied to 18. Here, it underwent heat treatment at 350°C for 1 hour in a nitrogen and oxygen atmosphere. Ta.

[0426] Next, a nitride insulating film 525 with a thickness of 100 nm was formed on the oxide insulating film 524. The insulating film 525 is subjected to silane at a flow rate of 50 sccm, nitrogen at a flow rate of 5000 sccm, and flow rate Using 100 sccm of ammonia gas as the raw material gas, with a processing chamber pressure of 100 Pa and a substrate temperature... The plasma CVD method was performed with a temperature of 350°C and 1000W of high-frequency power supplied to parallel plate electrodes. It was formed more.

[0427] Next, an oxide insulating film was formed on the protective film 526 (not shown). Here, the flow rate was 20 Ethyl silicate (TEOS: chemical formula Si(OC2H5)4), a 0 sccm organic silane gas. ) and oxygen at a flow rate of 10,000 sccm are used as the raw material gas, the pressure in the processing chamber is 175 Pa, and the substrate temperature is 175 Pa. A plasma CVD method was performed with a temperature of 350°C and 3300W of high-frequency power supplied to parallel plate electrodes. It was formed by [the following].

[0428] Next, a back gate electrode 527 was formed on the oxide insulating film on the protective film 526. This is a back gate electrode 527, formed by sputtering to create an oxide layer 100 nm thick. A conductive film of a zinc-tin oxide compound (ITO-SiO2) was formed. The composition of the target was In2O3:SnO2:SiO2 = 85:10:5 [weight %] This was followed by a heat treatment at 250°C for 1 hour in a nitrogen atmosphere.

[0429] Sample 1 of this embodiment was prepared by the above steps.

[0430] (Sample 2) Sample 2 differs from Sample 1 in the structure of the oxide semiconductor film 518. Specifically, Sample 2 The oxide semiconductor film 518 is constructed in a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film. did.

[0431] First, the first oxide semiconductor film is made by sputtering a target with In:Ga:Zn=3: A 1:2 (atomic ratio) target is used, and oxygen is sputtered at a flow rate of 100 sccm. It is supplied into the processing chamber of the sputtering apparatus, and the pressure inside the processing chamber is controlled to 0.6 Pa. It was formed by supplying 5kW of DC power.

[0432] Next, a second oxide semiconductor film was continuously formed on the first oxide semiconductor film in a vacuum. The second oxide semiconductor film is made by sputtering a target with In:Ga:Zn=1:3:2( The target is an atomic ratio of oxygen at a flow rate of 30 sccm and argon at a flow rate of 270 sccm. The gas is supplied as a sputtering gas to the processing chamber of the sputtering apparatus, and the pressure inside the processing chamber is The pressure was controlled to 0.6 Pa and 5 kW of DC power was supplied to form the material. The substrate temperature during the formation of the body film and the second oxide semiconductor film was set to 170°C.

[0433] For sample 2, the configuration is the same as sample 1 except for the oxide semiconductor film 518. This can be formed by referring to the description of Sample 1.

[0434] (Sample 3) Sample 3 differs from Sample 1 in the structure of the oxide semiconductor film 518. Specifically, Sample 3 The oxide semiconductor film 518 consists of a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide A stacked structure of semiconductor films was adopted.

[0435] First, the first oxide semiconductor film is made by sputtering a target with In:Ga:Zn=1: A 3:2 (atomic ratio) target was used, with oxygen flowing at 30 sccm and oxygen flowing at 270 sccm. Argon is supplied as a sputtering gas into the processing chamber of the sputtering apparatus, and the processing chamber The internal pressure was controlled to 0.6 Pa, and 5 kW of DC power was supplied to form the structure.

[0436] Next, a second oxide semiconductor film was continuously formed on the first oxide semiconductor film in a vacuum. The second oxide semiconductor film is made by sputtering a target with In:Ga:Zn=3:1:2( The target is an atomic ratio of oxygen at a flow rate of 100 sccm and aluminum at a flow rate of 100 sccm. Gon is supplied as a sputtering gas into the processing chamber of the sputtering apparatus, and the pressure in the processing chamber The force was controlled to 0.6 Pa, and the structure was formed by supplying 5 kW of DC power.

[0437] Next, a third oxide semiconductor film was continuously formed on the second oxide semiconductor film in a vacuum. The third oxide semiconductor film is made by sputtering a target with In:Ga:Zn=1:3:2( The target is an atomic ratio of oxygen at a flow rate of 30 sccm and argon at a flow rate of 270 sccm. The gas is supplied as a sputtering gas to the processing chamber of the sputtering apparatus, and the pressure inside the processing chamber is The pressure was controlled to 0.6 Pa and 5 kW of DC power was supplied to form the material. The substrate temperature during the formation of the body film, the second oxide semiconductor film, and the third oxide semiconductor film is set to 17 The temperature was set to 0°C.

[0438] For sample 3, the configuration other than the oxide semiconductor film 518 is the same as that of sample 1. This can be formed by referring to the description of Sample 1.

[0439] (Sample 4) Sample 4 consists of a substrate 511, a gate electrode 515 on the substrate 511, and the substrate 511 and gate A gate insulating film 517 on the electrode 515, and a gate insulating film 517 provided on the gate insulating film 517, and gate An oxide semiconductor film 518 provided in the region overlapping with pole 515, and a gate insulating film 517 and A pair of electrodes 521 and 522 on the oxide semiconductor film 518, and the oxide semiconductor film 518 and a pair A protective film 526 on electrodes 521 and 522, and a gate electrode provided on the protective film 526. It has a back gate electrode 528 provided in a region overlapping with 515 (see Figure 19). .

[0440] The protective film 526 consists of oxide insulating film 523, oxide insulating film 524, and nitride insulating film. It was formed with a 3-layer stacked structure of 525. The back gate electrode 528 is shown in Figure 19(B). As shown, it was formed so as to be located inside the edges of the oxide semiconductor film 518. The back gate electrode 528 is connected to the oxide via a protective film 526, as shown in Figure 19(C). It was formed so as to be located inside the semiconductor film 518. However, in Figure 19(C), One end of the gate electrode 528 extends outward beyond the oxide semiconductor film 518. It is forming.

[0441] Next, the method for preparing sample 4 shown in Figure 19 is described below.

[0442] The same manufacturing process as described above for sample 1 was followed up to the formation of the protective film 526.

[0443] Next, an oxide insulating film was formed on the protective film 526 (not shown). Here, the flow rate was 20 Ethyl silicate (TEOS: chemical formula Si(OC2H5)4), a 0 sccm organic silane gas. ) and oxygen at a flow rate of 10,000 sccm are used as the raw material gas, the pressure in the processing chamber is 175 Pa, and the substrate temperature is 175 Pa. A plasma CVD method was performed with a temperature of 350°C and 3300W of high-frequency power supplied to parallel plate electrodes. It was formed by [the following].

[0444] Next, a back gate electrode 527 was formed on the oxide insulating film on the protective film 526. This is a back gate electrode 527, formed by sputtering to create an oxide layer 100 nm thick. A conductive film of a zinc-tin oxide compound (ITO-SiO2) was formed. The composition of the target was In2O3:SnO2:SiO2 = 85:10:5 [weight %] This was followed by a heat treatment at 250°C for 1 hour in a nitrogen atmosphere.

[0445] Sample 4 of this embodiment was prepared through the above steps.

[0446] (Sample 5) Sample 5 differs from Sample 4 in the structure of its oxide semiconductor film 518. Specifically, Sample 5 The oxide semiconductor film 518 has a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film. did.

[0447] First, the first oxide semiconductor film is made by sputtering a target with In:Ga:Zn=3: A target with a 1:2 (atomic ratio) flow rate is used, with oxygen at a flow rate of 100 sccm and oxygen at a flow rate of 100 sccc. m argon is supplied as the sputtering gas into the processing chamber of the sputtering apparatus, and processing is performed. The room pressure was controlled to 0.6 Pa, and 5 kW of DC power was supplied to create the structure.

[0448] Next, a second oxide semiconductor film was continuously formed on the first oxide semiconductor film in a vacuum. The second oxide semiconductor film is made by sputtering a target with In:Ga:Zn=1:3:2( The target is an atomic ratio of oxygen at a flow rate of 30 sccm and argon at a flow rate of 270 sccm. The gas is supplied as a sputtering gas to the processing chamber of the sputtering apparatus, and the pressure inside the processing chamber is The pressure was controlled to 0.6 Pa and 5 kW of DC power was supplied to form the material. The substrate temperature during the formation of the body film and the second oxide semiconductor film was set to 170°C.

[0449] For sample 5, the configuration other than the oxide semiconductor film 518 is the same as that of sample 4. This can be formed by referring to the description of sample 4.

[0450] (Sample 6) Sample 6 differs from Sample 4 in the structure of its oxide semiconductor film 518. Specifically, Sample 6 The oxide semiconductor film 518 consists of a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide A stacked structure of semiconductor films was adopted.

[0451] First, the first oxide semiconductor film is made by sputtering a target with In:Ga:Zn=1: A 3:2 (atomic ratio) target was used, with oxygen flowing at 30 sccm and oxygen flowing at 270 sccm. Argon is supplied as a sputtering gas into the processing chamber of the sputtering apparatus, and the processing chamber The internal pressure was controlled to 0.6 Pa, and 5 kW of DC power was supplied to form the structure.

[0452] Next, a second oxide semiconductor film was continuously formed on the first oxide semiconductor film in a vacuum. The second oxide semiconductor film was formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2 ( atom ratio), and oxygen with a flow rate of 100 sccm and argon with a flow rate of 100 sccm were supplied into the processing chamber of the sputtering apparatus as sputtering gases. The pressure in the processing chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied for formation.

[0453] Next, a third oxide semiconductor film was continuously formed on the second oxide semiconductor film in a vacuum. The third oxide semiconductor film was formed using a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2 ( atom ratio), and oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm were supplied into the processing chamber of the sputtering apparatus as sputtering gases. The pressure in the processing chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied for formation. The substrate temperature when forming the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film was set to 170 °C.

[0454] For Sample 6, regarding the configuration other than the oxide semiconductor film 518, since it is the same as that of Sample 4, it can be formed by referring to the description of Sample 4.

[0455] Samples 1 to 6 prepared above are transistors with a channel length (L) of 6 μm and a channel width (W ) of 50 μm.

[0456] <Vg-Id Characteristics> Next, the Vg-Id characteristics were measured as the initial characteristics of the transistors of Samples 1 to 6. Here, the substrate temperature was set to 25 °C, the potential difference between the source and drain (hereinafter referred to as the drain voltage) was set to 1 V and 10 V, and the potential difference between the source and gate electrodes (hereinafter referred to as the gate voltage ​The current flowing between the source and drain when the voltage is varied from -15V to +20V ( Below, the drain current (Vg-Id) change characteristics were measured.

[0457] <Gate BT stress test> Next, the gate BT stress test (hereinafter,) was performed on samples 1 to 6 after the initial characteristics measurement was completed. A GBT test was performed. Here, the GBT test conditions were set with a substrate temperature of 60°C, and the measurement was performed. Under constant conditions, in a dark room (dark environment), a gate voltage of +30V was applied for 1 hour. The stresses were applied to samples 1 through 6. The GBT test is a type of accelerated stress test, and it is a long-term stress test. To quickly evaluate the changes in transistor characteristics (i.e., changes over time) caused by the use of [this method]. This can be done. Investigating the amount of change in transistor characteristics before and after the GBT test is reliable. It serves as an important indicator for determining sex.

[0458] Figures 20 and 21 show the Vg-Id characteristics of the transistors for each sample and the Vg after the GBT test. -Id characteristics are shown. Figure 20(A) shows the initial characteristics and characteristics after GBT for sample 1. Figure 20(B) shows the initial characteristics of sample 2 and the characteristics after GBT, and Figure 20(C) shows the initial characteristics of sample 3. Figure 21(A) shows the initial characteristics and post-GBT characteristics of sample 4. The results are shown in Figure 21(B) for the initial characteristics of sample 5 and the characteristics after GBT, and in Figure 21(C) for the test The initial characteristics and post-GBT characteristics of material 6 are shown, respectively.

[0459] Furthermore, in the graphs shown in Figures 20 and 21, the horizontal axis represents the gate voltage Vg, and the first vertical axis represents the gate voltage Vg. The first vertical axis represents the drain current Id, and the second vertical axis represents the field-effect mobility μFE.

[0460] The horizontal axis is shown from -15V to 20V. The solid line represents a drain voltage Vd of 1 The initial Vg-Id characteristics when V is 10V, and the characteristics when the gate voltage Vg is 10V. This shows the field-effect mobility of the initial characteristics with respect to the gate voltage. The dashed line represents the drain voltage Vd. The Vg-Id characteristics after GBT testing when the gate voltage Vg is 1V and 10V, and the gate voltage Vg is set to 10V. This represents the field effect mobility after the GBT test with respect to the gate voltage at that time. The mobility values ​​are those obtained in the saturation region for each sample.

[0461] Furthermore, 20 transistors with the same structure were fabricated on the substrate for each sample. In the graphs shown in Figures 20 and 21, the data from 20 transistors are superimposed. It is showing.

[0462] From Figures 20 and 21, in the initial characteristics shown by the solid lines for samples 1 to 6, It can be seen that good switching characteristics have been obtained. On the other hand, the dashed line shows the results after the GBT test. Regarding the characteristics, samples 1 to 3 showed little variation from their initial characteristics. The fluctuations are extremely small (the dashed line generally overlaps with the solid line in the diagram). However, In samples 4 to 6 shown in Figure 21, the initial characteristics shown by the solid line are compared with the G shown by the dashed line. Significant changes were observed in the characteristics after the BT test. Specifically, after the GBT test... The rising voltage is shifted in the negative direction. Also, the gate voltage (Vg) is shifted in the negative direction. When the direction is changed from the eggplant direction to the positive direction, it has two peaks that change in a gradual manner.

[0463] The large structures of Sample 1 to Sample 3, which represent one aspect of the present invention, and Sample 4 to Sample 6, which are for comparison, are as follows: The difference lies in the back gate electrodes (back gate electrode 527 and back gate electrode 528). The shape is different. In Sample 1 to Sample 3, which is one aspect of the present invention, the back gate electrode The shape of 527 covers the oxide semiconductor film 518 and overlaps with the gate electrode 515 and the edge. In other words, the side of the channel portion of the oxide semiconductor film 518 is the upper and lower gate electrodes (gate It can be said that the structure is covered by electrodes 515 and back gate electrode 527. Then, at the outer periphery of the channel side of the oxide semiconductor film 518, the upper and lower gate electrodes (gate electrodes) The poles 515 and back gate electrode 527) are dielectrics (gate insulating film 517 and protective film 526) It can also be described as a structure that is opposed to each other through a mediated connection.

[0464] On the other hand, in comparative samples 4 to 6, the shape of the back gate electrode 528 was acid It is formed inside the ionized semiconductor film 518.

[0465] After the GBT test, at the outer periphery of the channel side surface of the oxide semiconductor film 518, Live channels are easily formed. However, in one embodiment of the present invention, samples 1 to 3 are acid The outer periphery of the channel side of the semiconductor film 518 is connected to the upper and lower gate electrodes (gate electrodes 515 The structure is covered by the back gate electrode 527). Therefore, the upper and lower gates Parasitic channels may be generated on the outer periphery of the channel side surface of the oxide semiconductor film 518 due to the electrode. This can eliminate the parasitic channels or reduce their influence. [Examples]

[0466] This example describes the estimation of device lifetime in terms of degradation characteristics after GBT testing. .

[0467] In this embodiment, sample 7, which is one aspect of the present invention, was prepared. Samples 8 to 10 were also compared. This was used as an example. For sample 7, which is one embodiment of the present invention, refer to Figure 22 for comparative samples. Fees 8 through 10 will be explained with reference to Figures 23 and 24, respectively.

[0468] (Sample 7) Sample 7 consists of a substrate 511, a gate electrode 515 on the substrate 511, and the substrate 511 and gate A gate insulating film 517 on the electrode 515, and a gate insulating film 517 provided on the gate insulating film 517, and gate An oxide semiconductor film 518 provided in the region overlapping with pole 515, and a gate insulating film 517 and A pair of electrodes 521 and 522 on the oxide semiconductor film 518, and the oxide semiconductor film 518 and a pair A protective film 526 on electrodes 521 and 522, and a gate electrode provided on the protective film 526. It has a back gate electrode 527 provided in a region overlapping with 515 (see Figure 22). .

[0469] The protective film 526 consists of oxide insulating film 523, oxide insulating film 524, and nitride insulating film. It was formed with a three-layer stacked structure of 525. Also, both ends of the back gate electrode 527 are as shown in Figure 22. As shown in (B), it roughly coincides with both ends of the gate electrode 515. Also, the backgear As shown in Figure 22(C), the electrode 527 is connected to the oxide semiconductor film 51 via the protective film 526. It was formed to cover 8.

[0470] Regarding the preparation method for sample 7 shown in Figure 22, the same preparation method as for sample 1 shown in Example 1 is used. This is the method. Therefore, sample 7 can be formed by using the preparation method described for sample 1. It is possible.

[0471] (Sample 8) Sample 8 consists of a substrate 511, a gate electrode 515 on the substrate 511, and the substrate 511 and gate A gate insulating film 517 on the electrode 515, and a gate insulating film 517 provided on the gate insulating film 517, and gate An oxide semiconductor film 518 is provided in the region overlapping with the pole 515, and on the oxide semiconductor film 518 A retaining plate is provided and has a pair of openings 550, 552 that reach the oxide semiconductor film 518. A protective film 540 and a pair of electric fields provided on the protective film 540 and in contact with the oxide semiconductor film 518 Electrodes 521, 522, protective film 540 and protective film 542 on the pair of electrodes 521, 522, Backgear provided on the protective film 542 and in the region overlapping with the gate electrode 515 It has an electrode 544 (see Figure 23).

[0472] Furthermore, the end of the back gate electrode 544 is as shown in Figure 23(B), gate electrode 51 It is located inside the ends of 5. The back gate electrode 544 is shown in Figure 23(C). Thus, the oxide semiconductor film 518 is covered via protective films 540 and 542.

[0473] Next, the configuration of sample 8 shown in Figure 23 is described below.

[0474] The substrate 511 has a gate electrode 515. The gate electrode 515 is made of Mo with a thickness of 30 nm. - This is a laminated film consisting of a Ti film and a Cu film with a thickness of 315 nm.

[0475] The gate electrode 515 has a gate insulating film 517. The gate insulating film 517 has a thickness of 30 This is a laminated film consisting of a silicon nitride film with a thickness of nm and a silicon oxide film with a thickness of 400 nm.

[0476] The gate insulating film 517 has an oxide semiconductor film 518. The oxide semiconductor film 518 has a thickness This is a 50nm IGZO film.

[0477] The oxide semiconductor film 518 has a protective film 540 with openings 550 and 552. Film 540 is a silicon oxide film with a thickness of 100 nm.

[0478] A pair of electrodes 521 and 522 are provided on a protective film 540 so as to cover the openings 550 and 552. Electrodes 521 and 522 consist of a 30nm thick Mo-Ti film and a 425nm thick Cu film. It is a multilayer film.

[0479] The device has a protective film 540 and a protective film 542 on electrodes 521 and 522. The protective film 542 is thick It is a silicon oxide film with a thickness of 325 nm.

[0480] A back gate electrode 544 is provided on the protective film 542. The back gate electrode 544 has a thickness This is a multilayer film consisting of a 30nm Mo-Ti film and a 10nm thick ITO film.

[0481] (Sample 9) Sample 9 consists of a substrate 511, a gate electrode 515 on the substrate 511, and the substrate 511 and gate A gate insulating film 517 on the electrode 515, and a gate insulating film 517 provided on the gate insulating film 517, and gate An oxide semiconductor film 518 provided in the region overlapping with pole 515, and a gate insulating film 517 and A pair of electrodes 521 and 522 on the oxide semiconductor film 518, and the oxide semiconductor film 518, and It has a protective film 526 on a pair of electrodes 521, 522 (see Figure 24).

[0482] The protective film 526 consists of oxide insulating film 523, oxide insulating film 524, and nitride insulating film. It was formed with a 3-layer laminated structure of 525.

[0483] Furthermore, sample 9 has a structure that does not include a back gate electrode, compared to sample 7.

[0484] Next, the method for preparing sample 9 shown in Figure 24 is described below.

[0485] A gate electrode 515 was formed on the substrate 511. The gate electrode 515 had a thickness of 10n. A tungsten film of m was used.

[0486] Next, a gate insulating film 517 was formed on the gate electrode 515. Therefore, a silicon nitride film with a thickness of 400 nm and a silicon oxide nitride film with a thickness of 50 nm are laminated together. It was formed by [doing something].

[0487] Next, an oxide semiconductor film 518 was formed on the gate insulating film 517. For example 8, a 35 nm thick IGZO film was used. This IGZO film was composed of In:Ga:Zn= A target with a 1:1:1 (atomic ratio) was used.

[0488] Next, a pair of electrodes 521 and 522 were formed on the oxide semiconductor film 518. Electrodes 521, 5 22 consists of a tungsten film with a thickness of 50 nm and an aluminum film with a thickness of 400 nm. A 200 nm thick titanium film and a laminated film were used.

[0489] Next, a protective film 526 was formed on the oxide semiconductor film 518 and electrodes 521 and 522. The protective film 526 consists of a silicon oxidizride film with a thickness of 50 nm and a silicon oxidizride film with a thickness of 400 nm. A silicon film and a silicon nitride film with a thickness of 100 nm were used. The silicon oxide film was deposited at a substrate temperature of 350°C. Additionally, a 400nm thick nitrided film was formed. The silicon film and the 100 nm thick silicon nitride film were deposited at a substrate temperature of 220°C.

[0490] Sample 9 was prepared using the above procedure.

[0491] (Sample 10) Sample 10 is the same as Sample 9 described earlier, along with oxide semiconductor film 518 and oxide semiconductor film type 518. The post-forming heat treatment differs.

[0492] Specifically, the oxide semiconductor film 518 of sample 10 consists of a first oxide semiconductor film and a second A stacked structure of two oxide semiconductor films was adopted. The first oxide semiconductor film had a thickness of 35 nm. An IGZO film was used. The first oxide semiconductor film had an In:Ga:Zn ratio of 1:1:1. A target with an atomic ratio was used. Furthermore, the second oxide semiconductor film had a thickness of 20 nm. An IGZO film was used. The second oxide semiconductor film had a ratio of In:Ga:Zn=1:3:2 A target (based on the ratio of atoms) was used.

[0493] Furthermore, after the formation of the oxide semiconductor film 518 on sample 10, it was subjected to a nitrogen atmosphere at 450°C for 1 hour. Heat treatment was performed.

[0494] Sample 10 was prepared using the above steps. Note that, apart from the steps described above, the preparation of Sample 10 was carried out first. Since it is the same as sample 9 described above, sample 10 can be prepared by referring to the above description. .

[0495] The transistors in samples 7, 9, and 10 have a channel length (L) of 6 μm. The channel width (W) is 50 μm. Also, the transistor in sample 8 has a channel length (L). The channel width (W) is 10.2 μm and 82.6 μm.

[0496] <Regarding device life estimation in plus-GBT testing> Next, the Plus GBT test was performed on samples 7 to 10 prepared above. Here, Gate B The stress test conditions were set to a substrate temperature of 60°C and a darkroom environment for measurement. In the diagram below, a gate voltage of +30V was applied, and the stress time was conditioned accordingly.

[0497] Furthermore, for samples 7, 9, and 10, the stress time was 1 Set the threshold voltage fluctuation to 00 seconds, 500 seconds, 1500 seconds, 2000 seconds, and 3600 seconds. The following measurements were taken. For sample 8, stress times were measured at 100 seconds, 300 seconds, and 600 seconds. The threshold voltage fluctuation was measured at intervals of 1000 seconds, 1800 seconds, and 3600 seconds.

[0498] Figure 25 shows the variation in threshold voltage at each stress time for samples 7 to 10, and each variation The approximation curves obtained from the dynamic values ​​are shown. Note that all approximation curves shown in Figure 25 are power-law approximation curves. Furthermore, Figure 25 is a log-log graph, and in Figure 25, the horizontal axis represents stress time expressed on a logarithmic scale. The vertical axis shows the fluctuation amount of the threshold voltage (ΔVth) expressed logarithmically. Also, Figure 25 shows The log-log graph shown has equal intervals between the logarithmic scales on the horizontal and vertical axes.

[0499] As shown in Figure 25, the stress time expressed logarithmically for sample 7, which is one embodiment of the present invention, is This involves approximating the logarithmic fluctuation of the threshold voltage as a power, and the threshold voltage fluctuation as 0V It can be seen that the angle formed with the straight line is approximately 17°. Also, the stress time is 0.1 hours. It can be seen that the threshold voltage fluctuation is around 0.06V at that time. Also, the cumulative of sample 7 The slope of the approximation line was 0.3119 V / hr.

[0500] Furthermore, the threshold energy, expressed logarithmically, was compared with the stress time expressed logarithmically for the comparative sample 8. The angle between the power approximation line of the voltage fluctuation and the line where the threshold voltage fluctuation is 0V is approximately 31°. It can be seen that it is nearby. Also, the amount of change in threshold voltage when the stress time is 0.1 hours. It can be seen that it is near 0.05V. Also, the slope of the power approximation line for sample 8 is 0.599. It was 3V / hr.

[0501] Furthermore, the threshold energy, expressed logarithmically, was compared with the stress time, expressed logarithmically, for comparative sample 9. The angle between the power approximation line of the voltage fluctuation and the line where the threshold voltage fluctuation is 0V is approximately 24°. It can be seen that it is nearby. Also, the amount of change in threshold voltage when the stress time is 0.1 hours. It can be seen that it is near 0.4V. Also, the slope of the power approximation line for sample 9 is 0.41V / It was hr.

[0502] Furthermore, the logarithmic threshold value was expressed in relation to the stress time expressed logarithmically for the 10 comparative samples. The angle between the power-of-the-volume approximation line of the voltage fluctuation and the line where the threshold voltage fluctuation is 0V is 27°. It can be seen that they are in the vicinity. Also, the threshold voltage fluctuation when the stress time is 0.1 hours. It can be seen that the quantity is around 0.02V. Also, the slope of the power approximation line for sample 10 is 0.4 The voltage was 153V / hr.

[0503] As shown in Figure 25, sample 7 of one embodiment of the present invention has a stress time expressed in logarithm. , the logarithmic approximation line of the fluctuation amount of the threshold voltage and the linear approximation line of the fluctuation amount of the threshold voltage when it is 0V The threshold voltage when the angle with the line is 30° or less and the stress time is 0.1 hours is The fluctuation is less than 0.2V. Semiconductor devices using this relationship have a threshold voltage variation. The motion is small. Sample 7 of one embodiment of the present invention has a side surface of the channel formation region of an oxide semiconductor film. It has been found that covering the transistor gates with upper and lower gates can reduce the amount of variation in transistor characteristics. It was.

Claims

1. A first conductive film on the substrate, The first insulating film on the first conductive film, An oxide semiconductor film having a region overlapping with the first conductive film, via the first insulating film, A second conductive film electrically connected to the oxide semiconductor film, A third conductive film electrically connected to the oxide semiconductor film, The second insulating film on the oxide semiconductor film, A fourth conductive film having a region overlapping with the oxide semiconductor film, via the second insulating film, The first conductive film has a region that functions as the first gate electrode of the transistor. The oxide semiconductor film has a region that functions as a channel formation region of the transistor, The second conductive film has a region that functions as either the source electrode or the drain electrode of the transistor. The third conductive film has a region that functions as the source electrode or the other of the drain electrode of the transistor. The second insulating film comprises an oxide insulating film and a nitride insulating film on the oxide insulating film. The fourth conductive film has a region that functions as the second gate electrode of the transistor, In the channel width direction of the transistor, the first conductive film has a region that does not overlap with the oxide semiconductor film. In the channel width direction of the transistor, the fourth conductive film has a region that does not overlap with the oxide semiconductor film. In a darkroom gate BT stress test, The temperature of the substrate is set to 60°C. A +30V is applied to the first conductive film and the fourth conductive film. Assuming stress duration is 0.1 hours, A semiconductor device in which, when the drain voltage of the transistor is set to 1V or 10V before and after the gate BT stress test, the amount of fluctuation in the threshold voltage calculated from the Vg-Id characteristic is less than 0.2V.

2. A first conductive film on the substrate, The first insulating film on the first conductive film, An oxide semiconductor film having a region overlapping with the first conductive film, via the first insulating film, A second conductive film electrically connected to the oxide semiconductor film, A third conductive film electrically connected to the oxide semiconductor film, The second insulating film on the oxide semiconductor film, A fourth conductive film having a region overlapping with the oxide semiconductor film, via the second insulating film, The first conductive film has a region that functions as the first gate electrode of the transistor. The first insulating film comprises a first nitride insulating film and a first oxide insulating film on the first nitride insulating film. The oxide semiconductor film has a region that functions as a channel formation region of the transistor, The second conductive film has a region that functions as either the source electrode or the drain electrode of the transistor. The third conductive film has a region that functions as the source electrode or the other of the drain electrode of the transistor. The second insulating film comprises a second oxide insulating film and a second nitride insulating film on the second oxide insulating film. The fourth conductive film has a region that functions as the second gate electrode of the transistor, In the channel width direction of the transistor, the first conductive film has a region that does not overlap with the oxide semiconductor film. In the channel width direction of the transistor, the fourth conductive film has a region that does not overlap with the oxide semiconductor film. In a darkroom gate BT stress test, The temperature of the substrate is set to 60°C. A +30V is applied to the first conductive film and the fourth conductive film. Assuming stress duration is 0.1 hours, A semiconductor device in which, when the drain voltage of the transistor is set to 1V or 10V before and after the gate BT stress test, the amount of fluctuation in the threshold voltage calculated from the Vg-Id characteristic is less than 0.2V.

3. In claim 1 or claim 2, The oxide semiconductor film comprises In, M (where M is Al, Ga, Y, Zr, La, Ce, or Nd), and Zn, and is a semiconductor device.

Images