Encoder, decoder, and corresponding method using compact MV storage

Abstract

To provide a method for reducing memory capacity in storing information for deriving a temporal motion vector prediction, while keeping the motion vector representation and precision in reasonable ranges.SOLUTION: A motion vector compression method comprises: obtaining a temporal motion vector; determining a compressed motion vector using a binary representation of the temporal motion vector comprising an exponent part and / or a mantissa part. where the exponent part comprises N bits, the mantissa part comprises M bits, N is a non-negative integer and M is a positive integer; and performing a temporal motion vector prediction (TMVP) using the compressed motion vector.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] Embodiments of the present application generally relate to the field of image processing, and more specifically, to a technique for reducing the memory capacity for storing motion vector information.

Background Art

[0002] Video coding (video encoding and decoding) is used in a wide range of digital video applications, such as broadcast digital TV, video transmission via the Internet and mobile networks, or real-time conversational applications such as video chat, video conferencing, DVDs and Blu-ray discs, video content acquisition and editing systems, and camcorders for security applications.

[0003] Even when rendering a relatively short video, the amount of video data required can be quite large, and as a result, difficulties may arise when the data is to be streamed or otherwise communicated via a communication network with limited bandwidth capacity. Therefore, video data is generally compressed before being communicated via modern telecommunication networks. The size of the video can also be a problem when the video is stored on a storage device, as the memory resources may be limited. Video compression devices often use software and / or hardware at the source to encode the video data before transmission or storage, thereby reducing the amount of data required to represent the digital video image. The compressed data is then received at the destination by a video decompression device that decodes the video data. In view of limited network resources and the continuing demand for high video quality, improved compression and decompression techniques that improve the compression ratio without sacrificing much to almost no image quality are desired.

Summary of the Invention

[0004] The object of the present invention is to provide a means for reducing memory capacity while maintaining a reasonable range of motion vector representation and accuracy when storing information for deriving temporal motion vector predictions.

[0005] This problem is solved by the present invention by providing a motion vector compression method that includes the steps of: obtaining a temporal motion vector; determining a compressed motion vector using a binary representation of the temporal motion vector including an exponent and / or mantissa, wherein the exponent includes N bits and the mantissa includes M bits, where N is a non-negative integer and M is a positive integer; and performing temporal motion vector prediction (TMVP) using the compressed motion vector.

[0006] In one embodiment, a step may be applied in which at least one bit shift operation is performed based on the exponent or mantissa of the temporal motion vector to obtain a compressed motion vector.

[0007] In another embodiment, the exponent may correspond to the most significant bit (MSB) of the binary representation and the mantissa may correspond to the least significant bit (LSB) of the binary representation, or the exponent may correspond to the LSB of the binary representation and the mantissa may correspond to the MSB of the binary representation.

[0008] In addition, if the exponent corresponds to the MSB of the binary representation and the mantissa corresponds to the LSB of the binary representation, the value of the compressed motion vector may be derived by the following steps: deriving a first shift value by applying a right shift of M bits to the binary representation; deriving the last M bits of the binary representation as a first basic binary representation; and deriving the value of the compressed motion vector by applying a left shift of the bits of the first shift value to the first basic binary representation.

[0009] Alternatively, if the exponent corresponds to the LSB of the binary representation and the mantissa corresponds to the MSB of the binary representation, the value of the motion vector component may be derived by the following steps: deriving the last N bits of the binary representation as the second shift value; deriving the second basic binary representation by applying a right shift of N bits to the binary representation; and deriving the value of the compressed motion vector by applying a left shift of the bits of the second shift value to the second basic binary representation.

[0010] According to one embodiment, the temporal motion vector may include a horizontal component of the motion vector and a vertical component of the motion vector.

[0011] According to another embodiment, the motion vector compression method may include a step of encoding a first indicator, the first indicator being used to indicate whether or not a temporal motion vector has been compressed by the motion vector compression method according to the present invention.

[0012] The motion vector compression method may include a step of determining the value of N. Furthermore, the step of determining the value of N may include a step of encoding the value of N, or a step of setting a predetermined value as the value of N, or a step of deriving the value of N based on the resolution of an image unit, wherein the image unit includes an image or a tile set, or a step of deriving the value of N based on the size of a coding tree unit (CTU) or coding unit (CU).

[0013] More specifically, the step of deriving the value of N based on the resolution of the image unit may include the step of setting the value of N to 0 if the width of the image unit is less than a first threshold and the height of the image unit is less than a first threshold, or the step of coding a second indicator to represent the value of N if the width of the image unit is less than a second threshold and the height of the image unit is less than a second threshold, or the step of coding a third indicator to represent the value of N.

[0014] The second indicator may be binarized with 1 bit, and the third indicator may be binarized with 2 bits.

[0015] In one embodiment, the first indicator, the second indicator, and / or the third indicator may be included in the sequence parameter set (SPS), image parameter set (PPS), slice header, or tile group header in the bitstream.

[0016] Furthermore, the above problems are solved by the present invention by providing a motion vector compression method that includes the steps of: obtaining a temporal motion vector; determining the exponent or mantissa of the temporal motion vector; performing at least one bit shift operation based on the exponent or mantissa of the temporal motion vector to obtain a compressed motion vector, wherein the exponent corresponds to the least significant bit (LSB) of the compressed motion vector and the mantissa corresponds to the most significant bit (MSB) of the compressed motion vector; and performing temporal motion vector prediction (TMVP) using the compressed motion vector.

[0017] The above problem includes the steps of: coding a first flag; performing a first method if the first flag is a first value; and performing a second method if the first flag is a second value, wherein the first value is different from the second value, and the original value of the first motion vector component of the current image block is binarized by M bits, wherein the first method includes the steps of: applying an N-bit right shift to the original value, where (MN) is equal to a predetermined value, and N and M are positive integers; setting the right-shifted original value as a saved value for the first motion vector component; and coding a subsequent image block based on the saved value, wherein the second method includes the steps of: applying a clipping operation to the original value, where the clipped motion vector component represented by the clipped original value is -2 M-N-1 ~2 M-N-1The present invention further solves this problem by providing a motion vector-based coding method that includes a step limited to between -1, a step of setting the clipped original value as a saved value of the first motion vector component, and a step of coding subsequent image blocks based on the saved value.

[0018] In one embodiment, after setting the original right-shifted value as a saved value of the motion vector according to the first method, the method may further include the step of applying an N-bit left shift to the saved value, and the step of encoding a subsequent image block based on the saved value includes the step of encoding a subsequent image block based on the left-shifted saved value.

[0019] Alternatively, following the second method, the method may further include a step of determining a restored value of the first motion vector component based on the restored value, wherein the restored value is binarized in M ​​bits, the last (MN) bits of the restored value are the same as the restored value, if the restored value is positive, each of the first N bits of the restored value is equal to 0, and if the restored value is negative, each of the first N bits of the restored value is equal to 1, and a step of encoding a subsequent image block based on the restored value.

[0020] In one embodiment, the subsequent image block and the current block may be in different images, and the prediction mode for the subsequent image block may include temporal motion vector prediction (TMVP) and / or alternative temporal motion vector prediction (ATMVP).

[0021] In another embodiment, the first flag may be coded for each image, or for each tile, or for each tileset, or for each slice.

[0022] In another embodiment, the first flag may be included in a sequence parameter set (SPS), a picture parameter set (PPS), a slice header, or a tile group header in the bitstream.

[0023] According to one embodiment, the current image block may further have a second motion vector component, the coding method may further include a step of coding a second flag, and when the second flag is a first value, the first method may be executed for the second motion vector component, and when the second flag is a second value, the second method may be executed for the second motion vector component.

[0024] According to another embodiment, before coding the first flag, the coding method may further include a step of determining whether the resolution of the current image is greater than or equal to a first preset value, and the current image block may be within the current image.

[0025] Furthermore, when the resolution of the current image is smaller than the first preset value, the second method may be executed.

[0026] Also, when the current image is divided into a plurality of tile sets, the second method may be executed, or when the resolution of the tile set is smaller than a second preset value, the second method may be executed.

[0027] According to one embodiment, before coding the first flag, the coding method may further include a step of determining whether the size of the coding tree unit (CTU), coding unit (CU), image block, or unit of the current image block meets a first size condition.

[0028] Furthermore, if the size of the CTU, CU, image block, or unit of the current image block satisfies a second size condition, the first method may be executed, or if the size of the CTU, CU, image block, or unit of the current image block satisfies a third size condition, the second method may be executed.

[0029] In addition, the present invention includes a step of determining the size of the CTU, CU, image block, or unit of the current image block, a step of executing at least one of the first method and the second method based on the size, or a step of determining the resolution of the current image, and a step of executing at least one of the first method and the second method based on the resolution. The original value of the first motion vector component of the current image block is binarized with M bits, and the first method is a step of applying a right shift of N bits to the original value, where (M - N) is equal to a predetermined value, and N and M are positive integers. A step of setting the right-shifted original value as the stored value of the first motion vector component, and a step of coding subsequent image blocks based on the stored value. The second method is a step of applying a clipping operation to the original value, and the clipped motion vector component represented by the clipped original value is M-N-1 ~2 M-N-1 limited to -1, a step of setting the clipped original value as the stored value of the first motion vector component, and a step of coding subsequent image blocks based on the stored value. A coding method based on a motion vector is also provided.

[0030] In addition, the above problem is also solved by a program that causes a computer to execute any one of the above methods.

[0031] In addition, the above problem is also solved by a decoder including a circuit configured to execute any one of the above methods.

[0032] Furthermore, the above problems can also be solved by an encoder, which has a circuit configured to perform one of the methods described above.

[0033] The coding described above can be either encoding or decoding.

[0034] Further features and advantages of the present invention will be described with reference to the drawings. In the description, accompanying drawings intended to illustrate preferred embodiments of the present invention will be referenced. It will be understood that such embodiments do not represent the entire scope of the present invention. [Brief explanation of the drawing]

[0035] Embodiments of the present invention will be described in more detail below with reference to the attached drawings.

[0036] [Figure 1A] This block diagram shows an example of a video coding system configured to implement an embodiment of the present invention.

[0037] [Figure 1B] This block diagram shows another example of a video coding system configured to implement an embodiment of the present invention.

[0038] [Figure 2] This is a block diagram showing an example of a video encoder configured to implement an embodiment of the present invention.

[0039] [Figure 3] This is a block diagram illustrating an exemplary structure of a video decoder configured to implement an embodiment of the present invention.

[0040] [Figure 4] A block diagram showing an example of an encoding device or a decoding device.

[0041] [Figure 5]A block diagram showing another example of an encoding or decoding device.

[0042] [Figure 6] This figure shows an example of an implementation form of the present invention.

[0043] [Figure 7] This figure shows an example of another implementation form of the present invention.

[0044] [Figure 8] This figure shows an example of another implementation form of the present invention.

[0045] [Figure 9] This figure shows an example of another implementation form of the present invention.

[0046] [Figure 10] This is a flowchart illustrating the motion vector compression method according to the present invention.

[0047] Hereafter, unless explicitly specified otherwise, the same reference numeral refers to the same or at least functionally equivalent function. [Modes for carrying out the invention]

[0048] The following description refers to the accompanying drawings, which form part of the present disclosure and illustrate specific embodiments of the present invention or specific embodiments in which the present invention may be used. It is understood that the embodiments of the present invention may be used in other embodiments and may include structural or logical variations not shown in the drawings. Accordingly, the following detailed description should not be construed as limiting, and the scope of the present invention is defined by the appended claims.

[0049] For example, disclosures relating to a described method may also apply to a corresponding device or system configured to perform the method, and vice versa. For example, if one or more steps of a particular method are described, the corresponding device may include one or more such units, e.g., functional units, to perform the described steps of the one or more steps of the method (e.g., one unit performing the one or more steps, or multiple units each performing one or more of the steps), even if one or more of the units are not explicitly described or shown in the drawings. On the other hand, for example, if a particular device is described based on one or more units, e.g., functional units, the corresponding method may include one such step (e.g., one step performing the function of one or more units, or multiple steps each performing the function of one or more of the units), even if one or more of the steps are not explicitly described or shown in the drawings. Furthermore, unless otherwise specifically noted, it is understood that the features of the various exemplary embodiments and / or aspects described herein may be combined with each other.

[0050] Video coding typically refers to the processing of a series of images that make up a video or video sequence. The terms “frame” or “image” may be used as synonyms in the field of video coding instead of “image.” Video coding (or coding in general) consists of two parts: video encoding and video decoding. Video encoding is performed on the source side and typically involves processing the original video image (e.g., by compression) to reduce the amount of data required to represent the video image (for more efficient storage and / or transmission). Video decoding is performed on the destination side and typically involves the reverse processing compared to the encoder to reconstruct the video image. Embodiments referring to “coding” of video images (or images in general) shall be understood to relate to the “encoding” or “decoding” of the video image or each video sequence. The combination of the encoding and decoding parts is also referred to as a codec (coding and decoding).

[0051] In lossless video coding, the original video image can be reconstructed, meaning the reconstructed video image is of the same quality as the original video image (assuming there is no transmission loss or other data loss during storage or transmission). In lossy video coding, further compression is performed, for example, by quantization, to reduce the amount of data representing the video image, but this cannot be fully reconstructed in the decoder; that is, the quality of the reconstructed video image is lower or degraded compared to the quality of the original video image.

[0052] Several video coding standards belong to the group of “lossy hybrid video codecs” (i.e., combining spatial and temporal prediction in the sample domain with 2D transform coding to apply quantization in the transform domain). Each image in a video sequence is typically divided into a set of non-overlapping blocks, and coding is typically performed at the block level. In other words, in the encoder, video is typically processed, i.e., encoded, at the block (video block) level by generating predicted blocks using, for example, spatial (in-image) and / or temporal (inter-image) predictions, obtaining residual blocks by subtracting the predicted blocks from the current block (the block currently being processed / will be processed), transforming the residual blocks and quantizing the residual blocks in the transform domain to reduce (compress) the amount of data to be transmitted. Meanwhile, in the decoder, the reverse processing compared to the encoder is applied to the encoded or compressed blocks in order to reconstruct the current block for representation. Furthermore, as the encoder repeats the decoder's processing loop, both will generate the same predictions (e.g., intra and inter predictions) and / or reconstructions for processing subsequent blocks, i.e., for coding.

[0053] The following describes embodiments of the video coding system 10, video encoder 20, and video decoder 30 with reference to Figures 1A to 3.

[0054] Figure 1A is a schematic block diagram showing an exemplary coding system 10, for example, a video coding system 10 (or simply coding system 10), in which the technology of the present application may be used. The video encoder 20 (or simply encoder 20) and video decoder 30 (or simply decoder 30) of the video coding system 10 represent examples of devices that may be configured to perform the technology according to the various examples described herein.

[0055] As shown in Figure 1A, the coding system 10 includes a source device 12 configured to provide encoded image data 21 to a destination device 14 for decoding the encoded image data (13).

[0056] The source device 12 includes an encoder 20, and may also include, optionally, an image source 16, a preprocessor (or preprocessing unit) 18, for example, an image preprocessor 18, and a communication interface or communication unit 22.

[0057] The image source 16 may include or be any type of image capturing device, e.g., a camera that captures images of the real world, and / or any type of image generating device, e.g., a computer graphics processor that generates computer-animated images, or any other type of device that acquires and / or provides images of the real world, computer-generated images (e.g., screen content, virtual reality (VR) images), and / or any combination thereof (e.g., augmented reality (AR) images). The image source may be any type of memory or storage that stores any of the above-mentioned images.

[0058] To distinguish it from processing performed by the preprocessor 18 and the preprocessing unit 18, the image or image data 17 may also be referred to as the raw image or raw image data 17.

[0059] The preprocessor 18 is configured to receive (raw) image data 17 and perform preprocessing on the image data 17 to obtain a preprocessed image 19 or preprocessed image data 19. The preprocessing performed by the preprocessor 18 may include, for example, cropping, color format conversion (e.g., RGB to YCbCr), color correction, or noise reduction. It is understood that the preprocessing unit 18 may be any selected component.

[0060] The video encoder 20 is configured to receive pre-processed image data 19 and to provide encoded image data 21 (further details are described below, for example, based on Figure 2).

[0061] The communication interface 22 of the source device 12 may be configured to receive encoded image data 21 via the communication channel 13 and to transmit the encoded image data 21 (or any further processed version thereof) to another device, such as the destination device 14 or any other device, for storage or direct reconstruction.

[0062] The destination device 14 includes a decoder 30 (e.g., a video decoder 30), and may also include, optionally, a communication interface or communication unit 28, a post-processor 32 (or post-processing unit 32), and a display device 34.

[0063] The communication interface 28 of the destination device 14 is configured to receive encoded image data 21 (or any further processed version thereof) directly from, for example, the source device 12 or from any other source, such as a storage device, such as an encoded image data storage device, and to provide the encoded image data 21 to the decoder 30.

[0064] Communication interfaces 22 and 28 may be configured to transmit or receive encoded image data 21 or encoded data between the source device 12 and the destination device 14 via a direct communication link, for example, a direct wired or wireless connection, or via any type of network, for example, a wired or wireless network or any combination thereof, or any type of private and public network or any combination thereof (13).

[0065] The communication interface 22 may be configured to process the encoded image data, for example, by packaging the encoded image data 21 into an appropriate format, for example, into a packet, and / or by using any kind of transmission encoding or processing for transmission over a communication link or communication network.

[0066] A communication interface 28, which is the counterpart to communication interface 22, may be configured, for example, to receive transmitted data and process the transmitted data using any type of corresponding transmission decoding or processing and / or depackaging to obtain encoded image data 21.

[0067] Both communication interfaces 22 and 28 may be configured as unidirectional or bidirectional communication interfaces, as indicated by the arrows of the communication channel 13 pointing from the source device 12 to the destination device 14 in Figure 1A, and may be configured, for example, to send and receive messages, to establish connections, and to confirm and exchange any other information related to communication links and / or data transmission, such as the transmission of encoded image data.

[0068] The decoder 30 is configured to receive encoded image data 21 and to provide decoded image data 31 or decoded image 31 (further details are described below, for example, based on Figure 3 or Figure 5).

[0069] The post-processor 32 of the destination device 14 is configured to post-process the decoded image data 31 (also called reconstructed image data), for example, the decoded image 31, to obtain post-processed image data 33, for example, the post-processed image 33. The post-processing performed by the post-processing unit 32 may include, for example, color format conversion (e.g., YCbCr to RGB), color correction, cropping, or resampling, or any other processing, for the purpose of preparing the decoded image data 31 for display by the display device 34.

[0070] The display device 34 of the destination device 14 is configured to receive post-processed image data 33 for displaying the image to, for example, a user or viewer. The display device 34 may include any type of display for representing the reconstructed image, such as an integrated or external display or monitor. The display may include, for example, a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a plasma display, a projector, a microLED display, a liquid crystal on silicon (LCoS), a digital optical processor (DLP), or any other type of display.

[0071] Although Figure 1A shows the source device 12 and the destination device 14 as separate devices, the device embodiment may include both or both of their functions, i.e., the source device 12 or its corresponding function and the destination device 14 or its corresponding function. In such embodiments, the source device 12 or its corresponding function and the destination device 14 or its corresponding function may be implemented using the same hardware and / or software, or by separate hardware and / or software, or any combination thereof.

[0072] As will be apparent to those skilled in the art based on this description, the presence and (exact) division of functions in different units or functions within source device 12 and / or destination device 14, as shown in Figure 1A, may vary depending on the actual device and application.

[0073] The encoder 20 (e.g., video encoder 20) or the decoder 30 (e.g., video decoder 30), or both the encoder 20 and the decoder 30, may be implemented via processing circuits, such as those shown in Figure 1B, including one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, dedicated video coding components, or any combination thereof. The encoder 20 may be implemented via processing circuits 46 to embody various modules described in relation to the encoder 20 of Figure 2 and / or any other encoder systems or subsystems described herein. The decoder 30 may be implemented via processing circuits 46 to embody various modules described in relation to the decoder 30 of Figure 3 and / or any other decoder systems or subsystems described herein. The processing circuits may be configured to perform various operations, as will be described later. When the technology is partially implemented in software, as shown in Figure 5, the device may store instructions for the software in a suitable non-temporary computer-readable storage medium and implement the technology of the disclosure by executing the instructions using one or more processors in hardware. Either the video encoder 20 or the video decoder 30 may be integrated as part of a combined encoder / decoder (codec) within a single device, for example, as shown in Figure 1B.

[0074] The source device 12 and destination device 14 may comprise any type of handheld or stationary device, including a wide range of devices such as notebook or laptop computers, mobile phones, smartphones, tablets or tablet computers, cameras, desktop computers, set-top boxes, televisions, display devices, digital media players, video gaming consoles, video streaming devices (such as content service servers or content distribution servers), broadcast receiver devices, broadcast transmitter devices, etc., and may or may not use an operating system. In some cases, the source device 12 and destination device 14 may support wireless communication. Therefore, the source device 12 and destination device 14 may be wireless communication devices.

[0075] In some cases, the video coding system 10 shown in Figure 1A is merely an example, and the technology of the present invention may be applied to video coding configurations (e.g., video encoding or video decoding) that do not necessarily involve any data communication between an encoding device and a decoding device. In other examples, data is retrieved from local memory and streamed over a network, etc. A video encoding device may encode and store the data in memory, and / or a video decoding device may decode and retrieve the data from memory. In some examples, encoding and decoding are performed by devices that do not communicate with each other but simply encode the data in memory and / or retrieve and decode the data from memory.

[0076] For the sake of explanation, embodiments of the present invention will be described herein with reference to, for example, reference software for High Efficiency Video Coding (HEVC) or Multipurpose Video Coding (VVC), which are next-generation video coding standards developed by the ITU-T Video Coding Expert Group (VCEG) and the ISO / IEC Video Coding Expert Group (MPEG) Joint Working Team on Video Coding (JCT-VC). Those skilled in the art will understand that embodiments of the present invention are not limited to HEVC or VVC.

[0077] [Encoder and encoding method]

[0078] Figure 2 shows a schematic block diagram of an exemplary video encoder 20 configured to implement the technology of the present invention. In the example of Figure 2, the video encoder 20 comprises an input 201 (or input interface 201), a residual calculation unit 204, a transformation processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transformation processing unit 212, a reconstruction unit 214, a loop filter unit 220, a decoded image buffer (DPB) 230, a mode selection unit 260, an entropy encoding unit 270, and an output 272 (or output interface 272). The mode selection unit 260 may comprise an inter-prediction unit 244, an intra-prediction unit 254, and a segmentation unit 262. The inter-prediction unit 244 may comprise a motion estimation unit and a motion compensation unit (not shown). The video encoder 20 shown in Figure 2 may also be referred to as a hybrid video encoder or a video encoder with a hybrid video codec.

[0079] The residual calculation unit 204, the conversion processing unit 206, the quantization unit 208, and the mode selection unit 260 may be referred to as forming the forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse conversion processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded image buffer (DPB) 230, the inter-prediction unit 244, and the intra-prediction unit 254 may be referred to as forming the reverse signal path of the video encoder 20. The reverse signal path of the video encoder 20 corresponds to the signal path of the decoder (see video decoder 30 in Figure 3). The inverse quantization unit 210, the inverse conversion processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded image buffer (DPB) 230, the inter-prediction unit 244, and the intra-prediction unit 254 may also be referred to as forming the "built-in decoder" of the video encoder 20.

[0080] [Images and Image Classification (Images and Blocks)]

[0081] The encoder 20 may be configured to receive, for example, an image 17 (or image data 17), for example, an image from a series of images forming a video or video sequence, via the input 201. The received image or image data may be a pre-processed image 19 (or pre-processed image data 19). For simplicity, the following description will refer to image 17. Image 17 may also be referred to as the current image or the image being coded (particularly in video coding to distinguish the current image from other images, for example, previously encoded and / or decoded images of the same video sequence, i.e., the video sequence that also includes the current image).

[0082] A (digital) image is, or can be considered, a two-dimensional array or matrix of samples with intensity values. A sample in an array may also be called a pixel (an abbreviation for image element) or pelle. The number of samples in the horizontal and vertical (or axis) directions of the array or image defines the size and / or resolution of the image. Typically, three color components are used to represent color; that is, an image may be represented by or contain a three-sample array. In RGB format or color space, an image contains corresponding red, green, and blue sample arrays. However, in video coding, each pixel is typically represented in luminance and chrominance format or color space, e.g., YCbCr, which includes a luminance component represented by Y (sometimes L is used instead) and two chrominance components represented by Cb and Cr. The luminance (or abbreviated luma) component Y represents the brightness or intensity of the gray level (e.g., in a grayscale image), while the two chrominance (or abbreviated chroma) components Cb and Cr represent chromaticity or color information components. Therefore, an image in YCbCr format includes a luminance sample array of luminance sample values ​​(Y) and two chrominance sample arrays of chrominance values ​​(Cb and Cr). An image in RGB format can be converted to or transformed into YCbCr format, and vice versa; this process is also known as color conversion or transformation. If the image is monochrome, it may include only the luminance sample array. Thus, an image may be, for example, an array of luminance samples in monochrome format, or two corresponding arrays of luminance samples and chromance samples in 4:2:0, 4:2:2, and 4:4:4 color formats.

[0083] Embodiments of the video encoder 20 may include an image segmentation unit (not shown in Figure 2) configured to segment an image 17 into a plurality of (typically non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macroblocks (H.264 / AVC), coding tree blocks (CTB), or coding tree units (CTU) (H.265 / HEVC and VVC). The image segmentation unit may use the same block size for all images and corresponding grids defining the block sizes of the video sequence, or it may vary the block size between images or subsets or groups of images to segment each image into a corresponding block.

[0084] In a further embodiment, the video encoder may be configured to directly receive blocks 203 of the image 17, for example, one, some, or all of the blocks that make up the image 17. The image blocks 203 may also be referred to as the current image block or the encoded image block.

[0085] Similar to Image 17, here too, the image block 203 is smaller in dimensions than Image 17, but is or can be considered to be a two-dimensional array or matrix of samples having intensity values ​​(sample values). In other words, block 203 may comprise, for example, one sample array (e.g., a lumar array in the case of monochrome image 17, or a lumar or chromar array in the case of a color image), or three sample arrays (e.g., a lumar and two chromar arrays in the case of color image 17), or any other number and / or type of arrays depending on the applied color format. The number of samples in the horizontal and vertical (or axis) directions of block 203 defines the size of block 203. Thus, the block may be, for example, an M×N (M columns × N rows) array of samples, or an M×N array of conversion coefficients.

[0086] The embodiment of the video encoder 20 shown in Figure 2 may be configured to encode the image 17 block by block, for example, encoding and prediction are performed for each block 203.

[0087] [Residual calculation]

[0088] The residual calculation unit 204 may be configured to calculate the residual block 205 (also referred to as residual 205) based on the image block 203 and the prediction block 265 (further details regarding the prediction block 265 will be provided later), for example, by subtracting the sample value of the prediction block 265 from the sample value of the image block 203 for each sample (for each pixel) to obtain the residual block 205 in the sample region.

[0089] [conversion]

[0090] The conversion processing unit 206 may be configured to apply a conversion, such as a discrete cosine transform (DCT) or discrete sine transform (DST), to the sample values ​​of the residual block 205 to obtain conversion coefficients 207 in the conversion region. The conversion coefficients 207 may also be called conversion residual coefficients and represent the residual block 205 in the conversion region.

[0091] The conversion processing unit 206 may be configured to apply an integer approximation of the DCT / DST conversion, such as the conversion specified for H.265 / HEVC. Compared to the orthogonal DCT conversion, such an integer approximation is typically scaled by a specific coefficient. An additional scaling coefficient is applied as part of the conversion process to preserve the norm of the residual blocks processed by the forward and inverse conversions. The scaling coefficient is typically selected based on specific constraints, such as a scaling coefficient that is a power of 2 with respect to the shift operation, the bit depth of the conversion coefficient, or a trade-off between accuracy and implementation cost. For example, a specific scaling coefficient may be specified for the inverse conversion by the inverse conversion processing unit 212 (and the corresponding inverse conversion by the inverse conversion processing unit 312 in the video decoder 30, for example), and a corresponding scaling coefficient for the forward conversion by the conversion processing unit 206 in the encoder 20 may be specified accordingly.

[0092] Embodiments of the video encoder 20 (each a conversion processing unit 206) may be configured to encode or compress conversion parameters, such as one or more conversion types, for example, directly or via an entropy encoding unit 270, before outputting them, so that, for example, the video decoder 30 can receive and use the conversion parameters for decoding.

[0093] [Quantization]

[0094] The quantization unit 208 may be configured to obtain quantization coefficients 209 by quantizing the transformation coefficients 207, for example, by applying scalar quantization or vector quantization. The quantization coefficients 209 may also be referred to as quantization transformation coefficients 209 or quantization residual coefficients 209.

[0095] The quantization process can reduce the bit depth associated with some or all of the 207 conversion coefficients. For example, n-bit conversion coefficients may be rounded to m-bit conversion coefficients during quantization, where n is greater than m. The degree of quantization can be changed by adjusting the quantization parameter (QP). For example, in the case of scalar quantization, different scalings may be applied to achieve finer or coarser quantization. Smaller quantization step sizes correspond to finer quantization, while larger quantization step sizes correspond to coarser quantization. Applicable quantization step sizes can be indicated by the quantization parameter (QP). The quantization parameter may be, for example, an index to a predefined set of applicable quantization step sizes. For example, a small quantization parameter may correspond to finer quantization (smaller quantization step size), a large quantization parameter may correspond to coarser quantization (larger quantization step size), and vice versa. Quantization may involve division by the quantization stage size, and the corresponding and / or inverse dequantization by, for example, the inverse quantization unit 210 may involve multiplication by the quantization stage size. Embodiments according to some standards, e.g., HEVC, may be configured to use quantization parameters to determine the quantization stage size. Generally, the quantization stage size can be calculated based on quantization parameters using a fixed-point approximation of the equations, which involves division. Additional scaling factors may be introduced for quantization and dequantization to restore the norm of the residual block, which may be modified due to the scaling used in the fixed-point approximation of the equations for the quantization stage size and quantization parameters. In one example implementation, the scaling of the inverse transform and dequantization may be combined. Alternatively, a customized quantization table may be used and signaled, for example, from encoder to decoder in a bitstream. Quantization is an irreversible operation, and the loss increases with increasing quantization stage size.

[0096] Embodiments of the video encoder 20 (each a quantization unit 208) may be configured to encode and output quantization parameters (QP), for example, directly or via an entropy encoding unit 270, so that, for example, the video decoder 30 may receive and apply the quantization parameters for decoding.

[0097] [Dequantization]

[0098] The inverse quantization unit 210 is configured to apply the inverse quantization of the quantization unit 208 to the quantization coefficients, for example, by applying the inverse of the quantization scheme applied by the quantization unit 208 based on or using the same quantization stage size as the quantization unit 208, thereby obtaining the dequantization coefficient 211. The dequantization coefficient 211 may also be called the dequantization residual coefficient 211, and is typically not identical to the transformation coefficient due to the loss due to quantization, but corresponds to the transformation coefficient 207.

[0099] [Inverse transformation]

[0100] The inverse transformation processing unit 212 is configured to apply the inverse transformation of the transformation applied by the transformation processing unit 206, for example, the inverse discrete cosine transform (DCT) or the inverse discrete sine transform (DST) or other inverse transformations, to obtain the reconstructed residual block 213 (or the corresponding dequantization coefficient 213) in the sample region. The reconstructed residual block 213 may also be referred to as the transformation block 213.

[0101] [Reconfiguration]

[0102] The reconstruction unit 214 (e.g., an adder or summer 214) is configured to add the transformed block 213 (i.e., the reconstructed residual block 213) to the predicted block 265 by adding the sample value of the reconstructed residual block 213 and the sample value of the predicted block 265 for each sample, thereby obtaining the reconstructed block 215 in the sample region.

[0103] [filtering]

[0104] The loop filter unit 220 (or, for short, the "loop filter" 220) is configured to filter the reconstruction block 215 to obtain a filtered block 221, or, more generally, to filter the reconstruction sample to obtain a filtered sample. The loop filter unit is configured, for example, to smooth pixel transitions or to otherwise improve video quality. The loop filter unit 220 may comprise one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as a bilateral filter, an adaptive loop filter (ALF), a sharpening, smoothing or coordinating filter, or any combination thereof. Although the loop filter unit 220 is shown in Figure 2 as being within a loop filter, in other configurations, the loop filter unit 220 may be implemented as a post-loop filter. The filtered block 221 may also be referred to as the filtered reconstruction block 221.

[0105] Embodiments of the video encoder 20 (each a loop filter unit 220) may be configured to encode the loop filter parameters (such as sample-adaptive offset information) for example, directly or via an entropy encoding unit 270 before outputting them, so that, for example, the decoder 30 may receive and apply the same loop filter parameters or the respective loop filters for decoding.

[0106] [Decoded image buffer]

[0107] The decoded image buffer (DPB) 230 may be a memory that stores a reference image for encoding video data by the video encoder 20, or generally reference image data. The DPB 230 may be made up of any of the various memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM®), or other types of memory devices. The decoded image buffer (DPB) 230 may be configured to store one or more filtered blocks 221. The decoded image buffer 230 may be further configured to store other previously filtered blocks of the same current image or a different image, for example, other previously filtered blocks of a previously reconstructed image, for example, a previously reconstructed and filtered block 221, for example, to provide a previously reconstructed, i.e., decoded, complete image (and corresponding reference blocks and samples) and / or a partially reconstructed current image (and corresponding reference blocks and samples) for interpretation. The decoded image buffer (DPB) 230 may be configured to store, for example, one or more unfiltered reconstruction blocks 215, or generally, unfiltered reconstruction samples, or any other further processed versions of the reconstruction blocks or samples, if the reconstruction blocks 215 have not been filtered by the loop filter unit 220.

[0108] [Mode Selection (Classification and Prediction)]

[0109] The mode selection unit 260 comprises a segmentation unit 262, an inter-prediction unit 244, and an intra-prediction unit 254, and is configured to receive or acquire original image data, e.g., the original block 203 (the current block 203 of the current image 17), and reconstructed image data, e.g., filtered and / or unfiltered reconstructed samples or blocks from the same (current) image and / or one or more previously decoded images, e.g., from a decoded image buffer 230 or other buffers (e.g., a line buffer not shown). The reconstructed image data is used as reference image data for prediction, e.g., inter-prediction or intra-prediction, in order to obtain prediction blocks 265 or predictor factors 265.

[0110] The mode selection unit 260 may be configured to determine or select a segmentation and prediction mode (e.g., intra or inter-prediction mode) for the current block prediction mode (excluding segmentation), and to generate a corresponding prediction block 265, which is used for calculating the residual block 205 and for reconstructing the reconstruction block 215.

[0111] Embodiments of the mode selection unit 260 may be configured to select a segmentation and prediction mode (e.g., from those supported by or available to the mode selection unit 260) thereby providing the best match, or in other words, minimum residual (minimum residual meaning better compression for transmission or storage), or minimum signaling overhead (minimum signaling overhead meaning better compression for transmission or storage), or both, or a balanced combination. The mode selection unit 260 may be configured to determine the segmentation and prediction mode based on rate distortion optimization (RDO), i.e., to select a prediction mode that provides minimum rate distortion. In this context, terms such as “best,” “minimum,” and “optimal” do not necessarily refer to general “best,” “minimum,” and “optimal,” but may refer to the achievement of a termination or selection criterion where a value exceeds or falls below a threshold or other constraint, potentially leading to a “suboptimal selection” but reducing complexity and processing time.

[0112] In other words, the partitioning unit 262 may be configured to partition block 203 into smaller block partitions or subblocks (which also form blocks) by repeatedly using, for example, quadtree partitioning (QT), binary tree partitioning (BT), or ternary tree partitioning (TT), or any combination thereof, and to perform, for example, predictions for each of the block partitions or subblocks, where mode selection includes selecting the tree structure of the partitioned block 203, and prediction modes are applied to each of the block partitions or subblocks.

[0113] The following describes in more detail the segmentation (e.g., by the segmentation unit 260) and prediction processing (by the inter-prediction unit 244 and the intra-prediction unit 254) performed by the example video encoder 20.

[0114] [Partitioning]

[0115] The partitioning unit 262 may partition (or divide) the current block 203 into smaller partitions, for example, smaller blocks of a square or rectangular size. These smaller blocks (which may also be called subblocks) may be further partitioned into even smaller partitions. This is also called tree partitioning or hierarchical tree partitioning, where, for example, the root block at root tree level 0 (hierarchical level 0, depth 0) may be recursively partitioned, for example, into 2 or more blocks of nodes at the next lowest tree level, for example, tree level 1 (hierarchical level 1, depth 1). These blocks may then be further partitioned into 2 or more blocks at the next lowest level, for example, tree level 2 (hierarchical level 2, depth 2), until partitioning is terminated, for example, when a termination criterion is met, for example, when the maximum tree depth or minimum block size is reached. Blocks that are not further partitioned are also called leaf blocks or leaf nodes of the tree. A tree that uses division into two parts is called a binary tree (BT), a tree that uses division into three parts is called a ternary tree (TT), and a tree that uses division into four parts is called a quadary tree (QT).

[0116] As previously mentioned, the term “block” as used herein may refer to a portion of an image, particularly a square or rectangular portion. Referring to HEVC and VVC, for example, a block may be a coding tree unit (CTU), a coding unit (CU), a prediction unit (PU), and a transformation unit (TU), and / or a corresponding block, such as a coding tree block (CTB), a coding block (CB), a transformation block (TB), or a prediction block (PB), or may correspond to them.

[0117] For example, a coding tree unit (CTU) may be a CTB of luminal samples in an image having three sample arrays, two corresponding CTBs of chroma samples, or a CTB of samples in an image coded using three separate color planes and syntax structures used to code a monochrome image or samples, or may include these. Correspondingly, a coding tree block (CTB) may be an N×N block of samples with respect to some value of N, such that the division of the components into a CTB is a partitioning. A coding unit (CU) may be a coding block of luminal samples, two corresponding coding blocks of chroma samples in an image having three sample arrays, or a coding block of samples in an image coded using three separate color planes and syntax structures used to code a monochrome image or samples, or may include these. Correspondingly, a coding block (CB) may be an M×N block of samples with respect to some values ​​of M and N, such that the division of the CTB into a coding block is a partitioning.

[0118] For example, in an embodiment following HEVC, a coding tree unit (CTU) may be divided into CUs by using a quadtree structure represented as a coding tree. The decision of whether to code an image area using inter-image (time) prediction or intra-image (spatial) prediction is made at the CU level. Each CU can further be divided into one, two, or four PUs, depending on the PU division type. Within a single PU, the same prediction process is applied, and the relevant information is sent to the decoder on a PU basis. After obtaining residual blocks by applying the prediction process based on the PU division type, the CU can be partitioned into transformation units (TUs) according to another quadtree structure similar to the coding tree of the CU.

[0119] For example, in embodiments conforming to the latest video coding standard currently under development, known as Multipurpose Video Coding (VVC), quadtree and binary tree (QTBT) segmentation is used to segment coding blocks. In the QTBT block structure, CUs can be either square or rectangular. For example, a coding tree unit (CTU) is first segmented with a quadtree structure. The leaf nodes of the quadtree are further segmented with a binary or ternary (or triple) tree structure. The leaf nodes of the segmented tree are called coding units (CUs), and their segmentation is used for prediction and transformation processing without any further segmentation. That is, CUs, PUs, and TUs have the same block size in the QTBT coding block structure. In parallel, multiple segmentations, such as ternary tree segmentation, have also been proposed to be used in conjunction with the QTBT block structure.

[0120] In one example, the mode selection unit 260 of the video encoder 20 may be configured to perform any combination of the classification techniques described herein.

[0121] As described above, the video encoder 20 is configured to determine or select the best or most optimal prediction mode from a set of (predetermined) prediction modes. The set of prediction modes may include, for example, an intra-prediction mode and / or an inter-prediction mode.

[0122] [Intra prediction]

[0123] The set of intra-prediction modes may include 35 different intra-prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes, for example, as defined in HEVC, or 67 different intra-prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes, for example, as defined in VVC.

[0124] The intra-prediction unit 254 is configured to generate an intra-prediction block 265 according to an intra-prediction mode from a set of intra-prediction modes, using reconstruction samples of adjacent blocks of the same current image.

[0125] The intra-prediction unit 254 (or generally the mode selection unit 260) is further configured to output intra-prediction parameters (or generally information indicating the intra-prediction mode selected for a block) to the entropy encoding unit 270 in the form of syntax elements 266 so that they are included in the encoded image data 21, thereby allowing, for example, the video decoder 30 to receive and use the prediction parameters for decoding.

[0126] [Interface prediction]

[0127] The set of interpretation modes (or possible interpretation modes) depends on the available reference image (i.e., a previously at least partially decoded image stored in DBP230, for example) and other interpretation parameters, such as whether the entire reference image or only a portion of the reference image, e.g., the search window area around the current block area, was used to find the best-matching reference block, and / or whether pixel interpolation, e.g., half / semi-perpetual and / or quarter-perpetual interpolation, was applied.

[0128] In addition to the prediction modes described above, skip mode and / or direct mode may also be applied.

[0129] The interpretation unit 244 may include a motion prediction (ME) unit and a motion compensation (MC) unit (neither of which are shown in Figure 2). The motion estimation unit may be configured to receive or acquire, for motion prediction, an image block 203 (the current image block 203 of the current image 17) and a decoded image 231, or at least one or more previously reconstructed blocks, e.g., one or more other / different reconstructed blocks of the previously decoded image 231. For example, a video sequence may include the current image and the previously decoded image 231, or in other words, the current image and the previously decoded image 231 may be part of or form part of a set of images that make up the video sequence.

[0130] The encoder 20 may be configured, for example, to select a reference block from multiple reference blocks of the same or different images among multiple other images, and to provide the motion estimation unit with an offset (spatial offset) between the reference image (or reference image index) and / or the position (x, y coordinates) of the reference block and the position of the current block as interpretation parameters. This offset is also called a motion vector (MV).

[0131] The motion compensation unit is configured to acquire, for example, interprediction parameters and perform interprediction based on or using those interprediction parameters to acquire interprediction blocks 265. Motion compensation performed by the motion compensation unit may involve fetching or generating prediction blocks based on the motion / block vector determined by the motion prediction and optionally performing interpolation to sub-pixel precision. Interpolation filtering may generate further pixel samples from known pixel samples, thus potentially increasing the number of candidate prediction blocks that can be used to code the image block. Upon receiving the motion vector for the current image block's PU, the motion compensation unit may locate the prediction block pointed to by the motion vector in one of the reference image lists.

[0132] The motion compensation unit may generate syntax elements associated with blocks and video slices, which are used by the video decoder 30 when decoding image blocks of video slices.

[0133] [Entropy coding]

[0134] The entropy encoding unit 270 is configured to apply, for example, an entropy encoding algorithm or scheme (e.g., variable-length coding (VLC) scheme, context-adaptive VLC scheme (CAVLC), arithmetic coding scheme, binaryization, context-adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probabilistic interval-partitioned entropy (PIPE) coding, or another entropy encoding method or technique), or bypass (uncompressed), to the quantization coefficients 209, inter-prediction parameters, intra-prediction parameters, loop filter parameters, and / or other syntax elements, to obtain encoded image data 21 that can be output via output 272 in the form of an encoded bitstream 21, for example, so that the video decoder 30 may receive and use the parameters for decoding. The encoded bitstream 21 may be transmitted to the video decoder 30 or stored in memory for later transmission or retrieval by the video decoder 30.

[0135] Other structural variations of the video encoder 20 can be used to encode a video stream. For example, a non-conversion-based encoder 20 can directly quantize the residual signal without using a conversion processing unit 206 for a particular block or frame. In another implementation, the encoder 20 may have a quantization unit 208 and an inverse quantization unit 210 combined into a single unit.

[0136] [Decoder and decoding method]

[0137] Figure 3 shows an example of a video decoder 30 configured to implement the technology of the present invention. The video decoder 30 is configured to receive encoded image data 21 (e.g., encoded bitstream 21), which has been encoded by, for example, an encoder 20, and to obtain a decoded image 331. The encoded image data or bitstream includes information for decoding the encoded image data, such as data representing image blocks of an encoded video slice and associated syntax elements.

[0138] In the example in Figure 3, the decoder 30 comprises an entropy decoding unit 304, an inverse quantization unit 310, an inverse transformation unit 312, a reconstruction unit 314 (e.g., an aggregater 314), a loop filter 320, a decoded image buffer (DBP) 330, an interpretation unit 344, and an intraprediction unit 354. The interpretation unit 344 is or may comprise a motion compensation unit. In some examples, the video decoder 30 may perform a decoding path that is roughly the reverse of the encoding path described with respect to the video encoder 100 in Figure 2.

[0139] As described with respect to encoder 20, the inverse quantization unit 210, inverse processing unit 212, reconstruction unit 214, loop filter 220, decoded image buffer (DPB) 230, inter-prediction unit 344, and intra-prediction unit 354 are also referred to as forming the “built-in decoder” of video encoder 20. Thus, the inverse quantization unit 310 may be functionally identical to the inverse quantization unit 110, the inverse processing unit 312 may be functionally identical to the inverse processing unit 212, the reconstruction unit 314 may be functionally identical to the reconstruction unit 214, the loop filter 320 may be functionally identical to the loop filter 220, and the decoded image buffer 330 may be functionally identical to the decoded image buffer 230. Accordingly, the descriptions provided for each unit and function of video encoder 20 apply to the respective units and functions of video decoder 30.

[0140] [Entropy decoding]

[0141] The entropy decoding unit 304 is configured to parse the bitstream 21 (or generally the encoded image data 21) and, for example, perform entropy decoding on the encoded image data 21 to obtain any or all of the following: for example, quantization coefficients 309 and / or decoded coding parameters (not shown in Figure 3), for example, inter-prediction parameters (e.g., reference image index and motion vector), intra-prediction parameters (e.g., intra-prediction mode or index), transformation parameters, quantization parameters, loop filter parameters, and / or other syntax elements. The entropy decoding unit 304 may be configured to apply a decoding algorithm or scheme corresponding to the encoding scheme described with respect to the entropy encoding unit 270 of the encoder 20. The entropy decoding unit 304 may be further configured to provide the inter-prediction parameters, intra-prediction parameters, and / or other syntax elements to the mode selection unit 360, and other parameters to other units of the decoder 30. The video decoder 30 may receive the syntax elements at the video slice level and / or video block level.

[0142] [Dequantization]

[0143] The inverse quantization unit 310 may be configured to receive quantization parameters (QP) (or information generally related to inverse quantization) and quantization coefficients from encoded image data 21 (for example, by the entropy decoding unit 304, for example, by parsing and / or decoding), and to apply inverse quantization to the decoded quantization coefficients 309 based on the quantization parameters to obtain dequantization coefficients 311, which may also be called conversion coefficients 311. The inverse quantization process may include the use of quantization parameters determined by the video encoder 20 for each video block in the video slice to determine the degree of quantization and, likewise, the degree of inverse quantization to be applied.

[0144] [Inverse transformation]

[0145] The inverse transformation processing unit 312 may be configured to receive the dequantization coefficient 311, also referred to as the transformation coefficient 311, and to apply a transformation to the dequantization coefficient 311 in order to obtain the reconstructed residual block 213 in the sample region. The reconstructed residual block 213 may also be referred to as the transformation block 313. The transformation may be an inverse transformation, such as an inverse DCT, inverse DST, inverse integer transformation, or a conceptually similar inverse transformation process. The inverse transformation processing unit 312 may be further configured to receive transformation parameters or corresponding information from the encoded image data 21 (for example, by parsing and / or decoding by the entropy decoding unit 304) and determine the transformation to be applied to the dequantization coefficient 311.

[0146] [Reconfiguration]

[0147] The reconstruction unit 314 (for example, an adder or summer 314) may be configured to obtain the reconstruction block 315 in the sample region by adding the reconstruction residual block 313 to the prediction block 365, for example by adding the sample value of the reconstruction residual block 313 to the sample value of the prediction block 365.

[0148] [filtering]

[0149] The loop filter unit 320 (located either within or after the coding loop) is configured to filter the reconstructed block 315 to obtain the filtered block 321, for example, to smooth pixel transitions or to otherwise improve video quality. The loop filter unit 320 may comprise one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as a bilateral filter, an adaptive loop filter (ALF), a sharpening, smoothing, or co-processing filter, or any combination thereof. Although the loop filter unit 320 is shown in Figure 3 as being within the loop filter, in other configurations, the loop filter unit 320 may be implemented as a post-loop filter.

[0150] [Decoded image buffer]

[0151] The decoded video block 321 of the image is then stored in the decoded image buffer 330, which stores the decoded image 331 as a reference image for subsequent motion compensation of other images and / or for outputting their respective displays.

[0152] The decoder 30 is configured to output a decoded image 311, for example via output 312, for presentation or viewing by the user.

[0153] [prediction]

[0154] The inter-prediction unit 344 may be identical to the inter-prediction unit 244 (in particular, the motion compensation unit), and the intra-prediction unit 354 may be functionally identical to the inter-prediction unit 254, and performs division or division decisions and predictions based on division and / or prediction parameters or respective information received from the encoded image data 21 (for example, by parsing and / or decoding by the entropy decoding unit 304). The mode selection unit 360 may be configured to perform predictions (intra or inter-predictions) on a block-by-block basis based on the reconstructed image, block, or each sample (filtered or unfiltered), and to obtain a predicted block 365.

[0155] If the video slice is coded as an intra-coded (I) slice, the intra-prediction unit 354 of the mode selection unit 360 is configured to generate a prediction block 365 for the image block of the current video slice based on the signaled intra-prediction mode and data from previously decoded blocks of the current image. If the video image is coded as an inter-coded (i.e., B or P) slice, the inter-prediction unit 344 (e.g., motion compensation unit) of the mode selection unit 360 is configured to generate a prediction block 365 for the video block of the current video slice based on the motion vector and other syntax elements received from the entropy decoding unit 304. In inter-prediction, the prediction block may be generated from one of several reference images contained in one of several reference image lists. The video decoder 30 may construct reference frame lists, namely List 0 and List 1, based on reference images stored in the DPB 330 using a default construction technique.

[0156] The mode selection unit 360 is configured to determine prediction information for the video block of the current video slice by parsing motion vectors and other syntax elements, and uses the prediction information to generate a prediction block for the current video block being decoded. For example, the mode selection unit 360 uses some of the received syntax elements to determine the prediction mode used to code the video block of the video slice (e.g., intra or interpredict), the interpredict slice type (e.g., B slice, P slice, or GPB slice), configuration information relating to one or more of the reference image lists for the slice, the motion vector for each intercoded video block of the slice, the interpredict status for each intercoded video block of the slice, and other information for decoding the video block in the current video slice.

[0157] Other variations of the video decoder 30 can be used to decode encoded image data 21. For example, the decoder 30 can generate an output video stream without using a loop filtering unit 320. For example, a non-conversion-based decoder 30 can directly dequantize the residual signal without using an inverse conversion processing unit 312 for a particular block or frame. In another implementation, the video decoder 30 may have an inverse quantization unit 310 and an inverse conversion processing unit 312 combined into a single unit.

[0158] It should be understood that in encoder 20 and decoder 30, the processing result of the current stage may be further processed and then output to the next stage. For example, after interpolation filtering, motion vector derivation, or loop filtering, further operations such as clipping or shifting may be performed on the processing result of interpolation filtering, motion vector derivation, or loop filtering.

[0159] It should be noted that further operations may be applied to the derived motion vector of the current block (including, but not limited to, the control point motion vector in affine mode, the subblock motion vector in affine, planar, and ATMVP modes, the temporal motion vector, etc.). For example, the value of a motion vector is limited to a predetermined range according to its representation bits. If the representation bit of the motion vector is bitDepth, its range is -2^(bitDepth-1) to 2^(bitDepth-1)-1, where "^" means exponentiation. For example, if bitDepth is set to equal 16, its range is -32768 to 32767, and if bitDepth is set to equal 18, its range is -131072 to 131071. Below, we provide two methods for limiting motion vectors.

[0160] Method 1: Remove the overflow MSB (most significant bit) by performing the following operation.

number

[0161] For example, if the value of mvx is -32769 after applying equations (1) and (2), the resulting value is 32767. In a computer system, decimal numbers are stored as two's complement. The two's complement of -32769 is 1,0111,1111,1111,1111 (17 bits), and then the MSB is discarded, so the resulting two's complement is 0111,1111,1111,1111 (decimal is 32767). This is the same output as applying equations (1) and (2).

number

[0162] The operation may be applied to the sum of mvp and mvd, as shown in equations (5) to (8).

[0163] Method 2: Remove the overflow MSB by clipping the value.

number

number

[0164] Figure 4 is a schematic diagram of a video coding device 400 according to one embodiment of the present disclosure. The video coding device 400 is suitable for carrying out the embodiments disclosed herein. In one embodiment, the video coding device 400 may be a decoder such as the video decoder 30 in Figure 1A, or an encoder such as the video encoder 20 in Figure 1A.

[0165] The video coding device 400 comprises an inlet port 410 (or input port 410) and a receiver unit (Rx) 420 for receiving data, a processor, logic unit, or central processing unit (CPU) 430 for processing data, a transmitter unit (Tx) 440 and an exit port 450 (or output port 450) for transmitting data, and memory 460 for storing data. The video coding device 400 may also include optical / electrical (OE) components and electrical / optical (EO) components connected to the inlet port 410, the receiver unit 420, the transmitter unit 440, and the exit port 450 for the entry and exit of optical or electrical signals.

[0166] The processor 430 is implemented by hardware and software. The processor 430 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), FPGAs, ASICs, and DSPs. The processor 430 communicates with an inlet port 410, a receiver unit 420, a transmitter unit 440, an exit port 450, and memory 460. The processor 430 includes a coding module 470. The coding module 470 implements the embodiments disclosed above. For example, the coding module 470 performs, processes, prepares, or provides various coding operations. Thus, the inclusion of the coding module 470 provides a considerable improvement in the functionality of the video coding device 400, resulting in the conversion of the video coding device 400 to different states. Alternatively, the coding module 470 is implemented as instructions stored in memory 460 and executed by the processor 430.

[0167] Memory 460 may comprise one or more disks, tape drives, and solid-state drives, and may be used as an overflow data storage device to store the program if the program is selected for execution, and to store instructions and data read during program execution. Memory 460 may be, for example, volatile and / or non-volatile, and may be read-only memory (ROM), random access memory (RAM), tri-level associative memory (TCAM), and / or static random access memory (SRAM).

[0168] Figure 5 is a schematic block diagram of an apparatus 500 which may be used as either or both of the source device 12 and destination device 14 according to Figure 1A, as exemplified by this embodiment.

[0169] The processor 502 in the device 500 may be a central processing unit. Alternatively, the processor 502 may be any other type of device, or multiple devices, capable of manipulating or processing information, whether currently existing or to be developed in the future. The implementation of the disclosure can be carried out with a single processor, e.g., processor 502, as shown in the figure, but using more than one processor can provide benefits in terms of speed and efficiency.

[0170] The memory 504 in the device 500 may be a read-only memory (ROM) device or a random access memory (RAM) device in one implementation. Any other suitable type of storage device may be used as the memory 504. The memory 504 may comprise code and data 506 accessed by the processor 502 using a bus 512. The memory 504 may further comprise an operating system 508 and an application program 510, the application program 510 comprising at least one program that enables the processor 502 to perform the method described herein. For example, the application program 510 may comprise applications 1 to N, the applications 1 to N further comprising video coding applications that perform the method described herein.

[0171] The device 500 may also include one or more output devices, such as a display 518. In one example, the display 518 may be a touch-sensitive display combining a display with a touch sensor element that can operate to detect touch input. The display 518 can be connected to the processor 502 via the bus 512.

[0172] Although described herein as a single bus, the bus 512 of the device 500 can consist of multiple buses. Furthermore, the secondary storage 514 can be directly connected to other components of the device 500 or accessed via a network, and may include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Thus, the device 500 can be implemented in a wide variety of configurations.

[0173] The accuracy of the motion vector (MV), derived from the calculation of the intermediate value of the motion vector in affine prediction, increased from 1 / 4 to 1 / 16 in pixel length. This increase in accuracy allows the memory storage capacity for the motion vector field to be up to 18 bits per motion vector component. During the development of the video codec, each MV was stored at a granularity of 4x4 pixels. Several attempts were subsequently made to reduce the memory capacity for storing motion vector information. One proposal to reduce the granularity to an 8x8 grid size was adopted. Another attempt to reduce MV accuracy (temporal MV storage or local line buffer, or both) by simply removing the MSB (most significant bit) from the motion vector component value was made in [JVET-L0168], which resulted in a reduction of the MV representation range that could reduce the efficiency of prediction and compression of large images and 360° video. Such a 16-bit representation of motion vectors with 1 / 16 accuracy is not sufficient for 8K or higher resolution video coding. Two other solutions propose removing the LSB from the MV component in both the horizontal and vertical directions, attempting to adaptively remove the MSB / LSB with an additional bit for signaling.

[0174] The object of the present invention is to provide a solution / method and device that can reduce memory capacity while maintaining a reasonable range of motion vector representation and accuracy when storing information for deriving temporal motion vector predictions. Maintaining a reasonable range of accuracy means a certain degree of reduction in accuracy that results in a certain degree of distortion of the representation. Therefore, the result of conversion to floating-point representation is a distorted / quantized / rounded value of MV.

[0175] The currently available solution operates with 18-bit values ​​for each MV component stored in the reference frame (Figure 6, top). This results in a memory increase for MV storage of 12.5% ​​for hardware and 100% for software. The present invention proposes using a 16-bit binary floating-point representation of the MV component values ​​stored in the reference frame instead of 18 bits. However, the 16-bit floating-point representation is just one example, and the present invention also includes representations with fewer than 16 bits (e.g., 10-bit representation). Furthermore, in Embodiment 1, where the MSB is used as the floating-point exponent, there is no change in codec processing compared to the current solution when the image resolution is low.

[0176] The fundamental concept of this invention is a 16-bit binary floating-point representation of MV component values ​​stored within a reference frame, instead of an 18-bit representation.

[0177] To reduce the memory capacity required to store temporal MVs while maintaining reasonable MV representation and accuracy.

[0178] To address the above challenges, the following embodiments of the invention are disclosed, which can be applied individually or in combination: 1. Using a binary floating-point representation of the MV component. Method A. The exponent may be 3 bits, thereby enabling MV representations of different precisions from 1 / 16 (up to 256 pixels in terms of MV length) to 8 pixels (up to 32K in terms of MV length). Method B. Another possible implementation suggests 2 bits for the exponent, thereby reducing the maximum bit MV length to 512 (in terms of MV precision of 1 / 16) and 8K pixels (in terms of MV precision equal to 1 pixel). 2. The binary floating-point representation can be represented in two possible implementations (3 bits used for the exponent in the example): Method A. MV component value, exponent bit in MSB in Figure 6. With the following MV reconstruction steps (e.g., with respect to the X component): i. Shift = MVx >> 13 ii. Mvx = MVx & 0x01FFF iii. Mvx <<= Shift Method B. MV component values ​​The exponent bit in the LSB in Figure 7. This is accompanied by the following MV reconstruction steps (for example, with respect to the X component): i. Shift = MVx & 0x03 ii. Mvx = MVx >> 3 iii. Mvx <<= Shift 3. The proposed approach may be used conditionally, indicating the use of this mode within SPS / PPS / slice headers / tile group headers by: Method A. A special flag indicating the use of floating-point representation or HEVC 16-bit representation of MV Method B. Number of bits in the exponent of the MV value 4. Adaptively vary the size of the exponent depending on: Method A. If the image resolution iw < 2K and h < 2K: exp_size is derived as 0 (not signaled) ii. If w < 4K and h < 4K: Signal 1 bit for the shift value iii. Otherwise, signal 2 bits for the shift value Method B. Signaled with the exponent size at the CTU / CU / block / unit level Method C. Use within motion-limited tile sets (MCTS) i. In this case, the tileset size can strongly restrict the use of floating-point MV representations of small tileset resolution, such as in aspect 4)a of the present invention. 5. The vertical and horizontal components of the MV may have exponents of independent sizes. 6. One possible solution is to subtract the average of the vector components (meanMVx, meanMVy) from the values ​​of the same components of each MV belonging to the same CTU / CU / block / unit. Method A. The average of both components is stored separately for each CTU / CU / block / unit. The MV is derived as MVx=meanMVx+Mvx(i,j),MVy=meanMVy+Mvy(i,j). Method B. The average of both components is stored in one of the subunits of each CTU / CU / block / unit (top left, e.g., i=0,j=0). When (i!=0 and j!=0) and meanMVx=MVx(0,0) and meanMVy=MVy(0,0), MV is derived as MVx=meanMVx+Mvx(i,j) and MVy=meanMVy+Mvy(i,j). Method C. Here, the two above solutions (6).a and 6).b) are expressed as follows: i. 16-bit binary floating (Solution 1).a) ii. 16-bit integer

[0179] Furthermore, the present invention proposes the use of a 16-bit binary representation instead of an 18-bit representation for MV component values ​​stored within a reference frame, where the 16-bit value can be obtained by removing 2 LSBs (least significant bits) or 2 MSBs (most significant bits) from an 18-bit value, depending on the signaled value within the bitstream. Signaling can be performed by a predefined signaling mechanism as described in [JVET-L0168].

[0180] To reduce the memory capacity required to store temporal MVs while maintaining reasonable MV representation and accuracy.

[0181] To solve the above problems, the following embodiments of the invention are disclosed, each of which can be applied individually, and some of which can be applied in combination. 7. Before saving the MV to the motion buffer, the MV components are converted from an 18-bit binary representation to a 16-bit representation using one of the following methods, depending on the value signaled in the bitstream: Method A. Remove the LSB of 2 by an arithmetic right shift of 2 (as shown in Figure 8) Method B. (as shown in Figure 9) (e.g., range [-2 15 ,2 15 The MSB of 2 is removed by clipping to [-1]. The MV component is restored (conversion from 16-bit to 18-bit binary representation) using the following rules: ●When Method A is used, the 18-bit value is obtained from the 16-bit value by a left arithmetic shift of only 2; ●When Method B is used, the 18-bit value is obtained from the 16-bit value by setting the MSBs of 2 (the 17th and 18th bits) to 0 for positive values ​​or 1 for negative values. 8. The 16-bit binary representation is not used to store motion information of the current image, Embodiment 7. In this case, the MV in the 16-bit binary representation is used, for example, for TMVP (Temporal Motion Vector Prediction) and / or ATMVP (Alternative Temporal Motion Vector Prediction). 9. The method for converting the MV component from 18 bits to a 16-bit binary representation (Method A or Method B) is signaled in the bitstream per frame, Embodiment 8. 10. The method for converting the MV component from 18 bits to a 16-bit binary representation (Method A or Method B) is signaled in the bitstream per tile, Embodiment 8. 11. The method for converting the MV component from 18 bits to a 16-bit binary representation (Method A or Method B) is signaled in the bitstream per group of tiles, Embodiment 8. 12. The method for converting MV components from 18 bits to 16 bits binary representation (Method A or Method B) is signaled within the bitstream for each slice, aspect 8. 13. The method for converting from 18 bits to 16 bits (Method A or Method B) is signaled within the SPS / PPS / slice header / tile group header by a special flag, aspects 7-12. 14. The method for converting MV components from 18 bits to 16 bits binary representation is adaptively selected based on the following, aspects 7-8: a. If the image resolution iw < 2K and h < 2K: Method B is used (no signaling). ii. Otherwise, regardless of whether method A or B is used, one bit is signaled b. Signaled at the CTU / CU / block / unit level c. Used within motion-limited tile sets (MCTS) i. In this case, the tile set size may strongly limit the use of method B with respect to small tile set resolution 15. The vertical and horizontal components of MV may have independent signaling.

[0182] Figure 10 shows a flowchart of a comprehensive motion vector compression method according to the present invention. The method includes a step 101 of obtaining a temporal motion vector; a step 102 of determining a compressed motion vector using a binary representation of the temporal motion vector, wherein the binary representation includes an exponent and / or mantissa, the exponent includes N bits, the mantissa includes M bits, N is a non-negative integer, and M is a positive integer; and a step 103 of performing a temporal motion vector prediction (TMVP) using the compressed motion vector.

[0183] While embodiments of the present application are described primarily in relation to video coding, it should be noted that embodiments of the coding system 10, encoder 20, and decoder 30 (and correspondingly system 10) described herein, as well as other embodiments, may be configured for still image processing or coding, i.e., for processing or coding individual images independent of any preceding or consecutive images, as in video coding. Generally, when image processing coding is limited to a single image 17, only the interprediction units 244 (encoder) and 344 (decoder) may not be available. All other functions (also referred to as tools or techniques) of the video encoder 20 and video decoder 30 may equally be used for still image processing, e.g., residual calculation 204 / 304, transformation 206, quantization 208, inverse quantization 210 / 310, (inverse) transformation 212 / 312, segmentation 262 / 362, intra-prediction 254 / 354, and / or loop filtering 220, 320, as well as entropy coding 270 and entropy decoding 304.

[0184] For example, embodiments of encoder 20 and decoder 30, and functions described herein with reference to encoder 20 and decoder 30, may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, functions may be stored on a computer-readable medium or transmitted as one or more instructions or codes via a communication medium and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable storage medium corresponding to a tangible medium such as a data storage medium, or a communication medium including any medium that facilitates the movement of a computer program from one location to another, for example, according to a communication protocol. Thus, the computer-readable medium may generally correspond to (1) a non-temporary tangible computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. The data storage medium may be any available medium accessible by one or more computers or one or more processors to obtain instructions, codes, and / or data structures for implementing the technologies described herein. A computer program product may include a computer-readable medium.

[0185] Such computer-readable storage media may include, but are not limited to, computer-readable storage media, such as RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other media that can be used to store desired program code in the form of instructions or data structures and that are accessible by a computer. Any connection may also be referred to as computer-readable media as appropriate. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. However, it should be understood that computer-readable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but instead refer to non-temporary, tangible storage media. As used herein, "disk and disc" includes compact discs (CDs), laser discs, optical discs, digital multipurpose discs (DVDs), floppy disks, and Blu-ray discs, where, typically, a "disk" reproduces data magnetically, and a "disc" reproduces data optically using a laser. Any combination of the above should also be included within the scope of computer-readable media.

[0186] Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term “processor” as used herein may refer to any of the aforementioned structures or any other structure suitable for implementing the technology described herein. In addition, in some embodiments, the functions described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. Furthermore, the technology can be fully implemented in one or more circuits or logic elements.

[0187] The technology of this disclosure may be implemented in a wide variety of devices or apparatus, including wireless handsets, integrated circuits (ICs), or sets of ICs (e.g., chipsets). While various components, modules, or units are described in this disclosure to highlight the functional aspects of devices configured to perform the disclosed technology, implementation by different hardware units is not necessarily required. Rather, as described above, various units may be combined into a codec hardware unit in conjunction with suitable software and / or firmware, or as described above, they may be provided by a collection of interoperable hardware units including one or more processors.

[0188] For reference, the following logical operators are defined as follows: x&&y: Boolean logic "and" of x and y. The Boolean logic "or" of x and y ! Boolean logic "not" If x?y:zx is true or not equal to 0, then it becomes the value of y; otherwise, it becomes the value of z.

[0189] For reference, the following relational operators are defined as follows: > larger >= Above < Smaller <= Below = = equals != is not equal to

[0190] When a relational operator is applied to a syntax element or variable that has the value "na" (not applicable) assigned to it, the value "na" is treated as the distinct value of that syntax element or variable. The value "na" is considered not to be equal to any other value.

[0191] For reference, the following bitwise operators are defined as follows: & is a bitwise "and". When performing an operation on an integer term, the operation is performed on the two's complement representation of the integer value. When performing an operation on a binary term that contains fewer bits than another term, the shorter term is extended by adding higher bits equal to 0. | Bitwise "OR". When performing an operation on an integer term, the operation is performed on the two's complement representation of the integer value. When performing an operation on a binary term that contains fewer bits than another term, the shorter term is extended by adding higher bits equal to 0. ^ Bitwise "exclusive OR". When performing an operation on an integer term, the operation is performed on the two's complement representation of the integer value. When performing an operation on a binary term that contains fewer bits than another term, the shorter term is extended by adding higher bits equal to 0. An arithmetic right shift of the two's complement integer representation of x, where x >> yy is the binary representation only. This function is defined only for non-negative integer values ​​of y. The bit shifted to the most significant bit (MSB) as a result of the right shift has a value equal to the MSB of x before the shift operation. x<

Claims

1. The stage of obtaining an 18-bit temporal motion vector, A step of determining a compressed motion vector using at least one binary representation of the aforementioned temporal motion vector, wherein the binary representation of the compressed temporal motion vector includes an exponent or a mantissa, the exponent includes N bits, the mantissa includes M bits, N is a non-negative integer, M is a positive integer, and the binary representation of the compressed temporal motion vector is 10 bits. The steps include: performing temporal motion vector prediction (TMVP) using the compressed motion vector; A motion vector compression method, including...

2. The motion vector compression method according to claim 1, wherein the aforementioned temporal motion vector includes a horizontal component of the motion vector and a vertical component of the motion vector.

3. A motion vector compression method according to claim 1 or 2, further comprising the step of determining the value of N.

4. A decoder comprising a circuit configured to perform the motion vector compression method according to any one of claims 1 to 3.

5. An encoder comprising a circuit configured to perform the motion vector compression method according to any one of claims 1 to 3.

6. An encoding device for encoding the current block, wherein the encoding device includes motion vector compression as described in any one of claims 1 to 3.

7. A decoding device for decoding the current block from a received bitstream, wherein the decoding device includes motion vector compression according to any one of claims 1 to 3.

8. A computer-readable storage medium comprising program code for performing the motion vector compression method according to any one of claims 1 to 3, when executed on a computer or processor.

9. A method for generating decoded data by processing video data with the decoder described in Claim 4.

10. A method for generating an encoded bitstream by processing video data with the encoder described in Claim 5.

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