Drivers, electro-optical devices, and electronic equipment

Abstract

To provide a driver and the like that can achieve both an amplification factor and frequency response characteristics of an operational amplifier that drives a signal supply line of an electro-optical panel.SOLUTION: A driver 100 includes a first driving circuit 60 and a second driving circuit 70. The second driving circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, and a second feedback capacitor Cfb. The operational amplifier 71 is formed by a transistor with a withstand voltage lower than a withstand voltage of a transistor forming the first driving circuit 60. The output capacitor CQ is arranged between an output node NAMQ of the operational amplifier 71 and a signal supply line. The first feedback capacitor Cfa is arranged between an inverted input node NAN of the operational amplifier 71 and the signal supply line. One end of the second feedback capacitor Cfb is connected with the inverted input node NAN of the operational amplifier 71.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a driver, an electro-optical device, an electronic device, and the like.

Background Art

[0002] Patent Document 1 discloses a driver that includes a capacitance drive circuit and an amplifier circuit and drives an electro-optical panel. After the capacitance drive for driving the electro-optical panel by the capacitance drive circuit is started, the amplifier circuit performs voltage drive for outputting a data voltage corresponding to gradation data to a data voltage output terminal. Thereby, since the voltage drop of the data line after the source line switch of the electro-optical panel changes from off to on is compensated by the amplifier circuit, a decrease in the accuracy of the data voltage in capacitance drive is suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Depending on the type of liquid crystal panel, a high voltage is required for its driving. Therefore, for a driving circuit that drives such a liquid crystal panel, an operational amplifier composed of high-breakdown-voltage transistors is used. However, since high-breakdown-voltage transistors have low mobility, there is a problem that it is difficult to achieve both the amplification factor and the frequency response characteristics of the operational amplifier. For example, in order to increase the driving speed with high resolution or the like, it is necessary to increase the frequency response characteristics of the operational amplifier. However, if the frequency response characteristics are increased while maintaining the amplification factor of the operational amplifier, the power consumption of the operational amplifier will increase.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a driver comprising: a first drive circuit that supplies data signals to a signal supply line of an electro-optical panel based on grayscale data; an operational amplifier composed of transistors having a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit; an output capacitor disposed between the output node of the operational amplifier and the signal supply line; a first feedback capacitor disposed between the inverting input node of the operational amplifier and the signal supply line; and a second feedback capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier, and the second drive circuit being electrically connected to the signal supply line.

[0006] Other aspects of this disclosure relate to an electro-optical apparatus including the driver and the electro-optical panel.

[0007] Another aspect of this disclosure is an electronic device characterized by including the above-described driver. [Brief explanation of the drawing]

[0008] [Figure 1] An example of an electro-optical device configuration. [Figure 2] First detailed configuration example of the driver. [Figure 3] A diagram illustrating the relationship between grayscale data and data voltage. [Figure 4] A first detailed configuration example of the first drive circuit. [Figure 5] This diagram illustrates the relationship between grayscale data and the voltage in the low-voltage second drive circuit. [Figure 6] First detailed configuration example of the second drive circuit. [Figure 7] The first waveform example illustrates the operation of the first and second drive circuits. [Figure 8] A second waveform example illustrating the operation of the first and second drive circuits. [Figure 9] A third waveform example illustrating the operation of the first and second drive circuits. [Figure 10] Second detailed configuration example of the driver. [Figure 11]A diagram for explaining the relationship between gradation data, setting data, and data voltage. [Figure 12] A second detailed configuration example of the first drive circuit. [Figure 13] A fourth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 14] A second detailed configuration example of the second drive circuit. [Figure 15] The relationship between gradation data and D / A conversion voltage. [Figure 16] A third detailed configuration example of the second drive circuit. [Figure 17] A fifth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 18] A sixth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 19] A fourth detailed configuration example of the second drive circuit. [Figure 20] A seventh waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 21] An eighth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 22] A fifth detailed configuration example of the second drive circuit. [Figure 23] A sixth detailed configuration example of the second drive circuit. [Figure 24] A ninth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 25] A tenth waveform example for explaining the operations of the first drive circuit and the second drive circuit. [Figure 26] A configuration example of an electronic device.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present disclosure will be described in detail. Note that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in the embodiments are essential constituent elements.

[0010] 1. Electro-optical device Figure 1 shows an example of the configuration of an electro-optical device. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200. In the following description, an electro-optical device 400 with a phase-deployment drive system will be used as an example, but it is not limited to this, and for example, the electro-optical device 400 may also use a demultiplex drive system.

[0011] The driver 100 drives the electro-optic panel 200 by outputting a data signal to the signal supply line of the electro-optic panel 200. The voltage written to one pixel at a time is called the data voltage. When multiple pixels are driven in a time series, the data voltage for each pixel is output to the signal supply line as a time series signal, and this signal to the signal supply line is called the data signal.

[0012] The scan line driving circuit for driving the scan lines of the electro-optic panel 200 may be included in the driver 100 or provided outside the driver 100. The driver 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate. The driver 100 includes a control circuit 40 and first to k data line driving circuits DD1 to DDk. k is an integer of 2 or more. In the following explanation, the case where k=8 will be used as an example.

[0013] The control circuit 40 outputs corresponding grayscale data to each of the data line drive circuits DD1 to DD8. The control circuit 40 also outputs a control signal ENBX to the electro-optic panel 200 to control the data line switches.

[0014] The data line drive circuits DD1 to DD8 convert grayscale data into data voltages and output these data voltages as output voltages VQ1 to VQ8 to the signal supply lines SPL1 to SPL8 of the electro-optic panel 200. The output voltages VQ1 to VQ8 change according to the time-series grayscale data, and the signals produced by these changing output voltages VQ1 to VQ8 correspond to the data signals described above.

[0015] The electro-optical panel 200 includes the first to eighth signal supply lines SPL1 to SPL8, the first to 1280 data line switches SWEP1 to SWEP1280, and the first to 1280 data lines DL1 to DL1280. The number of data lines may be k × t, where t is an integer greater than or equal to 2. Here, WXGA is used as an example, and t = 160.

[0016] One end of data line switches SWEP((j-1)×k+1) to SWEP(j×k) among data line switches SWEP1 to SWEP1280 is connected to signal supply lines SPL1 to SPL8. j is an integer less than or equal to 160. For example, if j=1, it is data line switches SWEP1 to SWEP8.

[0017] Each of the data line switches SWEP1 to SWEP1280 is composed of, for example, a TFT and is controlled based on the control signal ENBX. TFT stands for Thin Film Transistor. For example, the electro-optic panel 200 includes a switch control circuit (not shown), which controls the data line switches SWEP1 to SWEP1280 to turn on or off based on the control signal ENBX.

[0018] The data line drive circuits DD1 to DD8 perform 160 drives during the horizontal scanning period, and in the j-th drive, data line switches SWEP((j-1)×k+1) to SWEP(j×k) are turned on, while the other data line switches are turned off. As a result, data lines DL((j-1)×k+1) to DL(j×k) are driven in the j-th drive. Focusing on data line drive circuit DD1, during the horizontal scanning period, data line switches SWEP1, SWEP2, ..., SWEP1273 are turned on sequentially, and data line drive circuit DD1 drives data lines DL1, DL2, ..., DL1273 sequentially.

[0019] 2. First Embodiment Figure 2 shows a first detailed configuration example of the driver. The driver 100 includes a data line drive circuit 110 and a control circuit 40. The data line drive circuit 110 corresponds to any one of the data line drive circuits DD1 to DD8 in Figure 1.

[0020] The data line drive circuit 110 includes a first drive circuit 60, a second drive circuit 70, a variable capacitance circuit 30, and a detection circuit 50. The control circuit 40 includes a processing circuit 42, an interface circuit 44, and a register circuit 48.

[0021] The interface circuit 44 performs interface processing between the driver 100 and the display controller 300 that controls the driver 100. The interface circuit 44 outputs the grayscale data GD[9:0] received from the display controller 300 to the processing circuit 42. The number of bits of the received grayscale data may be arbitrary. The interface circuit 44 is an image interface circuit such as an LVDS system, a parallel RGB system, or a DisplayPort system. LVDS stands for Low Voltage Differential Signaling.

[0022] The processing circuit 42 determines the setting data CSW[4:0] for the capacitance value of the variable capacitance circuit 30 during initialization processing when power is applied to the driver 100, and stores the setting data CSW[4:0] in the register circuit 48. During normal operation when driving the electro-optical panel 200, the processing circuit 42 sets the capacitance value of the variable capacitance circuit 30 using the setting data CSW[4:0] read from the register circuit 48. The processing circuit 42 also outputs the gradation data DTH[10:0] to the first drive circuit 60 and the gradation data DTL[10:0] to the second drive circuit 70 based on the gradation data GD[9:0]. The processing circuit 42 also outputs the polarity inversion signal FR to the second drive circuit 70. Depending on the configuration of the second drive circuit 70, the input of the polarity inversion signal FR to the second drive circuit 70 may be omitted.

[0023] Output node NVQ is the node connected to the data voltage output terminal TVQ, and the voltage of this output node NVQ is defined as the output voltage VQ. The load capacitance of the data voltage output terminal TVQ is defined as the electro-optic panel side capacitance CP.

[0024] The first drive circuit 60 supplies charge corresponding to the grayscale data DTH[10:0] to the output node NVQ by charge redistribution using a capacitor. This charge is then distributed to the variable capacitance circuit 30 and the electro-optic panel side capacitance CP, so that the output voltage VQ becomes the data voltage corresponding to the grayscale data DTH[10:0]. The first drive circuit 60 is composed of circuit elements with a high voltage resistance process that can drive the electro-optic panel 200. For example, if the electro-optic panel 200 is a high-temperature polysilicon type liquid crystal panel, the power supply voltage of the first drive circuit 60 is about 15V to 20V, and the first drive circuit 60 is composed of circuit elements with a voltage resistance higher than that power supply voltage.

[0025] If there is an error in the charge output by the first drive circuit 60, or if charge conservation at the output node NVQ is slightly not maintained, an error will occur between the output voltage VQ due to the charge output by the first drive circuit 60 and the target voltage corresponding to the grayscale data DTH[10:0]. The second drive circuit 70 corrects the output voltage VQ to the target voltage using feedback control with an operational amplifier. At this time, because the error between the output voltage VQ and the target voltage is small, the second drive circuit 70 only needs to output a small amount of charge. Taking advantage of this, the operational amplifier is constructed with circuit elements from a low-voltage process while DC blocking is performed between the operational amplifier and the output node NVQ with a capacitor. As an example, the voltage withstand capability of a low-voltage process is about 1 / 3 to 1 / 10 of the voltage withstand capability of a high-voltage process. The second drive circuit 70 operates at a power supply voltage lower than the voltage withstand capability of the low-voltage process.

[0026] This document describes a method for determining the capacitance value of the variable capacitance circuit 30 and an example configuration of the variable capacitance circuit 30 and the detection circuit 50.

[0027] The detection circuit 50 compares a given detection voltage with the output voltage VQ and outputs the result as a detection signal DET. The detection circuit 50 is, for example, a comparator.

[0028] The processing circuit 42 outputs gradation data DTH[10:0] corresponding to a given data voltage to the capacitor drive circuit 20. At this time, the given detection voltage is set to the same voltage as the given data voltage, which is the expected value of the output voltage VQ. The processing circuit 42 sequentially changes the capacitance value of the variable capacitance circuit 30 by sequentially changing the value of the setting data CSW[4:0]. The processing circuit 42 determines the capacitance value of the variable capacitance circuit 30 based on the detection signal DET at each capacitance value. That is, the processing circuit 42 determines the capacitance value at which the output voltage VQ becomes the given detection voltage based on the detection signal DET, and stores the setting data CSW[4:0] of that capacitance value in the register circuit 48.

[0029] The variable capacitance circuit 30 includes first to fifth adjustment capacitors and first to fifth adjustment switches. One end of the first adjustment switch is connected to the output node NVQ, and the other end is connected to one end of the first adjustment capacitor. The other end of the first adjustment capacitor is connected to the ground node. The same applies to the second to fifth adjustment capacitors and the second to fifth adjustment switches. The capacitance values ​​of the first to fifth adjustment capacitors are binary weighted. The first adjustment switch is controlled on or off by CSW[0]. Similarly, the second to fifth adjustment switches are controlled on or off by CSW[1] to CSW[4].

[0030] The details of the first drive circuit 60, the second drive circuit 70, the variable capacitance circuit 30, and the detection circuit 50 will be described below.

[0031] Figure 3 illustrates the relationship between grayscale data and data voltage.

[0032] The processing circuit 42 converts the input gradation data GD[9:0] into gradation data DTH[10:0]. Specifically, when driven by negative polarity, the processing circuit 42 converts GD[9:0] with gradation values ​​from 0 to 1023 into DTH[10:0] with gradation values ​​from 1023 to 0, and when driven by positive polarity, it converts GD[9:0] with gradation values ​​from 0 to 1023 into DTH[10:0] with gradation values ​​from 1024 to 2047.

[0033] VSH=0V is the low-potential power supply voltage of the first drive circuit 60. VDH=15V is the high-potential power supply voltage of the first drive circuit 60. The common voltage supplied to the counter electrode of the electro-optic panel 200 is VC=7.5V. The data voltage supplied to the pixels is 7.5V to 2.5V in negative polarity drive and 7.5V to 12.5V in positive polarity drive.

[0034] Figure 4 shows a first detailed configuration example of the first drive circuit. In the following, the same sign as the capacitor's symbol will be used to represent its capacitance value. For example, the capacitance value of capacitor C1 will be denoted as C1.

[0035] The capacitor circuit 10 includes the first to the nth capacitors C1 to Cn. The capacitor drive circuit 20 includes the first to the nth drive circuits DR1 to DRn. The following example describes the case where n=11, but n can be any integer greater than or equal to 2. n should be set to the same number of bits as the grayscale data DTH[10:0].

[0036] One end of capacitor Ci is connected to the output node NVQ, and the other end is connected to the capacitor drive node NDRi. i is an integer between 1 and n=11. Capacitors C1 to C10 have binary weighted capacitance values. Specifically, the capacitance value of capacitor Ci is 2 (i-1) ×C1

[0037] The processing circuit 42 outputs the i-th bit DTH[i-1] of the grayscale data DTH[10:0] to the input node of the drive circuit DRi. The drive circuit DRi outputs a first voltage level to the capacitor drive node NDRi when bit DTH[i-1] is at the first logic level, and outputs a second voltage level to the capacitor drive node NDRi when bit DTH[i-1] is at the second logic level. For example, the first logic level is "0", the second logic level is "1", the first voltage level is the low-potential side power supply voltage VSH, and the second voltage level is the high-potential side power supply voltage VDH. The drive circuit DRi is composed of high-voltage process transistors and operates with power supply voltages VDH and VSH. The drive circuit DRi is composed of, for example, a level shifter that level shifts the input logic level to the output voltage level of the drive circuit DRi, and a buffer circuit that buffers the output of the level shifter.

[0038] The drive circuits DR1 to DR11 drive capacitors C1 to C11, causing charge redistribution between capacitors C1 to C11, the variable capacitance circuit 30, and the electro-optic panel side capacitance CP. As a result, a data voltage is output to the output node NVQ.

[0039] The electro-optical panel capacitance CP is the sum of the capacitances visible from the data voltage output terminal TVQ. For example, the electro-optical panel capacitance CP is the sum of the parasitic capacitance of the printed circuit board, which is the board capacitance CP1, and the parasitic capacitance within the electro-optical panel 200, which is the panel capacitance CP2. The printed circuit board is the board on which the driver 100 is mounted and which is connected to the electro-optical panel 200.

[0040] Let's assume that the sum of the capacitance values ​​of capacitors C1 to C11 is Ctot = C1 + C2 + ... + C11, and the capacitance value of the variable capacitance circuit 30 is CF. For example, CF is set so that Ctot / (CF+CP)=2. In this case, at the maximum gradation value of DTH[10:0] 2047, VQ = 15V × {Ctot / (Ctot+CF+CP)} + 2.5V = 10V + 2.5V = 12.5V. At the minimum gradation value of DTH[10:0] 0, VQ = 0V × {Ctot / (Ctot+CF+CP)} + 2.5V = 0V + 2.5V = 2.5V. This achieves the same data voltage as in the example in Figure 3.

[0041] Figure 5 illustrates the relationship between grayscale data and the voltage in the low-voltage second drive circuit.

[0042] The processing circuit 42 converts the input grayscale data GD[9:0] into grayscale data DTL[10:0]. Specifically, when driven by negative polarity, the processing circuit 42 sets DTL

[10] =1 and DTL[9:0]=GD[9:0], and when driven by positive polarity, it sets DTL

[10] =0 and DTL[9:0]=XGD[9:0]. XGD[9:0] is data obtained by logically inverting each bit of GD[9:0].

[0043] VSL=0V is the low-potential power supply voltage of the second drive circuit 70. VDL=1.8V is the high-potential power supply voltage of the second drive circuit 70. The voltage corresponding to the common voltage VC=7.5V in Figure 3 is VCL=0.9V. In negative polarity drive, the voltages corresponding to the data voltages of 7.5V to 2.5V supplied to the pixels are 0.9V to 0.4V, and in positive polarity drive, the voltages corresponding to the data voltages of 7.5V to 12.5V supplied to the pixels are 0.9V to 1.4V.

[0044] Figure 6 shows a first detailed configuration example of the second drive circuit. The second drive circuit 70 includes an operational amplifier 71, a D / A conversion circuit 72, an output capacitor CQ, a first feedback capacitor Cfa, a second feedback capacitor Cfb, and an initialization switch SWR.

[0045] The D / A conversion circuit 72 performs D / A conversion on the grayscale data DTL[10:0] to obtain a D / A conversion voltage DAQ, and outputs this D / A conversion voltage DAQ to the non-inverting input node NAP of the operational amplifier 71. The correspondence between the grayscale data DTL[10:0] and the D / A conversion voltage DAQ is as explained in Figure 5. The D / A conversion circuit 72 includes, for example, a ladder resistor that divides the power supply voltage VDL and VSL into multiple voltages, and a switch circuit that selects a voltage corresponding to the grayscale data DTL[10:0] from these multiple voltages.

[0046] The operational amplifier 71 is composed of low-voltage process transistors and operates at power supply voltages VDL and VSL. Specifically, the source-drain distance of the transistors constituting the first drive circuit 60 is longer than the source-drain distance of the transistors constituting the second drive circuit 70, which includes the operational amplifier 71. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit 60 is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit 70, which includes the operational amplifier 71. However, the above is just one example of a configuration that gives the transistors different breakdown voltages; it is sufficient that the transistors in each drive circuit are configured such that the breakdown voltage of the transistors constituting the second drive circuit 70 is lower than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0047] One end of output capacitor CQ is connected to the output node NAMQ of the operational amplifier 71, and the other end is connected to the output node NVQ of the data line drive circuit 110. One end of first feedback capacitor Cfa is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the output node NVQ of the data line drive circuit 110. One end of second feedback capacitor Cfb is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to the node of the low-potential side power supply voltage VSL. The other end of second feedback capacitor Cfb only needs to be connected to a predetermined potential node to which a constant potential is supplied.

[0048] One end of the initialization switch SWR is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NVREF, which is supplied with a reference voltage VREF. The reference voltage VREF is a voltage higher than VSL and lower than VDL. Here, VREF = VCL = 0.9V. The reference voltage VREF is supplied to node NVREF from, for example, a voltage generation circuit (not shown) included in the driver 100. The initialization switch SWR is an analog switch, for example, an N-type transistor, a P-type transistor, or a transfer gate combining them.

[0049] In the examples in Figures 3 and 5, the output voltage VQ range is 10V, and the D / A conversion voltage DAQ range is 1V. In this case, the voltage range should be divided in a 9:1 ratio by the first feedback capacitor Cfa and the second feedback capacitor Cfb, so Cfb / Cfa = 9. Note that the ratio of Cfb to Cfa is not limited to 9, and can be set appropriately according to the ratio of the voltage ranges.

[0050] The capacitance value of the output capacitor CQ can be arbitrary, as long as it is set so that the output voltage AMQ of the operational amplifier 71 is within the range of VSL to VDL. For example, the capacitance value of the output capacitor CQ is set to approximately 1 to 10 times the sum of the capacitor circuit 10, the variable capacitance circuit 30, and the electro-optic panel side capacitance CP. As an example, if the capacitance value of the output capacitor CQ is 4 times the above sum, in order to compensate for an error of 0.1V in the output voltage VQ, the output voltage AMQ of the operational amplifier 71 only needs to change by 0.1V × (5 / 4) = 0.125V.

[0051] Figure 7 shows a first waveform example illustrating the operation of the first and second drive circuits. Assume that the gradation values ​​of the gradation data DTH[10:0] and DTL[10:0] change to 1024, 1535, and 1024. The target voltage corresponding to a gradation value of 1535 is 10.0V.

[0052] Assuming that the second drive circuit 70 is absent and the system is driven only by the first drive circuit 60, when the grayscale value changes from 1024 to 1535, the output voltage VQ changes from 7.5V to 9.9V. The difference from the target voltage of 10.0V is 0.1V. The operation of the second drive circuit 70 in this case will be explained below.

[0053] The D / A conversion circuit 72 changes the D / A conversion voltage DAQ from 0.9V to 1.15V when the grayscale value changes from 1024 to 1535. The output voltage VQ is changed from 7.5V to 9.9V by the first drive circuit 60, so the voltage VFB of the inverting input node NAN of the operational amplifier 71 changes from 0.9V to 0.9V + (9.9V - 7.5V) / 10 = 1.14V. The operational amplifier 71 changes the output voltage AMQ from 0.9V to 0.9V + (10.0V - 9.9V) × (5 / 4) = 1.025V in order to make VFB = DAQ = 1.15V. As a result, the output voltage VQ becomes the target voltage of 10.0V and the voltage VFB becomes 1.15V.

[0054] Figure 8 shows a second waveform example illustrating the operation of the first and second drive circuits. Figure 8 shows a waveform example of the horizontal scanning period during the positive polarity drive period of polarity reversal drive. Here, an example is shown in which grayscale values ​​of 0, 127, ..., 1023 are sequentially written to nine pixels, but the number of pixels driven during the horizontal scanning period and the grayscale values ​​written to each pixel can be arbitrary.

[0055] The rising edge of the horizontal synchronization signal HSYNC is used as the start timing for the horizontal scanning period. After the horizontal scanning period has started, the processing circuit 42 outputs DTH[9:0]=DTL[9:0]=0 and changes DTH

[10] =DTL

[10] from 0 to 1. Here, 0 is shown as a low level and 1 as a high level. This corresponds to DTH[10:0]=DTL[10:0]=1024, so the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0056] Next, the initialization switch SWR switches from off to on, and then from on to off. Here, off is represented by a low level, and on by a high level. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = 0.9V. The period during which the voltage VFB is initialized is called the initialization period. In Figure 8, the period during which the initialization switch SWR is on corresponds to the initialization period.

[0057] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTL[9:0] with grayscale values ​​of 0, 127, ..., 1023. As a result, the D / A conversion voltage DAQ changes sequentially from 0.9V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that the grayscale values ​​shown here are merely examples with easily understandable voltage ranges; as mentioned above, the grayscale values ​​written to each pixel can be arbitrary.

[0058] Figure 9 is a third waveform example illustrating the operation of the first and second drive circuits. Figure 9 shows an example waveform of the horizontal scanning period during the negative polarity drive period of polarity reversal drive.

[0059] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=DTL[9:0]=0 and changes DTH

[10] =DTL

[10] from 0 to 1. This corresponds to DTH[10:0]=DTL[10:0]=1024, so the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0060] Next, the initialization switch SWR switches from off to on, and then from on to off. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V.

[0061] Next, the processing circuit 42 changes DTH

[10] =DTL

[10] from 1 to 0. As a result, DTH[10:0]=DTL[10:0]=0, so the D / A conversion voltage DAQ changes from 0.9V to 0.4V, and the output voltage VQ changes from 7.5V to 2.5V.

[0062] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTL[9:0] with grayscale values ​​0, 127, ..., 1023. As a result, the D / A conversion voltage DAQ changes sequentially from 0.4V to 0.9V, and the output voltage VQ changes sequentially from 2.5V to 7.5V. Note that the grayscale values ​​shown here are merely examples with easily understandable voltage ranges; the grayscale values ​​written to each pixel can be arbitrary.

[0063] In the above, DTH[10:0] = DTL[10:0] was assumed, but DTH[10:0] ≠ DTL[10:0] is also possible when correction data is added to the gradation data DTH[10:0]. The correction data is, for example, data that corrects for excess or deficit charge. The excess or deficit charge is the difference between the charge output by the first drive circuit 60 in the gradation data DTH[10:0] without the addition of correction data, and the charge required to make the output voltage VQ the target voltage. The correction data is this excess or deficit charge converted into gradation values. By adding the correction data to the gradation data DTH[10:0], the error between the output voltage VQ due to the charge output by the first drive circuit 60 and the target voltage corresponding to the gradation data DTH[10:0] can be reduced. When such correction is performed, if an error still occurs between the output voltage VQ and the target voltage even after the correction, the second drive circuit 70 corrects that error by feedback control using the operational amplifier 71.

[0064] In the above embodiment, the driver 100 includes a first drive circuit 60 that supplies a data signal to the signal supply line of the electro-optic panel 200 based on grayscale data DTH[10:0], and a second drive circuit 70 electrically connected to the signal supply line. The second drive circuit 70 includes an operational amplifier 71, an output capacitor CQ, a first feedback capacitor Cfa, and a second feedback capacitor Cfb. The operational amplifier 71 is composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60. The output capacitor CQ is provided between the output node NAMQ of the operational amplifier 71 and the signal supply line. The first feedback capacitor Cfa is provided between the inverting input node NAN of the operational amplifier 71 and the signal supply line. One end of the second feedback capacitor Cfb is connected to the inverting input node NAN of the operational amplifier 71.

[0065] According to this embodiment, the output node NAMQ of the operational amplifier 71 and the signal supply line are coupled by the output capacitor CQ, and the inverting input node NAN of the operational amplifier 71 and the signal supply line are coupled by the first feedback capacitor Cfa. As a result, the operational amplifier 71 and the signal supply line are DC disconnected, so the operational amplifier 71 can be constructed using transistors with a voltage rating lower than the voltage rating of the transistors constituting the first drive circuit 60.

[0066] Furthermore, the voltage of the signal supply line is divided by the first feedback capacitor Cfa and the second feedback capacitor Cfb and fed back to the inverting input node NAN of the operational amplifier 71. As a result, a voltage lower than the voltage of the signal supply line is applied to the inverting input node NAN of the operational amplifier 71, so the operational amplifier 71 can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0067] Furthermore, by configuring the operational amplifier 71 with transistors having a lower voltage rating than the transistors constituting the first drive circuit 60, the operational amplifier 71 can be constructed with high-mobility transistors. This makes it possible to achieve both high amplification and high frequency response characteristics in the operational amplifier. For example, in order to increase the drive speed due to high resolution, it is necessary to increase the frequency response characteristics of the operational amplifier. However, it is possible to increase the frequency response characteristics while maintaining the amplification of the operational amplifier, and thus reduce the power consumption of the operational amplifier.

[0068] An electrical connection is defined as a connection that allows electrical signals to be transmitted, and is a connection that enables the transmission of information via electrical signals. An electrical connection may also be a connection mediated by active elements, etc.

[0069] In the above embodiment, the D / A conversion circuit 72 is connected to the non-inverting input node NAP of the operational amplifier 71, and the other end of the second feedback capacitor Cfb is at a constant voltage. However, it is not limited to this, and it is sufficient if one end of the second feedback capacitor Cfb is connected to the inverting input node NAN of the operational amplifier 71. For example, the second drive circuit 70 may be configured as a so-called capacitive DAC. That is, a reference voltage may be input to the non-inverting input node NAP of the operational amplifier 71, and the voltage at the other end of the second feedback capacitor Cfb may fluctuate based on the grayscale data. In this case as well, when a voltage corresponding to a certain grayscale data is applied to the other end of the second feedback capacitor Cfb, the voltage of the signal supply line is fed back by the voltage division between the first feedback capacitor Cfa and the second feedback capacitor Cfb, so the same effects as described above can be obtained.

[0070] In this embodiment, the second drive circuit 70 also includes a D / A conversion circuit 72. The D / A conversion circuit 72 supplies a D / A conversion voltage DAQ based on the grayscale data DTL[10:0] to the inverting input node NAN of the operational amplifier 71. The other end of the second feedback capacitor Cfb is electrically connected to a predetermined potential node.

[0071] According to this embodiment, when a difference occurs between the D / A conversion voltage DAQ and the voltage VFB fed back from the signal supply line to the inverting input node NAN of the operational amplifier 71, the operational amplifier 71 can supply charge to the signal supply line via the output capacitor CQ, thereby correcting the difference between the voltage of the signal supply line and the target voltage corresponding to the grayscale data GD[9:0]. As a result, even if there is an error between the voltage output to the signal supply line by the first drive circuit 60 and the target voltage, the second drive circuit 70 can correct that error.

[0072] Furthermore, since the above error is considered to be sufficiently small compared to the target voltage, the amount of charge that the operational amplifier 71 needs to supply can be considered small. As a result, the voltage change at the output node NAMQ of the operational amplifier 71 is small, and the operational amplifier 71 can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0073] Furthermore, in this embodiment, the capacitance of the second feedback capacitor Cfb is greater than the capacitance of the first feedback capacitor Cfa.

[0074] The gain of the second drive circuit 70 is (Cfa + Cfb) / Cfa. According to this embodiment, since the gain is greater than 2, the voltage range applied to the operational amplifier 71 becomes smaller than half the voltage range of the signal supply line. As a result, the operational amplifier 71 can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit 60.

[0075] In this embodiment, the source-drain distance of the transistors constituting the first drive circuit 60 is longer than the source-drain distance of the transistors constituting the second drive circuit 70. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit 60 is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit 70.

[0076] According to this embodiment, the transistors constituting the second drive circuit 70, which includes the operational amplifier 71, can be composed of transistors with a lower breakdown voltage than the transistors constituting the first drive circuit 60.

[0077] In this embodiment, the driver 100 also includes an initialization switch SWR. The initialization switch SWR is turned on during the initialization period and supplies a reference voltage VREF to the inverting input node NAN of the operational amplifier 71.

[0078] According to this embodiment, the inverting input node NAN of the operational amplifier 71 changes with respect to the reference voltage VREF. When the range of the D / A conversion voltage DAQ is expressed as VREF-ΔV1 to VREF+ΔV2, the reference voltage VREF should be set such that VREF-ΔV1 is higher than the low-potential side power supply voltage VSL of the second drive circuit 70, and VREF+ΔV2 is lower than the high-potential side power supply voltage VDL of the second drive circuit 70.

[0079] In this embodiment, the first drive circuit 60 includes a capacitor drive circuit 20 and a capacitor circuit 10. The capacitor drive circuit 20 outputs the first to nth capacitor drive voltages corresponding to the grayscale data DTH[10:0] to the first to nth capacitor drive nodes NDR1 to NDRn, where n is an integer of 2 or more. The capacitor circuit 10 has a signal supply line and first to nth capacitors C1 to Cn provided between the signal supply line and the first to nth capacitor drive nodes NDR1 to NDRn.

[0080] According to this embodiment, the capacitor drive circuit 20 outputs a first to nth capacitor drive voltage corresponding to the grayscale data DTH[10:0], causing the first to nth capacitors C1 to Cn to output a charge corresponding to the grayscale data DTH[10:0] to the signal supply line. As a result, a voltage corresponding to the grayscale data DTH[10:0] is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit 70 can correct this error by feedback control.

[0081] 3. Second Embodiment Figure 10 shows a second detailed configuration example of the driver. In this configuration example, the data line drive circuit 110 includes a first drive circuit 60 and a second drive circuit 70. The processing circuit 42 outputs setting data DP[9:0] and DN[9:0] which set the drive capability of the first drive circuit 60 based on the grayscale data GD[9:0]. Since the configuration and operation of the second drive circuit 70 are the same as in the first embodiment, the configuration and operation of the first drive circuit 60 will be mainly described below.

[0082] Figure 11 illustrates the relationship between grayscale data, setting data, and data voltage. The relationship between grayscale data GD[9:0], grayscale data DTH[10:0], and data voltage is the same as in Figure 3.

[0083] Assume that one pixel is driven with a gradation value DTH1, the next pixel is driven with a gradation value DTH2, and DTH2-DTH1>0. In this case, the processing circuit 42 outputs DP[9:0]=|DTH2-DTH1| and DN[9:0]=0. Assume that one pixel is driven with a gradation value DTH3, the next pixel is driven with a gradation value DTH4, and DTH4-DTH3<0. In this case, the processing circuit 42 outputs DP[9:0]=0 and DN[9:0]=|DTH4-DTH3|. Figure 11 shows an example of positive polarity driving, but the same applies to negative polarity driving.

[0084] Furthermore, since DTH

[10] is canceled when the difference is taken, it is also possible to directly calculate DP[9:0] and DN[9:0] from the grayscale data GD[9:0] without going through DTH[10:0].

[0085] Figure 12 shows a second detailed configuration example of the first drive circuit. In this configuration example, the first drive circuit 60 includes a first drive transistor group TRG1 and a second drive transistor group TRG2.

[0086] The first drive transistor group TRG1 includes P-type transistors TP1 to TP10 connected in parallel between the node of the high-potential side power supply voltage VDH and the output node NVQ. The gate of P-type transistor TP1 is input to the bit signal XDP[0]. Similarly, the gates of P-type transistors TP2 to TP10 are input to the bit signals XDP[1] to XDP[9]. XDP[9:0] is the data obtained by logically inverting each bit of DP[9:0]. The drive capability of P-type transistors TP1 to TP10 is binary weighted. That is, the drive capability of P-type transistor TPi is twice the drive capability of P-type transistor TP1. (i-1) It is double. The driving capability is adjusted by, for example, the gate width of the transistor or the number of unit transistors connected in parallel.

[0087] The second group of drive transistors, TRG2, includes N-type transistors TN1 to TN10 connected in parallel between the output node NVQ and the low-potential power supply voltage VSH. The gate of N-type transistor TN1 is input to the bit signal DN[0]. Similarly, the gates of N-type transistors TN2 to TN10 are input to the bit signals DN[1] to DN[9]. The drive capability of N-type transistors TN1 to TN10 is binary weighted. That is, the drive capability of N-type transistor TNi is twice the drive capability of N-type transistor TN1. (i-1) It is double.

[0088] For example, let Itp1 be the current that flows when a P-type transistor TP1 is ON, and let ton be the ON period for driving one pixel. The charge that the P-type transistor TP1 supplies to the output node NVQ is Itp1 × ton, and the change in output voltage VQ due to that charge is (Itp1 × ton) / CP. Itp1 is set so that this voltage change is 1 LSB, that is, the driving capability of the P-type transistor TP1 is set.

[0089] Figure 13 is a fourth waveform example illustrating the operation of the first and second drive circuits. Figure 13 shows an example waveform of the horizontal scanning period during the positive polarity drive period.

[0090] After the horizontal scanning period begins, the processing circuit 42 outputs DTL[9:0]=DP[9:0]=DN[9:0]=0 and changes DTL

[10] from 0 to 1. This corresponds to DTL[10:0]=1024, so the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0091] Next, the initialization switch SWR switches from off to on, and then from on to off. When the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V.

[0092] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTL[9:0] with grayscale values ​​of 0, 127, ..., 1023, and also sequentially outputs DP[9:0]=0, 127, 128, ..., 128. As a result, the D / A conversion voltage DAQ changes sequentially from 0.9V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that Figure 13 shows an example where DP[9:0]>0 and DN[9:0]=0, but when the grayscale value of DTL[9:0] decreases, DP[9:0]=0 and DN[9:0]>0. Note that the grayscale values ​​shown here are just examples that make the voltage range easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0093] The waveform diagram for the negative polarity drive period is omitted. During the negative polarity drive period, the waveforms of SWR, DTL[9:0], DP[9:0], and DN[9:0] are the same as in Figure 13. The waveforms of DTL

[10] , DAQ, and VQ are the same as in Figure 9.

[0094] In the above embodiment, the driver 100 includes a control circuit 40 that controls the first drive circuit 60. The first drive circuit 60 includes a first drive transistor group TRG1 provided between a node to which a high-potential-side power supply voltage VDH is supplied and a signal supply line, and a second drive transistor group TRG2 provided between a node to which a low-potential-side power supply voltage VSH is supplied and a signal supply line. The control circuit 40 controls each transistor of the first drive transistor group TRG1 or each transistor of the second drive transistor group TRG2 to be turned on or off based on the grayscale data GD[9:0].

[0095] According to this embodiment, based on the grayscale data GD[9:0], the transistor that is turned on from the first drive transistor group TRG1 or the second drive transistor group TRG2 outputs a charge corresponding to the grayscale data GD[9:0] to the signal supply line. As a result, a voltage corresponding to the grayscale data GD[9:0] is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit 70 can correct this error by feedback control.

[0096] 4. Third Embodiment In the third embodiment, the configuration and operation of the first drive circuit 60 are the same as in the first or second embodiment. The following will mainly describe the differences in the configuration and operation of the second drive circuit 70 compared to the first embodiment.

[0097] Figure 14 shows a second detailed configuration example of the second drive circuit. The second drive circuit 70 includes an operational amplifier 71, a D / A conversion circuit 72, an output capacitor CQ, a first feedback capacitor Cfa, a second feedback capacitor Cfb, and a voltage shift circuit 73.

[0098] The processing circuit 42 outputs grayscale data DTM[9:0] based on the grayscale data GD[9:0]. The D / A conversion circuit 72 performs D / A conversion on the grayscale data DTM[9:0] to a D / A conversion voltage DAQ. Figure 15 shows the relationship between the grayscale data and the D / A conversion voltage. The processing circuit 42 sets DTM[9:0]=GD[9:0] in positive polarity drive and DTM[9:0]=XGD[9:0] in negative polarity drive. The D / A conversion circuit 72 outputs DAQ=0.4V~1.4V for DTM[9:0]=0~1023.

[0099] The voltage shift circuit 73 includes an initialization switch SWR, a shift capacitor CFR, and a voltage output circuit DFR.

[0100] One end of the shift capacitor CFR is connected to the inverting input node NAN of the operational amplifier 71. The voltage output circuit DFR receives the signal XFR, which is the logic inverted signal of the polarity inversion signal FR. When the signal XFR is low, the voltage output circuit DFR outputs a signal with a voltage level of VSL=0V to the other end of the shift capacitor CFR, and when the signal XFR is high, it outputs a signal with a voltage level of VDL=1.8V to the other end of the shift capacitor CFR.

[0101] In both positive polarity drive and negative polarity drive, the capacitance values ​​of CFR, Cfb, and Cfa are set so that the output voltage VQ ranges to 5V for a D / A conversion voltage DAQ range of 1V. In this case, the voltage division ratio of Cfa and Cfb+CFR is 4:1, so (Cfb+CFR) / Cfa=4. Also, the capacitance values ​​of CFR and Cfb are set so that when the voltage at the other end of the shift capacitor CFR changes by 1.8V, the voltage VFB changes by 0.5V. In this case, the voltage division ratio of CFR and Cfb is 1.3:0.5, so Cfb / CFR=1.3V / 0.5V=2.6.

[0102] Figure 16 shows a third detailed configuration example of the second drive circuit. In this configuration example, the voltage shift circuit 73 further includes a level shifter LSFR. Also, the power supply voltages of the voltage output circuit DFR are VDH and VSH.

[0103] When the signal XFR is at a low level, i.e., VSL = 0V, the level shifter LSFR outputs a signal with a voltage level of VSH = 0V, and the voltage output circuit DFR outputs a signal with a voltage level of VSH = 0V to the other end of the shift capacitor CFR. When the signal XFR is at a high level, i.e., VDL = 1.8V, the level shifter LSFR outputs a signal with a voltage level of VDH = 15V, and the voltage output circuit DFR outputs a signal with a voltage level of VDH = 15V to the other end of the shift capacitor CFR.

[0104] When the voltage at the other end of the shift capacitor CFR changes by 15V, the voltage VFB changes by 0.5V, so the voltage division ratio of CFR and Cfb is 14.5:0.5. Therefore, Cfb / CFR = 14.5V / 0.5V = 29.

[0105] Figure 17 is a fifth waveform example illustrating the operation of the first and second drive circuits. Figure 17 shows an example waveform of the horizontal scanning period during the positive polarity drive period.

[0106] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=512, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0107] Next, the processing circuit 42 changes the signal XFR from a low level to a high level, and then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a high level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V. Next, the processing circuit 42 changes the signal XFR from a high level to a low level. As a result, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is shifted from 0.9V to 0.4V, which corresponds to the initialization voltage for positive polarity. In Figure 17, the period from when the initialization switch SWR is switched from off to on until the signal XFR changes from a high level to a low level corresponds to the initialization period.

[0108] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTM[9:0] with grayscale values ​​of 0, 127, ..., 1023. As a result, the D / A conversion voltage DAQ changes sequentially from 0.4V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that the grayscale values ​​shown here are merely examples with easily understandable voltage ranges, and the grayscale values ​​written to each pixel can be arbitrary.

[0109] Figure 18 is a sixth waveform example illustrating the operation of the first and second drive circuits. Figure 18 shows an example waveform of the horizontal scanning period during the negative polarity drive period.

[0110] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=512, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0111] Next, the processing circuit 42 changes the signal XFR from a high level to a low level, and then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a low level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V. Next, the processing circuit 42 changes the signal XFR from a low level to a high level. As a result, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is shifted from 0.9V to 1.4V, which corresponds to the initialization voltage for the negative polarity.

[0112] Next, writing to the pixels begins. The processing circuit 42 sets DTH

[10] from 1 to 0, and then sequentially outputs DTH[9:0]=DTM[9:0] with gradation values ​​of 1023, 895, ..., 0. As a result, the D / A conversion voltage DAQ changes sequentially from 1.4V to 0.4V, and the output voltage VQ changes sequentially from 7.5V to 2.5V. Note that the gradation values ​​shown here are merely examples with easily understandable voltage ranges, and the gradation values ​​written to each pixel can be arbitrary.

[0113] In the above embodiment, the driver 100 includes a voltage shift circuit 73. The voltage shift circuit 73 is electrically connected to the inverting input node NAN of the operational amplifier 71 and shifts the voltage VFB of the inverting input node NAN.

[0114] According to this embodiment, the voltage shift circuit 73 shifts the voltage VFB of the inverting input node NAN, thereby shifting the reference of the voltage VFB of the inverting input node NAN. By dividing the range of the output voltage VQ into multiple ranges and shifting the reference of the voltage VFB for each range, it becomes possible to associate each range of the output voltage VQ with the range of the D / A conversion voltage DAQ. This makes it possible to lower the gain (Cfa + Cfb) / Cfa of the second drive circuit 70 and to lower the number of gradations in the D / A conversion.

[0115] In this embodiment, the voltage shift circuit 73 sets different initialization voltages for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period to the inverting input node NAN of the operational amplifier 71 based on the polarity inversion signal FR.

[0116] According to this embodiment, the range of the output voltage VQ during the positive polarity drive period is associated with the range of the D / A conversion voltage DAQ, which is 7.5V to 12.5V, and the range of the output voltage VQ during the negative polarity drive period is associated with the range of the D / A conversion voltage DAQ, which is 7.5V to 2.5V. This makes it possible to reduce the gain (Cfa + Cfb) / Cfa of the second drive circuit 70 to approximately 1 / 2, and to reduce the number of gradations of the D / A conversion from 2048 to 1024 (half of 2048).

[0117] In this embodiment, the voltage shift circuit 73 includes an initialization switch SWR, a shift capacitor CFR, and a voltage output circuit DFR. The initialization switch SWR is turned on during the initialization period and supplies a reference voltage VREF to the inverting input node NAN of the operational amplifier 71. One end of the shift capacitor CFR is electrically connected to the inverting input node NAN of the operational amplifier 71. The voltage output circuit DFR outputs a voltage based on a polarity inversion signal FR to the other end of the shift capacitor CFR during the initialization period.

[0118] According to this embodiment, the voltage output circuit DFR changes the voltage at the other end of the shift capacitor CFR based on the polarity inversion signal FR, thereby shifting the voltage VFB of the inverting input node NAN of the operational amplifier 71 through voltage division between the shift capacitor CFR and the second feedback capacitor Cfb.

[0119] 5. Fourth Embodiment In the fourth embodiment, the configuration and operation of the first drive circuit 60 are the same as in the first or second embodiment. The following will mainly describe the differences in the configuration and operation of the second drive circuit 70 compared to the first and third embodiments.

[0120] Figure 19 shows a fourth detailed configuration example of the second drive circuit. In this configuration example, the voltage shift circuit 73 includes a first initialization switch SWRP and a second initialization switch SWRN.

[0121] One end of the first initialization switch SWRP is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NPVR, which is supplied with the initialization voltage PVR for positive polarity. One end of the second initialization switch SWRN is connected to the inverting input node NAN of the operational amplifier 71, and the other end is connected to node NNVR, which is supplied with the initialization voltage NVR for negative polarity. The initialization voltages PVR and NVR are supplied to nodes NPVR and NNVR from, for example, a voltage generation circuit (not shown) included in the driver 100.

[0122] Figure 20 is a seventh waveform example illustrating the operation of the first and second drive circuits. Figure 20 shows an example waveform of the horizontal scanning period during the positive polarity drive period.

[0123] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=0, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=0.4V and the output voltage VQ=7.5V.

[0124] Next, the processing circuit 42 switches the first initialization switch SWRP from off to on, and then from on to off. The second initialization switch SWRN remains off. When the first initialization switch SWRP is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the positive polarity initialization voltage PVR = 0.4V. In Figure 20, the period during which the first initialization switch SWRP is on corresponds to the initialization period.

[0125] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTM[9:0] with grayscale values ​​of 0, 127, ..., 1023. As a result, the D / A conversion voltage DAQ changes sequentially from 0.4V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that the grayscale values ​​shown here are merely examples with easily understandable voltage ranges, and the grayscale values ​​written to each pixel can be arbitrary.

[0126] Figure 21 is an example of the eighth waveform illustrating the operation of the first and second drive circuits. Figure 21 shows an example of the waveform during the horizontal scanning period in the negative polarity drive period.

[0127] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0 and DTM[9:0]=1023, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=1.4V and the output voltage VQ=7.5V.

[0128] Next, the processing circuit 42 switches the second initialization switch SWRN from off to on, and then from on to off. The first initialization switch SWRP remains off. When the second initialization switch SWRN is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the negative polarity initialization voltage NVR = 1.4V. In Figure 21, the period during which the second initialization switch SWRN is on corresponds to the initialization period.

[0129] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTM[9:0] with grayscale values ​​of 1023, 895, ..., 0. As a result, the D / A conversion voltage DAQ changes sequentially from 1.4V to 0.4V, and the output voltage VQ changes sequentially from 7.5V to 2.5V. Note that the grayscale values ​​shown here are merely examples with easily understandable voltage ranges, and the grayscale values ​​written to each pixel can be arbitrary.

[0130] In the above embodiment, the voltage shift circuit 73 includes a first initialization switch SWRP that supplies an initialization voltage PVR for positive polarity to the inverting input node NAN of the operational amplifier 71 during the initialization period of the positive polarity drive period, and a second initialization switch SWRN that supplies an initialization voltage NVR for negative polarity to the inverting input node NAN of the operational amplifier 71 during the initialization period of the negative polarity drive period.

[0131] According to this embodiment, different initialization voltages are set at the inverting input node NAN of the operational amplifier 71 for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period. This makes it possible to reduce the gain (Cfa + Cfb) / Cfa of the second drive circuit 70 to approximately 1 / 2 and to reduce the number of gradations of the D / A conversion from 2048 to 1024 (half of the original).

[0132] 6. Fifth Embodiment In the fifth embodiment, the configuration and operation of the first drive circuit 60 are the same as in the first or second embodiment. The following will mainly describe the differences in the configuration and operation of the second drive circuit 70 compared to the first and third embodiments.

[0133] Figure 22 shows a fifth detailed configuration example of the second drive circuit. In this configuration example, the voltage shift circuit 73 includes an initialization switch SWR, a first shift capacitor CFR, a first voltage output circuit DFR, a second shift capacitor CDM, and a second voltage output circuit DDM.

[0134] The lower bits DTM[8:0] of the grayscale data DTM[9:0] are input to the D / A conversion circuit 72. The D / A conversion circuit 72 performs D / A conversion on the lower bits DTM[8:0] to obtain the D / A conversion voltage DAQ.

[0135] One end of the second shift capacitor CDM is connected to the inverting input node NAN of the operational amplifier 71. The signal XDTM[9], which is the logic inverted signal of the upper bit DTM[9] of the grayscale data DTM[9:0], is input to the second voltage output circuit DDM. When the signal XDTM[9] is low level, the second voltage output circuit DDM outputs a signal with a voltage level of VSL=0V to the other end of the second shift capacitor CDM, and when the signal XDTM[9] is high level, it outputs a signal with a voltage level of VDL=1.8V to the other end of the second shift capacitor CDM.

[0136] The capacitance values ​​of CDM, CFR, Cfb, and Cfa are set so that the output voltage VQ ranges to 10V / 4 = 2.5V for a D / A conversion voltage DAQ range of 1V. In this case, the voltage division ratio of Cfa and Cfb+CFR+CDM is 1.5:1, so (Cfb+CFR+CDM) / Cfa = 1.5. Also, the capacitance values ​​of CDM, CFR, and Cfb are set so that when the voltage at the other end of the first shift capacitor CFR changes by 1.8V, the voltage VFB changes by 0.5V. In this case, the voltage division ratio of CFR and Cfb+CDM is 1.3:0.5, so (Cfb+CDM) / CFR = 1.3V / 0.5V = 2.6. Also, the capacitance values ​​of CDM, CFR, and Cfb are set so that when the voltage at the other end of the second shift capacitor CDM changes by 1.8V, the voltage VFB changes by 1.0V. In this case, the voltage division ratio of CDM to Cfb+CFR is 0.8:1, so (Cfb+CFR) / CDM = 0.8V / 1V = 0.8.

[0137] Figure 23 shows a sixth detailed configuration example of the second drive circuit. In this configuration example, the voltage shift circuit 73 further includes a first level shifter LSFR and a second level shifter LSDM. The power supply voltages for the first voltage output circuit DFR and the second voltage output circuit DDM are VDH and VSH, respectively. The operation of these level shifters and voltage output circuits is the same as that of the level shifters and voltage output circuits in Figure 16, so a detailed explanation is omitted.

[0138] Figure 24 is a ninth waveform example illustrating the operation of the first and second drive circuits. Figure 24 shows an example waveform of the horizontal scanning period during the positive polarity drive period.

[0139] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0, DTM[8:0]=255, and XDTM[9]=1, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0140] Next, the processing circuit 42 changes the signal XFR from a low level to a high level, and then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a high level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V. Next, the processing circuit 42 changes the signal XFR from a high level to a low level. As a result, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is shifted from 0.9V to 0.4V.

[0141] Next, writing to the pixels begins. The processing circuit 42 sequentially outputs DTH[9:0]=DTM[9:0] with grayscale values ​​of 0, 127, 255, 377, and 511. At this time, XDTM[9]=1 and DTM[8:0]=0, 127, 255, 377, and 511. As a result, the D / A conversion voltage DAQ changes sequentially from 0.4V to 1.4V, and the output voltage VQ changes sequentially from 7.5V to 10.0V.

[0142] The processing circuit 42 changes the signal XDTM[9] from a high level to a low level. This shifts the voltage VFB of the inverting input node NAN of the operational amplifier 71 from 1.4V to 0.4V. However, since the grayscale value for the next pixel is DTH[9:0]=637, VQ=10.0V+0.625V, and due to the voltage division of the feedback capacitor, VFB=0.4V+0.625 / 2.5=0.4V+0.25V. Also, since DTM[8:0]=127, DAQ=0.4V+0.25V.

[0143] The processing circuit 42 changes the signal XDTM[9] from a high level to a low level, and then outputs DTH[9:0]=DTM[9:0] with grayscale values ​​of 639, 767, 895, and 1023. At this time, XDTM[9]=0 and DTM[8:0]=127, 255, 377, and 511. As a result, the D / A conversion voltage DAQ changes sequentially from 0.65V to 1.4V, and the output voltage VQ changes sequentially from 10.625V to 10.0V. Thus, for DTH[9:0] with grayscale values ​​of 0, 127, ..., 1023, the output voltage VQ changes sequentially from 7.5V to 12.5V. Note that the grayscale values ​​shown here are merely examples of grayscale values ​​whose voltage ranges are easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0144] Figure 25 is a tenth waveform example illustrating the operation of the first and second drive circuits. Figure 25 shows an example waveform of the horizontal scanning period during the negative polarity drive period.

[0145] After the horizontal scanning period begins, the processing circuit 42 outputs DTH[9:0]=0, DTM[8:0]=255, and XDTM[9]=0, and changes DTH

[10] from 0 to 1. At this time, the D / A conversion voltage DAQ=0.9V and the output voltage VQ=7.5V.

[0146] Next, the processing circuit 42 changes the signal XFR from a high level to a low level, and then switches the initialization switch SWR from off to on, and then from on to off. When the signal XFR is at a low level and the initialization switch SWR is on, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is initialized to the reference voltage VREF = VCL = 0.9V. Next, the processing circuit 42 changes the signal XFR from a low level to a high level. As a result, the voltage VFB of the inverting input node NAN of the operational amplifier 71 is shifted from 0.9V to 1.4V.

[0147] Next, writing to the pixels begins. The processing circuit 42 changes DTH

[10] from 1 to 0. The processing circuit 42 sequentially outputs DTH[9:0]=DTM[9:0] with grayscale values ​​of 1023, 895, 767, 639, and 511. At this time, XDTM[9]=0 and DTM[8:0]=511, 377, 255, 127, and 0. As a result, the D / A conversion voltage DAQ changes sequentially from 1.4V to 0.4V, and the output voltage VQ changes sequentially from 7.5V to 5.0V.

[0148] When DTM[9:0] changes from 511 or less to 512 or more, the signal XDTM[9] changes from a low level to a high level. This shifts the voltage VFB of the inverting input node NAN of the operational amplifier 71 from 0.4V to 1.4V. However, since the grayscale value for the next pixel is DTH[9:0]=377, VQ=5.0V-0.625V, and due to the voltage division of the feedback capacitor, VFB=1.4V-0.625 / 2.5=1.4V-0.25V. Also, since DTM[8:0]=377, DAQ=1.4V-0.25V.

[0149] The processing circuit 42 sequentially outputs DTH[9:0]=DTM[9:0] with grayscale values ​​of 377, 255, 127, and 0. At this time, XDTM[9]=1 and DTM[8:0]=377, 255, 127, and 0. As a result, the D / A conversion voltage DAQ changes sequentially from 1.15V to 0.4V, and the output voltage VQ changes sequentially from 4.375V to 2.5V. Thus, for DTH[9:0] with grayscale values ​​of 1023, 895, ..., 0, the output voltage VQ changes sequentially from 7.5V to 2.5V. Note that the grayscale values ​​shown here are merely examples of grayscale values ​​whose voltage ranges are easy to understand, and the grayscale values ​​written to each pixel can be arbitrary.

[0150] In the above embodiment, the voltage shift circuit 73 shifts the voltage of the inverting input node NAN of the operational amplifier 71 based on the polarity inversion signal FR and the upper bit DTM[9] of the grayscale data DTM[9:0].

[0151] According to this embodiment, the output voltage VQ range of 2.5V to 12.5V is divided into four ranges: 2.5V to 5V, 5V to 7.5V, 7.5V to 10V, and 10V to 12.5V, and each of these ranges is associated with the D / A conversion voltage DAQ range of 0.4V to 1.4V. This makes it possible to reduce the gain (Cfa + Cfb) / Cfa of the second drive circuit 70 to approximately 1 / 4, and to reduce the number of gradations of the D / A conversion from 2048 to 512, which is 1 / 4 of the original.

[0152] In this embodiment, the voltage shift circuit 73 includes an initialization switch SWR, a first shift capacitor CFR, a first voltage output circuit DFR, a second shift capacitor CDM, and a second voltage output circuit DDM. The initialization switch SWR is turned on during the initialization period and supplies a reference voltage VREF to the inverting input node NAN of the operational amplifier 71. One end of the first shift capacitor CFR is electrically connected to the inverting input node NAN of the operational amplifier 71. The first voltage output circuit DFR outputs a voltage based on the polarity inversion signal FR to the other end of the first shift capacitor CFR during the initialization period. One end of the second shift capacitor CDM is electrically connected to the inverting input node NAN of the operational amplifier 71. The second voltage output circuit DDM outputs a voltage based on the upper bit DTM[9] of the grayscale data DTM[9:0] to the other end of the second shift capacitor CDM.

[0153] In this embodiment, the first voltage output circuit DFR changes the voltage at the other end of the first shift capacitor CFR based on the polarity inversion signal FR, thereby shifting the voltage VFB of the inverting input node NAN of the operational amplifier 71 through voltage division between the first shift capacitor CFR and the second feedback capacitor Cfb and the second shift capacitor CDM. Furthermore, the second voltage output circuit DDM changes the voltage at the other end of the second shift capacitor CDM based on the higher bit DTM[9], thereby shifting the voltage VFB of the inverting input node NAN of the operational amplifier 71 through voltage division between the second shift capacitor CDM and the second feedback capacitor Cfb and the first shift capacitor CFR.

[0154] 7. Electronic equipment Figure 26 shows an example of the configuration of an electronic device including the driver of this embodiment. Various electronic devices equipped with a display device can be envisioned as the electronic device of this embodiment. For example, the electronic device may be a projector, television system, information processing device, portable information terminal, car navigation system, or portable game terminal.

[0155] The electronic device 500 includes an electro-optical device 400, a display controller 300, a processing unit 310, a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 400 includes a driver 100 and an electro-optical panel 200.

[0156] The electro-optic panel 200 is, for example, a matrix-type liquid crystal display panel. Alternatively, the electro-optic panel 200 may be an EL display panel using self-luminescent elements. EL stands for Electro-Luminescence. The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it consists of buttons, a mouse, a keyboard, or a touch panel attached to the electro-optic panel 200. The data interface unit 340 is an interface unit that performs input and output of image data or control data. For example, it is a wired communication interface such as USB, or a wireless communication interface such as wireless LAN. The storage unit 320 stores the image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as the working memory of the processing unit 310 or the display controller 300. The processing unit 310 performs control processing of various parts of the electronic device and various data processing. The processing unit 310 is, for example, a processor such as a CPU or a microcomputer. The display controller 300 performs control processing of the driver 100. For example, the display controller 300 converts the image data transferred from the data interface unit 340 or the storage unit 320 into a format that the driver 100 can accept, and outputs the converted image data to the driver 100. The driver 100 drives the electro-optical panel 200 based on the image data transferred from the display controller 300.

[0157] The driver of this embodiment described above includes a first drive circuit that supplies data signals to the signal supply line of an electro-optical panel based on grayscale data, and a second drive circuit electrically connected to the signal supply line. The second drive circuit includes an operational amplifier composed of transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit, and an output capacitor placed between the output node of the operational amplifier and the signal supply line. The second drive circuit also includes a first feedback capacitor placed between the inverting input node of the operational amplifier and the signal supply line, and a second feedback capacitor with one end connected to the inverting input node of the operational amplifier.

[0158] In this embodiment, the output capacitor and the first feedback capacitor create a DC disconnection between the operational amplifier and the signal supply line. Furthermore, the voltage of the signal supply line is divided by the first and second feedback capacitors and fed back to the inverting input node of the operational amplifier. As a result, a voltage lower than the signal supply line voltage is applied to the inverting input node of the operational amplifier, allowing the operational amplifier to be constructed using transistors with a lower voltage rating than the transistors constituting the first drive circuit. By constructing the operational amplifier with low-voltage transistors, it is possible to construct the operational amplifier with high-mobility transistors. This allows for a balance between the amplification factor and frequency response characteristics of the operational amplifier. Additionally, this makes it possible to reduce the power consumption of the operational amplifier.

[0159] In this embodiment, the second drive circuit may also include a D / A conversion circuit that supplies a D / A conversion voltage based on grayscale data to the inverting input node of the operational amplifier. The other end of the second feedback capacitor may be electrically connected to a predetermined potential node.

[0160] According to this embodiment, when a difference occurs between the D / A conversion voltage and the voltage fed back from the signal supply line to the inverting input node of the operational amplifier, the operational amplifier can supply charge to the signal supply line via the output capacitor, thereby correcting the difference between the voltage of the signal supply line and the target voltage corresponding to the grayscale data. As a result, even if there is an error between the voltage output to the signal supply line by the first drive circuit and the target voltage, the second drive circuit can correct that error.

[0161] In this embodiment, the capacitance of the second feedback capacitor may be greater than the capacitance of the first feedback capacitor.

[0162] According to this embodiment, since the gain of the second drive circuit is greater than 2, the voltage range applied to the operational amplifier becomes less than half the voltage range of the signal supply line. As a result, the operational amplifier can be constructed using transistors with a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit.

[0163] In this embodiment, the source-drain distance of the transistors constituting the first drive circuit may be longer than the source-drain distance of the transistors constituting the second drive circuit. Alternatively, the thickness of the gate insulating film of the transistors constituting the first drive circuit may be thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit.

[0164] According to this embodiment, the transistors constituting the second drive circuit, which includes an operational amplifier, can be configured with transistors having a lower breakdown voltage than the transistors constituting the first drive circuit.

[0165] In this embodiment, the driver may also include an initialization switch that is turned on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier.

[0166] According to this embodiment, the inverting input node of the operational amplifier changes with respect to a reference voltage. When the range of the D / A conversion voltage is expressed as (reference voltage -ΔV1) to (reference voltage +ΔV2), the reference voltage should be set such that (reference voltage -ΔV1) is higher than the low-potential side power supply voltage of the second drive circuit and (reference voltage +ΔV2) is lower than the high-potential side power supply voltage of the second drive circuit.

[0167] In this embodiment, the first drive circuit may also include a capacitor drive circuit that outputs first to nth capacitor drive voltages corresponding to grayscale data to first to nth capacitor drive nodes, and a capacitor circuit having first to nth capacitors arranged between a signal supply line and the first to nth capacitor drive nodes, where n is an integer of 2 or more.

[0168] According to this embodiment, the capacitor drive circuit outputs a first to nth capacitor drive voltage corresponding to the grayscale data, causing the first to nth capacitors to output a charge corresponding to the grayscale data to the signal supply line. As a result, a voltage corresponding to the grayscale data is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit can correct this error by feedback control.

[0169] In this embodiment, the driver may also include a control circuit for controlling the first drive circuit. The first drive circuit may include a group of first drive transistors arranged between a node to which a high-potential power supply voltage is supplied and a signal supply line, and a group of second drive transistors arranged between a node to which a low-potential power supply voltage is supplied and a signal supply line. The control circuit may control each transistor of the first drive transistor group or each transistor of the second drive transistor group to be turned on or off based on grayscale data.

[0170] According to this embodiment, based on the grayscale data, the transistors that are turned on from the first group of drive transistors or the second group of drive transistors output a charge corresponding to the grayscale data to the signal supply line. As a result, a voltage corresponding to the grayscale data is output to the signal supply line. Since this drive is not feedback controlled, an error may occur between the voltage output by this drive and the target voltage. The second drive circuit can correct this error by feedback control.

[0171] In this embodiment, the driver may also include a voltage shift circuit that is electrically connected to the inverting input node of the operational amplifier and shifts the voltage of the inverting input node.

[0172] According to this embodiment, the voltage shift circuit shifts the voltage at the inverting input node of the operational amplifier, thereby shifting the voltage reference of the inverting input node. By dividing the voltage range output to the signal supply line into multiple ranges and shifting the voltage reference of the inverting input node for each range, it becomes possible to associate each range of voltage output to the signal supply line with the range of D / A conversion voltage. This makes it possible to lower the gain of the second drive circuit and reduce the number of gradations in D / A conversion.

[0173] In this embodiment, the voltage shift circuit may set different initialization voltages at the inverting input node of the operational amplifier for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period, based on the polarity inversion signal.

[0174] According to this embodiment, the range of voltage output to the signal supply line during the positive polarity drive period is associated with the range of the D / A conversion voltage, and the range of voltage output to the signal supply line during the negative polarity drive period is associated with the range of the D / A conversion voltage. This makes it possible to reduce the gain of the second drive circuit 70 to approximately 1 / 2 and to reduce the number of gradations of the D / A conversion to 1 / 2.

[0175] In this embodiment, the voltage shift circuit may also include an initialization switch that is turned on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier. The voltage shift circuit may also include a shift capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier, and a voltage output circuit that outputs a voltage based on a polarity inversion signal to the other end of the shift capacitor during the initialization period.

[0176] According to this embodiment, the voltage output circuit changes the voltage at the other end of the shift capacitor based on the polarity reversal signal, thereby shifting the voltage at the inverting input node of the operational amplifier due to the voltage division between the shift capacitor and the second feedback capacitor.

[0177] In this embodiment, the voltage shift circuit may also include a first initialization switch that supplies a positive polarity initialization voltage to the inverting input node of the operational amplifier during the initialization period of the positive polarity drive period, and a second initialization switch that supplies a negative polarity initialization voltage to the inverting input node of the operational amplifier during the initialization period of the negative polarity drive period.

[0178] According to this embodiment, different initialization voltages are set at the inverting input node of the operational amplifier for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period. This makes it possible to reduce the gain of the second drive circuit to approximately half and to reduce the number of gradations of the D / A conversion to half.

[0179] In this embodiment, the voltage shift circuit may also shift the voltage at the inverting input node of the operational amplifier based on the polarity inversion signal and the upper bits of the grayscale data.

[0180] According to this embodiment, the voltage range output to the signal supply line is divided into four ranges, and each of these ranges is associated with the range of the D / A conversion voltage. This makes it possible to reduce the gain of the second drive circuit to approximately 1 / 4 and to reduce the number of gradations of the D / A conversion to 1 / 4.

[0181] In this embodiment, the voltage shift circuit may also include an initialization switch that is turned on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier. The voltage shift circuit may also include a first shift capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier, and a first voltage output circuit that outputs a voltage based on a polarity inversion signal to the other end of the first shift capacitor during the initialization period. The voltage shift circuit may also include a second shift capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier, and a second voltage output circuit that outputs a voltage based on the upper bits of the grayscale data to the other end of the second shift capacitor.

[0182] In this embodiment, the first voltage output circuit changes the voltage at the other end of the first shift capacitor based on a polarity reversal signal, thereby shifting the voltage at the inverting input node of the operational amplifier through voltage division between the first shift capacitor and the second feedback capacitor and the second shift capacitor. Furthermore, the second voltage output circuit changes the voltage at the other end of the second shift capacitor based on the higher bits of the grayscale data, thereby shifting the voltage at the inverting input node of the operational amplifier through voltage division between the second shift capacitor and the second feedback capacitor and the first shift capacitor.

[0183] Furthermore, the electro-optical device of this embodiment includes a driver as described in any of the above and an electro-optical panel.

[0184] Furthermore, the electronic device of this embodiment includes a driver as described in any of the above.

[0185] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the configuration and operation of control circuits, data line drive circuits, drivers, electro-optic panels, electro-optic devices, and electronic equipment are not limited to those described in this embodiment, and various modifications are possible. [Explanation of Symbols]

[0186] 10...Capacitor circuit, 20...Capacitor drive circuit, 30...Variable capacitance circuit, 40...Control circuit, 42...Processing circuit, 44...Interface circuit, 48...Register circuit, 50...Detection circuit, 60...First drive circuit, 70...Second drive circuit, 71...Operational amplifier, 72...D / A conversion circuit, 73...Voltage shift circuit, 100...Driver, 110...Data line drive circuit, 200...Electro-optic panel, 300...Display controller, 310...Processing unit, 320...Storage unit, 330...User interface unit, 340...Data interface unit, 400...Electro-optic device, 500...Electronic equipment, C1~C11...Capacitors, CDM...Second shift capacitor, CFR...First shift capacitor, CQ...Output capacitor, Cf a…First feedback capacitor, Cfb…Second feedback capacitor, DDM…Second voltage output circuit, DFR…First voltage output circuit, DL1~DL1280…Data lines, DR1~DR11…Drive circuit, DTH[10:0]…Gradation data, DTM[9:0]…Gradation data, FR…Polarity inversion signal, GD[9:0]…Gradation data, LSDM…Second level shifter, LSFR…First level shifter, NVR, PVR…Initialization voltage, SPL1~SPL8…Signal supply lines, SWEP~SWEP1280…Data line switches, SWR…Initialization switch, SWRN…Second initialization switch, SWRP…First initialization switch, TRG1…First drive transistor group, TRG2…Second drive transistor group, VREF…Reference voltage

Claims

1. A capacitor drive circuit that outputs first to nth capacitor drive voltages (where n is an integer of 2 or more) corresponding to grayscale data to first to nth capacitor drive nodes, and a capacitor circuit having first to nth capacitors arranged between the first to nth capacitor drive nodes, wherein the first drive circuit supplies a voltage corresponding to the grayscale data to the signal supply line of the electro-optic panel by supplying a charge corresponding to the grayscale data to the signal supply line of the electro-optic panel through charge redistribution using the first to nth capacitors, A second drive circuit includes an operational amplifier composed of transistors having a lower breakdown voltage than the breakdown voltage of the transistors constituting the first drive circuit; a D / A conversion circuit electrically connected to the non-inverting input node of the operational amplifier and supplying a D / A conversion voltage based on the grayscale data; an output capacitor positioned between the output node of the operational amplifier and the signal supply line; a first feedback capacitor positioned between the inverting input node of the operational amplifier and the signal supply line; and a second feedback capacitor having one end electrically connected to the inverting input node of the operational amplifier and the other end electrically connected to a predetermined potential node, and is electrically connected to the signal supply line and corrects the voltage corresponding to the grayscale data to a target voltage by feedback control using the operational amplifier. A driver characterized by including [this].

2. In the driver described in claim 1, The capacitance of the second feedback capacitor is A driver characterized by having a capacitance greater than that of the first feedback capacitor.

3. In the driver described in claim 1, A driver characterized in that the source-drain distance of the transistors constituting the first drive circuit is longer than the source-drain distance of the transistors constituting the second drive circuit, or the thickness of the gate insulating film of the transistors constituting the first drive circuit is thicker than the thickness of the gate insulating film of the transistors constituting the second drive circuit.

4. In a driver according to any one of claims 1 to 3, A driver characterized by including an initialization switch that turns on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier.

5. In a driver according to any one of claims 1 to 3, Includes a control circuit for controlling the first drive circuit, The first drive circuit is, A first group of drive transistors is arranged between the node to which the high-potential power supply voltage is supplied and the signal supply line, A second group of drive transistors is arranged between the node to which the low-potential power supply voltage is supplied and the signal supply line, Includes, The aforementioned control circuit is A driver characterized by controlling each transistor in the first drive transistor group or each transistor in the second drive transistor group to be turned on or off based on the aforementioned grayscale data.

6. In a driver according to any one of claims 1 to 3, A driver characterized by including a voltage shift circuit that is electrically connected to the inverting input node of the operational amplifier and shifts the voltage of the inverting input node.

7. In the driver described in claim 6, The aforementioned voltage shift circuit is A driver characterized by setting different initialization voltages for the initialization period of the positive polarity drive period and the initialization period of the negative polarity drive period at the inverting input node of the operational amplifier, based on a polarity inversion signal.

8. In the driver described in claim 7, The aforementioned voltage shift circuit is An initialization switch that is turned on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier, A shift capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier, During the initialization period, a voltage output circuit outputs a voltage based on the polarity reversal signal to the other end of the shift capacitor, A driver characterized by including [this].

9. In the driver described in claim 6, The aforementioned voltage shift circuit is During the initialization period of the positive polarity drive period, a first initialization switch supplies a positive polarity initialization voltage to the inverting input node of the operational amplifier, During the initialization period of the negative polarity drive period, a second initialization switch supplies a negative polarity initialization voltage to the inverting input node of the operational amplifier, A driver characterized by including [this].

10. In the driver described in claim 6, The aforementioned voltage shift circuit is A driver characterized by shifting the voltage of the inverting input node of the operational amplifier based on a polarity inversion signal and the upper bits of the grayscale data.

11. In the driver described in claim 10, The aforementioned voltage shift circuit is An initialization switch that is turned on during the initialization period and supplies a reference voltage to the inverting input node of the operational amplifier, A first shift capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier, During the initialization period, a first voltage output circuit outputs a voltage based on the polarity reversal signal to the other end of the first shift capacitor, A second shift capacitor, one end of which is electrically connected to the inverting input node of the operational amplifier, A second voltage output circuit that outputs a voltage based on the upper bits of the grayscale data to the other end of the second shift capacitor, A driver characterized by including [this].

12. A driver as described in any one of claims 1 to 3, The aforementioned electro-optical panel, An electro-optical apparatus characterized by including [a certain component].

13. An electronic device comprising a driver as described in any one of claims 1 to 3.

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