Semiconductor equipment

Abstract

To provide a semiconductor device that can improve reliability and reduce insulation defects when a temperature change occurs.SOLUTION: A semiconductor device includes an insulated circuit board 1, semiconductor chips 3a, 3b, a printed circuit board 6, interposers 5a, 5b, and a sealing member 9, and each of the interposers 5a and 5b includes a plurality of post electrodes 51a to 51c, 51j whose ends are bonded to the semiconductor chips 3a, 3b via solder layers 8a, 8b, an insulating layer 53a having first through holes 56a, 56b that are provided opposite to and spaced apart from the semiconductor chips 3a, 3b and filled with parts of the solder layers 8a, 8b, and conductive layers 54a, 54b provided opposite to the printed circuit board 6 and connected to the other ends of the plurality of post electrodes 51a to 51c, 51j via the insulating layer 53a.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device (semiconductor module) incorporating a power semiconductor chip.

Background Art

[0002] Power semiconductor chips (hereinafter simply referred to as "semiconductor chips") are used, for example, as switching elements for power conversion.

[0003] Patent Document 1 discloses a semiconductor device including a semiconductor chip on an insulating circuit board, a printed circuit board disposed above the semiconductor chip, and an interposer disposed between the semiconductor chip and the printed circuit board, the interposer including an insulating layer, a conductor layer disposed on the upper surface of the insulating layer, and post electrodes penetrating the insulating layer and connected to the lower surface of the conductor layer.

[0004] Patent Document 2 discloses a semiconductor device including a semiconductor chip on a laminated substrate, a printed circuit board disposed above the semiconductor chip, and an interposer disposed between the semiconductor chip and the printed circuit board, the interposer including an insulating layer, emitter post electrodes and gate post electrodes provided on a surface of the insulating layer facing the semiconductor chip side, and an emitter copper pattern as a main electrode circuit layer and a gate copper pattern as a control electrode circuit layer provided on a surface of the insulating layer opposite to the semiconductor chip side.

[0005] Patent Document 3 discloses a step of soldering and joining a signal terminal and a connection terminal that penetrate a terminal through-hole in a state where a perforated insulating member is separated from a control circuit board during manufacture of a power conversion device. In this step, for example, when soldering is performed at an opening end on the opposite side of a through-hole, the solder moves through the through-hole to the opening end on the main circuit portion side due to capillary action and swells.

[0006] Patent Document 4 discloses a semiconductor device in which at least one slit may be formed in the solder contact portion of the outer lead, or at least one through hole may be formed in the solder contact portion of the outer lead, and in particular, by forming the surface area increase region with a through hole, solder is supplied to the through hole by capillary action, allowing more solder to be supplied to the outer lead, thereby improving the solder wettability.

[0007] Patent Document 5 discloses a semiconductor device in which, upon heating, the solder paste melts and is drawn into the small holes formed in the electrode terminal portion by capillary action, thereby joining the electrode terminal portion to the electrode pad. The copper foil thickness of the electrode terminal portion is approximately 35 μm. However, if there are no small holes, the molten solder will only adhere to the lower surface of the electrode terminal portion, which may result in poor bonding in some cases. By providing small holes, the solder is drawn into the openings and adheres to both the upper and lower surfaces of the electrode terminal portion, resulting in good and strong bonding between the electrode terminal portion and the electrode pad.

[0008] Patent document 6 discloses an interposer comprising an insulating plate-shaped member with an opening that conforms to the outer shape of an electronic component, and a pair of electrodes formed on one surface of the plate-shaped member, with the opening in between.

[0009] Patent Document 7 discloses a semiconductor device comprising: a laminated substrate having an insulating plate and a circuit board; a semiconductor chip having a main electrode and a control electrode on its front surface and fixed to the circuit board on its back surface; a first wiring board including a first conductive member and positioned opposite the main electrode, with the main electrode electrically connected to the first conductive member; a second wiring board including a second conductive member and positioned opposite the control electrode, having an opening; and a conductive post having one end electrically and mechanically connected to the control electrode and the other end electrically and mechanically connected to the second conductive member, wherein the first conductive member is thicker than the second conductive member, and the first wiring board is positioned inside the opening. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2022-22521 [Patent Document 2] Japanese Patent Publication No. 2021-82721 [Patent Document 3] Japanese Patent Publication No. 2009-266986 [Patent Document 4] Japanese Patent Publication No. 2000-228476 [Patent Document 5] Japanese Patent Application Publication No. 11-220070 [Patent Document 6] Japanese Patent Publication No. 2020-155512 [Patent Document 7] Japanese Patent Publication No. 2017-92185 [Overview of the Initiative] [Problems that the invention aims to solve]

[0011] In the semiconductor devices described in Patent Documents 1 and 2, when a semiconductor chip and an interposer are joined via solder, the solder creeps up along the post electrode of the interposer and further spreads to wet the surface of the semiconductor chip. As the solder creeps up, the gap between the insulating layer of the interposer and the solder narrows, preventing the sealing material from fitting into the gap. Also, as the solder spreads, the surface area of ​​the solder increases, increasing the contact area between the solder and the sealing material. Generally, the resin used as the sealing material and the solder have poor adhesion, so when a temperature change occurs in the semiconductor device, the restraining force at the interface between the sealing material and the solder weakens, making it easier for stress to be directly applied to each joint, which can easily lead to delamination and cracking. Furthermore, if the solder spreads and reaches the edges of the semiconductor chip, it may cause insulation failure.

[0012] In view of the above issues, the present invention aims to provide a semiconductor device that can improve reliability and reduce insulation failures when temperature changes occur. [Means for solving the problem]

[0013] One aspect of the present invention is a semiconductor device comprising (a) an insulating circuit board, (b) a semiconductor chip disposed on one main surface side of the insulating circuit board, (c) a printed circuit board provided opposite to one main surface of the insulating circuit board, (d) an interposer provided between the semiconductor chip and the printed circuit board, and (e) a sealing member for sealing the semiconductor chip, the interposer and the printed circuit board, wherein the interposer comprises a plurality of post electrodes, one end of which is joined to the semiconductor chip via a solder layer, an insulating layer provided opposite to the semiconductor chip and spaced apart from the semiconductor chip, having a first through-hole filled with a portion of the solder layer, and a conductor layer provided opposite to the printed circuit board and connected to the other ends of the plurality of post electrodes via the insulating layer.

[0014] Another aspect of the present invention is a semiconductor device comprising (a) an insulating circuit board, (b) a semiconductor chip disposed on one main surface side of the insulating circuit board, (c) a plurality of post electrodes one end of which is joined to the semiconductor chip via a solder layer, (d) a printed circuit board provided facing one main surface of the insulating circuit board, and (e) a sealing member for sealing the semiconductor chip and the printed circuit board, wherein the printed circuit board comprises an insulating layer having a first through hole filled with a portion of a solder layer, which is provided facing the semiconductor chip and spaced apart from the semiconductor chip, and a conductive layer connected to the other ends of the plurality of post electrodes via the insulating layer. [Effects of the Invention]

[0015] According to the present invention, it is possible to provide a semiconductor device that can improve reliability and reduce insulation failures when temperature changes occur. [Brief explanation of the drawing]

[0016] [Figure 1] This is a side view of a semiconductor device according to the first embodiment. [Figure 2] This is a plan view of the interposer of the semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view from direction AA in Figure 2. [Figure 4]It is a cross-sectional view seen from the B-B direction of FIG. 2. [Figure 5] It is a side view of a semiconductor device according to a comparative example. [Figure 6] It is a side view for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 7] It is a plan view of an interposer of a semiconductor device according to the second embodiment. [Figure 8] It is a plan view of an interposer of a semiconductor device according to the third embodiment. [Figure 9] It is a cross-sectional view seen from the A-A direction of FIG. 8. [Figure 10] It is a plan view of an interposer of a semiconductor device according to the fourth embodiment. [Figure 11] It is a side view of a semiconductor device according to the fifth embodiment.

Modes for Carrying Out the Invention

[0017] Hereinafter, the first to fifth embodiments will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationship and ratio are different even between the drawings. Further, the first to fifth embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the constituent parts as the following.

[0018] Also, the definitions of the directions such as up and down in the following description are merely definitions for convenience of explanation and do not limit the technical idea of the present invention. For example, it is needless to say that if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse.

[0019] (First Embodiment) As an example of a semiconductor device according to the first embodiment, a power semiconductor module called a "1-in-1" module, which has the function of one semiconductor element, is shown in Figure 1. The semiconductor device according to the first embodiment comprises an insulating circuit board 1, semiconductor chips 3a and 3b arranged on one main surface (upper surface) of the insulating circuit board 1, a printed circuit board 6 facing the upper surface of the insulating circuit board 1 and arranged above the semiconductor chips 3a and 3b, and interposers 5a and 5b that provide electrical connectivity between the semiconductor chips 3a and 3b and the printed circuit board 6. The upper and side surfaces of the insulating circuit board 1, the semiconductor chips 3a and 3b, the interposers 5a and 5b, and the printed circuit board 6 are sealed with a sealing member 9.

[0020] The insulating circuit board 1 comprises an insulating substrate 11, conductive layers (upper conductive layers) 12a, 12b arranged on the upper side of the insulating substrate 11, and conductive layers (lower conductive layers) 13a, 13b arranged on the lower side of the insulating substrate 11. The insulating circuit board 1 may be, for example, a direct copper bond (DCB) substrate or an activated dynamite (AMD) substrate. The insulating substrate 11 is made of a ceramic substrate made of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or a resin insulating substrate made of polymer material. The upper conductive layers 12a, 12b and the lower conductive layers 13a, 13b are made of conductive foil such as copper (Cu) or aluminum (Al).

[0021] The semiconductor chips 3a and 3b are mounted on the upper surface of the upper conductor layer 12a of the insulating circuit board 1 via bonding layers 2a and 2b made of solder or sintered material. As semiconductor chips 3a and 3b, for example, metal-oxide-semiconductor field-effect transistors (Si-MOSFETs) using silicon (Si) or MOSFETs using silicon carbide (SiC) (SiC-MOSFETs) can be used, but here we will illustrate the case where semiconductor chips 3a and 3b are Si-MOSFETs.

[0022] The semiconductor chips 3a and 3b have, for example, a rectangular planar pattern. The size of the semiconductor chips 3a and 3b is, for example, about 10 mm × 10 mm, but is not limited thereto. The thickness of the semiconductor chips 3a and 3b is, for example, about 100 μm, but is not limited thereto. Although not shown in Figure 1, the semiconductor chips 3a and 3b have a control electrode (gate electrode) and a first main electrode (source electrode) on their upper sides, respectively, and a second main electrode (drain electrode) on their lower sides, respectively.

[0023] Figure 1 illustrates two semiconductor chips 3a and 3b, but the number of semiconductor chips can be appropriately set according to the current capacity of the semiconductor module, etc., and is not particularly limited. For example, it may have one semiconductor chip, or it may have three or more semiconductor chips.

[0024] Interposers 5a and 5b are respectively placed on the upper surfaces of semiconductor chips 3a and 3b via solder layers 8a to 8d. Solder layers 8a to 8d are composed of lead-free solder such as tin-antimony (Sn-Sb), tin-copper (Sn-Cu), tin-copper-silver (Sn-Cu-Ag), tin-silver (Sn-Ag), tin-silver-copper (Sn-Ag-Cu), tin-silver-bismuth-copper (Sn-Ag-Bi-Cu), tin-indium-silver-bismuth (Sn-In-Ag-Bi), tin-zinc (Sn-Zn), tin-zinc-bismuth (Sn-Zn-Bi), tin-bismuth (Sn-Bi), or tin-indium (Sn-In) solder, or lead solder such as tin-lead (Sn-Pb).

[0025] Interposers 5a and 5b are positioned for each semiconductor chip 3a and 3b. By using interposers 5a and 5b to connect the semiconductor chips 3a and 3b to the printed circuit board 6, it becomes possible to connect the semiconductor chips 3a and 3b to the printed circuit board 6 even if the mounting positions of the semiconductor chips 3a and 3b are misaligned, compared to a configuration in which the semiconductor chips 3a and 3b are connected to the printed circuit board 6 via, for example, post electrodes, without using interposers 5a and 5b.

[0026] Figure 2 shows a plan view of the interposer 5a shown in Figure 1. In Figure 2, the through holes 55a to 55j provided in the insulating layer 53a hidden beneath the conductor layers 54a and 54b, and the post electrodes 51a to 51j, which are conductor members that penetrate the through holes 55a to 55j, are schematically shown by dashed lines. Figure 3 shows a cross-sectional view of the area around the interposer 5a as seen from direction AA in Figure 2, and Figure 4 shows a cross-sectional view of the area around the interposer 5a as seen from direction BB in Figure 2.

[0027] As shown in Figures 3 and 4, the semiconductor chip 3a has a source electrode 31 and a gate electrode 32 on its upper side. As shown in Figures 1 to 4, the interposer 5a comprises an insulating layer 53a positioned opposite the upper surface of the semiconductor chip 3a and spaced apart from the semiconductor chip 3a, conductive layers 54a and 54b arranged on the upper surface of the insulating layer 53a, and post electrodes 51a to 51j connected to the lower surfaces of the conductive layers 54a and 54b via through holes 55a to 55j provided in the insulating layer 53a.

[0028] For the insulating layer 53a, a resin such as polyimide can be used. For the conductive layers 54a and 54b, a metallic material such as copper (Cu) can be used. The post electrodes 51a to 51j may be rod-shaped (pin-shaped) or columnar, and specifically may be cylindrical, elliptical, triangular, or rectangular prisms or other polygonal prisms. The post electrodes 51a to 51j may also be protruding electrodes (bumps). For the post electrodes 51a to 51j, a metallic material such as copper (Cu) or gold (Au) can be used.

[0029] The length of post electrodes 51a to 51j is, for example, approximately 0.5 mm to 1.5 mm, but is not limited thereto. The diameter of post electrodes 51a to 51j is, for example, approximately 0.3 mm to 1 mm, but is not limited thereto.

[0030] As shown in Figures 1 to 3, the lower ends of the source post electrodes 51a to 51i are joined to the source electrode 31 of the semiconductor chip 3a via a solder layer 8a. The upper ends of the post electrodes 51a to 51i are connected to a conductor layer 54a. The post electrodes 51a to 51i are arranged in a 3x3 matrix. The pitch of the matrix of post electrodes 51a to 51i is, for example, about 1 mm or more and 2 mm or less, but is not limited to this. The number and arrangement of post electrodes 51a to 51i are not limited to this. On the other hand, the lower end of the gate post electrode 51j is joined to the gate electrode 32 of the semiconductor chip 3a via a solder layer 8b. The upper end of the post electrode 51j is connected to a conductor layer 54b.

[0031] As shown in Figures 1 to 4, the insulating layer 53a has through-holes 55a to 55i through which the post electrodes 51a to 51i pass, as well as through-holes 56a to 56d between the post electrodes 51a to 51i and the through-holes 55a to 55i. Figure 1 schematically shows the through-holes 56a and 56b hidden on the side surface of the insulating layer 53a. Figure 2 schematically shows the through-holes 56a to 56d hidden beneath the conductor layer 54a with dashed lines. The through-holes 56a to 56d penetrate the insulating layer 53a and expose the lower surface of the conductor layer 54a.

[0032] As shown in Figure 2, through-holes 56a are provided at equal distances from post electrodes 51a, 51b, 51d, and 51e. Through-holes 56b are provided at equal distances from post electrodes 51b, 51c, 51e, and 51f. Through-holes 56c are provided at equal distances from post electrodes 51d, 51e, 51g, and 51h. Through-holes 56d are provided at equal distances from post electrodes 51e, 51f, 51h, and 51i. Note that the placement of through-holes 56a to 56d is not limited to these positions; they may be placed between post electrodes 51a to 51i.

[0033] Figure 2 illustrates a case where the through holes 56a to 56d have a circular planar pattern similar to the through holes 55a to 55j, but the shape of the through holes 56a to 56d is not particularly limited and may differ from the shape of the through holes 55a to 55j. For example, the through holes 56a to 56d may have a triangular, rectangular, or elliptical planar pattern. Figure 2 illustrates a case where the through holes 56a to 56d are the same size as the through holes 55a to 55j, but the through holes 56a to 56d may be of a different size than the through holes 55a to 55j, for example, they may be larger than the through holes 55a to 55j, or smaller than the through holes 55a to 55j. Figure 2 illustrates four through holes 56a to 56d, but the number of through holes 56a to 56d is not limited and can be adjusted as appropriate depending on the number and density of post electrodes 51a to 51i, etc.

[0034] The through holes 56a to 56d are filled with a portion of the solder layer 8a that joins the source electrode 31 and post electrodes 51a to 51i of the semiconductor chip 3a. During the heat treatment that joins the source electrode 31 and post electrodes 51a to 51i of the semiconductor chip 3a, the solder layer 8a creeps up the post electrodes 51a to 51i, enters the through holes 56a to 56d by capillary action, and reaches the conductor layer 54a. The solder layer 8a is also provided between the post electrodes 51a to 51i.

[0035] The interposer 5b shown in Figure 1 has the same configuration as the interposer 5a. As shown in Figure 1, the interposer 5b comprises an insulating layer 53b facing the semiconductor chip 3b and spaced apart from the semiconductor chip 3b, conductive layers 54c and 54d arranged on the upper surface of the insulating layer 53b, and post electrodes 52a to 52c and 52j that penetrate the insulating layer 53b and are connected to the lower surfaces of the conductive layers 54a and 54b.

[0036] Of the post electrodes 52a-52c and 52j, the lower ends of the source post electrodes 52a-52c are joined to the source electrode (not shown) of the semiconductor chip 3b via the solder layer 8c. The upper ends of the post electrodes 52a-52c are connected to the conductor layer 54c. On the other hand, the lower end of the gate post electrode 52j is joined to the gate electrode (not shown) of the semiconductor chip 3b via the solder layer 8b. The upper end of the post electrode 52j is connected to the conductor layer 54d.

[0037] In addition to through holes (not shown) through which the post electrodes 52a to 52c pass, the insulating layer 53a is provided with through holes 57a and 57b between the post electrodes 52a to 52c. Figure 1 schematically shows the through holes 57a and 57b hidden on the side surface of the insulating layer 53b. Part of the solder layer 8c that joins the source electrode (not shown) of the semiconductor chip 3b to the post electrodes 52a to 52c fills the through holes 57a and 57b.

[0038] Above the semiconductor chips 3a and 3b shown in Figure 1, a printed circuit board 6 is positioned via interposers 5a and 5b. The printed circuit board 6 comprises an insulating layer 61, conductive layers (upper conductive layers) 62a and 62b positioned on the upper side of the insulating layer 61, and conductive layers (lower conductive layers) 63a to 63d positioned on the lower side of the insulating layer 61.

[0039] The insulating layer 61 is composed of insulating materials such as ceramics or resins, with alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4) as the main components. The insulating layer 61 may be a resin substrate made of polyimide resin or a combination of glass fibers and epoxy resin.

[0040] The upper conductor layers 62a, 62b and the lower conductor layers 63a to 63d are made of conductive foil, such as copper (Cu) or aluminum (Al). The upper conductor layers 62a, 62b and the lower conductor layers 63a to 63d may be plated with copper (Cu), nickel (Ni), tin (Sn), or the like.

[0041] The lower conductor layer 63a is joined to the conductor layer 54a of the interposer 5a via a bonding layer (not shown) such as solder or sintered material. The lower conductor layer 63b is joined to the conductor layer 54b of the interposer 5a via a bonding layer (not shown) such as solder or sintered material. The lower conductor layer 63c is joined to the conductor layer 54c of the interposer 5b via a bonding layer (not shown) such as solder or sintered material. The lower conductor layer 63d is joined to the conductor layer 54d of the interposer 5b via a bonding layer (not shown) such as solder or sintered material.

[0042] The upper conductor layer 62a is electrically connected to the lower conductor layers 63a and 63c via a conductive member (not shown) provided in a through-hole that penetrates the insulating layer 61. The upper conductor layer 62b is electrically connected to the lower conductor layers 63b and 63d via a conductive member (not shown) provided in a through-hole that penetrates the insulating layer 61.

[0043] A source-side connection terminal 7a is inserted into the printed circuit board 6 so as to penetrate the upper conductor layer 62a, the insulating layer 61, and the lower conductor layer 63a of the printed circuit board 6. The source-side connection terminal 7a is made of a metallic material such as copper (Cu). The lower end of the source-side connection terminal 7a is joined to the upper conductor layer 12b of the insulating circuit board 1 via a bonding layer (not shown) such as solder or sintered material. The upper end of the source-side connection terminal 7a protrudes from the upper surface of the sealing member 9 and is connected to an external circuit. The source-side connection terminal 7a allows current from the source electrode 31 of the semiconductor chip 3a and the source electrode (not shown) of the semiconductor chip 3b to flow to the external circuit via the interposer 5a, 5b and the printed circuit board 6.

[0044] The lower end of the gate connector 7b is joined to the upper conductor layer 62b of the printed circuit board 6 via a bonding layer (not shown) such as solder or sintered material. The gate connector 7b is made of a metallic material such as copper (Cu). The upper end of the gate connector 7b protrudes from the upper surface of the sealing member 9 and is connected to an external circuit. The gate connector 7b supplies control signals to control the on / off state of the semiconductor chips 3a and 3b to the gate electrode 32 of semiconductor chip 3a and the gate electrode (not shown) of semiconductor chip 3b via the printed circuit board 6 and interposers 5a and 5b.

[0045] The lower end of the drain-side connection terminal 7c is connected to the upper conductor layer 12a of the insulating circuit board 1 via a bonding layer (not shown) such as solder or sintered material. The drain-side connection terminal 7c is made of a metallic material such as copper (Cu). The upper end of the drain-side connection terminal 7c protrudes from the upper surface of the sealing member 9 and is connected to an external circuit. The drain-side connection terminal 7c supplies current to the drain electrodes (not shown) of the semiconductor chips 3a and 3b via the upper conductor layer 12a.

[0046] The semiconductor chips 3a, 3b, interposers 5a, 5b, and printed circuit board 6 are sealed by a sealing member 9 and electrically insulated from their surroundings. The insulating circuit board 1 is exposed from the lower surface of the sealing member 9. For the sealing member 9, a resin material such as a thermosetting resin can be used, specifically epoxy resin, maleimide resin, cyanate resin, etc.

[0047] <Comparative Example> Next, a semiconductor device relating to a comparative example will be described. As shown in Figure 5, the semiconductor device relating to the comparative example differs from the semiconductor device according to the embodiment shown in Figure 1 in that only through holes (not shown) through which post electrodes 51a~51c and 52a~52c are provided in the insulating layers 53a and 53b of the interposers 5a and 5b, and there are no through holes filled with a portion of the solder layers 8a and 8c.

[0048] In the semiconductor device of the comparative example, when joining semiconductor chips 3a, 3b and interposers 5a, 5b via solder layers 8a to 8d, the solder layers 8a, 8c creep up along the post electrodes 51a to 51c and 52a to 52c of the interposers 5a, 5b, creating gaps 81 to 84 between the insulating layers 53a, 53b of the interposers 5a, 5b and the solder layers 8a, 8c. If the gaps 81 to 84 are narrow, the sealing member 9 will not fit. In addition, the width W2 over which the solder layers 8a, 8c wet and spread across the surface of the semiconductor chips 3a, 3b increases, which increases the surface area of ​​the solder layers 8a, 8c and the contact area between the solder layers 8a, 8c and the sealing member 9.

[0049] Therefore, when using the semiconductor device according to the comparative example, when temperature changes such as heat cycles or power cycles occur, the restraining force at the interface between the sealing member 9 and the solder layers 8a and 8c weakens, making it easier for stress to be directly applied to each joint, which can easily lead to delamination or cracking. In addition, if the solder layers 8a and 8c that have spread over the surface of the semiconductor chips 3a and 3b reach the edges of the semiconductor chips 3a and 3b, insulation failure may occur.

[0050] In contrast, according to the semiconductor device of the first embodiment, as shown in Figures 1 to 4, the insulating layers 53a and 53b of the interposers 5a and 5b are provided with through-holes 56a to 56d, 57a and 57b between a plurality of post electrodes 51a to 51i and 52a to 52c, which penetrate the insulating layers 53a and 53b and expose the conductive layers 54a and 54c. As a result, when the semiconductor chips 3a and 3b and the interposers 5a and 5b are joined via solder layers 8a to 8d, the through-holes 56a to 56d, 57a and 57b pull the solder layers 8a and 8c by capillary action, so that any excess solder layer 8a and 8c travels along the post electrodes 51a to 51i and 52a to 52c and enters the through-holes 56a to 56d, 57a and 57b. As a result, it is possible to prevent gaps from forming between the solder layers 8a, 8c and the insulating layers 53a, 53b. In addition, since excess portions of the solder layers 8a, 8c tend to accumulate in the center of the post electrodes 51a~51i, 52a~52c, the width W1 (see Figure 1) over which the solder layers 8a, 8c spread on the surface of the semiconductor chips 3a, 3b can be narrowed, and the spreading of the solder layers 8a, 8c can be suppressed. Therefore, it is possible to improve the reliability and reduce insulation failures when temperature changes occur in the semiconductor device according to the first embodiment.

[0051] <Manufacturing method for semiconductor devices> Next, with reference to Figure 6, a method for manufacturing (assembly method) of a semiconductor device according to the first embodiment will be described. First, an insulating circuit board 1 is prepared, and semiconductor chips 3a and 3b are mounted on the insulating circuit board 1 via bonding layers 2a and 2b. Furthermore, solid solder layers 8a to 8d, formed into a plate shape, are mounted on the semiconductor chips 3a and 3b.

[0052] Furthermore, interposers 5a and 5b are prepared and mounted on semiconductor chips 3a and 3b via solder layers 8a to 8d. The interposer 5a is manufactured by using a mold to form through-holes 55a to 55j through which post electrodes 51a to 51j pass, and through-holes 56a to 56d into which a portion of the solder layer 8a is filled, in a film-like insulating layer 53a. Then, a conductive foil is attached to the insulating layer 53a, and the conductive foil is patterned by etching or the like to form conductive layers 54a and 54b. Alternatively, conductive layers 54a and 54b may be formed in advance by etching or the like, and then attached to the film-like insulating layer 53a. Afterward, the conductive layers 54a and 54b are plated, and the post electrodes 51a to 51j are press-fitted into the through-holes 55a to 55j in the insulating layers 53a and 53b to manufacture the interposer 5a. The method for manufacturing interposer 5b is the same as the method for manufacturing interposer 5a.

[0053] Furthermore, a printed circuit board 6 is prepared and mounted on the interposers 5a and 5b via a bonding layer (not shown) of solder or sintered material. Although not shown in Figure 6, the source-side connection terminal 7a shown in Figure 1 is inserted into the printed circuit board 6 and mounted on the insulating circuit board 1 via a bonding layer (not shown) of solder or sintered material. Also, the gate-side connection terminal 7b shown in Figure 1 is mounted on the printed circuit board 6 via a bonding layer (not shown) of solder or sintered material. Also, the drain-side connection terminal 7c shown in Figure 1 is mounted on the insulating circuit board 1 via a bonding layer (not shown) of solder or sintered material.

[0054] Next, the laminate of the insulating circuit board 1, semiconductor chips 3a, 3b, interposers 5a, 5b, and printed circuit board 6 is brought into the heating furnace. Through heat treatment in the heating furnace, the insulating circuit board 1, semiconductor chips 3a, 3b, interposers 5a, 5b, printed circuit board 6, source-side connection terminal 7a, gate-side connection terminal 7b, and drain-side connection terminal 7c are joined to each other. At this time, the solder layers 8a, 8c that join the semiconductor chips 3a, 3b to the interposers 5a, 5b melt, and the molten solder layers 8a, 8c crawl up the post electrodes 51a~51i, 52a~52c and are pulled by capillary action to the through holes 56a~56d, 57a, 57b provided in the insulating layers 53a, 53b of the interposers 5a, 5b. As a result, a portion of the solder layers 8a and 8c fills the through holes 56a to 56d, 57a, and 57b, while the solder layers 8a and 8c concentrate in the central part of the post electrodes 51a to 51i and 52a to 52c, thereby suppressing the wetting spread on the surface of the semiconductor chips 3a and 3b.

[0055] Next, the semiconductor chips 3a and 3b, the interposers 5a and 5b, and the printed circuit board 6 are sealed with a sealing member 9. In this way, the semiconductor device shown in Figure 1 is completed.

[0056] (Second Embodiment) The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that, as shown in Figure 7, the size of the through holes 56a to 56d, through which a portion of the solder layer 8a of the insulating layer 53a of the interposer 5a is filled, is larger than the size of the through holes 55a to 55i through which the post electrodes 51a to 51i pass, and the through holes 56a to 56d are in contact with the through holes 55a to 55i and the post electrodes 51a to 51i.

[0057] The through-hole 56a is in contact with the through-holes 55a, 55b, 55d, 55e and the post electrodes 51a, 51b, 51d, 51e. The through-hole 56b is in contact with the through-holes 55b, 55c, 55e, 55f and the post electrodes 51b, 51c, 51e, 51f. The through-hole 56c is in contact with the through-holes 55d, 55e, 55g, 55h and the post electrodes 51d, 51e, 51g, 51h. The through-hole 56d is in contact with the through-holes 55e, 55f, 55h, 55i and the post electrodes 51e, 51f, 51h, 51i. The interposer 5b shown in Figure 1 has the same configuration as the interposer 5a shown in Figure 7. The other configurations of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0058] According to the semiconductor device of the second embodiment, even when the through holes 56a to 56d of the insulating layer 53a of the interposer 5a are in contact with the through holes 55a to 55i and the post electrodes 51a to 51i, the through holes 56a to 56d pull the solder layer 8a due to capillary action, thereby suppressing the formation of gaps between the solder layer 8a and the insulating layer 53a, and also suppressing the wetting spread of the solder layer 8a. Therefore, when using the semiconductor device of the second embodiment, it is possible to improve reliability and reduce insulation failures when temperature changes occur.

[0059] (Third embodiment) Figure 8 is a plan view of the interposer 5a of the semiconductor device according to the third embodiment, and Figure 9 shows a cross-sectional view of the area around the interposer 5a as seen from direction AA in Figure 8. The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that, as shown in Figures 8 and 9, post electrodes 51a to 51i penetrate through holes 56a to 56i provided in the insulating layer 53a of the interposer 5a, and a portion of the solder layer 8a fills the gap between the post electrodes 51a to 51i and the through holes 56a to 56i.

[0060] In the semiconductor device according to the third embodiment, the through holes 56a to 56i have the function of penetrating the post electrodes 51a to 51i and also have the function of pulling the solder layer 8a by capillary action. The size of the through holes 56a to 56i is larger than the size of the post electrodes 51a to 51i, and the through holes 56a to 56i are spaced apart from the post electrodes 51a to 51i. However, a part of the outer surface of the post electrodes 51a to 51i may be in contact with the through holes 56a to 56i.

[0061] As shown in Figure 9, the conductive layer 54a is provided with recesses 57d to 57f corresponding to post electrodes 51d to 51f. The post electrodes 51d to 51f are press-fitted and fixed into the recesses 57d to 57f. Although not shown in the figures, the conductive layer 54a is also provided with recesses corresponding to post electrodes 51a to 51c and 51g to 51i. The interposer 5b shown in Figure 1 has the same configuration as the interposer 5a shown in Figures 8 and 9. The other configurations of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0062] According to the semiconductor device of the third embodiment, the gap between the through holes 56a to 56i and the post electrodes 51a to 51i pulls the solder layer 8a due to capillary action, thereby suppressing the formation of a gap between the solder layer 8a and the insulating layer 53a, and also suppressing the wetting spread of the solder layer 8a. Therefore, when using the semiconductor device of the third embodiment, it is possible to improve reliability and reduce insulation failures when temperature changes occur.

[0063] Furthermore, according to the semiconductor device of the third embodiment, compared to the case in which through holes through which post electrodes 51a to 51i pass and through holes in which a portion of the solder layer 8a is filled are provided separately, the area of ​​the through holes 56a to 56i in the insulating layer 53a is reduced, thereby improving the rigidity of the insulating layer 53a.

[0064] (Fourth Embodiment) The semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment in that, as shown in Figure 10, two gate post electrodes 51j and 51k penetrate the insulating layer 53b of the interposer 5a, and a through hole 56e is provided between the post electrodes 51j and 51k, with a portion of the solder layer 8b filled in it.

[0065] The insulating layer 53b has through holes 55j and 55k through which the two post electrodes 51j and 51k pass, as well as a through hole 56e between the through holes 55j and 55k for pulling the solder layer 8b. The interposer 5b shown in Figure 1 has the same configuration as the interposer 5a shown in Figure 10. The other configurations of the semiconductor device according to the fourth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0066] According to the semiconductor device of the fourth embodiment, on the source insulating layer 53a side, the through holes 56a to 56d pull the solder layer 8a by capillary action, thereby suppressing the formation of gaps between the solder layer 8a and the insulating layer 53a, and also suppressing the wetting spread of the solder layer 8a. On the other hand, on the gate insulating layer 53b side, by providing through holes 56e between the multiple post electrodes 51j and 51k, the through holes 56e pull the solder layer 8b by capillary action, thereby suppressing the formation of gaps between the solder layer 8b and the insulating layer 53b, and also suppressing the wetting spread of the solder layer 8b. Therefore, when using the semiconductor device of the fourth embodiment, it is possible to improve reliability and reduce insulation failures when temperature changes occur.

[0067] (Fifth embodiment) The semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment in that, as shown in Figure 11, it has one semiconductor chip 3a and does not have an interposer between the semiconductor chip 3a and the printed circuit board 6.

[0068] The semiconductor chip 3a and the printed circuit board 6 are electrically connected via post electrodes 51a to 51c and 51j. The printed circuit board 6 comprises an insulating layer 61, conductor layers (upper conductor layers) 62a and 62b located on the upper surface of the insulating layer 61, and conductor layers (lower conductor layers) 63a and 63b located on the lower surface of the insulating layer 61.

[0069] Of the post electrodes 51a-51c and 51j, the source post electrodes 51a-51c penetrate the insulating layer 61 and the upper conductor layer 62a and are electrically connected to the upper conductor layer 62a. On the other hand, the gate post electrode 51j penetrates the insulating layer 61, the upper conductor layer 62b and the lower conductor layer 63b and is electrically connected to the upper conductor layer 62b and the lower conductor layer 63b.

[0070] The insulating layer 61 of the printed circuit board 6 is provided with through-holes (not shown) through which post electrodes 51a~51c, 51j pass, and through-holes 64a, 64b through which a portion of the solder layer 8a is filled. The through-holes 64a, 64b are provided at equidistant distances from the through-holes (not shown) through which post electrodes 51a~51c, 51j pass. The other configurations of the semiconductor device according to the fifth embodiment are the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0071] According to the semiconductor device of the fifth embodiment, through holes 64a and 64b provided in the insulating layer 61 of the printed circuit board 6 pull the solder layer 8a by capillary action, thereby suppressing the formation of gaps between the solder layer 8a and the insulating layer 61, and also suppressing the wetting spread of the solder layer 8a. Therefore, when using the semiconductor device of the fifth embodiment, it is possible to improve reliability and reduce insulation failures when temperature changes occur.

[0072] Furthermore, through-holes 64a and 64b provided in the insulating layer 61 may be in contact with through-holes (not shown) through which post electrodes 51a to 51c pass. Alternatively, multiple post electrodes 51a to 51c may each pass through multiple through-holes 64a and 64b, and a portion of the solder layer 8a may be filled in the gaps between the multiple post electrodes 51a to 51c and the multiple through-holes 64a and 64b. In this case, multiple recesses may be provided in the upper conductor layer 62a, and the other ends of the multiple post electrodes 51a to 51c may be press-fitted into the multiple recesses.

[0073] (Other embodiments) As described above, the present invention has been described by the first to fifth embodiments, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0074] For example, as a semiconductor device according to the first to fifth embodiments, a power semiconductor module called a "1-in-1" module, which has the function of one semiconductor element, was given as an example, but the invention is not limited to this. For example, it can also be applied to a power semiconductor module called a "2-in-1" module, which has the function of two semiconductor elements.

[0075] Furthermore, the configurations disclosed in the first to fifth embodiments can be combined as appropriate, within a non-contradictory range. Thus, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are appropriate from the above description. [Explanation of symbols]

[0076] 1…Insulated circuit board 2a, 2b…bonding layer 3a, 3b… Semiconductor chips 5a, 5b... Interposer 6…Printed circuit board 7a...Source side connection terminal 7b…Gate connection terminal 7c...Drain side connection terminal 8a~8d...Solder layer 9...Sealing member 11…Insulating substrate 12a, 12b… Upper conductor layer 13a, 13b...lower conductor layer 31…Source electrode 32… Terminal gate 51a~51k...Post-electrode 52a~52c, 52j... Post-electrode 53a, 53b... Insulating layer 54a~54d...Conducting layer 55a~55j...Through holes 56a~56i…Through hole 57d~57f...recess 61…Insulating layer 62a, 62b… Upper conductor layer 63a~63d...lower conductor layer 64a, 64b… Through holes 81-84... Gap W1, W2... width

Claims

1. Insulated circuit board and A semiconductor chip disposed on one main surface side of the aforementioned insulating circuit board, A printed circuit board provided opposite to one of the main surfaces of the insulating circuit board, An interposer provided between the semiconductor chip and the printed circuit board, A sealing member that seals the semiconductor chip, the interposer, and the printed circuit board, Equipped with, The aforementioned interposer, A plurality of post electrodes, one end of which is joined to the semiconductor chip via a solder layer, An insulating layer having a first through-hole, which is provided opposite the semiconductor chip and spaced apart from the semiconductor chip, and in which a portion of the solder layer is filled; A conductive layer provided opposite the printed circuit board and connected to the other end of the plurality of post electrodes via the insulating layer, A semiconductor device characterized by comprising the following features.

2. Insulated circuit board and A semiconductor chip disposed on one main surface side of the aforementioned insulating circuit board, A plurality of post electrodes, one end of which is joined to the semiconductor chip via a solder layer, A printed circuit board provided opposite to one of the main surfaces of the insulating circuit board, A sealing member for sealing the semiconductor chip and the printed circuit board, Equipped with, The aforementioned printed circuit board An insulating layer having a first through-hole, which is provided opposite the semiconductor chip and spaced apart from the semiconductor chip, and in which a portion of the solder layer is filled; A conductive layer connected to the other end of the plurality of post electrodes via the insulating layer, A semiconductor device characterized by comprising the following features.

3. The semiconductor device according to claim 1 or 2, characterized in that the insulating layer further has a plurality of second through holes through which each of the plurality of post electrodes passes.

4. The semiconductor device according to claim 3, characterized in that the first through hole is provided at an equidistant distance from the adjacent second through hole.

5. The semiconductor device according to claim 3, characterized in that the first through hole is in contact with the second through hole.

6. Each of the multiple post electrodes penetrates the multiple first through holes, A portion of the solder layer is filled in the gaps between the plurality of post electrodes and the plurality of first through holes. The semiconductor device according to claim 1 or 2.

7. The semiconductor device according to claim 6, characterized in that a plurality of recesses are provided in the conductive layer, and the other ends of the plurality of post electrodes are press-fitted into the plurality of recesses, respectively.

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