Insulated-gate bipolar transistor

Abstract

To obtain IE effect and to suppress latch-up in an IGBT.SOLUTION: An insulated gate type bipolar transistor includes: a first active region (31); a second active region (32); and a non-active region (34) that is arranged between the first active region and the second active region and in which a plurality of dummy trenches are arranged. In a hole accumulation region (36) that is a region between a first boundary gate trench (14gx1) and a second boundary gate trench (14gx2), an inter-trench region is arranged so as to satisfy the following conditions: a plurality of non-contact inter-trench regions are arranged in an inactive region; at least one contact trench region is arranged in the non-active region; and the non-contact inter-trench regions are not adjacent to each other in the hole accumulation region.SELECTED DRAWING: Figure 1

Claims

1. An insulated-gate bipolar transistor, A semiconductor substrate (12) has multiple trenches (14) arranged at intervals on its upper surface, The emitter electrode (24) provided on the upper surface of the semiconductor substrate, A collector electrode (26) provided on the lower surface of the semiconductor substrate, A gate insulating film (18) covers the inner surface of each trench, A trench electrode (20) is disposed within each of the trenches and is insulated from the semiconductor substrate by the gate insulating film. It has, The plurality of trenches include gate trenches (14g) and dummy trenches (14d), The trench electrode in the gate trench is a gate electrode (20g) having a potential independent of the emitter electrode. The trench electrode in the dummy trench is a dummy electrode (20d) having a potential independent of the gate electrode. The aforementioned semiconductor substrate A first active region (31) in which multiple gate trenches are arranged, A second active region (32) in which multiple gate trenches are arranged, An inactive region (34) located between the first active region and the second active region, in which a plurality of dummy trenches are located, It has, The aforementioned semiconductor substrate A p-type collector layer (40) is distributed across the first active region, the second active region, and the inactive region, and is in contact with the collector electrode. An n-type drift layer (44) is distributed across the first active region, the second active region, and the inactive region, and is located above the collector layer, A p-type base layer (46) is distributed across the first active region, the second active region, and the inactive region, is located above the drift layer, and is positioned within the inter-trench region (16) located between each of the trenches, Multiple n-type emitter layers (48) are arranged within the first active region and within a plurality of inter-trench regions within the second active region, in contact with the gate insulating film, in contact with the emitter electrode, and separated from the drift layer by the base layer. It has, In the first active region and the inter-trench region within the second active region, the base layer is in contact with the emitter electrode. Within the hole accumulation region (36), which is the region between the first boundary gate trench (14gx1) in the first active region that is closest to the inactive region and the second boundary gate trench (14gx2) in the second active region that is closest to the inactive region, the following conditions apply, namely, - Multiple non-contact trench regions are arranged within the inactive region, which are trench regions in which the base layer is insulated from the emitter electrode. - At least one contact trench region is provided within the inactive region, which is the trench region in which the base layer is in contact with the emitter electrode. - Within the hole accumulation region, the non-contact trench regions are not adjacent to each other. The trench region is arranged such that it satisfies the following condition: Insulated-gate bipolar transistor.

2. When the dummy trench adjacent to the first boundary gate trench is designated as the first boundary dummy trench (14dx1), the inter-trench region between the first boundary gate trench and the first boundary dummy trench is the inter-contact trench region, and the inter-trench region between the first boundary dummy trench and the adjacent dummy trench is the inter-contact trench region. When the dummy trench adjacent to the second boundary gate trench is designated as the second boundary dummy trench (14dx2), the inter-trench region between the second boundary gate trench and the second boundary dummy trench is the inter-contact trench region, and the inter-trench region between the second boundary dummy trench and the adjacent dummy trench is the inter-contact trench region. The insulated gate bipolar transistor according to claim 1.

3. The aforementioned semiconductor substrate An n-type barrier layer (50) is distributed across the first active region, the second active region, and the inactive region, is located below the base layer, and is positioned within each of the trench-interval regions. A p-type lower base layer (46b) is distributed across the first active region, the second active region, and the inactive region, is positioned between the barrier layer and the drift layer, and is located within each of the trench-interval regions. Having, An insulated-gate bipolar transistor according to claim 1 or 2.

4. The insulated gate type bipolar transistor according to claim 3, wherein the semiconductor substrate has a plurality of n-type pillar layers (52) that extend from a position in contact with the emitter electrode to the barrier layer and are in Schottky contact with the emitter electrode.

5. The insulated gate type bipolar transistor according to claim 1 or 2, wherein the semiconductor substrate has an n-type cathode layer (60) adjacent to the collector layer and in contact with the collector electrode.

6. The collector layer is continuously distributed from the first active region through the hole accumulation region to the second active region, The inter-trench region is arranged within the hole accumulation region, which is within the range in which the collector layer is continuously distributed from the first active region through the hole accumulation region to the second active region, such that the above conditions are met. An insulated gate bipolar transistor according to claim 1 or 2.

7. The insulated gate bipolar transistor according to claim 6, wherein the collector layer is located directly below the region in which the base layer is in contact with the emitter electrode within the contact trench region.

Images