Image sensor and imaging device

Abstract

Provided is an imaging element comprising: a storage unit which stores a pixel signal converted to a digital signal; a control line through which a control signal for reading the pixel signal stored in the storage unit is output; an output line through which the pixel signal read from the storage unit is output; and an amplification unit which amplifies the pixel signal output through the output line. The output line may include a pair of positive-negative output lines connected to the amplification unit. The output line is connected to one of a pair of positive-negative inputs of the amplification unit, and the other input of the amplification unit may also be connected to a reference potential.

Description

Technical Field

[0001] The present invention relates to an imaging device and an imaging apparatus.

Background Art

[0002] An imaging device capable of processing signals output from a plurality of pixels in parallel is known (for example, Patent Document 1). Conventionally, an increase in power consumption due to parallel processing of signals from pixels has been a problem. [Prior Art Document] [Patent Document] [Patent Document 1] International Publication WO2013 / 129202 General Disclosure

[0003] In a first embodiment of the present invention, an image sensor comprises a storage unit for storing pixel signals converted into digital signals, a control line for outputting a control signal for reading out the pixel signals stored in the storage unit, an output line for outputting the pixel signals read out from the storage unit, and an amplification unit for amplifying the pixel signals output to the output line. The output line may have a positive and negative pair of output lines connected to the amplification unit. The amplification unit may be a differential amplifier. The output line may be connected to one of the positive and negative inputs of the amplification unit, and the other input of the amplification unit may be connected to a reference potential. A first partial output line may be further provided for outputting pixel signals read out from a plurality of storage units corresponding to a plurality of pixels. A first buffer may be further provided, with an input connected to the first partial output line and an output connected to the output line. A second partial output line may be further provided for outputting pixel signals read out from other plurality of storage units corresponding to other plurality of pixels. A second buffer may be further provided, with an input connected to the second partial output line and an output connected to the output line. A first partial output line may be further provided for outputting pixel signals read out from a plurality of storage units corresponding to a plurality of pixels. A first selection unit may be further provided, with an input connected to the first partial output line and an output connected to the output line. A second partial output line may be further provided, which outputs pixel signals read from other memory units corresponding to other pixels. A second selection unit may be further provided, with an input connected to the second partial output line and an output connected to the output line. The voltage across the output line may be smaller than the voltage across the first and second partial output lines. The control line is connected in common to multiple memory units corresponding to multiple pixels, and a repeater may be further provided, arranged between the multiple memory units on the control line to transfer control signals.

[0004] In a second embodiment of the present invention, there is an imaging device having the image sensor described above.

[0005] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0006] [Figure 1]This diagram shows an overview of the image sensor 400 according to this embodiment. [Figure 2] An example of a planar layout of the first substrate 100 is shown. [Figure 3] An example of a planar layout of the second substrate 200 is shown. [Figure 4] An example of the circuit configuration of pixel 112 and pixel circuit 212 is shown. [Figure 5] This is a schematic diagram illustrating the circuit for reading from the pixel memory 220. [Figure 6] This is a schematic diagram illustrating the circuit for reading from memory cell 221 in more detail. [Figure 7] Figure 6 shows an example of a timing chart for reading signals stored in memory cells 221 and 222. [Figure 8] This is a schematic diagram illustrating in detail the other circuits involved in reading from memory cell 221. [Figure 9] This is a schematic diagram illustrating in detail other circuits for reading from memory cell 221. [Figure 10] This is a schematic diagram illustrating in detail other circuits for reading from memory cell 221. [Figure 11] Figure 10 shows an example of a timing chart for reading signals stored in memory cell 221. [Figure 12] This is a schematic diagram illustrating other circuits for reading from the pixel memory 220. [Figure 13] This is a block diagram showing an example configuration of the imaging device 500 according to the embodiment. [Modes for carrying out the invention]

[0007] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] In this specification, the X and Y axes are orthogonal to each other, and the Z axis is orthogonal to the XY plane. The XYZ axes form a right-handed system. The direction parallel to the Z axis may be referred to as the stacking direction of the image sensor 400. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z axis direction. In this specification, the arrangement in the X axis direction is described as a "row," and the arrangement in the Y axis direction is described as a "column," but the matrix direction is not limited to these. Also, the Z axis direction is the optical axis direction from which light from the subject is incident.

[0009] Figure 1 is a diagram illustrating the overview of the image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 comprises a first substrate 100 and a second substrate 200. As shown in Figure 1, the first substrate 100 is stacked on the second substrate 200.

[0010] The first substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light. The first substrate 100 is sometimes referred to as a pixel chip.

[0011] The second substrate 200 has a processing circuit section 210 and a peripheral circuit section 230. The second substrate 200 is sometimes referred to as a signal processing chip.

[0012] The processing circuit 210 receives the pixel signal output from the first substrate 100. The processing circuit 210 processes the input pixel signal. For example, the processing circuit 210 performs a process to convert an analog signal into a digital signal. Specifically, the processing circuit 210 performs a process to convert the input pixel signal into a digital signal. The processing circuit 210 may also perform other signal processing.

[0013] The processing circuit unit 210 in this example is disposed on the second substrate 200 at a position facing the pixel unit 110. That is, the processing circuit unit 210 is arranged so as to at least partially overlap the pixel unit 110 in the optical axis direction. The processing circuit unit 210 may output a control signal for controlling the driving of the pixel unit 110 to the pixel unit 110.

[0014] The peripheral circuit unit 230 controls the driving of the processing circuit unit 210. The peripheral circuit unit 230 is disposed on the second substrate 200 around the processing circuit unit 210. Also, the peripheral circuit unit 230 may be electrically connected to the first substrate 100 and control the driving of the pixel unit 110.

[0015] In addition to the first substrate 100 and the second substrate 200, the imaging device 400 may have a third substrate laminated on the second substrate 200. For example, the third substrate is a memory chip, and performs image processing according to the signal output by the second substrate 200. Also, the structure of the imaging device 400 may be a back-illuminated type or a front-illuminated type. Hereinafter, an example of the back-illuminated type will be described.

[0016] FIG. 2 shows an example of the planar layout of the first substrate 100. The pixel unit 110 is disposed near the center in the plane of the first substrate 100.

[0017] The pixel unit 110 has a plurality of pixels 112 arranged side by side along the row direction and the column direction. The pixel unit 110 in this example has M×N pixels 112 (M and N are natural numbers). In this example, the case where M is different from N is illustrated, but M and N may be equal.

[0018] FIG. 3 shows an example of the planar layout of the second substrate 200. The processing circuit unit 210 is disposed near the center in the plane of the second substrate 200.

[0019] The processing circuit unit 210 has a plurality of pixel circuits 212 arranged side by side along the row direction and the column direction. The processing circuit unit 210 in this example has M×N pixel circuits 212.

[0020] In this embodiment, the pixel circuit 212 and the pixel 112 are arranged at overlapping positions when viewed from the optical axis direction. In this case, the areas of the pixel circuit 212 and the pixel 112 may be substantially the same including the margin between adjacent blocks.

[0021] The pixel circuit 212 controls the driving of the electrically connected pixel 112. The pixel circuit 212 and the pixel 112 being electrically connected may sometimes be referred to as being corresponding.

[0022] In this embodiment, the pixel circuit 212 and the pixel 112 arranged at overlapping positions are connected. However, instead of the pixel circuit 212 and the pixel 112 arranged at overlapping positions being connected, the pixel circuit 212 and the pixel 112 arranged at non-overlapping positions may be connected.

[0023] Around the processing circuit unit 210, a pixel control circuit 250, a readout control circuit 260, and an image processing / output unit 280, which are an example of the peripheral circuit unit 230, are arranged. The pixel control circuit 250 controls the pixel 112 and the pixel circuit 212. The pixel control circuit 250 supplies, for example, a control signal for the pixel circuit 212 to AD-convert a signal from the pixel 112. Also, the pixel control circuit 250 controls, for example, the exposure time of the pixel 112. The readout control circuit 260 controls the readout for outputting the pixel signal stored in the pixel circuit 212 to the image processing / output unit 280.

[0024] FIG. 4 shows an example of the circuit configuration of the pixel 112 and the pixel circuit 212. The pixel 112 includes a photoelectric conversion unit 130, a reset unit 132, an accumulation unit 134, and a transfer unit 136.

[0025] The photoelectric conversion unit 130 has a photoelectric conversion function of converting light into charges and an accumulation function of accumulating the photoelectrically converted charges. The photoelectric conversion unit 130 is, for example, a photodiode.

[0026] The storage unit 134 converts the charge generated in the photoelectric conversion unit 130 into a voltage corresponding to its amount. The storage unit 134 is an example of floating diffusion (FD).

[0027] The reset unit 132 discharges the charge from the storage unit 134 to the power supply wiring supplied with a predetermined power supply voltage VDD, based on the control signal φRST. The gate terminal of the reset unit 132 is connected to the pixel control circuit 250.

[0028] The transfer unit 136 transfers the charge stored in the photoelectric conversion unit 130 to the storage unit 134 based on the control signal φTX. The transfer unit 136 also resets the charge stored in the photoelectric conversion unit 130 based on the control signal φTX. For example, the transfer unit 136 resets the amount of charge stored in the photoelectric conversion unit 130 to 0 by simultaneously supplying the control signals φTX and φRST. The transfer unit 136 is an example of a transfer gate that transfers charge from the photoelectric conversion unit 130. In other words, the transfer unit 136 acts as the gate, the photoelectric conversion unit 130 as the source, and the storage unit 134 as the drain, and these together constitute a so-called transfer transistor.

[0029] The pixel circuit 212 comprises a comparator 216, a control circuit 214, and a pixel memory 220. The comparator 216 compares the voltage of the storage unit 134 with a reference voltage RAMP supplied from the pixel control circuit 250 and outputs the comparison result to the control circuit 214. The comparator 216 is configured, for example, as a differential pair. Alternatively, the comparator 216 may have a source follower circuit between it and the storage unit 134, for example. The control circuit 214 controls the pixel memory 220 based on the signal from the comparator 216 and the signal from φCTL.

[0030] The pixel memory 220 stores the pixel signals that have been converted into digital signals. For example, the pixel memory 220 receives a count signal supplied from the pixel control circuit 250, and stores the value of the count signal when the control signal output from the control circuit 214 is inverted. The pixel memory 220 further outputs the stored pixel signals based on the selection signal φSEL. An example of the pixel memory 220 is SRAM. The pixel memory 220 will be described in more detail later.

[0031] An example of the operation of pixel 112 and pixel circuit 212 for one frame will be described. First, at the start of accumulation for one frame, the pixel control circuit 250 resets the charge accumulated in the photoelectric conversion unit 130 by simultaneously supplying control signals φTX and φRST. Next, during the readout period at the end of one frame, the pixel control circuit 250 resets the voltage of the accumulation unit 134 to a predetermined voltage by supplying the control signal φRST. Subsequently, the pixel control circuit 250 stores a value corresponding to the reset voltage of the accumulation unit 134 in the pixel memory 220 by controlling the control signal φCTL, the reference voltage RAMP, and the count signal supplied to the pixel memory 220 (DARK conversion). Then, the readout control circuit 260 reads the DARK conversion result data stored in the pixel memory 220 to the image processing / output unit 280 by controlling the selection signal φSEL. The data readout from the pixel memory 220 will be described further later. Furthermore, the pixel control circuit 250 transfers the charge stored in the photoelectric conversion unit 130 to the storage unit 134 by supplying the control signal φTX. Subsequently, the pixel control circuit 250 controls the control signal φCTL, the reference voltage RAMP, and the count signal supplied to the pixel memory 220 to store a value corresponding to the voltage of the storage unit 134 after the charge transfer in the pixel memory 220 (SIG conversion). Finally, the readout control circuit 260 reads the SIG conversion result data stored in the pixel memory 220 to the image processing and output unit 280 by controlling the selection signal φSEL.

[0032] In this embodiment, one pixel circuit 212 is provided for each pixel 112, and all pixels 112 and pixel circuits 212 are controlled simultaneously. Therefore, a so-called global shutter operation is possible, in which multiple pixels 112 included in the pixel section 110 are exposed at the same time. It is also possible to expose each pixel 112 at different times.

[0033] Figure 5 is a schematic diagram illustrating the circuit for reading data from the pixel memory 220 to the image processing and output unit 280. Components that are not explained are omitted from the diagram.

[0034] M × N pixel memories 220 are arranged corresponding to M × N pixels 121. These pixel memories 220 are commonly connected to the row selection line 264 of the row selection circuit 262 of the read control circuit 260 for each row. The row selection line 264 outputs a row selection signal φSEL, which is an example of a control signal for reading pixel signals stored in the pixel memory 220. The row selection line 264 is sometimes also called a word selection line.

[0035] On the other hand, these pixel memories 220 are connected in common to output lines 266 to the image processing and output unit 280, row by row. Pixel signals read from the pixel memories 220 are output to the output lines 266. The output lines 266 are sometimes also called bit lines.

[0036] Here, the pixel memory 220 stores a digital signal with a number of bits corresponding to the gradation of the image signal, and therefore each pixel 112 has a memory cell corresponding to that number of bits. For example, if 8 bits are used to represent the pixel signal of one pixel with 256 monochrome gradations, then 8 memory cells will be used. Therefore, even for the output from the pixel memory 220, if time division is not used, at least the number of output lines 266 corresponding to the number of bits will be used for one row of pixel memory 220. In Figures 5 and later, diagonal lines are drawn on the wiring, as in output line 266 in Figure 5, to indicate that multiple wirings are represented by a single line.

[0037] In the readout configuration shown in Figure 5, readout operations are performed from many pixel memories 220 at once, which increases the current during readout. Therefore, in this embodiment, an SRAM-based sense amplifier is used to suppress the current during readout.

[0038] Figure 6 is a schematic diagram illustrating the circuit for reading from memory cell 221 in more detail. Components that are not explained are omitted from the diagram.

[0039] As described above, the pixel memory 220 corresponding to one pixel 112 has a number of memory cells corresponding to the number of bits, but Figure 6 shows a memory cell corresponding to one of those bits. For simplification, memory cell 221 in row n and memory cell 222 in row (n+1) of a column in the M row N column diagram are shown. Hereafter, unless otherwise specified, the multiple memory cells shown store the same bit in the pixel memory 220 corresponding to different pixels 112.

[0040] Memory cell 221 includes a flip-flop 224 that holds the value "0" or "1", and transfer gates 227 and 228 controlled by the row selection signal φSEL(n) of the row selection line 264. One end of transfer gate 227 is connected to output line 267, and one end of transfer gate 228 is connected to output line 268. Memory cell 222 has the same configuration, so its description is omitted.

[0041] The image processing and output unit 280 includes a sense amplifier 282 to which output lines 267 and 268 are input, an image processing unit 284 that processes digital pixel signals based on the output from the sense amplifier 282, and an output unit 286 that outputs the digital pixel signals processed by the image processing unit 284 to the outside of the chip. At least one sense amplifier 282 is provided for each row and each bit. Output line 267 is connected to the positive input of the sense amplifier 282, and output line 268 is connected to the negative input. The image processing unit 284 performs CDS (correlated double sampling) by subtracting the result of DARK conversion from the result of SIG conversion for each pixel. The input portion of the image processing unit 284 may be configured with a CMOS circuit.

[0042] In the configuration shown in Figure 6, a pair of output lines 267 and 268 are provided for each column and each bit. Therefore, 2k output lines are provided for k bits. Each output line 267 and 268 is selectively supplied with voltage VDD via transistor 308.

[0043] Figure 7 is an example of a timing chart for reading signals stored in memory cells 221 and 222 in Figure 6. For illustrative purposes, it is assumed that the value "1" is stored in memory cell 221 and the value "0" is stored in memory cell 222. Note that VDD is the higher reference potential, for example, the power supply potential, and VSS is the lower reference potential, for example, ground.

[0044] First, from time t0 to t1, a precharge signal φPRG is supplied, and a voltage VDD is applied to output lines 267 and 268, causing precharging. As a result, the output of the sense amplifier 282 is in an intermediate state (i.e., it is undetermined whether it is "H" or "L").

[0045] Subsequently, from time t2 to t4, a row selection signal φSEL(n) of High is transmitted from the row selection circuit 262 onto the row selection line 264 for a predetermined time. This turns on the transfer gates 227 and 228 of the memory cell 221 in the nth row for a predetermined time. In this case, the potential of the output line 267 corresponding to the value "1" remains unchanged, but the potential of the output line 268 corresponding to the value "0" drops to an intermediate potential between VDD and VSS. The sense amplifier 282 outputs "H" at time t3 when the difference between them becomes greater than a preset value. As a result, the value "1" stored in the memory cell 221 in the nth row of that column is read out.

[0046] Next, from time t5 to t6, the voltage VDD is applied again to output lines 267 and 268, causing them to precharge. Then, from time t7 to t9, a row selection signal φSEL(n+1) of high is transmitted from row selection circuit 262 onto row selection line 265 for a predetermined time. As a result, for the memory cell 221 of the (n+1)th row, the potential of output line 268 corresponding to the value "0" remains unchanged, but the potential of output line 267 corresponding to the value "1" drops to an intermediate potential between VDD and VSS. The sense amplifier 282 outputs "L" at time t8 when it becomes greater than the above set value. As a result, the value "0" stored in the memory cell 222 of the (n+1)th row in that column is read out.

[0047] Here, the preset value for the sense amplifier 282 to output "H" or "L" is smaller than the potential difference between VDD and VSS, for example, less than 1 / 10. In other words, the sense amplifier 282 functions as a differential amplifier. Therefore, even if the amplitude of the voltage change across output lines 267 and 268 is smaller than the potential difference between VDD and VSS, the sense amplifier 282 can detect the value stored in memory cell 221. Also, since the row selection signal φSEL goes low before the voltage across either output line 267 or 268 drops to VSS, the changing voltage amplitude across either output line 267 or 268 is smaller than the potential difference between VDD and VSS. As a result, the amount of current flowing through output lines 267 and 268 during reading can be made much smaller than the amount of current flowing when the potential of output lines 267 and 268 changes from VDD to VSS. Therefore, if the reading speed is the same, malfunctions due to voltage drops can be prevented even with more pixel memories 220. Furthermore, if the number of pixel memories 220 is the same, malfunctions due to voltage drop can be prevented even when operating at higher speeds. In addition, in the above configuration, it is not necessary to wait until either output line 267 or 268 drops to the reference potential VSS, thus improving the readout speed.

[0048] Figure 8 is a schematic diagram illustrating in detail other circuits for reading from memory cell 221. In Figure 8, components identical to those in Figures 1 to 7 are given the same reference numerals and their explanations are omitted.

[0049] In the example in Figure 8, output line 267 in Figure 6 is not provided, and output line 268 is connected to the negative input of sense amplifier 282. A predetermined voltage VTH1, which is lower than VDD and higher than VSS, is applied to the positive input of sense amplifier 282 as a reference potential.

[0050] In the above configuration, when the selection signal φSEL is set to High after precharging, the sense amplifier 282 outputs "H" if the potential of output line 268 drops, and outputs "L" if the potential remains VDD. Therefore, even in the above configuration, the pixel signal stored in memory cell 221 can be read out with a small amount of current.

[0051] Alternatively, instead of using Figure 8, output line 267 may be connected to the positive input of sense amplifier 282 without providing output line 268 in Figure 6. In that case, VTH1 should be connected to the negative input of sense amplifier 282.

[0052] Figure 9 is a schematic diagram illustrating in detail other circuits for reading from memory cell 221. In Figure 9, components identical to those in Figures 1 to 8 are given the same reference numerals and their explanations are omitted.

[0053] In Figure 9, a common output line 310 is connected to a group of memory cells 221 within a given column. As an example, in Figure 9, three adjacent rows of memory cells 211 are connected to the common output line 310. These memory cells 211 are called memory cell group n. Furthermore, in the rows below memory cell group n, three adjacent rows of memory cells 211 are connected to another common output line 320. These memory cells 211 are called memory cell group (n+1).

[0054] One end of output line 310 is connected to VDD via transistor 312, and the other end is grounded via capacitor 314. Capacitor 314 may be composed of parasitic capacitance. Output line 310 is connected to the input of buffer 316, and the output of buffer 316 is connected to output line 268. Buffer 316 is a 3-state buffer, and its enabled state, i.e., whether the output is low impedance or high impedance, is controlled by the selection signal φSEL2(n). These components—output line 310, transistor 312, capacitor 314, and buffer 316—operate with respect to the memory cell group n, and can therefore be considered local circuits.

[0055] Similarly, one end of output line 320 is connected to VDD via transistor 322, and the other end is grounded via capacitor 324. Capacitor 324 may be composed of parasitic capacitance. Output line 320 is connected to the input of buffer 326, and the output of buffer 326 is connected to output line 268. Buffer 326 is a three-state buffer, and its enabled state, i.e., whether the output is low impedance or high impedance, is controlled by the selection signal φSEL2(n+1).

[0056] When reading pixel signals from memory cell 221, a precharge signal φPRL is applied to at least the memory cell group to be read to precharge the local output line 310, and a precharge signal φPRG is applied to precharge the global output line 268. Then, a selection signal φSEL is applied to the memory cell 221 to be read, and a selection signal φSEL2 is applied to the memory cell group to be read. This allows the global output line 268 to be driven by the buffer 316 with high driving force, thereby increasing the response speed of the global output line 268. Furthermore, by shortening the time for which the selection signal φSEL2 is applied, the amplitude of the voltage change of the global output line 268 can be made smaller than the potential difference between VDD and VSS, thereby suppressing the current that flows when the global output line 268 is charged and discharged.

[0057] The number of memory cells 221 in one memory group is preferably several to several tens, and / or N / 1000 to N / 100, where N is the number of rows. Furthermore, the number of memory cells 221 in one memory group may be a power of 2 for ease of processing.

[0058] Figure 10 is a schematic diagram illustrating in detail other circuits for reading from memory cell 221. In Figure 10, components identical to those in Figures 1 to 9 are given the same reference numerals and their explanations are omitted.

[0059] In Figure 10, as in Figure 9, the memory cell group n is commonly connected to the local output line 310, and the memory cell group (n+1) is commonly connected to the output line 320. Furthermore, instead of the buffer 316 in Figure 9, transistors 317 and 318 are connected between output line 310 and output line 268. Transistor 317 is turned on by the selection signal φSEL2(n) from the row selection circuit 262. This selection signal can also be said to be a selection signal that selects the memory cell group n.

[0060] Similarly, instead of buffer 326, transistors 327 and 328 are connected between output line 320 and output line 268. Transistor 327 is turned on by the selection signal φSEL2(n+1) from row selection circuit 262.

[0061] One end of the global output line 268 is connected to a voltage VPC via transistor 309, where VPC is lower than VDD.

[0062] Furthermore, a sense amplifier 282 is connected to one end of the global output line 268. This configuration differs from that of Figure 9 in that a predetermined voltage VTH2, which is lower than VPC but higher than VSS, is applied to the positive input of the sense amplifier 282.

[0063] Figure 11 is an example of a timing chart for reading signals stored in memory cell 221 in Figure 10. For illustrative purposes, assume that the value "1" is stored in memory cell 221 of the first row (i.e., row (n,0)) of memory group n, and the value "0" is stored in memory cell 221 of the second row (i.e., row (n,1)) of memory group n.

[0064] First, at time ta, the precharge signal φPRL applies a voltage VDD to output line 310, and the precharge signal φPRG applies a voltage VPC to output line 268, precharging both. Then, at time tb, the row selection signal φSEL(n,0) turns on the transfer gate 228 of the memory cell 221 in row (n,0), and the value of the memory cell 221 in row (n,0) is output to the local output line 310. In this state, at time tc, the selection signal φSEL2(n) turns on transistor 317, and the value of the memory cell 221 in row (n,0) is output to the global output line 310. In this case, the potential of output line 268 corresponding to the value "0" has decreased, so the sense amplifier 282 outputs "H". As a result, the value "1" stored in the memory cell 221 in row (n,0) of that column is read out.

[0065] Next, at time td, voltage VDD is applied to output line 310 and voltage VPC is applied to output line 268, causing both to precharge. At time te, the row selection signal φSEL(n,1) turns on the transfer gate 228 of the memory cell 221 in row (n,1), and the value of the memory cell 221 in row (n,1) is output to the local output line 310. In this state, at time tc, the selection signal φSEL2(n) turns on transistor 317, and the value of the memory cell 221 in row (n,1) is output to the global output line 310. In this case, the potential of output line 268 corresponding to the value "0" does not drop, so the sense amplifier 282 outputs "L". As a result, the value "0" stored in the memory cell 221 in row (n,1) of that column is read out.

[0066] Here, the voltage VPC across the global output line 268 can be lower than the voltage VDD across the local output line 310. Therefore, the amount of current flowing through the global output line 268 during readout can be made very small.

[0067] Furthermore, the amplitude variation of the global output line 268 will be explained in comparison with the configuration in Figure 9. In the case of Figure 9, the voltage amplitude of the global output line 268, which changes during readout, is determined by the driving force of buffers 316 and 326 and the time for which the selection signal φSEL2 is applied. Therefore, if the driving force of buffers 316 and 326 varies, the voltage amplitude of the global output line 268 during readout will also vary. On the other hand, in the configuration of Figure 10, the voltage amplitude of the global output line 268 during readout is determined by the differential voltage between VPC and VSS, regardless of the characteristics of transistors 317, 318, 327, and 328. Therefore, even if the characteristics of transistors 317, 318, 327, and 328 vary, the variation in the voltage amplitude of the global output line 268 during readout can be suppressed, and the design can be simplified.

[0068] Figure 12 is a schematic diagram illustrating other circuits for reading from the pixel memory 220. In Figure 12, components identical to those in Figure 5 are given the same reference numerals and their explanations are omitted.

[0069] In Figure 12, a repeater 270 is placed between adjacent pixel memories 220 on the row selection line 264. The repeater 270 receives the row selection signal φSEL flowing along the row selection line 264 and forwards it. This prevents the rising edge of the row selection signal φSEL from becoming sluggish, thereby suppressing a decrease in response speed. Note that the repeater 270 may be placed at a ratio of one for multiple pixel memories 220. Repeaters may also be placed for other control lines, such as the row selection signal φSEL2.

[0070] As described above, according to this embodiment, the amount of current flowing during reading can be reduced. In the above embodiment, one control circuit 214 is provided for one pixel 112. Alternatively, one control circuit 214 may be provided for multiple pixels 112. In that case, if the multiple pixels 112 corresponding to one control circuit 214 are called a pixel block, then the pixels 112 included in one pixel block are arranged in m rows and n columns (where m is a natural number of 2 or more and less than M, and n is a natural number of 2 or more and less than N), and multiple such pixel blocks may be arranged in the matrix direction.

[0071] Figure 13 is a block diagram showing an example configuration of an imaging device 500 according to an embodiment. The imaging device 500 comprises an image sensor 400, a system control unit 501, a drive unit 502, a photometer 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographic lens 520.

[0072] The imaging lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The imaging lens 520 is composed of multiple optical lens groups and forms an image of the subject light beam from the scene near its focal plane. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. In Figure 13, the imaging lens 520 is represented by a single virtual lens positioned near the pupil.

[0073] The drive unit 514 drives the photographic lens 520. In one example, the drive unit 514 moves the optical lens group of the photographic lens 520 to change the focus position. The drive unit 514 may also drive the iris diaphragm within the photographic lens 520 to control the amount of light beam incident on the image sensor 400.

[0074] The drive unit 502 has a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 400 according to instructions from the system control unit 501. The operation unit 508 receives instructions from the imager via a release button or the like.

[0075] The image sensor 400 passes pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 uses the work memory 504 as a workspace to generate image data after performing various image processing steps. For example, when generating image data in JPEG file format, it generates a color video signal from the signal obtained by the Bayer array and then performs compression processing. The generated image data is recorded in the recording unit 505 and converted into a display signal, which is then displayed in the display unit 506 for a preset time.

[0076] Prior to the series of shooting sequences that generate image data, the photometering unit 503 detects the brightness distribution of the scene. The photometering unit 503 includes, for example, an AE sensor with about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometering unit 503 and calculates the brightness of each region of the scene.

[0077] The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated brightness distribution. The photometering unit 503 may also be integrated into the image sensor 400. The calculation unit 512 also performs various calculations for operating the imaging device 500. The drive unit 502 may be partially or entirely mounted on the image sensor 400. Part of the system control unit 501 may also be mounted on the image sensor 400.

[0078] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0079] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.

Claims

1. A pixel section having a plurality of pixels, A storage unit for storing digital signals, comprising a first storage unit electrically connected to a first pixel among the plurality of pixels, A storage unit for storing digital signals, comprising a second storage unit electrically connected to a second pixel among the plurality of pixels, A first buffer circuit section having a first input section electrically connected to the first storage section and a first output section electrically connected to a first output line on which a digital signal is output, A second buffer circuit section having a second input section electrically connected to the second storage section and a second output section electrically connected to the first output line, The first amplifier section is electrically connected to the first output line and An image sensor equipped with the following features.

2. In the image sensor according to Claim 1, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, The first input unit is electrically connected to the third storage unit. Image sensor.

3. In the image sensor according to Claim 1, A first transistor for electrically connecting the first input unit and the first supply unit to which a predetermined voltage is supplied, A second transistor for electrically connecting the second input unit and the second supply unit to which a predetermined voltage is supplied, An image sensor equipped with the following features.

4. In the image sensor according to claim 3, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, The first input unit is electrically connected to the third storage unit. Image sensor.

5. In the image sensor according to claim 3, An image sensor comprising a third transistor for electrically connecting the first output line and a third supply unit to which a predetermined voltage is supplied.

6. In the image sensor according to claim 5, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, The first input unit is electrically connected to the third storage unit. Image sensor.

7. In the image sensor according to claim 1, The aforementioned pixel portion is arranged on the first semiconductor substrate. The first storage unit and the second storage unit are arranged on a second semiconductor substrate stacked together with the first semiconductor substrate. Image sensor.

8. In the image sensor according to claim 7, The second semiconductor substrate has a storage unit for storing digital signals, and a third storage unit is arranged thereon, which is electrically connected to the third pixel among the plurality of pixels. The first input unit is electrically connected to the third storage unit. Image sensor.

9. In the image sensor according to claim 7, The first storage unit and the second storage unit are positioned opposite the pixel unit in the stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked. Image sensor.

10. In the image sensor according to claim 9, The first buffer circuit section and the second buffer circuit section are arranged in positions facing the pixel section in the stacking direction. Image sensor.

11. In the image sensor according to claim 9, The second semiconductor substrate has a storage unit for storing digital signals, and a third storage unit is arranged thereon, which is electrically connected to the third pixel among the plurality of pixels. The first input unit is electrically connected to the third storage unit. Image sensor.

12. In the image sensor according to claim 11, The third storage unit is positioned opposite the pixel unit in the stacking direction. Image sensor.

13. In the image sensor according to claim 12, The first buffer circuit and the second buffer circuit are arranged in positions facing the pixel in the stacking direction. Image sensor.

14. In the image sensor according to claim 1, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, A storage unit for storing digital signals, the fourth storage unit being electrically connected to the fourth pixel among the plurality of pixels, A third buffer circuit section having a third input section electrically connected to the third storage section and a third output section electrically connected to a second output line on which a digital signal is output, A fourth buffer circuit section having a fourth input section electrically connected to the fourth storage section and a fourth output section electrically connected to the second output line, The second amplifier section is electrically connected to the second output line and An image sensor equipped with the following features.

15. In the image sensor according to claim 14, A storage unit for storing digital signals, the fifth storage unit being electrically connected to the fifth pixel among the plurality of pixels, A storage unit for storing digital signals, the sixth storage unit being electrically connected to the sixth pixel among the plurality of pixels, A storage unit for storing digital signals, the seventh storage unit being electrically connected to the seventh pixel among the plurality of pixels, A storage unit for storing digital signals, the eighth storage unit being electrically connected to the eighth pixel among the plurality of pixels. Equipped with, The first input unit is electrically connected to the fifth storage unit, The second input unit is electrically connected to the sixth storage unit, The third input unit is electrically connected to the seventh storage unit, The fourth input unit is electrically connected to the eighth storage unit. Image sensor.

16. In the image sensor according to claim 14, The aforementioned pixel portion is arranged on the first semiconductor substrate. The first storage unit, the second storage unit, the third storage unit, and the fourth storage unit are arranged on a second semiconductor substrate stacked together with the first semiconductor substrate. Image sensor.

17. In the image sensor according to claim 16, The first buffer circuit section, the second buffer circuit section, the third buffer circuit section, and the fourth buffer circuit section are arranged in positions facing the pixel section in the stacking direction. Image sensor.

18. A pixel section having a plurality of pixels, A storage unit for storing digital signals, comprising a first storage unit electrically connected to a first pixel among the plurality of pixels, A storage unit for storing digital signals, comprising a second storage unit electrically connected to a second pixel among the plurality of pixels, A first switch unit for electrically connecting the first storage unit and the first output line on which a digital signal is output, A second switch unit for electrically connecting the second storage unit and the first output line, An amplification section electrically connected to the first output line, An image sensor equipped with the following features.

19. In the image sensor according to claim 18, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, The first switch unit is electrically connected to the third storage unit. Image sensor.

20. In the image sensor according to claim 18, The first switch unit has a first transistor for electrically connecting the first storage unit and the first output line. The second switch unit has a second transistor for electrically connecting the second memory unit and the first output line. Image sensor.

21. In the image sensor according to claim 20, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, The first switch unit is electrically connected to the third storage unit. Image sensor.

22. In the image sensor according to claim 20, The first switch unit has a third transistor including a gate unit that is electrically connected to the first memory unit. The second switch unit has a fourth transistor including a gate unit that is electrically connected to the second memory unit. The third transistor is electrically connected to the first output line via the first transistor. The fourth transistor is electrically connected to the first output line via the second transistor. Image sensor.

23. In the image sensor according to claim 22, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, The gate portion of the third transistor is electrically connected to the third memory unit. Image sensor.

24. In the image sensor according to claim 22, A fifth transistor for electrically connecting the gate portion of the third transistor and a first supply unit to which a predetermined voltage is supplied, A sixth transistor for electrically connecting the gate portion of the fourth transistor and a second supply unit to which a predetermined voltage is supplied, An image sensor equipped with the following features.

25. In the image sensor according to claim 24, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, The gate portion of the third transistor is electrically connected to the third memory unit. Image sensor.

26. In the image sensor according to claim 24, An image sensor comprising a seventh transistor for electrically connecting the first output line and a third supply unit to which a predetermined voltage is supplied.

27. ​​In the image sensor according to claim 26, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, Equipped with, The gate portion of the third transistor is electrically connected to the third memory unit. Image sensor.

28. In the image sensor according to claim 18, The aforementioned pixel portion is arranged on the first semiconductor substrate. The first storage unit and the second storage unit are arranged on a second semiconductor substrate stacked together with the first semiconductor substrate. Image sensor.

29. In the image sensor according to claim 28, The second semiconductor substrate has a storage unit for storing digital signals, and a third storage unit is arranged thereon, which is electrically connected to the third pixel among the plurality of pixels. The first switch unit is electrically connected to the third storage unit. Image sensor.

30. In the image sensor according to claim 28, The first storage unit and the second storage unit are positioned opposite the pixel unit in the stacking direction in which the first semiconductor substrate and the second semiconductor substrate are stacked. Image sensor.

31. In the image sensor according to claim 30, The second semiconductor substrate has a storage unit for storing digital signals, and a third storage unit is arranged thereon, which is electrically connected to the third pixel among the plurality of pixels. The first switch unit is electrically connected to the third storage unit. Image sensor.

32. In the image sensor according to claim 30, The first switch section and the second switch section are arranged in positions facing the pixel section in the stacking direction. Image sensor.

33. In the image sensor according to claim 32, The second semiconductor substrate has a storage unit for storing digital signals, and a third storage unit is arranged thereon, which is electrically connected to the third pixel among the plurality of pixels. The first switch unit is electrically connected to the third storage unit. Image sensor.

34. In the image sensor according to claim 18, A storage unit for storing digital signals, comprising a third storage unit electrically connected to a third pixel among the plurality of pixels, A storage unit for storing digital signals, the fourth storage unit being electrically connected to the fourth pixel among the plurality of pixels, A third switch unit having a third input unit electrically connected to the third storage unit, and a third output unit electrically connected to a second output line on which a digital signal is output, A fourth switch unit having a fourth input unit electrically connected to the fourth storage unit and a fourth output unit electrically connected to the second output line, The second amplifier section is electrically connected to the second output line and An image sensor equipped with the following features.

35. In the image sensor according to claim 34, A storage unit for storing digital signals, the fifth storage unit being electrically connected to the fifth pixel among the plurality of pixels, A storage unit for storing digital signals, the sixth storage unit being electrically connected to the sixth pixel among the plurality of pixels, A storage unit for storing digital signals, the seventh storage unit being electrically connected to the seventh pixel among the plurality of pixels, A storage unit for storing digital signals, the eighth storage unit being electrically connected to the eighth pixel among the plurality of pixels. Equipped with, The first switch unit is electrically connected to the fifth storage unit, The second switch unit is electrically connected to the sixth storage unit, The third switch unit is electrically connected to the seventh storage unit, The fourth switch unit is electrically connected to the eighth storage unit. Image sensor.

36. In the image sensor according to claim 34, The aforementioned pixel portion is arranged on the first semiconductor substrate. The first storage unit, the second storage unit, the third storage unit, and the fourth storage unit are arranged on a second semiconductor substrate stacked together with the first semiconductor substrate. Image sensor.

37. In the image sensor according to claim 36, The second semiconductor substrate is provided with a storage unit for storing digital signals, a fifth storage unit electrically connected to the fifth pixel among the plurality of pixels, a sixth storage unit for storing digital signals, a sixth storage unit electrically connected to the sixth pixel among the plurality of pixels, a seventh storage unit for storing digital signals, a seventh storage unit electrically connected to the seventh pixel among the plurality of pixels, and an eighth storage unit for storing digital signals, an eighth storage unit electrically connected to the eighth pixel among the plurality of pixels. The first switch unit is electrically connected to the fifth storage unit, The second switch unit is electrically connected to the sixth storage unit, The third switch unit is electrically connected to the seventh storage unit, The fourth switch unit is electrically connected to the eighth storage unit. Image sensor.

38. In the image sensor according to claim 36, The first switch section, the second switch section, the third switch section, and the fourth switch section are arranged in positions facing the pixel section in the stacking direction. Image sensor.

39. In the image sensor according to claim 38, The second semiconductor substrate is provided with a storage unit for storing digital signals, a fifth storage unit electrically connected to the fifth pixel among the plurality of pixels, a sixth storage unit for storing digital signals, a sixth storage unit electrically connected to the sixth pixel among the plurality of pixels, a seventh storage unit for storing digital signals, a seventh storage unit electrically connected to the seventh pixel among the plurality of pixels, and an eighth storage unit for storing digital signals, an eighth storage unit electrically connected to the eighth pixel among the plurality of pixels. The first switch unit is electrically connected to the fifth storage unit, The second switch unit is electrically connected to the sixth storage unit, The third switch unit is electrically connected to the seventh storage unit, The fourth switch unit is electrically connected to the eighth storage unit. Image sensor.

40. An imaging device comprising an image sensor according to any one of claims 1 to 39.

41. In the imaging device according to claim 40, An imaging device comprising a drive unit that drives a photographic lens that emits light to the image sensor.

42. In the imaging device according to claim 41, An imaging device equipped with the aforementioned photographic lens.

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