Gaming machine

Abstract

To provide a game machine permitting suitable soldering when mounting an electronic component, a connector, and the like onto a printed wiring board.SOLUTION: A first operation hole detection sensor 951 for detecting entry into a first operation hole is connected to a main control board 61 via a first harness 951a, and a second operation hole detection sensor 952 for detecting entry into a second operation hole is connected to the main control board 61 via a second harness 952a. The main control board 61 includes: a first via hole 793s for inserting a first pin 784s used for connection of the second harness 952a, and a second via hole 793t for inserting a second pin 784t. Short-circuiting prevention holes 761, which suppress formation of a solder bridge between the first pin 784s and the second pin 784t, are provided around the first via hole 793s and the second via hole 793t each.SELECTED DRAWING: Figure 103

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As gaming machines, pachinko machines, slot machines, etc. are known. For example, a pachinko machine includes a main control device that controls the main game and a sound and light control device that outputs sounds and lights for effects based on commands received from the main control device. These main control devices, sound and light control devices, etc. have a substrate inside, and the substrate is configured by mounting electronic components such as ICs and resistors and connectors on a printed wiring board. The electronic components, connectors, etc. are fixed in a state of being electrically connected to the wiring formed on the printed wiring board by soldering (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, in a gaming machine such as the above example, it is necessary to appropriately manage the gaming machine, and there is still room for improvement in this regard.

[0005] The present invention has been made in view of the above-exemplified circumstances, etc., and an object thereof is to provide a gaming machine capable of appropriately managing a gaming machine.

Means for Solving the Problems

[0006] To solve the above problems, the invention described in claim 1 includes a predetermined storage execution means that performs a predetermined storage process so that when a predetermined event occurs as a result of playing a game, the storage of information corresponding to that event is performed in the predetermined storage means, thereby causing predetermined information to be stored in the predetermined storage means, Each time a predetermined calculation trigger occurs, an information calculation means calculates behavioral information corresponding to the results of the game during a predetermined period, using the predetermined information. A result storage execution means that sequentially stores the pattern information obtained by the calculation by the information calculation means into the calculation result storage means, Equipped with, The result storage execution means includes means for causing the manner information to be stored among the manner information obtained by the calculation by the information calculation means to be stored in the calculation result storage means, Of the configuration information obtained by the calculation by the information calculation means, the configuration information that is not to be stored is stored by the calculation result storage means Including the memory means of this gaming machine This configuration does not result in a state where it is stored in memory. This gaming machine is A predetermined control means capable of executing predetermined progress processing for advancing the game, A means of creating a specific period of advantage when a specific trigger occurs, A notification means capable of notifying the content corresponding to the configuration information stored in the calculation result storage means, A means for which, when the supply of operating power is stopped, the notification of the content corresponding to the mode information in the notification means is terminated, but when the supply of operating power is resumed, the notification of the content corresponding to the mode information before the supply of operating power was stopped is performed, Equipped with, In the event of a specific event that causes the game's progress control to stop, the predetermined storage process by the predetermined storage execution means is not executed. The information calculation means is characterized in that it calculates the manner information corresponding to the result of the game during the predetermined period by using the predetermined information during the specific advantageous period. [Effects of the Invention]

[0007] According to the present invention, it becomes possible to suitably manage amusement machines. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing a pachinko machine in the first embodiment. [Figure 2] This is a perspective view showing the main components of a pachinko machine in disassembled form. [Figure 3] This is a front view showing the configuration of the game board. [Figure 4] This is an explanatory diagram illustrating the configuration for discharging game balls that have flowed down the game area. [Figure 5] This is a block diagram showing the electrical configuration of a pachinko machine. [Figure 6] This is an explanatory diagram illustrating the functions of various counters used in lotteries and other similar processes. [Figure 7] This flowchart shows the main processing performed by the primary CPU. [Figure 8] This flowchart shows the timer interrupt processing performed by the main CPU. [Figure 9] This is an explanatory diagram illustrating a configuration in which the detection results of the ball entry detection sensor are input to the main CPU. [Figure 10] This flowchart shows the ball entry detection process executed by the main CPU. [Figure 11] This is a block diagram illustrating the electrical configuration of the dispensing control device and the various devices that communicate with the dispensing control device. [Figure 12] This flowchart shows the timer interrupt processing performed by the payout-side CPU. [Figure 13] This is a block diagram illustrating the electrical configuration of the management IC. [Figure 14] This is an explanatory diagram illustrating the configuration of the input ports on the management interface. [Figure 15]It is an explanatory diagram for explaining the configuration of the correspondence memory. [Figure 16] It is an explanatory diagram for explaining the configuration of the history memory. [Figure 17] It is a flowchart showing the recognition process executed by the main CPU. [Figure 18] It is a flowchart showing the management process executed by the management CPU. [Figure 19] (a) to (d) It is a time chart showing a state in which information on the correspondence relationship between the first to fifteenth buffers and the signal types is stored in the correspondence memory. [Figure 20] It is a flowchart showing the management output process executed by the main CPU. [Figure 21] It is a flowchart showing the history setting process executed by the management CPU. [Figure 22] (a) to (e) It is a time chart showing a state in which history information is stored in the history memory. [Figure 23] It is a flowchart showing the data output process executed by the main CPU. [Figure 24] It is a flowchart showing the external output process executed by the management CPU. [Figure 25] It is an explanatory diagram for explaining the configuration of the input port of the management side I / F in the second embodiment. [Figure 26] It is a flowchart showing the recognition process executed by the main CPU. [Figure 27] It is a flowchart showing the management process executed by the management CPU. [Figure 28] (a) to (h) It is a time chart showing a state in which information on the correspondence relationship between the first to twelfth buffers and the signal types is stored in the correspondence memory. [Figure 29] It is a block diagram for explaining the electrical configuration of the management IC in the third embodiment. [Figure 30] It is an explanatory diagram for explaining the configuration of the input port of the management side I / F. [Figure 31]This flowchart shows the power outage information storage process executed by the main CPU. [Figure 32] This is a flowchart showing the power outage response process executed by the management CPU. [Figure 33] This flowchart shows the processing for external output that is executed on the management CPU. [Figure 34] This flowchart shows the power outage response process executed by the management CPU in the fourth embodiment. [Figure 35] (a) A flowchart showing the trigger identification process executed by the main CPU in the fifth embodiment, and (b) A flowchart showing the arithmetic process executed by the management CPU. [Figure 36] This is a flowchart showing the trigger identification process executed by the main CPU in the sixth embodiment. [Figure 37] This is a flowchart showing the arithmetic processing performed by the management CPU in the seventh embodiment. [Figure 38] This is a flowchart showing the history setting process executed by the management CPU in the eighth embodiment. [Figure 39] This is an explanatory diagram illustrating the configuration of the history memory in the ninth embodiment. [Figure 40] This is a flowchart showing the history setting process executed by the management CPU. [Figure 41] This is a block diagram illustrating the electrical configuration of the MPU of the main control unit in the tenth embodiment. [Figure 42] This flowchart shows the ball entry detection process executed by the main CPU. [Figure 43] This is a block diagram illustrating the electrical configuration of the main control device in the 11th embodiment. [Figure 44] This is an explanatory diagram illustrating the configuration of the input ports on the management interface. [Figure 45] This is an explanatory diagram illustrating the configuration of the history memory. [Figure 46]This is a flowchart showing the history setting process executed by the management CPU. [Figure 47] This flowchart shows the processing for external output that is executed on the management CPU. [Figure 48] This flowchart shows the parameter management process executed by the primary CPU. [Figure 49] This is a block diagram illustrating the configuration of the signal path for transmitting the detection results of each ball entry detection sensor to the main CPU and the management IC in the 12th embodiment. [Figure 50] This is a front view of the game board in the 13th embodiment. [Figure 51] (a) is a perspective view of the first left-right splitting nail, (b) is a plan view of the first left-right splitting member, and (c) is a rear view of the first left-right splitting member. [Figure 52] (a) A perspective view of the fixing member, and (b) an end view of the cross-section of the first left and right distribution nails when the game board is cut with a plane perpendicular to the surface. [Figure 53] (a) This is an end view of the longitudinal section of the first left and right distribution pins showing the game balls that collide with the first distribution surface; (b) This is an explanatory diagram for explaining the path of a game ball that falls from above and collides with the first distribution surface; and (c) This is an explanatory diagram for explaining the path of a game ball that flows down from the upper left and collides with the first distribution surface. [Figure 54] (a) This is an end view of the longitudinal section of the first left and right distribution pins showing the game balls that collide with the second distribution surface; (b) This is an explanatory diagram for illustrating the path of a game ball that falls from above and collides with the second distribution surface; and (c) This is an explanatory diagram for illustrating the path of a game ball that flows down from the upper left and collides with the second distribution surface. [Figure 55] (a) is a perspective view of the second left-right splitting nail, (b) is a plan view of the second left-right splitting member, and (c) is a rear view of the second left-right splitting member. [Figure 56] (a) A table showing the direction of the force acting on a game ball when it collides with the first left-right splitting pins, (b) A table showing the direction of the force acting on a game ball when it collides with the second left-right splitting pins, and (c) A table showing the direction of the force acting on a game ball when it collides with an obstacle pin. [Figure 57] (a) This is an explanatory diagram illustrating how game balls located at the back are guided to the group of guide pins on the left, and (b) This is an explanatory diagram illustrating how game balls located at the front are guided to the group of guide pins on the left. [Figure 58] (a) This is an explanatory diagram illustrating how game balls located at the back are guided to the group of guide pins on the right, and (b) This is an explanatory diagram illustrating how game balls located at the front are guided to the group of guide pins on the right. [Figure 59] This is a front view of the game board showing an enlarged view of the area around the left-side guide member in another embodiment of the 13th embodiment. [Figure 60] This is a front view of a game board in which the first left-right distribution pins and the second left-right distribution pins are located near the upstream of the operating opening, and a magnified view of the area around the operating opening. [Figure 61] (a) A perspective view of the first left and right distribution pins, and (b) an end view of the cross-section of the first left and right distribution pins when the game board is cut with a plane perpendicular to the surface. [Figure 62] (a) A perspective view of the reversing nail; (b) An end view of the cross-section when the reversing nail is cut with a plane perpendicular to the surface of the game board; (c) An explanatory diagram for illustrating the path of a game ball colliding with the first reversing surface; and (d) An explanatory diagram for illustrating the path of a game ball colliding with the second reversing surface. [Figure 63] This is a front view of the game board in the 14th embodiment, and an enlarged view of the area around the upstream part of the left-side guide pin group. [Figure 64] (a) is a perspective view of the front and rear distribution nails, (b) is a plan view of the front and rear distribution member, and (c) and (d) are end views of the cross-section of the front and rear distribution nails when cut with a plane perpendicular to the surface of the game board. [Figure 65] (a) is a perspective view of the rear nail, and (b) and (c) are end views of the cross-section of the rear nail when cut with a plane perpendicular to the surface of the game board. [Figure 66] (a) This is an explanatory diagram for explaining the path of the game ball in the left-hand guide pin group located at the back of the game area, and (b) This is an explanatory diagram for explaining the path of the game ball in the left-hand guide pin group located at the front of the game area. [Figure 67](a) A plan view of the forward priority member in another embodiment of the 14th embodiment, and (b) An explanatory diagram for illustrating the path of the game ball in the left-side guide pin group including the forward priority member. [Figure 68] This is a front view of the game board and an enlarged view of the area around the rebound pins in the 15th embodiment. [Figure 69] (a) is an exploded perspective view of the rebound nail, and (b) is a longitudinal cross-sectional view of the rebound nail. [Figure 70] (a) This is an end view of the cross-section when the rebound nail is cut with a plane perpendicular to the plane of the game board; (b) This is an explanatory diagram for illustrating the path of the game ball as it collides with the high-rebound part; (c) This is an end view of the cross-section when the rebound nail is cut with a plane perpendicular to the plane of the game board; and (d) This is an explanatory diagram for illustrating the path of the game ball as it collides with the low-rebound member. [Figure 71] (a) This is an explanatory diagram illustrating the path of a game ball when it collides with the high-rebound portion of a rebound nail, and (b) This is an explanatory diagram illustrating the path of a game ball after it collides with the low-rebound portion of a rebound nail. [Figure 72] This is a front view of the game board in the 16th embodiment. [Figure 73] (a) is a perspective view of the front / rear distribution platform, (b) is a plan view of the front / rear distribution platform, and (c) and (d) are end views of the cross-section when the front / rear distribution platform is cut by a plane perpendicular to the surface of the game board. [Figure 74] This is a front view of the game board, showing a magnified view of the left central section. [Figure 75] This is a front view of the game board in another embodiment of the 16th embodiment. [Figure 76] (a) and (b) are front views of the game board showing enlarged views of the front and rear distribution platform and the area around the left-side guide pin group. [Figure 77] (a) A perspective view of a front-to-back ball sorting machine equipped with a groove that guides the balls on the far side to the furthest back and a groove that guides the balls on the near side to the furthest front, and (b) A perspective view of a front-to-back ball sorting machine equipped with a groove that guides the balls on the far side to the furthest front and a groove that guides the balls on the near side to the furthest back. [Figure 78]This is a front view of the game board and an enlarged view of the area around the position change passage in the 17th embodiment. [Figure 79] (a) is a perspective view of the passage forming member, (b) is a front view of the passage forming member, and (c) and (d) are end views of the cross-section when the passage forming member is cut with a plane perpendicular to the surface of the game board. [Figure 80] (a) and (b) are front views of the game board showing an enlarged view of the area downstream of the position change passage. [Figure 81] (a) and (b) are end views of the cross-section when the replacement passage forming member is cut with a plane perpendicular to the surface of the game board. [Figure 82] This is a front view of the game board in the 18th embodiment. [Figure 83] (a) is an exploded perspective view of the guide member, and (b) is a left side view of the guide member. [Figure 84] This is an end view of the cross-section when the guide member is cut with a plane perpendicular to the surface of the game board. [Figure 85] (a) and (b) are front views of the game board showing an enlarged view of the area downstream of the guide passage. [Figure 86] This is an end view of the cross-section when a replacement guide member is cut with a plane perpendicular to the surface of the game board. [Figure 87] (a) An end view of the cross-section when the guide member is cut in a plane perpendicular to the surface of the game board in another embodiment of the 18th embodiment, and (b) An end view of the cross-section when the replacement guide member is cut in a plane perpendicular to the surface of the game board. [Figure 88] (a) A surface view of the main control board showing an enlarged portion of the main control board in the 19th embodiment, and (b) A surface view of the main control board showing an enlarged view of the area around the single-row connector. [Figure 89] (a) is a perspective view of a single-row connector, (b) is a perspective view of a two-pole connector, and (c) is a perspective view of a two-row connector. [Figure 90] (a) is a perspective view showing a magnified portion of the back surface of the printed circuit board, and (b) is a longitudinal cross-sectional view showing a magnified portion of the area around the via holes in the printed circuit board, cut with a plane perpendicular to the surface. [Figure 91] This is a magnified longitudinal cross-sectional view showing the area around the pins of a printed circuit board, cut with a plane perpendicular to the surface. [Figure 92] (a) This is a rear view showing a magnified portion of the main control board, and (b) This is a rear view of the printed circuit board showing a magnified rear area for the single-row connector before it is installed. [Figure 93] (a) This is an explanatory diagram for illustrating the flow of molten solder, and (b) This is an explanatory diagram for illustrating how the flow of solder hits the back surface of a printed circuit board. [Figure 94] (a) A longitudinal cross-sectional view of a comparative printed circuit board to illustrate the state in which the second, third, and fourth pins of a single-row connector are in contact with the jet; (b) A longitudinal cross-sectional view of a comparative printed circuit board to illustrate the state in which the second pin of a single-row connector is released from contact with the jet; and (c) A longitudinal cross-sectional view of a comparative printed circuit board to illustrate the state in which the third pin of a single-row connector is released from contact with the jet. [Figure 95] (a) A longitudinal cross-sectional view of a comparative printed circuit board to illustrate the state in which the third pin of a single-row connector has come out of contact with the jet; (b) A longitudinal cross-sectional view of a comparative printed circuit board to illustrate the state in which the fourth pin of a single-row connector has come out of contact with the jet; and (c) A longitudinal cross-sectional view of a comparative printed circuit board showing the state in which a solder bridge has formed between the third and fourth pins of a single-row connector. [Figure 96] This is a longitudinal cross-sectional view of a printed circuit board shown to illustrate the solder fillet formed around the fourth pin of a single-row connector. [Figure 97] (a) A rear view of the printed circuit board showing an enlarged view of the rear area for the 2-pole connector before the 2-pole connector is installed, and (b) A rear view of the printed circuit board showing an enlarged view of the rear area for the 2-row connector before the 2-row connector is installed. [Figure 98](a) A rear view of a printed circuit board showing an enlarged view of the single-row rear area equipped with inclined short-circuit prevention holes in another embodiment of the 19th embodiment; (b) A rear view of a printed circuit board showing an enlarged view of the single-row rear area; and (c) A rear view of a printed circuit board showing an enlarged view of the single-row rear area in the printed circuit board. [Figure 99] (a) A rear view of the printed circuit board showing an enlarged view of the back surface area for a single row in the 20th embodiment, and (b) A longitudinal cross-sectional view of the printed circuit board showing an enlarged view of the area around the pins of a single-row connector. [Figure 100] (a) A rear view of a printed circuit board showing an enlarged view of the rear surface area for a single row in which six separable short-circuit prevention holes are formed in another embodiment of the 20th embodiment, and (b) A rear view of a printed circuit board showing an enlarged view of the rear surface area for a single row in which two three-way separable short-circuit prevention holes are formed. [Figure 101] This is a rear view of a printed circuit board showing an enlarged view of the single-row rear area where a group of short-circuit prevention holes for suppressing the occurrence of solder bridges is formed in the 21st embodiment. [Figure 102] This is a front view of the game board in the 22nd embodiment. [Figure 103] (a) This is an explanatory diagram illustrating the connection configuration between the first and second operation port detection sensors and the main control board, and (b) This is a rear view of the printed circuit board showing enlarged views of the first and second operation port areas. [Modes for carrying out the invention]

[0009] <First Embodiment> The following describes in detail, based on the drawings, a first embodiment of a pachinko gaming machine (hereinafter referred to as "pachinko machine"), which is a type of gaming machine. Figure 1 is a perspective view of the pachinko machine 10, and Figure 2 is a perspective view showing the main components of the pachinko machine 10 in an exploded view. For convenience, the components within the gaming area PA of the pachinko machine 10 are omitted in Figure 2.

[0010] As shown in Figure 1, the pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a game machine body 12 that is rotatably attached to the outer frame 11 in the forward direction. The outer frame 11 is constructed by connecting wooden boards on all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in a game hall by attaching and fixing the outer frame 11 to the island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10, and the outer frame 11 may be installed on the island equipment of the game hall.

[0011] As shown in Figure 2, the gaming machine body 12 comprises an inner frame 13, a front door frame 14 positioned in front of the inner frame 13, and a back pack unit 15 positioned behind the inner frame 13. The inner frame 13 of the gaming machine body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 is rotatable forward with the left side as the base end of rotation and the right side as the tip end of rotation when viewed from the front.

[0012] The front door frame 14 is rotatably supported on the inner frame 13, and can rotate forward with the left side as the pivot end and the right side as the pivot end when viewed from the front. The rear pack unit 15 is also rotatably supported on the inner frame 13, and can rotate backward with the left side as the pivot end and the right side as the pivot end when viewed from the front.

[0013] Furthermore, the gaming machine body 12 is equipped with a locking device at its rotating tip, which has the function of locking the gaming machine body 12 to the outer frame 11 in a state where it cannot be opened, and also has the function of locking the front door frame 14 to the inner frame 13 in a state where it cannot be opened. These locking states can be released by performing an unlocking operation using an unlocking key on a cylinder lock 17 that is exposed on the front of the pachinko machine 10.

[0014] Next, we will describe the configuration of the front side of the gaming machine body 12.

[0015] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is almost identical to that of the outer frame 11. A roughly oval-shaped window opening 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front of the game board 24 is exposed to the front side of the inner frame 13 through the window opening 23 of the resin base 21.

[0016] Here, the configuration of the game board 24 will be explained based on Figure 3. Figure 3 is a front view of the game board 24.

[0017] The game board 24 is fitted with an inner rail section 25 and an outer rail section 26 so as to demarcate a part of the outer edge of the game area PA, and these inner rail section 25 and outer rail section 26 constitute a guide rail that serves as a guide means. Game balls launched from the game ball launching mechanism 27 (see Figure 2), which is attached below the window hole 23 on the resin base 21, are guided to the upper part of the game area PA by the guide rail.

[0018] Incidentally, the game ball launching mechanism 27 includes a launching rail 27a extending toward a guide rail, a ball feeding device 27b that supplies game balls stored in the upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c, which is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by the rotation of the launching operation device (or operation handle) 28 provided on the front door frame 14, and the game balls are launched.

[0019] The game board 24 has multiple openings of varying sizes that penetrate in the front-to-back direction. Each opening is provided with a general prize entry point 31, a special electric prize entry device 32, a first operation opening 33, a second operation opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a regular symbol unit 38, among others. There are a total of four general prize entry points 31, and one of each of the other types.

[0020] Even if a ball enters the through gate 35, no game balls will be dispensed. On the other hand, if a ball enters the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, or the second operation opening 34, a predetermined number of game balls will be dispensed. Specifically regarding the number of prize balls dispensed, if one game ball enters the first operation opening 33 or one game ball enters the second operation opening 34, one prize ball will be dispensed; if one game ball enters the general prize entry opening 31, ten prize balls will be dispensed; and if one game ball enters the special electric prize entry device 32, fifteen prize balls will be dispensed.

[0021] The above number of prize balls is arbitrary; for example, the second operating port 34 may be configured to award fewer prize balls than the first operating port 33, or the second operating port 34 may be configured to award more prize balls than the first operating port 33.

[0022] In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various prize slots are discharged from the game area PA through the outlet 24a. Furthermore, the game board 24 is equipped with numerous nails 24b to appropriately disperse and adjust the direction in which the game balls fall, as well as various components such as windmills.

[0023] Here, "entering the game" means that a game ball passes through a predetermined opening, and includes not only the mode in which the game ball is discharged from the game area PA after passing through the opening, but also the mode in which the game ball continues to flow down the game area PA without being discharged after passing through the opening. However, in the following explanation, in order to clearly distinguish it from the entry of a game ball into the out opening 24a, the entry of a game ball into the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, the second operation opening 34, and the through gate 35 will also be expressed as "winning a prize."

[0024] The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. Both the first operating port 33 and the second operating port 34 are open upwards. Furthermore, both operating ports 33 and 34 are aligned vertically so that the first operating port 33 is at the top. The second operating port 34 is provided with a guide piece, a general-purpose device 34a, which consists of a pair of movable pieces on the left and right. When the general-purpose device 34a is closed, game balls cannot enter the second operating port 34, but when the general-purpose device 34a is opened, it becomes possible for game balls to enter the second operating port 34.

[0025] A through gate 35 is provided upstream of the second operating port 34 in the direction of the flow of the game ball. The through gate 35 has a through hole (not shown) that penetrates vertically, and game balls that enter the through gate 35 flow down the game area PA after entering. This makes it possible for game balls that enter the through gate 35 to enter the second operating port 34.

[0026] Based on the entry of a ball into the through gate 35, the normal electric mechanism 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is conducted triggered by the entry of a ball into the through gate 35, and the normal diagram display section 38a of the normal diagram unit 38, which is located in the lower right corner of the game area PA where the game ball does not pass, displays a changing pattern. If the result of the internal lottery is a win for opening the electric mechanism, and the stop result corresponding to that result is displayed and the changing display on the normal diagram display section 38a ends, the system transitions to the normal electric open state. In the normal electric open state, the normal electric mechanism 34a is in an open state in a predetermined manner.

[0027] The general display unit 38a is configured as a segment display in which multiple segment light-emitting units are arranged in a predetermined manner, but is not limited to this, and may be configured as other types of display devices such as liquid crystal displays, organic EL displays, CRTs, or dot matrix displays. Furthermore, the patterns that can be displayed in the general display unit 38a may include configurations in which multiple types of characters are displayed in a variable manner, configurations in which multiple types of symbols are displayed in a variable manner, configurations in which multiple types of characters are displayed in a variable manner, or configurations in which multiple types of colors are switched and displayed.

[0028] In the regular display unit 38, a regular display reserve display unit 38b is provided adjacent to the regular display unit 38a. Up to four game balls are reserved when they enter the through gate 35, and the number of reserved balls is displayed by the illumination of the regular display reserve display unit 38b.

[0029] A prize draw is triggered when a ball enters the first or second operating port 33. The result of the draw is then clearly displayed through the display effects on the symbol display device 41 of the special display unit 37 and the variable display unit 36.

[0030] More specifically, the special symbol unit 37 is provided with a special symbol display unit 37a. The display area of ​​the special symbol display unit 37a is narrower than the display surface 41a of the symbol display device 41. In the special symbol display unit 37a, a winning lottery is held triggered by a win in the first operation opening 33 or the second operation opening 34, resulting in a display of changing patterns or a predetermined display. The result corresponding to the lottery result is then displayed. The special symbol display unit 37a is composed of a segment display device in which multiple segment light-emitting units are arranged in a predetermined manner, but is not limited to this, and may be composed of other types of display devices such as liquid crystal displays, organic EL displays, CRTs, or dot matrix displays. Furthermore, the patterns displayed in the special symbol display unit 37a may include configurations that display multiple types of characters, multiple types of symbols, multiple types of characters, or multiple types of colors.

[0031] In the special feature unit 37, a special feature hold display unit 37b is provided adjacent to the special feature display unit 37a. Up to four game balls are held in the first operation opening 33 or the second operation opening 34, and the number of held balls is displayed by the illumination of the special feature hold display unit 37b.

[0032] More specifically, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and its display content is controlled by a display control device described later. The pattern display device 41 is not limited to a liquid crystal display device; it may be another display device having a display screen, such as a plasma display device, an organic EL display device, or a CRT, or it may be a dot matrix display device.

[0033] In the symbol display device 41, when a symbol variation display or predetermined display is performed on the special symbol display unit 37a based on a win in the first operation opening 33 or a win in the second operation opening 34, the symbol variation display or predetermined display is performed accordingly. For example, the display surface 41a of the symbol display device 41 has three symbol rows set as multiple display areas: upper, middle, and lower. In each symbol row, the main symbols numbered "1" to "9" are displayed in ascending or descending order in a scrolling display. In this scrolling display, scrolling is started for all symbol rows first, then switches from scrolling to standby display in the order of upper symbol row → lower symbol row → middle symbol row, and finally ends with a predetermined symbol displayed statically in each symbol row. For example, in a game round in which the game result is a jackpot, a predetermined combination of symbols is stopped and displayed on the active line set in advance on the display surface 41a of the symbol display device 41.

[0034] Furthermore, the symbol display device 41 performs not only display effects triggered by a win in the first or second operation port 33, but also display effects during the opening / closing execution mode that is entered after a win is achieved. In addition, based on a win in either operation port 33 or 34, the display on the special symbol display unit 37a and the symbol display device 41 starts, and the period until the predetermined result is displayed and the display ends constitutes one game round. Furthermore, the manner in which the symbols are displayed in the symbol display device 41 is not limited to those described above and is arbitrary, and the number of symbol rows, the direction of the symbol display in the symbol rows, and the number of symbols in each symbol row can be changed as appropriate. Also, the symbols displayed in the symbol display device 41 are not limited to the symbols described above, and for example, a configuration in which only numbers are displayed as symbols is also possible.

[0035] If a jackpot is won in the winning lottery based on a ball entering the first operating port 33 or the second operating port 34, the system transitions to an opening / closing execution mode in which a ball can enter the special electric prize entry device 32. The special electric prize entry device 32 has a large prize entry port (not shown) that leads to the back of the game board 24, and also has an opening / closing door 32a that opens and closes the large prize entry port. The opening / closing door 32a can be positioned in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state in which game balls cannot enter, and is switched to an open state in which game balls can enter if the internal lottery results in a transition to the opening / closing execution mode. Incidentally, the opening / closing execution mode is the mode that is entered when a winning result is obtained. Note that while it is not impossible to enter in the closed state, it may be configured in such a way that it is less likely to result in a win than in the open state.

[0036] Figure 4 is an explanatory diagram illustrating the configuration for discharging game balls that have flowed down the game area PA.

[0037] As already explained, game balls that enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a are discharged from the game area PA. In other words, game balls launched from the game ball launching mechanism 27 and flowing into the game area PA are discharged from the game area PA by entering any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a. Game balls that enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, the second operation slot 34, and the out slot 24a are guided to the back side of the game board 24.

[0038] On the back of the game board 24, discharge passages 42 to 48 are formed corresponding to the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, respectively. Game balls that flow into the discharge passages 42 to 48 are guided down the discharge passages 42 to 48 to the lower end of the game board 24 on the back side of the game board 24 and are collected in a discharge ball collection section (not shown). The game balls collected in the discharge ball collection section are then discharged into the ball circulation device of the island equipment where the pachinko machine 10 is installed in the game hall.

[0039] Each of the discharge passages 42 to 48 is equipped with various detection sensors 42a to 48a for detecting game balls. These discharge passages 42 to 48 and detection sensors 42a to 48a are described below. As already explained, there are four general prize slots 31, and there are discharge passages 42 to 44 corresponding to each of these four slots. In this case, one detection sensor 42a and one detection sensor 43a are provided for the first discharge passage 42 corresponding to the leftmost general prize slot 31 and the second discharge passage 43 corresponding to the general prize slot 31 to its right. Specifically, the first prize slot detection sensor 42a is provided such that its detection range is located midway through the first discharge passage 42, and the second prize slot detection sensor 43a is provided such that its detection range is located midway through the second discharge passage 43. A game ball that enters the leftmost general prize slot 31 is detected by the first prize slot detection sensor 42a while passing through the first discharge passage 42, and a game ball that enters the general prize slot 31 to its right is detected by the second prize slot detection sensor 43a while passing through the second discharge passage 43. In addition, a third discharge passage 44 is provided that is formed to merge with the two general prize slots 31 on the right at an intermediate position. The third discharge passage 44 has an entrance-side region corresponding to each of the two general prize slots 31, and these entrance-side regions merge midway to form a single exit-side region. A third prize slot detection sensor 44a is provided such that the detection range exists at an intermediate position in the exit-side region of the third discharge passage 44. A game ball that enters either of the two general prize slots 31 on the right is detected by the third prize slot detection sensor 44a while passing through the third discharge passage 44.

[0040] A fourth discharge passage section 45 exists corresponding to the special electric prize entry device 32. A special electric detection sensor 45a is provided so that its detection range is located midway through the fourth discharge passage section 45, and game balls that enter the special electric prize entry device 32 are detected by the special electric detection sensor 45a as they pass through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operation port 33. A first operation port detection sensor 46a is provided so that its detection range is located midway through the fifth discharge passage section 46, and game balls that enter the first operation port 33 are detected by the first operation port detection sensor 46a as they pass through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operation port 34. A second operation port detection sensor 47a is provided such that its detection range exists midway through the sixth discharge passage 47, and a game ball that enters the second operation port 34 is detected by the second operation port detection sensor 47a while passing through the sixth discharge passage 47. A seventh discharge passage 48 exists corresponding to the out port 24a. An out port detection sensor 48a is provided such that its detection range exists midway through the seventh discharge passage 48, and a game ball that enters the out port 24a is detected by the out port detection sensor 48a while passing through the seventh discharge passage 48.

[0041] Furthermore, a game ball detected by any one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. In addition, a gate detection sensor 49a is also provided for the through gate 35, and game balls that pass through the through gate 35 while flowing down the game area PA are detected by the gate detection sensor 49a.

[0042] The various detection sensors 42a to 49a are all electromagnetic induction type proximity sensors, but any sensor can be used as long as it can individually detect the game balls. Furthermore, the various detection sensors 42a to 49a are electrically connected to the main control unit 60, which will be described later, and the detection results from the various detection sensors 42a to 49a are output to the main control unit 60. Specifically, the various detection sensors 42a to 49a output a LOW level signal when they do not detect a game ball, and a HI level signal when they detect a game ball. However, this is not the only way to do it; the relationship between HI and LOW may be reversed.

[0043] As shown in Figure 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13, to which the game board 24 configured above is attached to the resin base 21. As shown in Figure 1, the front door frame 14 has a window portion 51 formed therein so that almost the entire area of ​​the game area PA can be seen from the front. The window portion 51 is roughly elliptical in shape, and a window panel 52 is fitted into it. The window panel 52 is made of glass and is colorless and transparent, but is not limited to this and may be made of synthetic resin and is colorless and transparent, or it may be made of colored transparent material as long as the game area PA can be seen from the front of the pachinko machine 10 through the window panel 52.

[0044] An indicator light-emitting unit 53 is provided above the window section 51. A pair of left and right speaker sections 54 are also provided, which output sound effects according to the game state. Below the window section 51, an upper bulge 55 and a lower bulge 56 are arranged vertically side by side, bulging outwards towards the front. An upper tray 55a, which opens upwards, is provided inside the upper bulge 55, and a lower tray 56a, which also opens upwards, is provided inside the lower bulge 56. The upper tray 55a has the function of temporarily storing game balls dispensed from the dispensing device (described later) and guiding them to the game ball launching mechanism 27 while aligning them in a line. The lower tray 56a has the function of storing game balls that are left over in the upper tray 55a.

[0045] Next, we will describe the configuration of the back side of the gaming machine body 12.

[0046] As shown in Figure 2, a main control device 60, which is responsible for the main control of the game, is mounted on the back of the inner frame 13 (specifically, the game board 24). The main control device 60 consists of a main control board 61 housed in a board box 60a. The board box 60a may be provided with a means to leave a trace of its opening, or a structure to leave a trace of its opening. Possible means to leave a trace include a configuration in which multiple case bodies constituting the board box 60a are inseparably joined and require the destruction of a predetermined part when separated, or a configuration in which a sealing seal is attached across the boundaries between multiple case bodies so that the adhesive layer remains on the object to which it is attached when peeled off, leaving a trace of its removal. Possible structures to leave a trace include applying adhesive to the boundaries between multiple case bodies constituting the board box 60a.

[0047] The back pack unit 15 is installed so as to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 is equipped with a back pack 72 made of transparent synthetic resin, and the dispensing mechanism 73 and the control device assembly unit 74 are attached to the back pack 72.

[0048] The dispensing mechanism 73 includes a tank 75 into which game balls supplied from the island equipment of the gaming hall are replenished sequentially, and a dispensing device 76 for dispensing the game balls stored in the tank 75. The game balls dispensed from the dispensing device 76 are discharged into the upper tray 55a or lower tray 56a through a dispensing passage provided downstream of the dispensing device 76. The dispensing mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back-pack circuit board having a power switch for turning the power ON and OFF.

[0049] The control unit 74 includes a payout control device 77 that has the function of controlling the payout device 76, and a power supply / launch control device 78 that generates and outputs predetermined power required by various control devices, and controls the launch of game balls in accordance with the operation of the launching device 28 by the player. The payout control device 77 and the power supply / launch control device 78 are arranged front to back, with the payout control device 77 facing the rear of the pachinko machine 10.

[0050] <Electrical configuration of pachinko machine 10> Figure 5 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0051] The main control device 60 comprises a main control board 61 that is in charge of the main control of the game, and a power failure monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. In addition to the main CPU 63, which is an arithmetic processing unit including a control unit and an arithmetic unit, the MPU 62 also incorporates a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also incorporates interrupt circuits, timer circuits, data input / output circuits, and various counter circuits as random number generators.

[0052] The main ROM 64 is a memory (i.e., a non-volatile storage means) that does not require an external power supply for storage, such as NOR flash memory and NAND flash memory, and is used in read-only mode. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

[0053] The main RAM 65 is a memory (i.e., volatile memory) that requires an external power supply for memory retention, such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 allows random access and, when compared with the main ROM 64 for the same data capacity, has a faster read time. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

[0054] The management IC 66 is a management device that manages the pattern of game ball entry into the game area PA based on information supplied from the main CPU 63. As will be described in detail later, the management IC 66 grasps the history of game ball entry into the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, and also grasps the frequency of entry into the general prize entry opening 31, the special electric prize entry device 32, the first operation opening 33, and the second operation opening 34 according to the grasped entry history.

[0055] The MPU62 is provided with input and output ports. The input side of the MPU62 is connected to the power outage monitoring board 67 and the payout control device 77, which are provided on the main control device 60. The power outage monitoring board 67 is connected to the power supply / launch control device 78, which has the function of supplying operating power, and the MPU62 is supplied with operating power via the power outage monitoring board 67.

[0056] Various sensors, such as ball entry detection sensors 42a to 49a, are connected to the input side of the MPU 62. As previously explained, the ball entry detection sensors 42a to 49a are the first prize entry hole detection sensor 42a, the second prize entry hole detection sensor 43a, the third prize entry hole detection sensor 44a, the special electric detection sensor 45a, the first operation hole detection sensor 46a, the second operation hole detection sensor 47a, the out hole detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 makes a determination of whether the ball has entered each entry area. In addition, the main CPU 63 executes various lotteries based on whether the ball has entered the first operation hole 33 and also executes various lotteries based on whether the ball has entered the second operation hole 34.

[0057] The output side of the MPU62 is connected to a power outage monitoring board 67, a payout control device 77, and a sound and light emission control device 81. The payout control device 77 outputs a prize ball command based on, for example, when a game ball enters the prize ball corresponding entry section of the ball entry section, where the occurrence of a ball entry corresponds to the payout of game balls. The sound and light emission control device 81 outputs various commands such as variation commands, type commands, and opening commands.

[0058] The output side of the MPU 62 is connected to the special electric drive unit 32b, which opens and closes the opening and closing door 32a of the special electric prize winning device 32; the general electric drive unit 34b, which opens and closes the general electric mechanism 34a of the second operating port 34; the special symbol unit 37; and the general symbol unit 38. Incidentally, the special symbol unit 37 is equipped with a special symbol display unit 37a and a special symbol hold display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the general symbol unit 38 is equipped with a general symbol display unit 38a and a general symbol hold display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 performs drive control of the various drive units and various display units through these driver circuits.

[0059] In other words, in the opening / closing execution mode, the main CPU 63 controls the drive unit 32b for the special electric prize device 32 so that it is opened and closed. Also, if the open state of the regular electric prize device 34a is selected, the main CPU 63 controls the drive unit 34b for the regular electric prize device 34a so that it is opened and closed. Furthermore, for each game round, the main CPU 63 controls the display of the special symbol display unit 37a. In addition, when the result of the lottery to determine whether or not to open the regular electric prize device 34a is displayed, the main CPU 63 controls the display of the regular symbol display unit 38a. Furthermore, when a prize is awarded in the first operation port 33 or the second operation port 34, or when a variable display is started in the special display unit 37a, the main CPU 63 executes display control of the special hold display unit 37b. When a prize is awarded in the through gate 35, or when a variable display is started in the general display unit 38a, the main CPU 63 executes display control of the general hold display unit 38b.

[0060] The power outage monitoring board 67 relays the main control board 61 and the power supply / launch control device 78, and monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 controls the payout of prize balls and loaned balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0061] The power supply and launch control device 78 is connected to a commercial power supply (external power supply) in, for example, a gaming hall. Based on the external power supplied from the commercial power supply, it generates the necessary operating power for the main control board 61, the payout control device 77, etc., and supplies the generated operating power. Incidentally, the power supply and launch control device 78 is equipped with a power supply unit for when the power is off, such as a backup capacitor, so that even when the power to the pachinko machine 10 is off, power for memory retention is supplied from this power supply unit to the main RAM 65 of the main control device 60 and the payout control device 77. Furthermore, the power supply and launch control device 78 is responsible for the launch control of the game ball launching mechanism 27, and the game ball launching mechanism 27 is driven when predetermined launch conditions are met.

[0062] The sound and light emission control device 81 drives and controls the display light emission unit 53 and speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 performs display control of the pattern display device 41 based on commands received from the sound and light emission control device 81.

[0063] <Electrical configuration for performing various lottery draws on the main CPU 63> Next, the electrical configuration for performing various lotteries on the main CPU 63 will be explained using Figure 6.

[0064] The main CPU 63 uses various counter information during gameplay to perform tasks such as the lottery for the occurrence of a jackpot, setting the display of the special symbol display unit 37a, setting the symbol display of the symbol display device 41, and setting the display of the regular symbol display unit 38a. Specifically, as shown in Figure 6, it uses a random number counter C1 used for the lottery for the occurrence of a jackpot, a jackpot type counter C2 used for determining the type of jackpot, a random number counter C3 used for the lottery for the occurrence of a reach when the symbol display device 41 is fluctuating to a miss, a random number initial value counter CINI used for setting the initial value of the random number counter C1, and a fluctuation type counter CS that determines the display duration in the special symbol display unit 37a and the symbol display device 41. Furthermore, it uses a regular power mechanism open counter C4 used for the lottery for whether or not to set the regular power mechanism 34a of the second operation port 34 to the regular power open state. Note that each of the above counters C1 to C3, CINI, CS, and C4 are provided in the various counter areas 65b of the main RAM 65.

[0065] Each counter C1-C3, CINI, CS, and C4 is a loop counter in which 1 is added to the previous value each time it is updated, and it returns to "0" after reaching the maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in the reserve storage area 65a provided as an acquired information storage means in the main RAM 65 when a prize is awarded to the first operation port 33 or the second operation port 34.

[0066] The hold storage area 65a comprises a hold area RE and an execution area AE. The hold area RE comprises a first hold area RE1, a second hold area RE2, a third hold area RE3, and a fourth hold area RE4. In accordance with the winning history of the first operation port 33 or the second operation port 34, a combination of numerical information from the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as hold information in one of the hold areas RE1 to RE4.

[0067] In this case, when multiple consecutive entries into the first or second operating port 33 occur, the numerical information is stored chronologically in the first to fourth holding areas RE1, RE2, RE3, and RE4, respectively. With these four holding areas RE1 to RE4, up to four entries of the game ball entry history into the first or second operating port 33 can be stored in reserve.

[0068] Furthermore, the number of items that can be stored in reserve is not limited to four; it can be any number, such as two, three, five or more, or even a single item.

[0069] The execution area AE is an area for moving the numerical information stored in the first reserve area RE1 of the reserve area RE when the variable display of the special display unit 37a is started. At the start of each game round, a win / loss determination is made based on the various numerical information stored in the execution area AE.

[0070] The above counters will be explained in detail below.

[0071] First, let's explain the regular electric feature release counter C4. The regular electric feature release counter C4 is configured to increment by 1 sequentially within the range of 0 to 250, and then return to "0" after reaching the maximum value. The regular electric feature release counter C4 is updated periodically and stored in the regular electric reserve area 65c of the main RAM 65 when a game ball enters the through gate 35. Then, at a predetermined timing, a lottery is held to determine whether or not to control the regular electric feature 34a to the open state based on the value of the stored regular electric feature release counter C4.

[0072] In this pachinko machine 10, multiple support modes are set so that the manner of support provided by the electric power supply mechanism 34a differs from one another. Specifically, the support modes include a high-frequency support mode and a low-frequency support mode, which are set so that the frequency at which the electric power supply mechanism 34a of the second operating port 34 is open per unit time is relatively high or low when compared in a situation where game balls are continuously launched in the game area PA in a similar manner.

[0073] In both the high-frequency support mode and the low-frequency support mode, the probability of winning the normal electric power opening state in the normal electric power opening lottery using the normal electric power opening counter C4 is the same (for example, 4 / 5 in both modes). However, in the high-frequency support mode, the number of times the normal electric power opening state is opened when the normal electric power opening state is won is set to be greater than in the low-frequency support mode, and the duration of each opening is also set to be longer. In this case, when the normal electric power opening state is won in the high-frequency support mode and the normal electric power opening state of the normal electric power opening state occurs multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the duration of one opening. Furthermore, in the high-frequency support mode, the minimum time required to ensure that the next normal electric power opening lottery is held after one normal electric power opening lottery is held (i.e., the duration of one display in the normal electric power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0074] As described above, in high-frequency support mode, the probability of a ball entering the second operating port 34 is higher than in low-frequency support mode. In other words, in low-frequency support mode, the probability of a ball entering the first operating port 33 is higher than in the second operating port 34, but in high-frequency support mode, the probability of a ball entering the second operating port 34 is higher than in the first operating port 33. When a ball enters the second operating port 34, a predetermined number of game balls are dispensed, so in high-frequency support mode, players can play without significantly reducing their number of balls.

[0075] Furthermore, the configuration for making the high-frequency support mode more frequent than the low-frequency support mode in terms of the frequency of normal power opening per unit time is not limited to the above, and for example, a configuration that increases the probability of winning the normal power opening state in the normal power opening lottery may also be used. In addition, in a configuration where multiple types of reservation time are available for the period between one normal power opening lottery and the next normal power opening lottery (for example, the time for the variable display executed by the normal power display unit 38a based on the entry into the through gate 35), the high-frequency support mode may be set to be more likely to select a shorter reservation time or to have a shorter average reservation time than the low-frequency support mode. Moreover, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one of the following conditions or any combination of conditions: increasing the number of openings, increasing the opening time, decreasing the reservation time between one normal power opening lottery and the next normal power opening lottery, decreasing the average time of the reservation time, and increasing the probability of winning.

[0076] Next, let's explain the winning random number counter C1. The winning random number counter C1 is configured to increment by 1 sequentially within a range of, for example, 0 to 599, and then return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 completes one cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically and stored in the reserve storage area 65a of the main RAM 65 when a game ball enters the first operation opening 33 or the second operation opening 34.

[0077] The random number values ​​that result in a jackpot are stored in the main ROM 64 as a win / loss table. Two win / loss tables are set up: one for the low probability mode and one for the high probability mode. In other words, this pachinko machine 10 has a low probability mode and a high probability mode set up as the lottery mode for the win / loss lottery mechanism.

[0078] In the game state where the win / loss table for low probability mode is referenced during the above lottery, the number of random numbers that result in a jackpot is 2. On the other hand, in the game state where the win / loss table for high probability mode is referenced during the above lottery, the number of random numbers that result in a jackpot is 20. However, if the probability of winning is higher in high probability mode than in low probability mode, the number of random numbers that result in a jackpot is arbitrary.

[0079] The jackpot type counter C2 is configured to increment by 1 in the range of 0 to 29, and then return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically and stored in the reserve storage area 65a when a game ball enters the first operation opening 33 or the second operation opening 34.

[0080] In this pachinko machine 10, multiple jackpot results are set. These multiple jackpot results are set by making differences in three conditions: (1) the manner of opening and closing control of the special electric prize entry device 32 in the opening and closing execution mode, (2) the lottery mode in the win / loss lottery means after the opening and closing execution mode has ended, and (3) the support mode of the regular electric mechanism 34a of the second operating port 34 after the opening and closing execution mode has ended.

[0081] In the opening and closing execution mode, the opening and closing control of the special electric prize winning device 32 is configured such that the frequency of winning to the special electric prize winning device 32 during the period from the start to the end of the opening and closing execution mode is relatively high or low, with a high-frequency winning mode and a low-frequency winning mode being set. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the game is executed up to a predetermined number of rounds.

[0082] Here, a round game is a game that continues until either a predetermined maximum duration has elapsed, or a predetermined maximum number of game balls have entered the special electric prize winning device 32, is met. Furthermore, the number of round games in the opening / closing execution mode triggered by a jackpot result is fixed and the same regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the type of jackpot result, the maximum number of round games is set to 15 rounds.

[0083] Furthermore, in this pachinko machine 10, the opening mode of the special electric prize winning device 32 is set to have multiple variations, differing in the duration of opening from the time the special electric prize winning device 32 is opened until it is closed. Specifically, there is a long-duration mode in which the duration of opening is set to a long 29 seconds, and a short-duration mode in which the duration of opening is set to a shorter 0.06 seconds.

[0084] In this pachinko machine 10, when the launching device 28 is operated by the player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched towards the game area PA every 0.6 seconds. Also, the maximum number of balls required to complete a round game is set to 9. In this case, in the long-duration mode of opening, the opening duration is set to be longer than the product of the game ball launching cycle and the duration of one round game. On the other hand, in the short-duration mode, the opening duration is set to be shorter than the product of the game ball launching cycle and the duration of one round game, or more specifically, shorter than the game ball launching cycle. Therefore, when an opening occurs in the long-duration mode, it is expected that the special electric prize winning device 32 will receive the maximum number of balls that can be won in one round game, while when an opening occurs in the short-duration mode, it is expected that no balls will be won into the special electric prize winning device 32, or that only about one ball will be won.

[0085] In the high-frequency winning mode, the special electric winning device 32 is opened once in a long-duration manner during each round of gameplay. On the other hand, in the low-frequency winning mode, the special electric winning device 32 is opened once in a short-duration manner during each round of gameplay.

[0086] Furthermore, the number of times the special electric prize device 32 is opened and closed, the number of rounds played, the duration of opening for each opening, and the maximum number of prizes per round in the high-frequency prize mode and low-frequency prize mode are not limited to the above values ​​and are arbitrary, as long as the frequency of prizes entering the special electric prize device 32 from the start to the end of the opening and closing execution mode is higher in the high-frequency prize mode than in the low-frequency prize mode.

[0087] The distribution of game results for the jackpot type counter C2 is stored as a distribution table in the main ROM 64. The distribution destinations are set as low probability jackpot results, low-scoring high probability jackpot results, and most advantageous jackpot results.

[0088] A low-probability jackpot result is one in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the win / loss lottery mode becomes the low-probability mode, and the support mode becomes the high-frequency support mode. However, this high-frequency support mode will revert to the low-frequency support mode if the number of games played after the transition reaches the termination threshold (specifically, 100 games).

[0089] A low-stakes, high-probability jackpot result is one in which the opening / closing execution mode becomes the low-frequency winning mode, and after the opening / closing execution mode ends, the win / fail lottery mode becomes the high-probability mode, and the support mode becomes the high-frequency support mode. These high-probability modes and high-frequency support modes continue until the lottery result in a jackpot state is won, and the game transitions to the jackpot state as a result.

[0090] The most advantageous jackpot result is one in which the opening / closing execution mode becomes a high-frequency winning mode, and after the opening / closing execution mode ends, the win / fail lottery mode becomes a high-probability mode, and the support mode becomes a high-frequency support mode. These high-probability modes and high-frequency support modes continue until the lottery result in a jackpot state is won, and the game transitions to the jackpot state.

[0091] Furthermore, in relation to the above game states, the "normal game state" refers to a state that is not in the opening / closing execution mode, and furthermore, the win / loss lottery mode is in the low probability mode, and the support mode is in the low-frequency support mode. In addition, the game result may be configured so that a low-winning, high-probability jackpot result is not set. Also, in the opening / closing execution mode for the low-winning, high-probability jackpot result, the number of rounds played may be configured to be fewer than in the case of the low-probability jackpot result and the most advantageous jackpot result.

[0092] In the distribution table, among the values ​​of the jackpot type counter C2 from "0 to 29", "0 to 9" correspond to low probability jackpot results, "10 to 14" correspond to low-winning high probability jackpot results, and "15 to 29" correspond to the most advantageous jackpot results.

[0093] Next, the reach random number counter C3 will be explained. The reach random number counter C3 is configured to increment by 1 sequentially within the range of 0 to 238, for example, and then return to "0" after reaching the maximum value. Here, in this pachinko machine 10, an expectation effect is set as a type of display effect in the symbol display device 41. An expectation effect is a display state that makes the player think that the symbol display state is likely to result in the aforementioned assigned result, in a game machine equipped with a symbol display device 41 capable of displaying changing symbols, where the final stop result in a game round that results in a predetermined jackpot is the assigned result. This occurs in the stage from when the changing symbol display on the symbol display device 41 starts until the stop result is derived and displayed. Specifically, the assigned result is a combination of symbols with the same number on any of the active lines that is displayed as a stop.

[0094] There are two types of anticipation-based effects: a "reach" display and a pre-announcement display that anticipates the occurrence of a reach display or the corresponding result before the reach display occurs.

[0095] The reach display includes a display state in which a combination of reach symbols is displayed by stopping the symbols in some of the multiple symbol sequences displayed on the display surface 41a of the symbol display device 41, and then the remaining symbol sequences are displayed in a variable state. Furthermore, the reach effect is performed by displaying the combination of reach symbols as described above, then displaying the remaining symbol sequences in a variable state, and displaying predetermined characters as animations on the background screen, or by reducing or hiding the combination of reach symbols, and then displaying predetermined characters as animations on almost the entire display surface 41a to perform the reach effect.

[0096] The notification display includes a mode in which a character is displayed separately from the symbols on the symbol rows when the symbol variation display has started on the display surface 41a of the symbol display device 41, and when the symbols are varying in all symbol rows, or when the symbols are varying in some symbol rows but multiple symbol rows are varying. It also includes modes in which the background screen is changed to a predetermined mode different from the previous mode, or when the symbols on the symbol rows are changed to a predetermined mode different from the previous mode. Such notification displays can occur in both game rounds when a reach display is made and when a reach display is not made, but they are set to occur with a higher probability when a reach display is made than when a reach display is not made.

[0097] The reach display is executed regardless of the value of the reach random number counter C3 in game rounds where the same combination of symbols ultimately stops and is displayed. Also, in game rounds corresponding to a jackpot result where the same combination of symbols does not stop and is not displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Furthermore, in game rounds corresponding to a losing result, the reach display is executed if the reach random number counter C3, obtained at a predetermined timing by referring to the reach table stored in the main ROM 64, corresponds to the occurrence of a reach display.

[0098] On the other hand, the decision of whether or not to display a notification is made not by the main control device 60, but by the sound and light emission control device 81. In this case, the sound and light emission control device 81 executes a lottery process for displaying notifications so that at least one of the following conditions is met: the notification is more likely to occur in the game round corresponding to a jackpot result compared to the game round corresponding to a losing result, and the notification with a low appearance rate is more likely to occur. Incidentally, the result of this lottery is reflected when the game round's effects are executed by the symbol display device 41.

[0099] Next, the variation type counter CS will be explained. The variation type counter CS is configured to increment by 1 sequentially within a range of, for example, 0 to 198, and then return to "0" after reaching the maximum value. The variation type counter CS is used by the main CPU 63 to determine the display duration in the special display unit 37a and the display duration of the symbols in the symbol display device 41. The variation type counter CS is updated once each time the normal processing described later is executed, and is repeatedly updated even within the remaining time of the normal processing. The buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variation display in the special display unit 37a and at the start of the variation of the symbols by the symbol display device 41.

[0100] <Regarding the processing configuration of the main CPU63> Next, we will explain the processes executed by the main CPU 63 to advance the game. These processes of the main CPU 63 can be broadly divided into the main process, which is started when the power is turned on, and the timer interrupt process, which is started periodically (at a 4 msec cycle in this embodiment).

[0101] <Main Processing> First, we will explain the main process while referring to the flowchart in Figure 7.

[0102] First, a power-on wait process is performed (step S101). In this power-on wait process, for example, the system waits without proceeding to the next process until a predetermined waiting time (specifically 1 second) has elapsed after the main process has started. During the execution period of this power-on wait process, the operation start and initial setup of the graphic display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102), and the internal function registers of the main CPU 63 are set (step S103).

[0103] Subsequently, it is determined whether the RAM erase switch on the power supply / launch control device 78 has been manually operated (step S104), and further, it is determined whether the power outage flag of the main RAM 65 is set to "1" (step S105). In addition, a checksum calculation process is performed to calculate a checksum (step S106), and it is determined whether the checksum matches the checksum saved when the power was cut off, that is, the validity of the stored data (step S107).

[0104] In this pachinko machine 10, when the RAM data is initialized when the power is turned on, for example, at the start of business at the gaming hall, the RAM erase switch is pressed while the power is turned on. Therefore, if the RAM erase switch is pressed, the process proceeds to step S108. Similarly, if the information about the occurrence of a power outage is not set, or if an abnormality in the stored data is confirmed by the checksum, the process also proceeds to step S108. In step S108, the main RAM 65 is cleared. After that, the process proceeds to step S109.

[0105] On the other hand, if the RAM erase switch is not pressed, and provided that the power outage flag is set to "1" and the checksum is normal, the process in step S108 is not executed and the process proceeds to step S109. In step S109, the power-on setting process is executed. In the power-on setting process, predetermined areas of the main RAM 65, such as the power outage flag, are set to their initial values, and a command corresponding to the current game state is sent to the sound and light emission control device 81. After executing the process in step S109, a recognition process (step S110) is executed to allow the management IC 66 to recognize various information, and a data output process (step S111) is executed to output various data to a reader connected to the MPU 62. Details of these recognition and data output processes will be explained later.

[0106] The main CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited when the main processing starts. This state of prohibition on timer interrupt processing is released when the processing in step S111 is completed and before the processing in step S112 is executed, and the execution of timer interrupt processing is permitted. As a result, when power supply to the main CPU 63 is started, the timer interrupt processing will not be executed until the data output processing in step S111 is completed and before the processing in step S112 is started. Therefore, until this situation occurs, the processing to advance the game will not be started in the main CPU 63.

[0107] Subsequently, the process proceeds to the residual processing steps S112 to S115. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is residual time between one timer interrupt processing and the next. This residual time will vary depending on the processing completion time of each timer interrupt processing, and the residual processing steps S112 to S115 are repeatedly executed using this irregular time. In this respect, the residual processing steps S112 to S115 can be said to be an irregular process that is executed irregularly.

[0108] In the remaining processing, first in step S112, the interrupt disable setting is performed to prevent the occurrence of timer interrupt processing. In the following step S113, the random number initial value update process is executed to update the random number initial value counter CINI, and in step S114, the variation counter update process is executed to update the variation type counter CS. In these update processes, the current numerical information is read from the corresponding counter in the main RAM 65, the read numerical information is incremented by 1, and then the original counter is overwritten. In this case, when the counter value reaches the maximum value, it is cleared to "0". After that, in step S115, the interrupt enable setting is performed to switch from a state where the occurrence of timer interrupt processing is prohibited to a state where it is enabled. After the process in step S115 is executed, the process returns to step S112 and steps S112 to S115 are repeated.

[0109] <Timer interrupt handling> Next, we will explain the timer interrupt handling process while referring to the flowchart in Figure 8. The timer interrupt handling process is executed periodically (for example, every 4 msec).

[0110] First, the power outage information storage process is executed (step S201). In the power outage information storage process, the power outage monitoring board 67 monitors whether or not a power outage signal corresponding to the occurrence of a power interruption has been received. If a power outage is identified, the power outage processing is executed, followed by an infinite loop. In the power outage processing, the power outage flag in the main RAM 65 is set to "1", a checksum is calculated, and the calculated checksum is saved.

[0111] Subsequently, the random number update process for the lottery is executed (step S202). In the random number update process for the lottery, the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal electric device release counter C4 are updated. Specifically, the current numerical information is read sequentially from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal electric device release counter C4, and after the read numerical information is incremented by 1, the original counters are overwritten. In this case, when the counter value reaches the maximum value, it is cleared to "0". Subsequently, in step S203, the random number initial value update process is executed in the same way as in step S113, and in step S204, the variable counter update process is executed in the same way as in step S114.

[0112] Subsequently, a fraud detection process is executed to monitor whether a predetermined event, which is set as a target for monitoring fraud, has occurred (step S205). In this fraud detection process, the occurrence of multiple types of events is monitored, and upon confirming that a predetermined event has occurred, the game stop flag provided in the main RAM 65 is set to "1". In the following step S206, it is determined whether the game has stopped by checking whether the game stop flag is set to "1". If the determination in step S206 is negative, the processes from step S207 onwards are executed.

[0113] In step S207, port output processing is performed. In port output processing, if output information was set in the previous timer interrupt processing, processing is performed to output the corresponding output information to the various drive units 32b and 34b. For example, if information is set to switch the special electric prize device 32 to the open state, the output of a drive signal to the special electric drive unit 32b is started, and if information is set to switch it to the closed state, the output of the drive signal is stopped. Also, if information is set to switch the regular electric mechanism 34a of the second operating port 34 to the open state, the output of a drive signal to the regular electric drive unit 34b is started, and if information is set to switch it to the closed state, the output of the drive signal is stopped.

[0114] Subsequently, a read operation is performed (step S208). In the read operation, signals other than the power outage signal and the prize winning signal are read, and the read information is stored for use in subsequent processing.

[0115] Subsequently, ball entry detection processing is performed (step S209). In this ball entry detection processing, signals received from each ball entry detection sensor 42a to 49a are read, and based on the reading results, it is determined whether or not a ball has entered the out gate 24a, the general prize gate 31, the special electric prize device 32, the first operation gate 33, the second operation gate 34, and the through gate 35. Details of the ball entry detection processing will be explained later.

[0116] Subsequently, a timer update process is executed to update the numerical information of multiple types of timer counters provided in the main RAM 65 (step S210). In this case, the configuration is to aggregate and handle timer counters whose stored numerical information is updated by subtraction, but it is also possible to aggregate and perform updates for both subtraction-type timer counters and addition-type timer counters.

[0117] Subsequently, a launch control process is executed to control the launch of the game balls (step S211). If the launch operation to the launch operation device 28 is continued, one game ball is launched every 0.6 seconds, which is a predetermined launch cycle. In the following step S212, as an input state monitoring process, based on the information read in the reading process of step S208, the system checks for disconnections in each ball entry detection sensor 42a to 49a and confirms that the game machine body 12 and the front door frame 14 are open.

[0118] Subsequently, a special feature and special electric control process is executed to control the execution of game rounds and the execution of the opening and closing execution mode (step S213). In this special feature and special electric control process, if a prize is won into the first operation port 33 or the second operation port 34 while the number of reserved information stored in the reserved storage area 65a is less than the upper limit, the process is executed to store the numerical information of the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 at that time as reserved information in chronological order in the reserved storage area 65a. Furthermore, in the special feature and special electric control process, provided that it is not during a game round or the opening and closing execution mode and that reserved information is stored, a win / failure determination process is executed to determine whether the reserved information corresponds to a jackpot win, and if it corresponds to a jackpot win, a distribution determination process is executed to determine which jackpot result the reserved information corresponds to. Furthermore, in the special symbol and special electric control processing, in addition to the win / loss determination processing and distribution determination processing, if the held information does not correspond to a big win, a reach determination processing is executed to determine whether or not the held information corresponds to a reach occurrence, and a process is executed to select the duration of the game round using the numerical information of the variation type counter CS at that time. Then, a variation command containing information on the duration according to the results of each of these processes and a type command containing information on the game result are transmitted to the sound and light emission control device 81, and the variation display of the symbols on the special symbol display unit 37a is started. Upon receiving the variation command and type command, the sound and light emission control device 81 starts the game round effects corresponding to the content of these commands on the display and light emission unit 53 and speaker unit 54. The sound and light emission control device 81 also transmits a variation pattern command corresponding to the content of the variation command and type command to the display control device 82. Upon receiving the variation pattern command, the display control device 82 starts the variation display of the symbols corresponding to the content of the variation pattern command on the symbol display device 41. This puts the game round into a state where one game round has started.

[0119] In the special feature control process, during the execution of one game round, it is determined whether the duration of the game round, which was determined at the start of the game round, has elapsed, thereby determining whether it is time to end the game round. If it is time to end the game round, the process to end the game round is executed with a display corresponding to the game result. In this case, if the current game round corresponds to the occurrence of any jackpot result, the symbols corresponding to the type of jackpot result are stopped and displayed on the special feature display unit 37a, and if the current game round corresponds to a losing result, the symbols corresponding to the losing result are stopped and displayed on the special feature display unit 37a. A final stop command indicating that the game round should be ended is also sent to the sound and light emission control device 81. Upon receiving the final stop command, the sound and light emission control device 81 terminates the effects for the current game round in the display and light emission unit 53 and the speaker unit 54. The sound and light emission control device 81 also sends the final stop command to the display control device 82. Upon receiving the final stop command, the display control device 82 terminates the effects for the current game round in the symbol display device 41.

[0120] In the special feature special electric control processing, if the result of the game round corresponds to a transition to the opening / closing execution mode, processing is executed to start the opening / closing execution mode. At this start, an opening command indicating that the opening / closing execution mode is starting is sent to the sound and light emission control device 81. In addition, the special feature special electric control processing executes processing to start each round of gameplay and processing to end each round of gameplay. When a round of gameplay starts, the special electric prize winning device 32 is opened, and when a round of gameplay ends, the special electric prize winning device 32 is closed. In each of these processes, an opening command indicating that a round of gameplay is starting is sent to the sound and light emission control device 81, and a closing command indicating that a round of gameplay is ending is also sent to the sound and light emission control device 81. In addition, when the opening / closing execution mode is ending, the special feature special electric control processing sends an ending command indicating this to the sound and light emission control device 81. The sound and light emission control device 81 executes effects for the opening / closing execution mode in the display and light emission unit 53 and the speaker unit 54 in a manner corresponding to the various commands received during the opening / closing execution mode. Furthermore, the sound and light emission control device 81 transmits a command corresponding to the command received during the opening / closing execution mode to the display control device 82. The display control device 82 causes the symbol display device 41 to execute the effects for the opening / closing execution mode in a manner corresponding to the various commands received during the opening / closing execution mode. In addition, in the special symbol special electric control processing, when the opening / closing execution mode is terminated, processing is performed to ensure that the win / loss lottery mode and support mode after the termination of the opening / closing execution mode become modes corresponding to the type of jackpot result that triggered the execution of the opening / closing execution mode.

[0121] In the timer interrupt processing, after executing the special feature special power control processing in step S213, the normal feature normal power control processing is executed (step S214). In the normal feature normal power control processing, if a prize is awarded to the through gate 35, processing is performed to acquire the normal feature side hold information. If the normal feature side hold information is stored, an open determination is made for that hold information, and processing is performed to perform a normal feature effect triggered by that open determination. Furthermore, based on the result of the open determination, processing is performed to open and close the normal power mechanism 34a of the second operation port 34. In this case, if the support mode is the low-frequency support mode, the corresponding processing is executed, and if the support mode is the high-frequency support mode, the corresponding processing is executed. Also, if the open / close execution mode is selected, the support mode will be the low-frequency support mode even if the previous support mode was the high-frequency support mode.

[0122] In the following step S215, based on the processing results of the preceding steps S213 and S214, output information is set to reflect the increase or decrease in the number of reserved information related to the special figure display unit 37a in the special figure reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information related to the general figure display unit 38a in the general figure reserved display unit 38b. Also in step S215, based on the processing results of the preceding steps S213 and S214, output information is set to update the display content of the special figure display unit 37a, and output information is set to update the display content of the general figure display unit 38a.

[0123] Subsequently, the system checks the contents of the commands and signals received from the payout control device 77 and executes a payout status reception process to perform processing corresponding to the confirmation results (step S216). It also executes a payout output process to set the prize ball command as the output target (step S217). Furthermore, it executes an external information setting process to control the start and end of the output of external signals according to the processing results of the various processes performed in this timer interrupt process (step S218). Finally, it executes a management output process to output information corresponding to the ball entry results in the game area PA to the management IC 66 (step S219). Details of the management output process will be explained later.

[0124] Next, we will explain the configuration for the main CPU 63 to determine whether or not a game ball has entered the out gate 24a, the general prize gate 31, the special electric prize device 32, the first operation gate 33, the second operation gate 34, and the through gate 35, based on the detection results of each ball entry detection sensor 42a to 49a. Figure 9 is an explanatory diagram illustrating the configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

[0125] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface to handle eight types of signals simultaneously. Each terminal has a corresponding area where information of "0" or "1" is stored according to the voltage of each signal. Specifically, this area consists of bits 0 (D0) to 7 (D7). In addition, more than eight types of signals may be input to the input port 63a, but in order to limit the number of signals that can be input simultaneously to eight, the group of signals that can be input to the input port 63a is switched via switching control by a driver IC.

[0126] In the ball entry detection process (step S209) of the timer interrupt processing (Figure 8), the group of signals to be input to the input port 63a is set to the group of signals from each ball entry detection sensor 42a to 49a. In this setting, the 0th bit D0 stores information corresponding to the detection signal from the 1st prize entry detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the 2nd prize entry detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the 3rd prize entry detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special electric detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the 1st operation entry detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the 2nd operation entry detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the out entry detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

[0127] Each of the ball entry detection sensors 42a to 49a outputs a LOW level signal indicating no detection when it does not detect the passage of a game ball, and outputs a HI level signal indicating detection when it does detect the passage of a game ball. The input port 63a stores "0" information in the corresponding bit when it receives a LOW level signal, and stores "1" information in the corresponding bit when it receives a HI level signal. In other words, when the ball entry detection sensors 42a to 49a do not detect the passage of a game ball, "0" information corresponding to the information indicating no detection is stored in the corresponding bit, and when the passage of a game ball is detected, "1" information corresponding to the information indicating detection is stored in the corresponding bit.

[0128] Figure 10 is a flowchart showing the ball entry detection process executed in step S209 of the timer interrupt processing (Figure 8).

[0129] When it is confirmed that the state in the 0th bit D0 has switched from storing the information "0" to storing the information "1", the first prize-winning slot detection sensor 42a determines that one game ball has been detected (step S301: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S302), and the value of the 10-ball payout counter provided in the main RAM 65 is incremented by 1 (step S303). The first output flag is a flag used by the main CPU 63 to determine that the management IC 66 should output information indicating that one game ball has been detected by the first prize-winning slot detection sensor 42a. The 10-ball payout counter is a counter used by the main CPU 63 to determine the number of times the payout of 10 game balls should be performed. If the value of the 10-prize ball counter is 1 or greater, the payout output process in step S217 of the timer interrupt processing (Figure 8) outputs a 10-prize ball command to the payout control device 77, and the value of the 10-prize ball counter is decremented by 1 each time the 10-prize ball command is output. When the payout control device 77 receives the 10-prize ball command, it drives and controls the payout device 76 so that 10 game balls are dispensed.

[0130] When it is confirmed that the first bit D1 has switched from storing the information "0" to storing the information "1", the second prize-winning slot detection sensor 43a determines that one game ball has been detected (step S304: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S305), and the value of the 10-ball prize counter provided in the main RAM 65 is incremented by 1 (step S306). The second output flag is a flag used by the main CPU 63 to specify to the management IC 66 that it should output information indicating that one game ball has been detected by the second prize-winning slot detection sensor 43a.

[0131] When it is confirmed that the second bit D2 has switched from storing the information "0" to storing the information "1", the third prize-winning slot detection sensor 44a determines that one game ball has been detected (step S307: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S308), and the value of the 10-prize ball counter provided in the main RAM 65 is incremented by 1 (step S309). The third output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the third prize-winning slot detection sensor 44a.

[0132] When it is confirmed that the third bit D3 has switched from storing the information "0" to storing the information "1", the special electric detection sensor 45a determines that one game ball has been detected (step S310: YES). In this case, the special electric prize flag provided in the main RAM 65 is set to "1" (step S311), the fourth output flag provided in the main RAM 65 is set to "1" (step S312), and the value of the 15-ball prize counter provided in the main RAM 65 is incremented by 1 (step S313). The special electric prize flag is a flag used by the main CPU 63 to identify that one game ball has entered the special electric prize device 32 during a round game in the opening / closing execution mode. In the timer interrupt processing (Figure 8), the special feature special electric control processing (step S213) confirms that the special electric prize entry flag is set to "1", thereby identifying that one game ball has entered the special electric prize entry device 32, and the remaining number of balls that can enter the special electric prize entry device 32 in the round game is reduced by 1. When this process of reducing the number of balls that can enter by 1 is executed, the special electric prize entry flag is cleared to "0". The fourth output flag is a flag used by the main CPU 63 to identify that the management IC 66 should output information indicating that one game ball has been detected by the special electric detection sensor 45a. The 15-ball prize counter is a counter used by the main CPU 63 to identify the number of times that 15 game balls should be dispensed. If the value of the 15-prize ball counter is 1 or greater, the payout output process in step S217 of the timer interrupt processing (Figure 8) outputs a 15-prize ball command to the payout control device 77, and if the 15-prize ball command is output once, the value of the 15-prize ball counter is decremented by 1. When the payout control device 77 receives the 15-prize ball command, it drives and controls the payout device 76 so that 15 game balls are dispensed.

[0133] When it is confirmed that the information stored in the 4th bit D4 has switched from "0" to "1", the first operation port detection sensor 46a determines that one game ball has been detected (step S314: YES). In this case, the first operation entry flag provided in the main RAM 65 is set to "1" (step S315), the 5th output flag provided in the main RAM 65 is set to "1" (step S316), and the value of the 1-ball prize counter provided in the main RAM 65 is incremented by 1 (step S317). The first operation entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the first operation port 33. In the timer interrupt processing (Figure 8), the special feature special electric control processing (step S213) confirms that the first operation prize flag is set to "1", and if the number of reserve information stored in the reserve area RE of the reserve storage area 65a is less than the upper limit of 4, the processing to newly store reserve information is executed. In the special electric electric control processing (step S213), if it is confirmed that the first operation prize flag is set to "1" and the processing corresponding to that confirmation is executed, the first operation prize flag is cleared to "0". The fifth output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the first operation port detection sensor 46a. The single prize ball counter is a counter used by the main CPU 63 to specify the number of times that one game ball should be dispensed. If the value of the single-prize ball counter is 1 or greater, the payout output process in step S217 of the timer interrupt processing (Figure 8) outputs a single-prize ball command to the payout control device 77, and if the single-prize ball command is output once, the value of the single-prize ball counter is decremented by 1. When the payout control device 77 receives a single-prize ball command, it drives and controls the payout device 76 so that one game ball is dispensed.

[0134] When it is confirmed that the information stored in the 5th bit D5 has switched from "0" to "1", the second operation port detection sensor 47a determines that one game ball has been detected (step S318: YES). In this case, the second operation entry flag provided in the main RAM 65 is set to "1" (step S319), the 6th output flag provided in the main RAM 65 is set to "1" (step S320), and the value of the 1-ball prize counter provided in the main RAM 65 is incremented by 1 (step S321). The second operation entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the second operation port 34. In the timer interrupt processing (Figure 8), the special feature special electric control processing (step S213) confirms that the second operation winning flag is set to "1", and if the number of hold information stored in the hold area RE of the hold storage area 65a is less than the upper limit of 4, the processing to newly store hold information is executed. In the special electric electric control processing (step S213), if it is confirmed that the second operation winning flag is set to "1" and the processing corresponding to that confirmation is executed, the second operation winning flag is cleared to "0". The sixth output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the second operation opening detection sensor 47a.

[0135] When it is confirmed that the information stored in the 6th bit D6 has switched from "0" to "1", the out-port detection sensor 48a determines that one game ball has been detected (step S322: YES). In this case, the 7th output flag provided in the main RAM 65 is set to "1" (step S323). The 7th output flag is a flag used by the main CPU 63 to specify that the management IC 66 should output information indicating that one game ball has been detected by the out-port detection sensor 48a.

[0136] When it is confirmed that the 7th bit D7 has switched from storing the information "0" to storing the information "1", the gate detection sensor 49a determines that one game ball has been detected (step S324: YES). In this case, the gate entry flag provided in the main RAM 65 is set to "1" (step S325). The gate entry flag is a flag used by the main CPU 63 to identify that one game ball has entered the through gate 35. In the timer interrupt processing (Figure 8), the normal power control processing (step S214) confirms that the gate entry flag is set to "1", and, provided that the number of normal power reserve information stored in the normal power reserve area 65c is less than the upper limit of 4, the current numerical information of the normal power mechanism release counter C4 is stored in the normal power reserve area 65c as normal power reserve information. In the general power control process (step S214), it is confirmed that the gate entry flag is set to "1", and if the process corresponding to that confirmation is executed, the gate entry flag is cleared to "0".

[0137] As explained earlier, the timer interrupt processing (Figure 8) is activated at a 4 msec cycle. Therefore, when one ball entry detection sensor 42a to 49a starts detecting one game ball, the main CPU 63 identifies that one game ball has been detected by the ball entry detection sensor 42a to 49a while the sensor continues to detect that one game ball. Consequently, it is sufficient to have one of each of the first to seventh output flags.

[0138] Next, we will explain the processing performed by the dispensing control device 77. First, we will explain the electrical configuration of the dispensing control device 77 and the various devices that communicate with the dispensing control device 77, referring to the block diagram in Figure 11.

[0139] The payout control device 77 is equipped with an MPU 91. In addition to the payout-side CPU 92, which is an arithmetic processing unit including a control unit and an arithmetic unit, the MPU 91 also incorporates a payout-side ROM 93, a payout-side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, and the like.

[0140] The dispensing-side ROM 93 is a memory (i.e., a non-volatile storage means) that does not require an external power supply for storage, such as NOR-type flash memory and NAND-type flash memory, and is used for read-only purposes. The dispensing-side ROM 93 stores various control programs and fixed value data executed by the dispensing-side CPU 92.

[0141] The dispensing-side RAM 94 is a memory (i.e., volatile memory) that requires an external power supply for memory retention, such as SRAM and DRAM, and is used for both reading and writing. The dispensing-side RAM 94 allows random access and, when compared with the same data capacity, has a faster read time than the dispensing-side ROM 93. The dispensing-side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing-side ROM 93.

[0142] The payout-side CPU 92 is capable of bidirectional communication with the main-side CPU 63. Upon receiving a prize ball command from the main-side CPU 63, the payout-side CPU 92 drives and controls the payout device 76 so that the number of game balls corresponding to the prize ball command are dispensed. The payout-side CPU 92 also monitors whether it is possible to dispense game balls normally, and if it determines that it is not possible to dispense them normally, it stops the payout device 76 even if the payout-side RAM 94 has information on the number of undispensed prize balls stored in it. The payout-side CPU 92 also sends a payout restriction command to the main-side CPU 63 indicating that it is not possible to dispense game balls normally. Upon receiving this payout restriction command, the main-side CPU 63 sends a notification command to the sound and light emission control device 81 so that a notification indicating that it is not possible to dispense game balls normally is executed by the symbol display device 41, the display light emission unit 53, and the speaker unit 54. The following states make it impossible to dispense game balls normally: a full state where the lower tray 56a is completely filled with game balls; a ball-less state where the tank 75 is not replenished with game balls; a payout abnormal state where the payout device 76 does not operate normally; a body-open state where the game machine body 12 is separated from the outer frame 11; and a front door open state where the front door frame 14 is separated from the inner frame 13.

[0143] A full-tank detection sensor (not shown) is provided at an intermediate position in the game ball passage leading from the payout device 76 to the lower tray 56a, and the detection result of the full-tank detection sensor is input to the payout-side CPU 92. The payout-side CPU 92 determines that the machine is full when the full-tank detection sensor continuously detects game balls, and determines that the machine is no longer full when the full-tank detection sensor stops continuously detecting game balls.

[0144] A ball-less detection sensor (not shown) is installed at an intermediate position in the game ball passage leading from the tank 75 to the payout device 76, and the detection result of the ball-less detection sensor is input to the payout-side CPU 92. The payout-side CPU 92 identifies a ball-less state when no game balls are continuously detected by the ball-less detection sensor, and identifies the ball-less state as being released when the state of no game balls being continuously detected by the ball-less detection sensor is released.

[0145] The dispensing device 76 is equipped with a dispensing detection sensor (not shown) for detecting game balls dispensed from the dispensing device 76, and the detection result of the dispensing detection sensor is input to the dispensing-side CPU 92. The dispensing-side CPU 92 determines that one game ball has been dispensed from the dispensing device 76 when a game ball is detected by the dispensing detection sensor. Furthermore, the dispensing-side CPU 92 determines that there is a dispensing abnormality if the dispensing device 76 is being driven and controlled to dispense game balls, but no game balls are continuously detected by the dispensing detection sensor, and determines that the dispensing abnormality has been resolved when the state in which no game balls are continuously detected by the dispensing detection sensor is resolved.

[0146] A front door open sensor 95 is provided on the front of the inner frame 13 (see Figure 2), and the detection result of the front door open sensor 95 is input to the dispensing side CPU 92. In this case, if the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 sends a closed detection signal to the dispensing side CPU 92, and if the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 sends an open detection signal to the dispensing side CPU 92. The dispensing side CPU 92 identifies the front door frame 14 as closed when it receives a closed detection signal from the front door open sensor 95, and identifies the front door frame 14 as open when it receives an open detection signal from the front door open sensor 95. Furthermore, the dispensing side CPU 92 sends a front door open command to the main side CPU 63 when it identifies that the front door frame 14 has changed from a closed state to an open state, and sends a front door closed command to the main side CPU 63 when it identifies that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when it receives a front door open command, and determines that the front door frame 14 is in a closed state when it receives a front door close command.

[0147] A main unit open sensor 96 is provided on the front of the back pack unit 15 (see Figure 2), and the detection result of the main unit open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main unit 12 is closed relative to the outer frame 11, the main unit open sensor 96 sends a closed detection signal to the payout side CPU 92, and when the gaming machine main unit 12 is open relative to the outer frame 11, the main unit open sensor 96 sends an open detection signal to the payout side CPU 92. The payout side CPU 92 identifies the gaming machine main unit 12 as being in a closed state when it receives a closed detection signal from the main unit open sensor 96, and identifies the gaming machine main unit 12 as being in an open state when it receives an open detection signal from the main unit open sensor 96. Furthermore, when the payout side CPU 92 identifies that the gaming machine main unit 12 has changed from a closed state to an open state, it sends a main unit open command to the main side CPU 63, and when it identifies that the gaming machine main unit 12 has changed from an open state to a closed state, it sends a main unit closed command to the main side CPU 63. The main CPU 63 determines that the gaming machine body 12 is in an open state when it receives a main unit open command, and determines that the gaming machine body 12 is in a closed state when it receives a main unit close command.

[0148] Referring to the time chart in Figure 12, we will explain the timer interrupt processing executed by the payout CPU 92. The timer interrupt processing is repeatedly activated at a predetermined period (for example, 2 msec).

[0149] First, the full tank processing is performed (step S401). In the full tank processing, as already explained, it is determined whether or not the tank is full based on the detection result of the full tank detection sensor. If the tank is full, processing is performed to stop the payout of game balls, and a command indicating that the tank is full is sent to the main CPU 63. If the full tank state is released, processing is performed to enable the payout of game balls, and a command indicating that the full tank state has been released is sent to the main CPU 63.

[0150] Subsequently, the ball-dead state processing is performed (step S402). In the ball-dead state processing, as already explained, it is determined whether or not there are no balls based on the detection result of the ball-dead detection sensor. If there are no balls, processing is performed to stop the payout of game balls, and a command indicating that there are no balls is sent to the main CPU 63. If the ball-dead state is resolved, processing is performed to enable the payout of game balls, and a command indicating that the ball-dead state has been resolved is sent to the main CPU 63.

[0151] Subsequently, the payout abnormality monitoring process is executed (step S403). In the payout abnormality monitoring process, as already explained, the system determines whether or not there is a payout abnormality based on the detection result of the payout detection sensor. If there is a payout abnormality, the system executes a process to stop the payout of game balls and sends a command to the main CPU 63 indicating that there is a payout abnormality. If the payout abnormality is resolved, the system executes a process to enable the payout of game balls and sends a command to the main CPU 63 indicating that the payout abnormality has been resolved.

[0152] Subsequently, the front door open monitoring process is executed (step S404). In the front door open monitoring process, as already explained, the system determines whether the front door frame 14 is open or not based on the detection result of the front door open sensor 95. If the front door frame 14 is open, the system executes a process to stop the payout of game balls and sends a front door open command to the main CPU 63. If the front door frame 14 is closed, the system executes a process to enable the payout of game balls and sends a front door closed command to the main CPU 63.

[0153] Subsequently, the main unit open monitoring process is executed (step S405). In the main unit open monitoring process, as already explained, it is determined whether or not the gaming machine main unit 12 is in an open state based on the detection result of the main unit open sensor 96. If the gaming machine main unit 12 is in an open state, a process is executed to stop the payout of game balls, and a main unit open command is sent to the main CPU 63. If the gaming machine main unit 12 is closed, a process is executed to enable the payout of game balls, and a main unit closed command is sent to the main CPU 63.

[0154] Subsequently, a command reading process is executed (step S406). In this command reading process, a process is executed to read the prize ball command sent by the main CPU 63. Then, the prize ball command is stored in the payout RAM 94. After executing a prize ball setting process to add the number corresponding to the received prize ball command to the unpaid prize ball count information in the payout RAM 94 (step S407), a payout control process is executed to control the execution of the payout of game balls by the payout device 76 (step S408). In the payout control process, if the unpaid prize ball count information stored in the payout RAM 94 is a value of 1 or more, the drive control of the payout device 76 is performed, and when one game ball is detected by the payout detection sensor, the value of the prize ball count information is deducted by 1. Then, when the value of the prize ball count information becomes "0", the drive control of the payout device 76 is stopped. Subsequently, an external information setting process is executed to control the start and end of the output of external signals according to the processing results of the various processes performed in this timer interrupt process (step S409).

[0155] Next, we will explain the configuration for outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall.

[0156] As shown in Figure 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with numerous external terminals, some of which are electrically connected to the main CPU 63, and some of which are electrically connected to the payout CPU 92. Because the main CPU 63 and the payout CPU 92 are each electrically connected to the external terminal board 97 in this way, as shown in Figure 11, the main CPU 63 and the payout CPU 92 can output information to the hall computer HC.

[0157] One external terminal on the external terminal board 97 is electrically connected to the front door open sensor 95, and another external terminal on the external terminal board 97 is electrically connected to the main unit open sensor 96. In detail regarding the configuration of this electrical connection, a signal relay board 98 is provided at an intermediate position in the signal path from the front door open sensor 95 to the payout side CPU 92. The signal relay board 98 is provided with a branch path SL2 that branches off from the signal path SL1 from the front door open sensor 95 to the payout side CPU 92. This branch path SL2 is connected to the external terminal for front door opening on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the payout side CPU 92, but also to the external terminal for front door opening on the external terminal board 97. This makes it possible to output a signal indicating whether the front door frame 14 is in an open state to the hall computer HC without going through control by the payout side CPU 92.

[0158] More specifically regarding the main unit open sensor 96, the signal relay board 98 is provided with a branch path SL4 that branches off from the signal path SL3 that runs from the main unit open sensor 96 to the payout-side CPU 92. This branch path SL4 is connected to the external terminal for main unit open on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the main unit open sensor 96 is input not only to the payout-side CPU 92 but also to the external terminal for main unit open on the external terminal board 97. This makes it possible to output a signal to the hall computer HC indicating whether or not the gaming machine main unit 12 is in an open state, without going through control by the payout-side CPU 92.

[0159] Next, we will explain the contents of the information output externally from the main CPU 63 and the payout CPU 92 to the hall computer HC. First, we will explain the contents of the information output externally from the main CPU 63 to the hall computer HC.

[0160] In the timer interrupt processing (Figure 8), the main CPU 63 sets the output of information to each external terminal assigned to the main CPU 63 on the external terminal board 97 during the external information setting process (step S218). The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the system is in open / close execution mode, information indicating that the support mode is in high-frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number of game balls (for example, 100) have been ejected from the game area PA through one of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34, information indicating that a game ball has entered the first operation port 33, and information indicating that a game ball has entered the second operation port 34.

[0161] In the timer interrupt processing (Figure 12), the payout-side CPU 92 sets the output of information to each external terminal assigned to the payout-side CPU 92 on the external terminal board 97 during the external information setting process (step S409). The information output from the payout-side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been dispensed.

[0162] The hall computer HC can understand the execution method of dispensing game balls in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example, • Payout rate: This is the ratio of the number of game balls dispensed to the number of game balls dispensed from the game area PA of the pachinko machine 10 until 100 game balls are dispensed. • Payout rate in normal gameplay mode, excluding open / close execution mode and high-frequency support mode (hereinafter, this payout rate will be referred to as "B"). • Payout rate in opening / closing mode • Payout rate in high-frequency support mode The number of game rounds played until 100 game balls are dispensed from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S"). • BS × "Number of prize balls awarded for winning in the first operating port 33 and the second operating port 34" The number of game balls that enter the first operating port 33 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S1"). The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S2"). B - (S1 × "Number of prize balls awarded for winning in the first operating port 33" + S2 × "Number of prize balls awarded for winning in the second operating port 34") These are calculated. This makes it possible for the hall computer HC to manage the way game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are dispensed when one game ball enters the corresponding ball entry section.

[0163] <Configuration for managing the winning patterns of game balls> Next, we will explain the configuration for managing the winning patterns of game balls using the management IC66. First, we will explain the electrical configuration of the management IC66, referring to the block diagram in Figure 13.

[0164] As already explained, the MPU 62 of the main control unit 60 is equipped with a main CPU 63, main ROM 64, main RAM 65, and management IC 66. In addition to these, the MPU 62 is also equipped with an I / F 101 and a read terminal 102.

[0165] I / F101 is an interface for sending and receiving signals between the MPU62 and external devices. I / F101 is electrically connected to the main CPU63 via the internal bus 103. Detection results from sensors such as the ball entry detection sensors 42a to 49a, and commands from the payout CPU92 are input to the MPU62 through the input port of I / F101, and various processes are executed in the main CPU63 based on the input detection results and command content as previously described. Furthermore, if a signal output is performed to devices such as the special electric drive unit 32b as a result of the various processes performed in the main CPU63, this signal output is performed through the output port of I / F101. Similarly, if a command output is performed to the payout CPU92 and the sound and light emission control device 81 as a result of the various processes performed in the main CPU63, this command output is performed through the output port of I / F101.

[0166] The reading terminal 102 is a terminal for electrically connecting a reading device, which is an external device of the pachinko machine 10, to the MPU 62, and is provided on the surface of the MPU 62 such that the terminal portion for connection is exposed. However, as already explained, the main control board 61 on which the MPU 62 is mounted is housed in a board box 60a, and the reading terminal 102 faces the wall of the board box 60a so as not to be exposed to the outside of the main control device 60. Therefore, in order to electrically connect the reading device to the reading terminal 102, it is necessary to open the board box 60a and expose the MPU 62. This makes it possible to prevent unauthorized electrical connection of the reading device to the reading terminal 102. However, this is not the only option, and an opening may be formed in the board box 60a to expose the reading terminal 102 to the outside of the main control device 60, so that the electrical connection of the reading device to the reading terminal 102 can be made without destroying the board box 60a.

[0167] The management IC66 includes a management interface 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a memory for correspondence 116, and a history memory 117. These devices are connected bidirectionally via an internal bus 66a provided on the management IC66.

[0168] The management interface 111 is an interface for receiving various signals from the main CPU 63 via a unidirectional communication signal path group 118 built into the MPU 62, and for transmitting various signals to the read terminal 102 via a unidirectional communication signal path group 119 built into the MPU 62. Various signals from the main CPU 63 are input to the input port of the management interface 111, and various signals to the read terminal 102 are output from the output port of the management interface 111. The main CPU 63 is electrically connected to the read terminal 102 via a bidirectional communication signal path group 120 built into the MPU 62.

[0169] The management CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management ROM 113 is a memory (i.e., non-volatile storage means) such as NOR flash memory and NAND flash memory that does not require an external power supply for storage, and is used for read-only purposes. The management ROM 113 stores various control programs and fixed value data executed by the management CPU 112. The management RAM 114 is a memory (i.e., volatile storage means) such as SRAM and DRAM that requires an external power supply for storage, and is used for both read and write purposes. The management RAM 114 allows random access and has a faster read time than the management ROM 113 when compared with the same data capacity. The management RAM 114 temporarily stores various data for the execution of control programs stored in the management ROM 113.

[0170] The RTC115 is a real-time clock that constantly measures date and time information and, according to instructions from the management CPU 112, can output the measured date and time information. The RTC115 is also equipped with a backup power supply, allowing it to measure date and time information even when the pachinko machine 10 is powered off.

[0171] The correspondence memory 116 is a memory (i.e., volatile memory) such as SRAM and DRAM that requires an external power supply for memory retention, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each buffer 122a to 122p provided at the input port 121 of the management I / F 111 and the types of signals input to those buffers 122a to 122p. Details of the contents of the correspondence memory 116 will be explained later.

[0172] The history memory 117 is a memory that does not require an external power supply for storage (i.e., a non-volatile storage means), such as NOR-type flash memory and NAND-type flash memory, and is used for both reading and writing. The history memory 117 is used to store information regarding the entry of game balls received from the main CPU 63 via the management I / F 111. Details of the contents of the history memory 117 will be explained later.

[0173] Next, the configuration of the input port 121 provided on the management interface 111 will be described. Figure 14 is an explanatory diagram illustrating the configuration of the input port 121 of the management interface 111.

[0174] Input port 121 is provided with multiple buffers 122a to 122p. Specifically, the first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can receive one type of signal through signal paths 118a to 118p. When the input signal is at a LOW level, each of the first to sixteenth buffers 122a to 122p stores "0" as the first data, and when the input signal is at a HI level, it stores "1" as the second data. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0175] The first buffer 122a receives a first signal corresponding to the detection result of the first prize-winning slot detection sensor 42a. In this case, the main CPU 63 outputs a LOW level first signal when no new game balls are detected by the first prize-winning slot detection sensor 42a, and outputs a HI level first signal for a specific period when one game ball is detected by the first prize-winning slot detection sensor 42a. This specific period is sufficient for the management CPU 112 to determine that a HI level first signal has been input to the first buffer 122a.

[0176] The second buffer 122b receives a second signal corresponding to the detection result of the second prize-winning slot detection sensor 43a. In this case, the main CPU 63 outputs a LOW level second signal when no new game balls are detected by the second prize-winning slot detection sensor 43a, and outputs a HI level second signal for a specific period when one game ball is detected by the second prize-winning slot detection sensor 43a. This specific period is sufficient for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

[0177] The third buffer 122c receives a third signal corresponding to the detection result of the third prize-winning slot detection sensor 44a. In this case, the main CPU 63 outputs a LOW level third signal when no new game balls are detected by the third prize-winning slot detection sensor 44a, and outputs a HI level third signal for a specific period when one game ball is detected by the third prize-winning slot detection sensor 44a. This specific period is sufficient for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

[0178] The fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a. In this case, the main CPU 63 outputs a LOW level fourth signal when no new game balls are detected by the special electric detection sensor 45a, and outputs a HI level fourth signal for a specific period when one game ball is detected by the special electric detection sensor 45a. This specific period is sufficient for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

[0179] The fifth buffer 122e receives the fifth signal corresponding to the detection result of the first operation port detection sensor 46a. In this case, the main CPU 63 outputs a LOW level fifth signal when no new game balls are detected by the first operation port detection sensor 46a, and outputs a HI level fifth signal for a specific period when one game ball is detected by the first operation port detection sensor 46a. This specific period is sufficient for the management CPU 112 to determine that a HI level fifth signal has been input to the fifth buffer 122e.

[0180] The sixth buffer 122f receives the sixth signal corresponding to the detection result of the second operation port detection sensor 47a. In this case, the main CPU 63 outputs a LOW level sixth signal when no new game balls are detected by the second operation port detection sensor 47a, and outputs a HI level sixth signal for a specific period when one game ball is detected by the second operation port detection sensor 47a. This specific period is sufficient for the management CPU 112 to determine that a HI level sixth signal has been input to the sixth buffer 122f.

[0181] The seventh buffer 122g receives the seventh signal corresponding to the detection result of the out-port detection sensor 48a. In this case, the main CPU 63 outputs a LOW level seventh signal when no new game balls are detected by the out-port detection sensor 48a, and outputs a HI level seventh signal for a specific period when one game ball is detected by the out-port detection sensor 48a. This specific period is sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

[0182] The eighth buffer 122h receives the eighth signal, which corresponds to whether or not the switch is in switch execution mode. In this case, the main CPU 63 continuously outputs the eighth signal at a LOW level when it is not in switch execution mode, and continuously outputs the eighth signal at a HI level when it is in switch execution mode.

[0183] The ninth buffer 122i receives the ninth signal, which corresponds to whether or not the high-frequency support mode is active. In this case, the main CPU 63 continuously outputs the ninth signal at a LOW level when it is not in high-frequency support mode, and continuously outputs the ninth signal at a HI level when it is in high-frequency support mode.

[0184] The tenth buffer 122j receives a tenth signal corresponding to whether or not the front door frame 14 is open. In this case, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HI level tenth signal when the front door frame 14 is open.

[0185] The 16th buffer 122p receives an output instruction signal to the management CPU 112 to recognize the trigger for outputting the history information stored in the history memory 117 to the read terminal 102. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output the history information, and outputs a HI level output instruction signal for a specific period when there is a need to output the history information. This specific period is sufficient for the management CPU 112 to determine that a HI level output instruction signal has been input to the 16th buffer 122p.

[0186] The 11th buffer 122k, the 12th buffer 122l, the 13th buffer 122m, the 14th buffer 122n, and the 15th buffer 122o are capable of receiving signals from the main CPU 63, but in this pachinko machine 10, they are blank and do not receive normal signals. In this way, the number of buffers 122a to 122p is provided as input port 121 of the management I / F 111, which is greater than the number of signals output from the main CPU 63 to the management IC 66 in this pachinko machine 10. This makes it possible to reuse the management IC 66 in models other than this pachinko machine 10. This increases the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and each of the first to sixteenth buffers 122a to 122p, with a one-to-one correspondence between the first to sixteenth buffers 122a to 122p, but this is not the only option, and a configuration in which signal paths 118k to 118o are not formed between the buffers to be blanked 122k to 122o is also possible.

[0187] It was determined during the design phase of the management IC 66 that an output instruction signal is input to the 16th buffer 122p at the input port 121 of the management I / F 111. Therefore, the management CPU 112 can identify that an output instruction signal is input to the 16th buffer 122p without receiving instructions from the main CPU 63. On the other hand, the types of signals that are input to the 1st to 15th buffers 122a to 122o were not determined during the design phase of the management IC 66. The types of these signals are identified by the management CPU 112 after receiving instructions from the main CPU 63. The identification of these signal types by the management CPU 112 is performed by sending a type identification command from the main CPU 63 to the management CPU 112 when control is started in both the main CPU 63 and the management CPU 112 in conjunction with the supply of operating power to the MPU 62, as will be described in detail later. In this case, the information on the types of signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of signals while operating power is supplied, the information stored in the correspondence memory 116 is referenced.

[0188] Figure 15 is an explanatory diagram illustrating the configuration of the correspondence memory 116. The correspondence memory 116 is provided with first to 15 correspondence areas 123a to 123o that correspond one-to-one with the first to 15 buffers 122a to 122o provided at the input port 121 of the management I / F 111.

[0189] The first correspondence area 123a stores information indicating that the signal input to the first buffer 122a is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the first correspondence area 123a also stores information (10) indicating the number of game balls that will be dispensed when one game ball enters the general prize slot 31. The second correspondence area 123b stores information indicating that the signal input to the second buffer 122b is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the second correspondence area 123b also stores information (10) indicating the number of game balls that will be dispensed when one game ball enters the general prize slot 31. The third correspondence area 123c stores information indicating that the signal input to the third buffer 122c is a general prize slot 31, which is used by the management CPU 112 to identify the type of signal. In addition, the third correspondence area 123c also stores information (10 balls) indicating the number of game balls that will be dispensed when one game ball enters the general prize slot 31.

[0190] The fourth correspondence area 123d stores information indicating that the signal input to the fourth buffer 122d is the special electric prize winning device 32, which is used by the management CPU 112 to identify the type of signal. In addition, the fourth correspondence area 123d also stores information (15) indicating the number of game balls that will be dispensed when one game ball enters the special electric prize winning device 32. The fifth correspondence area 123e stores information indicating that the signal input to the fifth buffer 122e is the first operation port 33, which is used by the management CPU 112 to identify the type of signal. In addition, the fifth correspondence area 123e also stores information (1) indicating the number of game balls that will be dispensed when one game ball enters the first operation port 33. The sixth correspondence area 123f stores information indicating that the signal input to the sixth buffer 122f is the second operation port 34, which is used by the management CPU 112 to identify the type of signal. In addition, the sixth correspondence area 123f also stores information indicating that the signal is the second operation port 34, as well as information indicating the number of game balls that will be dispensed (1) when one game ball enters the second operation port 34. The seventh correspondence area 123g stores information indicating that the signal input to the seventh buffer 122g is the output port 24a, which is used by the management CPU 112 to identify the type of signal.

[0191] The 8th correspondence area 123h stores information indicating that it is in open / close execution mode, which is used by the management CPU 112 to identify the type of signal input to the 8th buffer 122h. The 9th correspondence area 123i stores information indicating that it is in high-frequency support mode, which is used by the management CPU 112 to identify the type of signal input to the 9th buffer 122i. The 10th correspondence area 123j stores information indicating that it is the front door frame 14, which is used by the management CPU 112 to identify the type of signal input to the 10th buffer 122j.

[0192] The 11th correspondence area 123k stores information indicating that it is a blank, meaning it does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the 11th buffer 122k. The 12th correspondence area 123l stores information indicating that it is a blank, meaning it does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the 12th buffer 122l. The 13th correspondence area 123m stores information indicating that it is a blank, meaning it does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the 13th buffer 122m. The 14th correspondence area 123n stores information indicating that it is a blank, meaning it does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the 14th buffer 122n. The 15th correspondence area 123o stores information indicating that it is a blank, meaning it does not correspond to any of the signals, which is used by the management CPU 112 to identify the type of signal input to the 15th buffer 122o.

[0193] As described above, by configuring the system so that the type of signal input to the first to fifteenth buffers 122a to 122o is determined by the management CPU 112 upon receiving instructions from the main CPU 63, the management IC 66 can be reused in models other than this pachinko machine 10. This increases the versatility of the management IC 66.

[0194] Furthermore, instead of outputting information to recognize the type of signal each time a signal corresponding to the storage of history information is output to the first to fifteenth buffers 122a to 122o, the system outputs information to recognize the type of signal in advance, and based on that output information, information for the management CPU 112 to identify the type of signal to be input to the first to fifteenth buffers 122a to 122o is stored in the correspondence memory 116. This configuration makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration where information to recognize the type of signal is output each time a signal corresponding to the storage of history information is output to the first to fifteenth buffers 122a to 122o.

[0195] Furthermore, the output of information for the management CPU 112 to identify the type of signals input to the first to fifteenth buffers 122a to 122o is performed when the power supply for operation begins. This makes it possible for the management CPU 112 to identify the type of signals input to the first to fifteenth buffers 122a to 122o when gameplay begins on the pachinko machine 10.

[0196] Furthermore, the information setting that an output instruction signal will be input to the 16th buffer 122p is performed during the design phase of the management IC 66. As a result, not only in this pachinko machine 10 but also in other pachinko machines that use the management IC 66, it is possible to omit the processing required to identify the type of signal input to the 16th buffer 122p for output instruction signals that are reliably used. Therefore, the processing load required to identify the type of such signal can be reduced.

[0197] Next, we will describe the history memory 117 of the management IC 66. Figure 16 is an explanatory diagram illustrating the configuration of the history memory 117.

[0198] The history memory 117 is provided with a history area 124 for sequentially storing history information. The history area 124 has multiple pointer information set sequentially, and a history information storage area 125 is set to correspond one-to-one with each pointer information. The history information storage area 125 can store combinations of RTC information and correspondence information. In this case, each history information storage area 125 has a data capacity of 2 bytes, with 1 byte allocated for the area to store RTC information and 1 byte allocated for the area to store correspondence information. When it becomes necessary to store correspondence information in accordance with the signals input to the 1st to 15th buffers 122a to 122o (actually the 1st to 10th buffers 122a to 122j in this pachinko machine 10), first, the date and time information measured by the current RTC 115 is stored in the area of ​​the history information storage area 125 that is set to store RTC information and corresponds to the pointer information currently being written. Subsequently, the correspondence information corresponding to buffers 122a to 122o, which triggered the current information storage, is read from the correspondence areas 123a to 123o in the correspondence memory 116 that correspond to buffers 122a to 122o, and the read correspondence information is stored in the area of ​​the history information storage area 125 that stores correspondence information corresponding to the pointer information currently being written.

[0199] Specifically, regarding the correspondence information stored in the history information storage area 125, as already explained, the first to seventh buffers 122a to 122g receive signals corresponding to the detection results of the ball entry detection sensors 42a to 48a, so the first to seventh correspondence areas 123a to 123g in the correspondence memory 116 store information corresponding to the types of ball entry detection sensors 42a to 48a. More specifically, the first to seventh correspondence areas 123a to 123g store information corresponding to the type of ball entry section corresponding to each of the ball entry detection sensors 42a to 48a. In this pachinko machine 10, as already explained, the first to third prize entry detection sensors 42a to 44a all detect game balls that have entered the general prize entry area 31, so the first to third correspondence areas 123a to 123c corresponding to these first to third prize entry detection sensors 42a to 44a all store information indicating that it is the general prize entry area 31. Furthermore, the fourth correspondence area 123d stores information indicating that it is the special electric prize winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the out port 24a. If the buffers 122a to 122o that triggered the information storage in this case are any of the first to seventh buffers 122a to 122g, then the information of the type of ball entry area corresponding to that buffer 122a to 122g is read from any of the first to seventh correspondence areas 123a to 123g, and the read information of the type of ball entry area is stored as is in the area for storing correspondence information in the history information storage area 125.

[0200] On the other hand, the eighth buffer 122h receives a signal indicating whether or not it is in opening / closing execution mode, the ninth buffer 122i receives a signal indicating whether or not it is in high-frequency support mode, and the tenth buffer 122j receives a signal indicating whether or not the front door frame 14 is open. Therefore, the eighth corresponding relationship area 123h stores information indicating that it is in opening / closing execution mode, the ninth corresponding relationship area 123i stores information indicating that it is in high-frequency support mode, and the tenth corresponding relationship area 123j stores information indicating that it is the front door frame 14.

[0201] As previously explained, the main CPU 63 continuously outputs the 8th signal at a LOW level when it is not in the opening / closing execution mode, and continuously outputs the 8th signal at a HI level when it is in the opening / closing execution mode. Therefore, the management CPU 112 can determine that the opening / closing execution mode has started when the 8th signal changes from a LOW level to a HI level, and that the opening / closing execution mode has ended when the 8th signal changes from a HI level to a LOW level. In both cases, the management CPU 112 determines that an opportunity has arisen to store correspondence information in the history information storage area 125. In other words, when the 8th signal changes from a LOW level to a HI level, not only the information indicating that it is in the opening / closing execution mode, read from the 8th correspondence area 123h, but also the start information is stored together in the area for storing correspondence information in the history information storage area 125. Furthermore, when the 8th signal changes from a HI level to a LOW level, not only the information indicating that it is in the opening / closing execution mode, read from the 8th correspondence area 123h, but also the termination information is stored together in the area for storing correspondence information in the history information storage area 125.

[0202] As previously explained, the main CPU 63 continuously outputs the 9th signal at a LOW level when not in high-frequency support mode, and continuously outputs the 9th signal at a HI level when in high-frequency support mode. Therefore, the management CPU 112 can determine that high-frequency support mode has started when the 9th signal changes from LOW to HI, and that high-frequency support mode has ended when the 9th signal changes from HI to LOW. In both cases, the management CPU 112 determines that an opportunity has arisen to store correspondence information in the history information storage area 125. In other words, when the 9th signal changes from LOW to HI, not only the information indicating that it is in high-frequency support mode, read from the 9th correspondence area 123i, but also the start information is stored together in the area of ​​the history information storage area 125 for storing correspondence information. Furthermore, when the 9th signal changes from a HI level to a LOW level, not only the information indicating that it is in high-frequency support mode, read from the 9th correspondence area 123i, but also the termination information is stored together in the area for storing correspondence information in the history information storage area 125.

[0203] As previously explained, the main CPU 63 continuously outputs a LOW level 10th signal when the front door frame 14 is closed, and a HI level 10th signal when the front door frame 14 is open. Therefore, the management CPU 112 can determine that the front door frame 14 has been opened when the 10th signal changes from LOW to HI, and that the front door frame 14 has been closed when the 10th signal changes from HI to LOW. In both cases, the management CPU 112 determines that an opportunity has arisen to store correspondence information in the history information storage area 125. In other words, when the 10th signal changes from LOW to HI, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j, but also the opening start information is stored together in the area for storing correspondence information in the history information storage area 125. Furthermore, when the 10th signal changes from a HI level to a LOW level, not only the information indicating that it is the front door frame 14, read from the 10th correspondence area 123j, but also the information indicating that the door has been opened are stored together in the area for storing correspondence information in the history information storage area 125.

[0204] The history information storage area 125 is provided with enough space to store all the history information that occurs during a 10-day consecutive business day, even if the pachinko machine 10 continues to fire game balls from opening to closing time. For example, if 60,000 history information entries are generated per day, then more than 600,000 history information storage areas 125 are provided. This makes it possible to store and retain all history information in the history memory 117 for at least 10 days.

[0205] The history memory 117 has a pointer area 126 separate from the history area 124. The pointer area 126 stores information that allows the management CPU 112 to identify the pointer information currently being written to in the history memory 117. Specifically, at the time of shipment of the pachinko machine 10, the pointer area 126 is set to specify the pointer information of "0" as the writing target. Each time a new piece of history information is stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information in the sequence becomes the writing target and history information is stored in the history information storage area 125 corresponding to that last pointer information, the information in the pointer area 126 is updated so that the pointer information of "0" becomes the writing target. As a result, if the number of history information items that can be stored exceeds the number of history information items that need to be stored, the new history information will overwrite the oldest history information in the history information storage area 125 first.

[0206] Furthermore, when the reading device reads history information from the history memory 117, the history information storage area 125 is completely cleared to "0", and the information in the pointer area 126 is updated so that the "0" pointer information becomes the target of writing. This prevents history information that has already been read from becoming the target of reading again.

[0207] Next, we will describe the specific processing configuration for managing the winning patterns of game balls using the management IC 66. First, we will describe the processing configuration for storing information on the correspondence between the first to 15th buffers 122a to 122o, provided at the input port 121 of the management I / F 111, and the types of signals in the correspondence memory 116. Figure 17 is a flowchart showing the recognition process executed by the main CPU 63. The recognition process is executed in step S110 of the main process (Figure 7).

[0208] First, the recognition output counter in the main RAM 65 is set to "15" (step S501). The recognition output counter is used by the main CPU 63 to determine the remaining number of times information output is required to allow the management CPU 112 to recognize which type of signal each buffer 122a to 122p of the input port 121 in the management I / F 111 corresponds to. As already explained, the 15 buffers 1 to 15, 122a to 122o, are the targets for signal type recognition, so the recognition output counter is set to "15".

[0209] Subsequently, the process of outputting the identification start command is executed (step S502). The main CPU 63 outputs various commands to the management CPU 112 in order to make the management CPU 112 recognize which type of signal corresponds to the first to fifteenth buffers 122a to 122o. The first to eighth signals input to the first to eighth buffers 122a to 122h are used for this command output. In other words, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 on the trigger for storing history information are used to output commands in order to make the management CPU 112 recognize which type of signal corresponds to the first to fifteenth buffers 122a to 122o. This makes it possible to reduce the number of signal paths and simplify the configuration compared to a configuration in which a separate signal path for outputting such commands is provided in addition to the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has an 8-bit data capacity, and the data of each bit is input as the 1st to 8th signals to the 1st to 8th buffers 122a to 122h. In the output processing of the identification start command, the output state of the 9th signal is switched to HI level at the timing when the output of the identification start command begins, so that the management CPU 112 recognizes that a new command has been sent. The output period of the identification start command and the period during which the output state of the 9th signal is maintained at HI level are set to be sufficient for the management CPU 112 to recognize these identification start commands and the output state of the 9th signal. Upon receiving the identification start command, the management CPU 112 determines that it should start processing to store information on the correspondence between the 1st to 15th buffers 122a to 122o and the types of signals in the correspondence memory 116.

[0210] Subsequently, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S503). In this case, the first buffer 122a is the first to be set as the signal type, and then the nth buffer, followed by the (n+1)th buffer, and so on, as the recognition settings for the signal types corresponding to the first to fifteenth buffers 122a to 122o are performed. Therefore, if the recognition output counter is "15" to "13", a type identification command indicating that it is the general prize entry port 31 and the number of prize balls awarded is read; if the recognition output counter is "12", a type identification command indicating that it is the special electric prize entry device 32 and the number of prize balls awarded is read; if the recognition output counter is "11", a type identification command indicating that it is the first operation port 33 and the number of prize balls awarded is read; if the recognition output counter is "10", a type identification command indicating that it is the second operation port 34 and the number of prize balls awarded is read; if the recognition output counter is "9", a type identification command indicating that it is the out port 24a is read; if the recognition output counter is "8", a type identification command indicating that it is in the opening / closing execution mode is read; if the recognition output counter is "7", a type identification command indicating that it is in the high-frequency support mode is read; if the recognition output counter is "6", a type identification command indicating that it is the front door frame 14 is read; and if the recognition output counter is "5" to "1", a type identification command indicating that it is blank is read.

[0211] Subsequently, the output processing of the read type identification command is executed (step S504). The type identification command, like the identification start command, has a data capacity of 8 bits, and the data of each bit is input as the 1st to 8th signals to the 1st to 8th buffers 122a to 122h. In addition, in the output processing of the identification type command, the output state of the 9th signal is switched to the HI level at the timing when the output of the identification type command begins, so that the management CPU 112 recognizes that a new command has been sent. The output period of the identification type command and the period during which the output state of the 9th signal is maintained at the HI level are set to be sufficient for the management CPU 112 to recognize these identification type commands and the output state of the 9th signal. Upon receiving the identification type command, the management CPU 112 stores the information corresponding to that identification type command in the corresponding relationship areas 123a to 123o of the 1st to 15th buffers 122a to 122o that are the target of this configuration.

[0212] Subsequently, the value of the recognition output counter in the main RAM 65 is deducted by 1 (step S505), and it is determined whether the value of the recognition output counter after the deduction is "0" (step S506). If the value of the recognition output counter is 1 or greater (step S506: NO), processing is performed to output a type identification command corresponding to the value of the recognition output counter after the deduction (steps S503 and S504).

[0213] On the other hand, when the value of the recognition output counter is "0" (step S506: YES), the output process of the identification end command is executed (step S507). The identification end command has a data capacity of 8 bits, and the data of each bit is input as the first to eighth signals to the first to eighth buffers 122a to 122h, respectively. Also, in the output process of the identification end command, in order to make the management side CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification end command. Also, the output period of the identification end command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management side CPU 112 to recognize these identification end command and the output state of the ninth signal. By receiving the identification end command, the management side CPU 112 identifies that the process for storing the information on the correspondence between the first to fifteenth buffers 122a to 122o and the signal types in the correspondence memory 116 has been completed.

[0214] Next, the management process executed by the management side CPU 112 will be described while referring to the flowchart of FIG. 18. The management process starts when the supply of operating power to the management side CPU 112 is started. Note that the processing speed of the management side CPU 112 is configured to be faster than the processing speed of the main side CPU 63, and from the start of one timer interrupt process (FIG. 8) in the main side CPU 63 until the start of the next timer interrupt process (FIG. 8), the combination of the processes after step S606 in the management process is executed 16 times or more.

[0215] When the management side CPU 112 receives the identification start command (step S601: YES), the value of the setting target counter provided in the management side RAM 114 is cleared to "0" (step S602). The setting target counter is a counter for the management side CPU 112 to identify the types of the buffers 122a to 122o that are the setting targets of the signal types. The first buffer 122a is the first to be the setting target of the signal type, and then the (n + 1)th buffer becomes the setting target of the signal type after the nth buffer.

[0216] Thereafter, on condition that the main CPU 63 has received a type identification command (step S603: YES), a correspondence setting process is executed (step S604). In the correspondence setting process, among the first to fifteenth correspondence areas 123a to 123o of the correspondence memory 116, the information on the signal type set in the type identification command received this time is stored in the correspondence area corresponding to the current value in the setting target counter of the management side RAM 114. Thereafter, the value of the setting target counter of the management side RAM 114 is incremented by 1 (step S605).

[0217] If a negative determination is made in step S603, or if the process of step S605 is executed, it is determined whether an identification end command has been received from the main CPU 63 (step S606). If the identification end command has not been received (step S606: NO), the process returns to step S603, and on condition that a new type identification command is received from the main CPU 63 (step S603: YES), the processes of step S604 and step S605 are executed again.

[0218] If an identification end command has been received from the main CPU 63 (step S606: YES), the processes of step S607 and step S608 are repeatedly executed. Although the details will be described later, in step S607, a history setting process for storing the history information corresponding to the type of the signal received from the main CPU 63 in the history memory 117 is executed. Although the details will be described later, in step S608, an external output process for outputting the history information stored in the history memory 117 to the reading terminal 102 is executed.

[0219] Figure 19 is a time chart showing how information regarding the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o is stored in the correspondence memory 116. Figure 19(a) shows the period during which commands are output from the main CPU 63 to the management CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), Figure 19(b) shows the period during which the output state of the ninth signal is at a HI level, Figure 19(c) shows the execution period of the identification state during which processing is performed to identify the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o, and Figure 19(d) shows the timing when the correspondence setting process (step S604) is executed in the management CPU 112.

[0220] When power is supplied to the main CPU 63 and the management CPU 112, at timing t1, the output of an identification start command using the first to eighth signals begins, as shown in Figure 19(a). Also at timing t1, the output state of the ninth signal changes from LOW to HI, as shown in Figure 19(b). Subsequently, at timing t2, while the output of the identification start command is still continuing, the output state of the ninth signal changes again from HI to LOW, as shown in Figure 19(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h, and understands the content of the command received from the main CPU 63. In this case, since an identification start command has been received, the management CPU 112 enters the identified state by making an affirmative judgment in step S601 of the management process (Figure 18). Subsequently, at timing t3, the output of the identification start command stops, as shown in Figure 19(a).

[0221] Subsequently, at timing t4, the output of the first type identification command using the 1st to 8th signals begins, as shown in Figure 19(a). Also at timing t4, the output state of the 9th signal is changed from LOW to HI, as shown in Figure 19(b). Then, at timing t5, while the output of the type identification command is still continuing, the output state of the 9th signal is changed again from HI to LOW, as shown in Figure 19(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking that the output state of the 9th signal has changed from HI to LOW, and understands the content of the command received from the main CPU 63 by checking the information in the 1st to 8th buffers 122a to 122h. In this case, since the first type identification command has been received, the management CPU 112 executes the correspondence setting process at timing t5, as shown in Figure 19(d). In this correspondence setting process, information indicating that it is a general prize slot 31 and information on the number of prize balls awarded are stored in the first correspondence area 123a of the correspondence memory 116. Subsequently, at timing t6, the output of the type identification command is stopped as shown in Figure 19(a).

[0222] Subsequently, at timings t7 to t9, t10 to t12, t13 to t15, and t16 to t18, the management CPU 112 executes a correspondence setting process corresponding to the type identification command output from the main CPU 63, similar to the timings t4 to t6. In this case, the correspondence setting process corresponding to the 15th type identification command is completed at timings t16 to t18.

[0223] Subsequently, at timing t19, the output of an identification termination command using the 1st to 8th signals begins, as shown in Figure 19(a). Also at timing t19, the output state of the 9th signal is changed from LOW to HI, as shown in Figure 19(b). Then, at timing t20, while the output of the identification termination command is still continuing, the output state of the 9th signal is changed again from HI to LOW, as shown in Figure 19(b). The management CPU 112 confirms that a command has been sent from the main CPU 63 by checking the information in the 1st to 8th buffers 122a to 122h, and understands the content of the command received from the main CPU 63. In this case, since an identification termination command has been received, the identification state of the management CPU 112 ends at timing t20, as shown in Figure 19(c). Then, at timing t21, the output of the identification termination command is stopped, as shown in Figure 19(a).

[0224] As described above, by using the 9th signal to allow the management CPU 112 to recognize whether or not a command is being output, it is possible to clearly allow the management CPU 112 to recognize that a command is being output, even in a configuration where command output is performed using the 1st to 8th signals (i.e., the 1st to 8th signal path) which are used to instruct the management CPU 112 on when to store history information.

[0225] Next, we will describe the processing configuration for storing history information in the history memory 117. Figure 20 is a flowchart showing the management output processing executed by the main CPU 63. The management output processing is executed in step S219 of the timer interrupt processing (Figure 8).

[0226] First, the managed object counter located in the main RAM 65 is set to "10" (step S701). The managed object counter is used by the main CPU 63 to determine whether or not there are managed objects that are not the target of the determination of whether or not the signal output state to the management CPU 112 should be changed in this management output processing, and also to determine whether or not the signal output state to the management CPU 112 should be changed for each managed object. In a single management output processing, the managed objects that the main CPU 63 determines whether or not the signal output state to the management CPU 112 should be changed are a total of 10 objects: the seven ball entry detection sensors 42a to 48a, whether or not the opening / closing execution mode is executed, whether or not the high-frequency support mode is executed, and whether or not the front door frame 14 is opened or closed. Therefore, the managed object counter is set to "10" first.

[0227] Next, it is determined whether the signal output status to the management CPU 112 for the managed object corresponding to the current managed counter value is at a HI level (step S702). If it is not at a HI level (step S702: NO), it is determined whether the managed object corresponding to the managed counter value is 4 or greater, thereby identifying whether it is one of the seven ball entry detection sensors 42a to 48a (step S703).

[0228] If a positive determination is made in step S703, it is determined whether the output flag of the main RAM 65 corresponding to the value of the managed counter is set to "1" (step S704). Specifically, if the value of the managed counter is "10" and corresponds to the first prize-winning slot detection sensor 42a, it is determined whether the first output flag is set to "1", if the value of the managed counter is "9" and corresponds to the second prize-winning slot detection sensor 43a, it is determined whether the second output flag is set to "1", if the value of the managed counter is "8" and corresponds to the third prize-winning slot detection sensor 44a, it is determined whether the third output flag is set to "1", and if the value of the managed counter is "7" and corresponds to the special electric detection sensor 45a If it corresponds to the first operation port detection sensor 46a, it is determined whether the fourth output flag is set to "1". If the value of the managed counter is "6" and it corresponds to the first operation port detection sensor 46a, it is determined whether the fifth output flag is set to "1". If the value of the managed counter is "5" and it corresponds to the second operation port detection sensor 47a, it is determined whether the sixth output flag is set to "1". If the value of the managed counter is "4" and it corresponds to the out port 24a, it is determined whether the seventh output flag is set to "1". As previously explained, these first to seventh output flags are set to "1" during the ball entry detection process (Figure 10).

[0229] If the output flag corresponding to the value of the managed counter is set to "1" (step S704: YES), the output state of the signal corresponding to the value of the managed counter among the 1st to 7th signals is set to HI level (step S705). Then, the output flag corresponding to the value of the managed counter is cleared to "0" (step S706).

[0230] If a negative determination is made in step S703, it is determined whether an event has occurred that triggers switching the output state of the signal corresponding to the value of the managed counter to the HI level (step S707). Specifically, if the value of the managed counter is "3", it is determined whether a transition to the opening / closing execution mode has occurred; if the value of the managed counter is "2", it is determined whether a transition to the high-frequency support mode has occurred; and if the value of the managed counter is "1", it is determined whether the front door frame 14 has entered the open state. If a positive determination is made in step S707, the output state of the signal corresponding to the value of the managed counter is set to the HI level (step S708).

[0231] If a positive result is obtained in step S702, it is determined whether an event has occurred that triggers a switch to a LOW level for the output state of the signal corresponding to the value of the managed counter (step S709). Specifically, if the value of the managed counter is 4 or more and the currently managed object is one of the ball entry detection sensors 42a to 48a, it is determined whether a HI output duration period (specifically 10 msec) has elapsed since the output state of the signal corresponding to the value of the managed counter among the 1st to 7th signals was switched from a LOW level to a HI level. This HI output duration period is set in the management CPU 112 to be longer than the longest processing interval of the history setting process (step S607) of the management process (Figure 18), and is a period during which the management CPU 112 can reliably identify the output state of the signal that has switched from a LOW level to a HI level. Furthermore, if the value of the managed counter is "3" and the current managed object is in opening / closing execution mode, it is determined whether the opening / closing execution mode has ended. If the value of the managed counter is "2" and the current managed object is in high-frequency support mode, it is determined whether the high-frequency support mode has ended. If the value of the managed counter is "1" and the current managed object is the front door frame 14, it is determined whether the front door frame 14 is in a closed state. If an event occurs that triggers switching the output state of the signal corresponding to the value of the managed counter to a LOW level (step S709: YES), the output state of the signal corresponding to the value of the managed counter is set to a LOW level (step S710).

[0232] If a negative result is obtained in step S704, if the process in step S706 is executed, if a negative result is obtained in step S707, if the process in step S708 is executed, if a negative result is obtained in step S709, or if the process in step S710 is executed, the value of the managed counter in the main RAM 65 is decremented by 1 (step S711). Then, it is determined whether the value of the managed counter after the decrement is "0" (step S712). If the value of the managed counter is 1 or greater (step S712: NO), the process from step S702 onwards is executed for the managed object corresponding to the new managed counter value.

[0233] Next, the history setting process executed by the management CPU 112 will be explained with reference to the flowchart in Figure 21. The history setting process is executed in step S607 of the management process (Figure 18).

[0234] First, the number of buffers to be checked by the management CPU 112 from among the first to fifteenth buffers 122a to 122o is set in the verification target counter provided in the management RAM 114 (step S801). Specifically, the number of correspondence areas in the correspondence memory 116 that contain information other than information indicating that they are blank is identified, and this identified number of items is set in the verification target counter. In this pachinko machine 10, as already explained, information other than information indicating that they are blank is stored in the first to tenth correspondence areas 123a to 123j, so in step S801, "10" is set in the verification target counter.

[0235] Subsequently, the system checks whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fifteenth buffers 122a to 122o has changed from "0" to "1", thereby determining whether the output state of the input signal from the main CPU 63 to the buffer has switched from a LOW level to a HI level (step S802). If the value of the counter to be checked is "n", then the nth buffer 122a to 122o becomes the target of numerical information check. For example, if the value of the counter to be checked is "10", then the tenth buffer 122j becomes the target of numerical information check, and if the value of the counter to be checked is "5", then the fifth buffer 122e becomes the target of numerical information check.

[0236] If a positive determination is made in step S802, the RTC information, which consists of date and time information, is read from the RTC 115 (step S803). Then, the write process to the history memory 117 is executed (step S804). In this write process, the pointer information of the history area 124 currently being written to is identified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S803 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information being written to. In addition, correspondence information is read from the correspondence areas 123a to 123o corresponding to the current value of the counter to be checked, and this correspondence information is written to the history information storage area 125 corresponding to the pointer information being written to. Furthermore, if the correspondence information is information indicating that it is in opening / closing execution mode, information indicating that it is in high-frequency support mode, or information indicating that it is the front door frame 14, then not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information being written to. If the value of the counter to be checked is "n", then the nth correspondence area 123a to 123o will be the target for reading the correspondence information. For example, if the value of the counter to be checked is "10", then the 10th correspondence area 123j will be the target for reading the correspondence information, and if the value of the counter to be checked is "5", then the 5th correspondence area 123e will be the target for reading the correspondence information.

[0237] When the writing process is executed as described above, if the value of the confirmation target counter is any one of the output port 24a, the general winning port 31, the special power winning device 32, the first operating port 33, and the second operating port 34, in the history information storage area 125 corresponding to the pointer information to be written, a combination of the RTC information and the correspondence information indicating that it is any one of the output port 24a, the general winning port 31, the special power winning device 32, the first operating port 33, and the second operating port 34 is stored as history information. Also, if the value of the confirmation target counter is any one of the open / close execution mode, the high-frequency support mode, and the front door frame 14, in the history information storage area 125 corresponding to the pointer information to be written, a combination of the RTC information, the correspondence information indicating that it is any one of the open / close execution mode, the high-frequency support mode, and the front door frame 14, and the start information is stored as history information.

[0238] Thereafter, an update process for the target pointer is executed (step S805). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read out and incremented by 1. It is determined whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment of 1 is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

[0239] If a negative determination is made in step S802, or if the process in step S805 is executed, it is determined in step S806 whether the corresponding relationship information for which the signal output should be checked whether or not has been switched to a LOW level is stored in the corresponding relationship area 123a to 123o that corresponds to the current value of the counter to be checked. Specifically, if the current value of the counter to be checked is "8" to "10", then one of the following information is stored in the corresponding relationship area 123h to 123j: information indicating that it is in opening / closing execution mode, information indicating that it is in high-frequency support mode, or information indicating that it is the front door frame 14. Therefore, an affirmative determination is made in step S806.

[0240] If a positive determination is made in step S806, it is determined whether the output state of the input signal from the main CPU 63 to the buffer has been switched from a HI level to a LOW level by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fifteenth buffers 122a to 122o has been changed from "1" to "0" (step S807). If a positive determination is made in step S807, the RTC information is read in the same way as in step S803 (step S808), and then the write process to the history memory 117 is executed (step S809). In this write process, the RTC information read in step S808 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, correspondence information is read from the correspondence area 123a to 123o corresponding to the current value of the counter to be checked, and this correspondence information is written to the history information storage area 125 corresponding to the pointer information to be written. Furthermore, in addition to the correspondence information, termination information is also written to the history information storage area 125 corresponding to the pointer information to be written. When this writing process is executed, if the value of the counter to be checked is one of the open / close execution mode, high-frequency support mode, or front door frame 14, the history information storage area 125 corresponding to the pointer information to be written will store as history information a combination of RTC information, correspondence information indicating that it is one of the open / close execution mode, high-frequency support mode, or front door frame 14, and termination information. After that, the target pointer update process is executed in the same way as in step S805 (step S810).

[0241] If a negative determination is made in step S806, step S807, or step S810, the value of the counter to be checked in the management RAM 114 is decremented by 1 (step S811). Then, it is determined whether the value of the counter to be checked after the decrement is "0" (step S812). If the value of the counter to be checked is 1 or greater (step S812: NO), the processing from step S802 onwards is executed for the item to be checked corresponding to the new value of the counter to be checked.

[0242] Next, we will explain how history information is stored in the history memory 117, referring to the time chart in Figure 22. Figure 22(a) shows the period when a HI level signal is input to any of the first to seventh buffers 122a to 122g, Figure 22(b) shows the period when a HI level signal is input to the eighth buffer 122h, Figure 22(c) shows the period when a HI level signal is input to the ninth buffer 122i, Figure 22(d) shows the period when a HI level signal is input to the tenth buffer 122j, and Figure 22(e) shows the timing of writing history information to the history memory 117.

[0243] At timing t1, as shown in Figure 22(a), the output state of the signal input to one of the first to seventh buffers 122a to 122g is switched from LOW level to HI level. Therefore, at timing t1, history information is written to the history memory 117 as shown in Figure 22(e). Subsequently, at timing t2, as shown in Figure 22(a), the signal that was switched to HI level at timing t1 is switched to LOW level. However, since this signal is input to one of the first to seventh buffers 122a to 122g, and the LOW level switch is not subject to storage of history information, the writing of history information is not performed at timing t2 as shown in Figure 22(e).

[0244] Subsequently, at timings t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to one of the first to seventh buffers 122a to 122g is switched from LOW level to HI level, as shown in Figure 22(a). Therefore, history information is written at each of these timings, as shown in Figure 22(e).

[0245] As shown in Figure 22(b), the output state of the signal input to the eighth buffer 122h is at a HI level from timing t4 to timing t7. This eighth buffer 122h corresponds to whether or not the opening / closing execution mode has occurred. Therefore, as shown in Figure 22(e), history information is written at timing t4, which is the timing when the output state of the signal input to the eighth buffer 122h switches to a HI level, and at timing t7, which is the timing when the output state of the signal switches to a LOW level. In this case, the history information written at timing t4 includes start information, and the history information written at timing t7 includes end information. This makes it possible to understand the execution period of the opening / closing execution mode by checking the history information in the history memory 117.

[0246] Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the out slots 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during the opening / closing execution mode. In addition, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the out slots 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during the opening / closing execution mode by comparing it with the RTC information.

[0247] As shown in Figure 22(c), the output state of the signal input to the ninth buffer 122i is at a HI level from timing t8 to timing t11. This ninth buffer 122i corresponds to whether or not the high-frequency support mode is occurring. Therefore, as shown in Figure 22(e), history information is written at timing t8, which is the timing when the output state of the signal input to the ninth buffer 122i switches to a HI level, and at timing t11, which is the timing when the output state of the signal switches to a LOW level. In this case, the history information written at timing t8 includes start information, and the history information written at timing t11 includes end information. This makes it possible to understand the execution period of the high-frequency support mode by checking the history information in the history memory 117.

[0248] Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether or not the history information indicating that a ball entered any of the out slot 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during high-frequency support mode. In addition, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball entered any of the out slot 24a, general prize slot 31, special electric prize device 32, first operation slot 33, and second operation slot 34 occurred during high-frequency support mode by comparing it with the RTC information.

[0249] As shown in Figure 22(d), the output state of the signal input to the 10th buffer 122j is at a HI level from timing t12 to timing t15. This 10th buffer 122j corresponds to whether the front door frame 14 is open or closed. Therefore, as shown in Figure 22(e), history information is written at timing t12, which is the timing when the output state of the signal input to the 10th buffer 122j switches to a HI level, and at timing t15, which is the timing when the output state of the signal switches to a LOW level. In this case, the history information written at timing t12 includes start information, and the history information written at timing t15 includes end information. This makes it possible to determine the period during which the front door frame 14 is in an open state by checking the history information in the history memory 117.

[0250] Furthermore, history information is written to the history memory 117 in chronological order. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred while the front door frame 14 was open. In addition, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the out-out port 24a, general prize-winning port 31, special electric prize-winning device 32, first operation port 33, and second operation port 34 occurred while the front door frame 14 was open by comparing it with the RTC information.

[0251] Next, we will describe the processing configuration for outputting history information stored in the history memory 117 to a reading device electrically connected to the reading terminal 102 of the MPU 62. Figure 23 is a flowchart showing the data output processing executed by the main CPU 63. The data output processing is executed in step S111 of the main processing (Figure 7).

[0252] In the data output processing, it is first determined whether or not a connection signal indicating that the reading device is electrically connected to the reading terminal 102 is received from the reading terminal 102 (step S901). The reading device is configured to output a connection signal when it is electrically connected to the reading terminal 102, and if the reading device receives the connection signal through the reading terminal 102, it is determined to be positive in step S901.

[0253] If a negative determination is made in step S901, the data output process is terminated. In this case, in order for the data output process to be executed, the supply of operating power to the MPU 62 must be restarted. Thus, in order for the history information to be output externally, the supply of operating power to the MPU 62 must be restarted with the reading device electrically connected to the reading terminal 102. The power control unit for stopping and starting the supply of operating power to the MPU 62 is located on the back of the back pack unit 15. Therefore, in order to perform these stopping and starting operations, the gaming machine body 12 must be opened from the outer frame 11 to expose the back of the back pack unit 15. Under these circumstances, by configuring the system so that the supply of operating power to the MPU 62 is restarted with the reading device electrically connected to the reading terminal 102 in order for the history information to be output externally, it becomes difficult for anyone other than the gaming hall manager to read the history information.

[0254] If a positive result is obtained in step S901, it is determined whether or not a signal for confirming control information is received from the reading terminal 102, thereby determining whether the current connection of the reading device to the reading terminal 102 corresponds to the confirmation of control information (program and data) of the main ROM 64 (step S902). The reading device is configured to perform both confirmation of control information and confirmation of history information. If confirmation of control information is selected by manual operation of the reading device, a signal for confirming control information is transmitted from the reading device. If confirmation of history information is selected by manual operation of the reading device, a signal for confirming history information is transmitted from the reading device. However, this is not limited to this configuration, and the reading device for confirming control information and the reading device for confirming history information may be separate. In this case, if the reading device for confirming control information is electrically connected to the reading terminal 102, a signal for confirming control information is transmitted from that reading device. If the reading device for confirming history information is electrically connected to the reading terminal 102, a signal for confirming history information is transmitted from that reading device.

[0255] If a positive result is obtained in step S902, output processing for confirming control information is executed (step S903). In this output processing, the program and data are read from the main ROM 64 as control information, and the read control information is output to the reading terminal 102. This makes it possible to read the control information with a reading device electrically connected to the reading terminal 102, and to confirm whether the control information is legitimate or normal.

[0256] If a negative determination is made in step S902, an output instruction signal is sent to the management CPU 112 (step S904). Specifically, the output state of the output instruction signal is switched from LOW level to HI level. This HI level output state is maintained for a specific period. This specific period is sufficient for the management CPU 112 to determine that a HI level output instruction signal has been input to the 16th buffer 122p. When the output state of the output instruction signal is switched to HI level, the management CPU 112 executes a process to output history information. This process will be explained in detail later.

[0257] If the process in step S903 or step S904 is executed, it is determined whether the electrical connection of the reading device to the reading terminal 102 is still maintained (step S905). If it is maintained (step S905: YES), the process remains in wait at step S905. This prevents processes that are scheduled to run later than the data output process from being executed until the electrical connection of the reading device to the reading terminal 102 is disconnected. If the electrical connection of the reading device to the reading terminal 102 is disconnected (step S905: NO), the data output process is terminated.

[0258] Next, the external output processing performed by the management CPU 112 will be explained with reference to the flowchart in Figure 24. Note that the external output processing is performed in step S608 of the management processing (Figure 18).

[0259] If the output state of the output instruction signal received from the main CPU 63 is switched from LOW level to HI level (step S1001: YES), the process for outputting history information from step S1002 onwards is executed. Specifically, first, the number of balls that enter the outlet 24a is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence information indicating that it is the outlet 24a is stored (step S1002). Next, the number of balls that enter the general prize pocket 31 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence information indicating that it is the general prize pocket 31 is stored (step S1003). Finally, the number of balls that enter the special prize pocket 32 ​​is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where correspondence information indicating that it is the special prize pocket 32 ​​is stored (step S1004). Furthermore, the number of balls that enter the first operation port 33 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that it is the first operation port 33 (step S1005). Furthermore, the number of balls that enter the second operation port 34 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that it is the second operation port 34 (step S1006).

[0260] Subsequently, the number of balls that entered each of the out-port 24a, general-purpose-entry-port 31, special-purpose-entry-device 32, first-operation-port 33, and second-operation-port 34 when the front door frame 14 was in the open state is calculated by referring to the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence information and start information indicating that it is the front door frame 14, and the history information storage area 125 in which correspondence information and end information indicating that it is the front door frame 14. Furthermore, if there are multiple intervals in the entire sequence of pointer information between the history information storage area 125 where correspondence information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 where correspondence information and end information indicating that it is the front door frame 14 are stored, the total number of balls that enter each interval is calculated. Also, if there is a history information storage area 125 where correspondence information and start information indicating that it is the front door frame 14 are stored, but the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence information and start information indicating that it is the front door frame 14 is stored does not contain the correspondence information and start information indicating that it is the front door frame 14, then the history information in the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence information and start information indicating that it is the front door frame 14 are stored is treated as if the front door frame 14 was in an open state.

[0261] Subsequently, various parameters are calculated using the calculation results from steps S1002 to S1007 (step S1008). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1007, is subtracted from the number of balls that entered calculated in each of steps S1002 to S1006. Then, the following parameters are calculated using the number of balls that entered after this subtraction. Furthermore, the difference between the number of balls entered through the out-port 24a calculated in step S1007 and the number of balls entered in step S1002 is defined as the number of balls entered K1, the difference between the number of balls entered through the general prize-winning port 31 calculated in step S1007 and the number of balls entered in step S1003 is defined as the number of balls entered K2, the difference between the number of balls entered through the special electric prize-winning device 32 calculated in step S1007 and the number of balls entered in step S1004 is defined as the number of balls entered K3, the difference between the number of balls entered through the first operating port 33 calculated in step S1007 and the number of balls entered in step S1005 is defined as the number of balls entered K4, and the difference between the number of balls entered through the second operating port 34 calculated in step S1007 and the number of balls entered in step S1006 is defined as the number of balls entered K5. • Parameter 1: Total number of game balls dispensed (K2 × "Number of prize balls for winning at the general prize slot 31" + K3 × "Number of prize balls for winning at the special electric prize device 32" + K4 × "Number of prize balls for winning at the first operating slot 33" + K5 × "Number of prize balls for winning at the second operating slot 34") / Ratio of the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (Hereafter, this ratio will be referred to as "D1") • Second parameter: The ratio of the total number of game balls entered into the general prize slot 31 (K2) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5). • Third parameter: The ratio of the total number of game balls entered into the special prize-winning device 32 (K3) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5). • Fourth parameter: The ratio of the total number of game balls entered into the first operating port 33 (K4) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D2"). • Fifth parameter: The ratio of the total number of game balls entered into the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D3"). • Parameter 6: D1 - (D2 × "Number of prize balls awarded for winning in the first operating slot 33" + D3 × "Number of prize balls awarded for winning in the second operating slot 34") • Parameter 7: (K3 × "Number of prize balls awarded for winning into the special electric prize device 32" + K5 × "Number of prize balls awarded for winning into the second operating port 34") / Ratio of the total number of game balls dispensed (K2 × "Number of prize balls awarded for winning into the general prize port 31" + K3 × "Number of prize balls awarded for winning into the special electric prize device 32" + K4 × "Number of prize balls awarded for winning into the first operating port 33" + K5 × "Number of prize balls awarded for winning into the second operating port 34") • Parameter 8: K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" / Total number of game balls dispensed (K2 × "Number of prize balls awarded for winning in the general prize winning slot 31" + K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" + K4 × "Number of prize balls awarded for winning in the first operating slot 33" + K5 × "Number of prize balls awarded for winning in the second operating slot 34") Subsequently, the oldest and newest RTC information in the history area 124 of the history memory 117 is used to calculate the total time required to extract all the history information that was the subject of the calculation (step S1009). Then, the first output processing is executed (step S1010). In the first output processing, all the history information stored in the history area 124 of the history memory 117 is sequentially output to the read terminal 102. In addition, the various parameters calculated in step S1008 are sequentially output to the read terminal 102, and the total time calculated in step S1009 is also output to the read terminal 102. As a result, each piece of information that was the target of output in the first output processing is read by a reading device electrically connected to the read terminal 102.

[0262] Subsequently, the number of balls that entered each of the out gate 24a, general prize gate 31, special electric prize device 32, first operation gate 33, and second operation gate 34 while in the open / close execution mode is calculated by referring to the history information storage area 125 that exists during the period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in the open / close execution mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in the open / close execution mode (step S1011). The period between the history information storage area 125 in the history area 124 of the history memory 117, which stores correspondence relationship information and start information indicating that it is in the open / close execution mode, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in the open / close execution mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple intervals in the entire sequence of pointer information between the history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode are stored and the history information storage area 125 where correspondence relationship information and end information indicating that it is in open / close execution mode are stored, the total number of balls entered for each interval is calculated. Also, if there is a history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode are stored, but the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode is stored does not contain the correspondence relationship information and start information indicating that it is in open / close execution mode, then the history information in the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence relationship information and start information indicating that it is in open / close execution mode is treated as being in open / close execution mode.

[0263] Subsequently, during the period of the opening / closing execution mode identified in step S1011, the number of balls that entered each of the out-out opening 24a, general prize-winning opening 31, special electric prize-winning device 32, first operating opening 33, and second operating opening 34 while the front door frame 14 was in the open state is calculated (step S1012). The method for calculating these ball entry numbers is the same as in step S1007, except that it assumes the period of the opening / closing execution mode identified in step S1011.

[0264] Subsequently, various parameters are calculated using the calculation results from steps S1011 and S1012 (step S1013). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1012, is subtracted from the number of balls that entered each way, calculated in step S1011. Then, the following parameters are calculated using the number of balls that entered each way after this subtraction. Note that the difference between the number of balls that entered the out-out opening 24a calculated in step S1011 and the number of balls that entered the out-out opening 24a calculated in step S1012 is defined as the number of balls that entered, and the difference between the number of balls that entered the general prize-winning opening 31 calculated in step S1011 and the number of balls that entered the general prize-winning opening 31 calculated in step S1012 is defined as the number of balls that entered, calculated in step S1012. The difference in the number of balls that enter the special electric prize device 32 calculated in step S1012 is defined as the number of balls entered K13, the difference in the number of balls that enter the first operating port 33 calculated in step S1012 compared to the number of balls that enter the first operating port 33 calculated in step S1011 is defined as the number of balls entered K14, and the difference in the number of balls that enter the second operating port 34 calculated in step S1012 compared to the number of balls that enter the second operating port 34 calculated in step S1011 is defined as the number of balls entered K15. • Parameter 11: Total number of game balls dispensed (K12 × "Number of prize balls for winning at the general prize slot 31" + K13 × "Number of prize balls for winning at the special electric prize device 32" + K14 × "Number of prize balls for winning at the first operating slot 33" + K15 × "Number of prize balls for winning at the second operating slot 34") / Ratio of the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (Hereafter, this ratio will be referred to as "D11") • Parameter 12: The ratio of the total number of game balls entered into the general prize slot 31 (K12) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15). • Parameter 13: The ratio of the total number of game balls entered into the special prize-winning device 32 (K13) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15). • Parameter 14: The ratio of the total number of game balls entered into the first operating port 33 (K14) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D12"). • Parameter 15: The ratio of the total number of game balls entered into the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13"). • Parameter 16: D11 - (D12 × "Number of prize balls awarded for winning in the first operating slot 33" + D13 × "Number of prize balls awarded for winning in the second operating slot 34") • Parameter 17: (K13 × "Number of prize balls awarded for winning into the special electric prize device 32" + K15 × "Number of prize balls awarded for winning into the second operating port 34") / Ratio of the total number of game balls dispensed (K12 × "Number of prize balls awarded for winning into the general prize port 31" + K13 × "Number of prize balls awarded for winning into the special electric prize device 32" + K14 × "Number of prize balls awarded for winning into the first operating port 33" + K15 × "Number of prize balls awarded for winning into the second operating port 34") • Parameter 18: K13 × "Number of prize balls awarded for winning in the special electric prize winning device 32" / Ratio of total number of game balls dispensed (K12 × "Number of prize balls awarded for winning in the general prize winning slot 31" + K13 × "Number of prize balls awarded for winning in the special electric prize winning device 32" + K14 × "Number of prize balls awarded for winning in the first operating slot 33" + K15 × "Number of prize balls awarded for winning in the second operating slot 34") Subsequently, the second output processing is performed (step S1014). In the second output processing, the various parameters calculated in step S1013 are sequentially output to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads each piece of information that was output in the second output processing.

[0265] Subsequently, the number of balls that entered each of the out gate 24a, general prize gate 31, special electric prize device 32, first operation gate 33, and second operation gate 34 during the high-frequency support mode is calculated by referring to the history information storage area 125 that exists during the period between the history information storage area 125 in the history area 124 of the history memory 117, where correspondence relationship information and start information indicating that it is in high-frequency support mode are stored, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in high-frequency support mode (step S1015). The period between the history information storage area 125 in the history area 124 of the history memory 117, where correspondence relationship information and start information indicating that it is in high-frequency support mode are stored, and the history information storage area 125 that stores correspondence relationship information and end information indicating that it is in high-frequency support mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple intervals in the entire sequence of pointer information between the history information storage area 125 where correspondence relationship information and start information indicating high-frequency support mode are stored and the history information storage area 125 where correspondence relationship information and end information indicating high-frequency support mode are stored, the total number of balls entered for each interval is calculated. Also, if there is a history information storage area 125 where correspondence relationship information and start information indicating high-frequency support mode are stored, but the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence relationship information and start information indicating high-frequency support mode are stored does not contain correspondence relationship information and start information indicating high-frequency support mode, then the history information in the history information storage area 125 where RTC information corresponding to a later time than the history information storage area 125 where correspondence relationship information and start information indicating high-frequency support mode are stored is treated as being in high-frequency support mode.

[0266] Subsequently, during the period of high-frequency support mode identified in step S1015, the number of balls that entered each of the out-port 24a, general-purpose entry port 31, special-electric entry device 32, first-operation port 33, and second-operation port 34 while the front door frame 14 was in an open state is calculated (step S1016). The method for calculating these ball entry numbers is the same as in step S1007, except that it assumes the period of high-frequency support mode identified in step S1015.

[0267] Subsequently, various parameters are calculated using the calculation results from steps S1015 and S1016 (step S1017). Specifically, first, the number of balls that entered while the front door frame 14 was open, calculated in step S1016, is subtracted from the number of balls that entered each way, calculated in step S1015. Then, the following parameters are calculated using the number of balls that entered each way after this subtraction. Note that the difference between the number of balls that entered the out-out opening 24a calculated in step S1015 and the number of balls that entered the out-out opening 24a calculated in step S1016 is defined as the number of balls entered, the difference between the number of balls that entered the general prize-winning opening 31 calculated in step S1015 and the number of balls that entered the general prize-winning opening 31 calculated in step S1016 is defined as the number of balls entered, and the step of the number of balls that entered the special electric prize-winning device 32 calculated in step S1015 is defined as the number of balls entered. The difference in the number of balls that enter the special electric prize device 32 calculated in step S1016 is defined as the number of balls entered K23, the difference in the number of balls that enter the first operating port 33 calculated in step S1016 compared to the number of balls that enter the first operating port 33 calculated in step S1015 is defined as the number of balls entered K24, and the difference in the number of balls that enter the second operating port 34 calculated in step S1016 compared to the number of balls that enter the second operating port 34 calculated in step S1015 is defined as the number of balls entered K25. • Parameter 21: Total number of game balls dispensed (K22 × "Number of prize balls for entry into general prize slot 31" + K23 × "Number of prize balls for entry into special electric prize device 32" + K24 × "Number of prize balls for entry into first operation slot 33" + K25 × "Number of prize balls for entry into second operation slot 34") / Ratio of the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (Hereafter, this ratio will be referred to as "D11") • Parameter 22: The ratio of the total number of game balls entered into the general prize slot 31 (K22) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25). • Parameter 23: The ratio of the total number of game balls entered into the special prize-winning device 32 (K23) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25). • Parameter 24: The ratio of the total number of game balls entered into the first operating port 33 (K24) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D22"). • Parameter 25: The ratio of the total number of game balls entered into the second operating port 34 (K25) to the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio will be referred to as "D23"). • Parameter 26: D21 - (D22 × "Number of prize balls awarded for winning in the first operating slot 33" + D23 × "Number of prize balls awarded for winning in the second operating slot 34") Subsequently, the third output process is executed (step S1018). In the third output process, the various parameters calculated in step S1017 are sequentially output to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads each piece of information that was output in the third output process. After that, a clear process is executed (step S1019). In the clear process, the history information storage area 125 of the history memory 117 is cleared to "0", and the pointer area 126 is also cleared to "0". As a result, the history area 124 is initialized.

[0268] The embodiment described in detail above provides the following excellent effects.

[0269] Since game balls are dispensed when they enter any of the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, and the second operation slot 34, players play the game expecting game balls to enter one of these entry slots. In this configuration, when a game ball enters any of the out slot 24a, the general prize entry slot 31, the special electric prize entry device 32, the first operation slot 33, and the second operation slot 34 (hereinafter also referred to as the history target entry slots), the corresponding history information is stored in the history memory 117 of the management IC 66. This makes it possible for the pachinko machine 10 to store information for managing the number of game balls entered or the frequency of entry into each history target entry slot, and by using this managed information, it becomes possible to appropriately manage the manner in which game balls enter each history target entry slot. Furthermore, since the history information is stored in the pachinko machine 10 itself, it is possible to prevent unauthorized access to or modification of the history information.

[0270] All ball entry points that eject game balls from the game area PA are subject to history information storage processing and management using that history information. This makes it possible to manage the ball entry frequency for any target ball entry point using the history information. Furthermore, it becomes possible to manage the ratio of the number of game balls entered into each target ball entry point to the total number of game balls ejected from the game area PA using the history information.

[0271] The history information includes RTC information, which corresponds to the timing when a game ball entered the designated ball entry area that triggered the recording of that history information. This makes it possible to understand in detail the history of game balls entering the designated ball entry area by using the history information.

[0272] The history memory 117 stores not only history information corresponding to when a game ball enters the history target ball entry section, but also history information indicating whether or not the system is in opening / closing execution mode, whether or not it is in high-frequency support mode, and whether or not the front door frame 14 is open. This makes it possible to distinguish between each of these situations and manage the manner in which game balls enter the history target ball entry section.

[0273] The history information stored in the history memory 117 can be output to a reading device, which is an external device of the pachinko machine 10. This allows the reading device to read the history information and use that information to analyze the pattern of game balls entering the history target ball entry section.

[0274] The MPU62 is provided with a read terminal 102, and a read device electrically connected to this terminal 102 can read the program from the main ROM64. This makes it possible to verify whether the program is valid or not. In this configuration, the read terminal 102 for outputting the program externally is used to output the history information stored in the history memory 117 externally. This makes it possible to output the history information externally while preventing the configuration from becoming overly complex.

[0275] The system identifies whether the information to be output from the reading terminal 102 is program information or history information, and the information corresponding to that identification result is output externally through the reading terminal 102. In this configuration, where history information is output externally using the reading terminal 102 used for outputting programs, the pachinko machine 10 identifies whether the information to be output externally is program information or history information, and that identified information is output externally. Therefore, even in a configuration where the reading terminal 102 is used for both purposes, it is possible to read only the necessary information.

[0276] Based on the information received from the reading device electrically connected to the reading terminal 102, it is determined whether the information to be output from the reading terminal 102 is program information or history information. This makes it possible to avoid complicating the configuration for selecting the information to be output externally.

[0277] The MPU 62, which has a main ROM 64 for pre-storing programs, also has a management IC 66 and a read terminal 102. This makes it possible to consolidate the signal path to the read terminal 102 within the MPU 62. Therefore, it becomes difficult to perform unauthorized access to the signal path to the read terminal 102, while achieving the excellent effects already described.

[0278] In addition to the main CPU 63, which performs processing to ensure that game balls are dispensed based on the entry of game balls into any of the general prize entry slot 31, special electric prize entry device 32, first operation slot 33, and second operation slot 34, a separate management CPU 112 is provided. The management CPU 112 performs processing to store history information in the history memory 117. This makes it possible to manage the entry patterns of game balls into each history target entry slot without excessively increasing the processing load of the main CPU 63.

[0279] The main CPU 63 and the management CPU 112 are provided on the same chip as the MPU 62. This makes it possible to prevent unauthorized access to the communication path between the main CPU 63 and the management CPU 112.

[0280] The main CPU 63 transmits information corresponding to the detection results of each ball entry detection sensor 42a to 48a to the respective buffers 122a to 122g of the input port 121 of the management IC 66, using the signal paths corresponding to each of the ball entry detection sensors 42a to 48a. This ensures that the type of information transmitted from the main CPU 63 corresponds to each buffer 122a to 122g (i.e., each signal path), simplifying the configuration required for the management CPU 112 to distinguish between different types of information.

[0281] The main CPU 63 transmits information corresponding to whether or not it is in opening / closing execution mode, information corresponding to whether or not it is in high-frequency support mode, and information corresponding to whether or not the front door frame 14 is open to the respective buffers 122h to 122j of the input port 121 of the management IC 66, using the signal paths corresponding to each of these conditions. This ensures that the type of information corresponding to each of these conditions corresponds to each buffer 122h to 122j (i.e., each signal path), simplifying the configuration for the management CPU 112 to distinguish between the types of information.

[0282] The main CPU 63 transmits correspondence information to the management CPU 112 indicating which type of information each buffer 122a to 122j (i.e., each signal path 118a to 118j) corresponds to. This eliminates the need for the management IC 66 to store this correspondence information in advance. Thus, the versatility of the management IC 66 can be increased.

[0283] When power is supplied to the main CPU 63, correspondence information is transmitted from the main CPU 63 to the management IC 66. This makes it possible for the management IC 66 to identify the correspondence between the information transmitted from the main CPU 63 and the history target ball entry unit in situations where a game ball may be entered into the history target ball entry unit.

[0284] Correspondence information is transmitted from the main CPU 63 to the management IC 66 using signal paths 118a to 118g, which are used to transmit information indicating whether or not a game ball has entered the ball entry section for history tracking. This simplifies the communication configuration compared to a configuration that provides a dedicated signal path for transmitting correspondence information.

[0285] The management IC 66 is equipped with a correspondence memory 116, and the correspondence information transmitted from the main CPU 63 to the management IC 66 is stored in the correspondence memory 116. This eliminates the need for the main CPU 63 to provide information that would allow the management IC 66 to identify the history target ball entry section corresponding to the information to be transmitted, each time it transmits the detection result information from each ball entry detection sensor 42a to 48a. Therefore, it is possible to reduce the amount of information transmitted from the main CPU 63 regarding the detection result information from each ball entry detection sensor 42a to 48a.

[0286] When the output state of the output instruction signal output from the main CPU 63 to the management IC 66 switches from a LOW level to a HI level, information is output from the management IC 66 to the read terminal 102. In this case, the management CPU 112 can determine that the signal path corresponding to the 16th buffer 122p corresponds to the output instruction signal without receiving correspondence information from the main CPU 63. This makes it possible to prevent the configuration for transmitting correspondence information from becoming excessively complex.

[0287] The management IC 66 is equipped with buffers 122a to 122p capable of receiving information from the main CPU 63, with a number of buffers greater than the number of types of information that the main CPU 63 needs to send to the management IC 66. This makes it possible to accommodate changes in the number of types of information depending on the model of the pachinko machine 10 without changing the configuration of buffers 122a to 122p. Thus, the versatility of the management IC 66 can be increased.

[0288] When history information is transmitted from the management IC 66 to the reading terminal 102, each history entry contains correspondence information indicating the type of ball entry section that corresponds to the history information. This makes it possible to identify the method of ball entry into each ball entry section using the read history information.

[0289] In the management IC66, various parameters (parameters 1-8, 11-18, 21-26) corresponding to the ball entry patterns in the game area PA during a predetermined period are calculated using the history information stored in the history memory 117. This makes it possible to output the various parameters calculated using the history information to an external source.

[0290] Various parameters are calculated while excluding historical information corresponding to the situation where the front door frame 14 is open. This makes it possible to derive various parameters for the normal situation where the front door frame 14 is closed. In addition, various parameters corresponding to the situation in open / close execution mode and the situation in high-frequency support mode are calculated. This makes it possible for managers of gaming halls to understand the ball entry patterns according to each situation.

[0291] When various parameters are calculated, the history memory 117 is initialized by executing a clear process. This makes it less likely that history information that should be stored in the history memory 117 will be overwritten and erased, as the amount of history information to be stored in the history memory 117 will exceed its storage capacity.

[0292] When various parameters are output to the read terminal 102, the history information stored in the history memory 117 is also output to the read terminal 102. This makes it possible to read various parameters and analyze the ball entry patterns in the game area PA, by referring not only to the various parameters but also to the history information that formed the basis for the calculation of those parameters.

[0293] The management CPU 112 calculates various parameters when a reading device is electrically connected to the reading terminal 102. This makes it possible to reduce the frequency of calculating various parameters.

[0294] The main CPU 63 identifies that a reading device is electrically connected to the reading terminal 102, and when output instruction information is transmitted from the main CPU 63, various parameters are calculated by the management IC 66, and the various parameters resulting from these calculations are output to the reading terminal 102. This makes it possible to output various parameters to a reading device outside the pachinko machine 10 based on instructions from the main CPU 63.

[0295] During the power supply start-up process executed by the main CPU 63, it is determined whether or not a reading device is electrically connected to the reading terminal 102. If it is determined that the reading device is electrically connected, output instruction information is sent from the main CPU 63 to the management IC 66. As a result, while the power supply start-up process is being executed by the main CPU 63, that is, before the normal processing for advancing the game is started by the main CPU 63, the calculation of various parameters and the external output of the calculation results of those parameters are completed. Therefore, it is possible to prevent the calculation of various parameters and the external output of the calculation results from occurring in situations where a game ball may be entered into the history target ball entry section, thereby reducing the processing load on the management IC 66.

[0296] In a configuration where an external output is made via the external terminal board 97 when a game ball enters the first operation port 33 or the second operation port 34, history information is stored in the history memory 117. This makes it possible to easily grasp the number and frequency of game balls entering the first operation port 33 or the second operation port 34 by using the information output externally via the external terminal board 97, and to accurately grasp the number and frequency of game balls entering the history target ball entry section by using the history information stored in the history memory 117.

[0297] <Second Embodiment> In this embodiment, the type of buffer among the first to 16th buffers 122a to 122p of the input port 121 of the management I / F 111, in which the type of input signal is determined at the design stage of the management IC 66, differs from that of the first embodiment. Also, the processing configuration executed by the main CPU 63 to specify the type of input signal to the management CPU 112 differs from that of the first embodiment. The configurations that differ from those of the first embodiment will be described below. Configurations that are the same as those of the first embodiment will generally not be described.

[0298] Figure 25 is an explanatory diagram illustrating the configuration of the input port 121 of the management interface 111 in this embodiment.

[0299] The first to seventh buffers 122a to 122g and the sixteenth buffer 122p are input to the same type of signal as in the first embodiment described above. In detail, the first buffer 122a receives a first signal corresponding to the detection result of the first prize-winning slot detection sensor 42a, the second buffer 122b receives a second signal corresponding to the detection result of the second prize-winning slot detection sensor 43a, the third buffer 122c receives a third signal corresponding to the detection result of the third prize-winning slot detection sensor 44a, the fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a, the fifth buffer 122e receives a fifth signal corresponding to the detection result of the first operation slot detection sensor 46a, the sixth buffer 122f receives a sixth signal corresponding to the detection result of the second operation slot detection sensor 47a, the seventh buffer 122g receives a seventh signal corresponding to the detection result of the output slot detection sensor 48a, and the sixteenth buffer 122p receives an output instruction signal.

[0300] On the other hand, in the first embodiment described above, a signal corresponding to the opening / closing execution mode is input to the eighth buffer 122h as the eighth signal, a signal corresponding to the high-frequency support mode is input to the ninth buffer 122i as the ninth signal, and a signal corresponding to the front door frame 14 is input to the tenth buffer 122j as the tenth signal. However, in this embodiment, the buffers to which these signals are input are different. Specifically, a signal corresponding to the opening / closing execution mode is input to the thirteenth buffer 122m as an opening / closing execution mode signal, a signal corresponding to the high-frequency support mode is input to the fourteenth buffer 122n as a high-frequency support mode signal, and a signal corresponding to the front door frame 14 is input to the fifteenth buffer 122o as a door open signal.

[0301] The fact that the open / close execution mode signal is input to the 13th buffer 122m, the high-frequency support mode signal is input to the 14th buffer 122n, the door open signal is input to the 15th buffer 122o, and the output instruction signal is input to the 16th buffer 122p is determined during the design phase of the management IC 66. Without receiving instructions from the main CPU 63, the management CPU 112 can identify that the corresponding signals are input to the 13th to 16th buffers 122m to 122p. On the other hand, the types of signals input to the 1st to 12th buffers 122a to 122l are not determined during the design phase of the management IC 66, and the types of these signals are identified by the management CPU 112 upon receiving instructions from the main CPU 63. This process for identifying the types of signals is executed when power is supplied to the main CPU 63 and the management CPU 112, similar to the first embodiment described above.

[0302] Figure 26 is a flowchart showing the recognition process of this embodiment, which is executed by the main CPU 63. The recognition process is executed in step S110 of the main process (Figure 7), similar to the first embodiment described above.

[0303] First, the recognition output counter of the main RAM 65 is set to "12," which is the number of the first to twelfth buffers 122a to 122l that are the targets for recognition of the signal type (step S1101). Then, the output processing of the identification start signal is executed (step S1102). In this output processing, the output state of the first signal input to the first buffer 122a, the open / close execution mode signal input to the thirteenth buffer 122m, and the high-frequency support mode signal input to the fourteenth buffer 122n are set to HI level to start outputting the identification start signal. The period for which these signals are maintained at HI level is set to a period sufficient for the management CPU 112 to recognize the output state of these signals.

[0304] Subsequently, the output count information corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64, and this read output count information is set in the output count counter provided in the main RAM 65 (step S1103). The output count counter is a counter used by the main CPU 63 to identify the number of outputs of the type identification signal.

[0305] In this embodiment, when the management CPU 112 is made to recognize the type of signal input to the first buffer 122a to the twelfth buffer 122l, it outputs a type identification signal the same number of times as the number of prize balls set for the ball entry unit corresponding to that signal type. The management CPU 112 stores information corresponding to the number of times the type identification signal has been received for each of the first buffer 122a to the twelfth buffer 122l in the first to twelfth correspondence areas 123a to 123l of the correspondence memory 116. In other words, the type of signal input to the first buffer 122a to the twelfth buffer 122l is understood as the number of prize balls set for the ball entry unit corresponding to that signal type.

[0306] In step S1103, if the value of the recognition output counter is "12", "11", or "10", the output count counter is set to "10", which corresponds to the number of prize balls awarded by the general prize slot 31. If the value of the recognition output counter is "9", the output count counter is set to "15", which corresponds to the number of prize balls awarded by the special electric prize slot 32. If the value of the recognition output counter is "8", the output count counter is set to "1", which corresponds to the number of prize balls awarded by the first operation slot 33. If the value of the recognition output counter is "7", the output count counter is set to "1", which corresponds to the number of prize balls awarded by the second operation slot 34. If the value of the recognition output counter is "6", although it corresponds to the out slot 24a, the game balls will not be dispensed even if a game ball enters the out slot 24a, so the output count counter is set to "0". Furthermore, if the value of the recognition output counter is any of "5" to "1", it means that there is no corresponding ball entry area and it is blank, so the output count counter is set to "0".

[0307] Subsequently, the output processing of the start trigger signal is performed (step S1104). In this output processing, the output state of the first signal input to the first buffer 122a is set to a HI level to start outputting the start trigger signal. The period for which the first signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the first signal.

[0308] Subsequently, provided that the value of the output count counter in the main RAM 65 is not "0" (step S1105: YES), that is, provided that a value of 1 or more was set in the output count counter in step S1103, the process proceeds to step S1106. In step S1106, the output processing of the type identification signal is performed. In this output processing, the output of the type identification signal is started by setting the output state of the second signal input to the second buffer 122b to a HI level. The period for which the second signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the second signal.

[0309] Subsequently, the value of the output count counter in the main RAM 65 is deducted by 1 (step S1107), and it is determined whether the value of the output count counter after the deduction is "0" (step S1108). If the value of the output count counter is 1 or greater (step S1108: NO), the process returns to step S1106.

[0310] If a positive determination is made in step S1105, or in step S1108, the termination signal output process is executed (step S1109). In this output process, the output state of the third signal input to the third buffer 122c is set to HI level to start outputting the termination signal. The period for which the third signal is maintained at HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the third signal.

[0311] Subsequently, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S1110), and it is determined whether the value of the recognition output counter after the 1-decrement is "0" or not (step S1111). If the value of the recognition output counter is 1 or greater (step S1111: NO), the process returns to step S1103 and executes a process to recognize the type of signal corresponding to the value of the recognition output counter after the 1-decrement.

[0312] On the other hand, if the value of the recognition output counter is "0" (step S1111: YES), the process of outputting the identification completion signal is executed (step S1112). In this output process, the output state of the third signal input to the third buffer 122c, the open / close execution mode signal input to the thirteenth buffer 122m, and the high-frequency support mode signal input to the fourteenth buffer 122n are set to HI level, thereby initiating the output of the identification completion signal. The period for which these signals are maintained at HI level is set to a period sufficient for the management CPU 112 to recognize the output state of these signals.

[0313] Next, the management process in this embodiment, which is executed by the management CPU 112, will be explained with reference to the flowchart in Figure 27. The management process starts when the supply of operating power to the management CPU 112 begins, similar to the first embodiment described above.

[0314] If the reception of the identification start signal from the main CPU 63 is complete (step S1201: YES), the value of the setting target counter in the management RAM 114 is cleared to "0" (step S1202). Then, assuming that the start trigger signal has been received from the main CPU 63 (step S1203: YES), the process proceeds to step S1204. In step S1204, it is determined whether or not a type identification signal has been received from the main CPU 63. If a type identification signal has been received (step S1204: YES), the value of the reception count counter in the management RAM 114 is incremented by 1 (step S1205). The reception count counter is used by the management CPU 112 to determine the number of times the type identification signal has been received from the main CPU 63. The value of the reception count counter is cleared to "0" if a positive determination is made in step S1203.

[0315] If a negative determination is made in step S1204, or if the process in step S1205 is executed, it is determined whether or not a termination trigger signal has been received from the main CPU 63 (step S1206). If a termination trigger signal has not been received (step S1206: NO), the process returns to step S1204. If a termination trigger signal has been received (step S1206: YES), the correspondence setting process is executed (step S1207). In the correspondence setting process, the value set in the reception count counter is stored in the correspondence area of ​​the first to twelfth correspondence areas 123a to 123l of the correspondence memory 116 that corresponds to the current value of the setting target counter in the management RAM 114. In this case, the first correspondence area 123a, the second correspondence area 123b, and the third correspondence area 123c are set to "10" corresponding to the number of prize balls awarded by the general prize slot 31, the fourth correspondence area 123d is set to "15" corresponding to the number of prize balls awarded by the special electric prize device 32, the fifth correspondence area 123e is set to "1" corresponding to the number of prize balls awarded by the first operation slot 33, and the sixth correspondence area 123f is set to "1" corresponding to the number of prize balls awarded by the second operation slot 34. In addition, the seventh to twelfth correspondence areas 123g to 123l are set to "0". After that, the value of the setting target counter in the management side RAM 114 is incremented by 1 (step S1208).

[0316] If a negative determination is made in step S1203, or if the process in step S1208 is executed, it is determined whether or not the reception of the identification end signal from the main CPU 63 has finished (step S1209). If the reception of the identification end signal has not finished (step S1209: NO), the process returns to step S1203, and the process from step S1204 onwards is executed on the condition that a start trigger signal is received from the main CPU 63 (step S1203: YES). If the reception of the identification end signal from the main CPU 63 has finished (step S1209: YES), the history setting process in step S1210 and the external output process in step S1211 are repeatedly executed.

[0317] Figure 28 is a time chart showing how information regarding the correspondence between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l is stored in the correspondence memory 116. Figure 28(a) shows the period during which the output state of the first signal is at a HI level, Figure 28(b) shows the period during which the output state of the second signal is at a HI level, Figure 28(c) shows the period during which the output state of the third signal is at a HI level, Figure 28(d) shows the period during which the output state of the signal is at a HI level during the opening / closing execution mode, Figure 28(e) shows the period during which the output state of the signal is at a HI level during the high-frequency support mode, Figure 28(f) shows the execution period of the identification state during which processing is performed to identify the correspondence between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l, Figure 28(g) shows the timing when the value of the reception count counter in the management RAM 114 is incremented by 1, and Figure 28(h) shows the timing when the correspondence setting processing (step S1207) is executed in the management CPU 112.

[0318] As power is supplied to the main CPU 63 and the management CPU 112, at timing t1, the output states of the first signal, the switching execution mode signal, and the high-frequency support mode signal are changed from LOW to HI, as shown in Figures 28(a), 28(d), and 28(e). This initiates the output of the identification start signal from the main CPU 63 to the management CPU 112. Subsequently, at timing t2, the output states of the first signal, the switching execution mode signal, and the high-frequency support mode signal are changed from HI to LOW. This stops the output of the identification start signal from the main CPU 63 to the management CPU 112. At timing t2, the management CPU 112 makes an affirmative judgment in step S1201 of the management process (Figure 27), and enters the identified state as shown in Figure 28(f).

[0319] Subsequently, from timing t3 to t4, the output state of the first signal is maintained at a HI level, as shown in Figure 28(a). This results in the start trigger signal being output to the management CPU 112. Then, from timing t5 to t7, the output state of the second signal is maintained at a HI level, as shown in Figure 28(b). This results in the type identification signal being output once to the management CPU 112. In this case, at timing t6, the value of the reception count counter in the management RAM 114 is incremented by 1, as shown in Figure 28(g).

[0320] Subsequently, from timing t8 to timing t10, the output state of the third signal is maintained at a HI level as shown in Figure 28(c). This results in the management CPU 112 receiving a termination signal. In this case, at timing t9, the management CPU 112 executes the correspondence relationship setting process as shown in Figure 28(h). At the time when this correspondence relationship setting process is executed, the value of the reception count counter is "1", so the information "1" is stored as correspondence relationship information in the correspondence relationship areas 123a to 123l of the correspondence relationship memory 116 that are the target of this setting.

[0321] Subsequently, from timing t11 to t12, the output state of the first signal is maintained at a HI level, as shown in Figure 28(a). This results in the start trigger signal being output to the management CPU 112. Then, from timing t13 to t15, from timing t16 to t18, from timing t19 to t21, and from timing t22 to t24, the output state of the second signal is maintained at a HI level, as shown in Figure 28(b). This results in the type identification signal being output to the management CPU 112 once for each of these timings. In this case, at timings t14, t17, t20, and t23, the value of the reception count counter in the management RAM 114 is incremented by 1, as shown in Figure 28(g).

[0322] Subsequently, from timing t25 to t27, the output state of the third signal is maintained at a HI level as shown in Figure 28(c). This results in the termination trigger signal being output to the management CPU 112. In this case, at timing t26, the management CPU 112 executes the correspondence relationship setting process as shown in Figure 28(h). At the time when this correspondence relationship setting process is executed, the value of the reception count counter is "10", so the information "10" is stored as correspondence relationship information in the correspondence relationship areas 123a to 123l of the correspondence relationship memory 116 that are the target of this setting.

[0323] Subsequently, at timing t28, as shown in Figures 28(c), 28(d), and 28(e), the output state of the third signal, the switching execution mode signal, and the high-frequency support mode signal is changed from LOW to HI. This initiates the output of an identification completion signal from the main CPU 63 to the management CPU 112. Then, at timing t29, the output state of the third signal, the switching execution mode signal, and the high-frequency support mode signal is changed from HI to LOW. This stops the output of the identification completion signal from the main CPU 63 to the management CPU 112. At timing t29, the management CPU 112 makes an affirmative judgment in step S1209 of the management process (Figure 27), and the identification state is released as shown in Figure 28(f).

[0324] In this embodiment, since the number of prize balls is stored as correspondence information, the history information stored in the history memory 117 includes the number of prize balls corresponding to the ball entry point that triggered the storage of that history information as correspondence information. In this configuration, if there are multiple types of ball entry points with the same number of prize balls, it is not possible to distinguish between them in the history information. Specifically, since the first operation port 33 and the second operation port 34 both have a prize ball of 1, it is not possible to distinguish between the first operation port 33 and the second operation port 34 in the history information. In this case, the number of prize balls for the first operation port 33 and the second operation port 34 may be made different. This makes it possible to distinguish between the first operation port 33 and the second operation port 34 in the history information, even in a configuration where history information is stored as in this second embodiment.

[0325] Furthermore, in this embodiment, in step S801 of the history setting process, the counter to be checked in the management RAM 114 is set to "15". As a result, all of the first to fifteenth buffers 122a to 122o become targets for checking.

[0326] As described in detail above, according to this embodiment, not only the output instruction signal, but also the information corresponding to whether or not the machine is in opening / closing execution mode, whether or not it is in high-frequency support mode, and whether or not the front door frame 14 is open can be identified by the management CPU 112 as corresponding to the signal path from the main CPU 63 without receiving correspondence relationship information from the main CPU 63. In this case, only the information corresponding to the detection results of each ball entry detection sensor 42a to 48a is information that requires the main CPU 63 to recognize the correspondence relationship between each piece of information and each signal path 118a to 118g from the management CPU 112. When the management CPU 112 recognizes the correspondence relationship information, the same number of pulse signals as the number of prize balls corresponding to each ball entry detection sensor 42a to 48a are output from the main CPU 63 to the management CPU 112 using the second signal. This simplifies the configuration for transmitting correspondence relationship information.

[0327] <Third Embodiment> In this embodiment, the trigger for the calculation of various parameters using historical information differs from that of the first embodiment. The configurations that differ from the first embodiment will be described below. Configurations identical to those in the first embodiment will generally not be described.

[0328] Figure 29 is a block diagram illustrating the electrical configuration of the management IC 66 in this embodiment. The management IC 66 is equipped with a management-side I / F 111, a management-side CPU 112, a management-side ROM 113, a management-side RAM 114, an RTC 115, a correspondence memory 116, and a history memory 117, similar to those in the first embodiment. These functions are the same as those in the first embodiment.

[0329] In addition to the above, the management IC66 is also provided with a calculation result memory 131. In this embodiment, as will be described in detail later, when a calculation trigger occurs, the management CPU 112 calculates various parameters using the history information stored in the history memory 117 at that time. These calculated parameters are then sequentially stored in the calculation result memory 131. The parameters stored in the calculation result memory 131 are output to a reading device electrically connected to the reading terminal 102.

[0330] The calculation of various parameters occurs before the reading device is electrically connected to the reading terminal 102. This makes it possible to differentiate the timing of parameter calculation from the timing of outputting the results to the reading device, thereby distributing the processing load.

[0331] Furthermore, the provision of a calculation result memory 131 for storing the calculation results of various parameters makes it possible to store not only the various parameters for a single calculation event, but also the various parameters for multiple calculation events at once. This makes it possible to shorten the time required to calculate the various parameters for each calculation event.

[0332] Figure 30 is an explanatory diagram illustrating the configuration of the input port 121 of the management interface 111 in this embodiment.

[0333] The first to tenth buffers 122a to 122j and the sixteenth buffer 122p are input to the same type of signal as in the first embodiment described above. Specifically, the first buffer 122a is input to the first signal corresponding to the detection result of the first prize-winning opening detection sensor 42a, the second buffer 122b is input to the second signal corresponding to the detection result of the second prize-winning opening detection sensor 43a, the third buffer 122c is input to the third signal corresponding to the detection result of the third prize-winning opening detection sensor 44a, the fourth buffer 122d is input to the fourth signal corresponding to the detection result of the special electric detection sensor 45a, and the fifth buffer 122e is input to the fifth signal corresponding to the detection result of the first operation opening detection sensor 46a. A signal is input, the sixth signal corresponding to the detection result of the second operation port detection sensor 47a is input to the sixth buffer 122f, the seventh signal corresponding to the detection result of the outlet port detection sensor 48a is input to the seventh buffer 122g, the signal corresponding to the opening / closing execution mode is input to the eighth buffer 122h, the signal corresponding to the high-frequency support mode is input to the ninth buffer 122i, the signal corresponding to the front door frame 14 is input to the tenth buffer 122j, and the output instruction signal is input to the sixteenth buffer 122p.

[0334] In this embodiment, in addition to the various signals described above, a calculation instruction signal is input to the 15th buffer 122o. The calculation instruction signal is a signal output from the main CPU 63 to provide the management CPU 112 with a trigger for calculating various parameters. The input of the calculation instruction signal to the 15th buffer 122o is determined during the design phase of the management IC 66, similar to the input of the output instruction signal to the 16th buffer 122p. Without receiving instructions from the main CPU 63, the management CPU 112 can determine that the respective signals described above are input to these 15th to 16th buffers 122o to 122p. On the other hand, the types of signals input to the 1st to 14th buffers 122a to 122n are not determined during the design phase of the management IC 66. The types of these signals are determined by the management CPU 112 upon receiving instructions from the main CPU 63. The process for determining the type of signal is executed when power is supplied to the main CPU 63 and the management CPU 112, as in the first embodiment described above.

[0335] Next, we will describe the processing configuration for which the management CPU 112 performs calculations of various parameters in response to the occurrence of a calculation trigger. Figure 31 is a flowchart of the power outage information storage process executed by the main CPU 63. Note that the power outage information storage process is executed in step S201 of the timer interrupt processing (Figure 8).

[0336] In the power outage information storage process, if a power outage signal corresponding to a power interruption is received from the power outage monitoring board 67 (step S1301: YES), the output processing of the arithmetic instruction signal is executed (step S1302). In this output processing, the output state of the arithmetic instruction signal input to the 15th buffer 122o at the input port 121 of the management I / F 111 is maintained at a HI level for a specific period of time. This specific period is sufficient for the management CPU 112 to recognize that the output state of the arithmetic instruction signal is at a HI level. After that, in step S1303, the power outage processing is executed, and an infinite loop is entered, waiting until the supply of operating power to the main CPU 63 is completely stopped. In the power outage processing, the power outage flag in the main RAM 65 is set to "1", a checksum is calculated, and the calculated checksum is saved.

[0337] Figure 32 is a flowchart showing the power outage response process executed by the management CPU 112. Note that the power outage response process is executed after the external output process in the management process (Figure 18). In the management process, after receiving the identification completion command from the main CPU 63 (step S606: YES), the history setting process in step S607, the external output process in step S608, and the power outage response process are repeatedly executed in this order.

[0338] In the power outage response process, if the output status of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1401: YES), steps S1402 to S1406 calculate the number of balls that enter each of the outlet 24a, general prize entry 31, special electric prize entry device 32, first operation 33, and second operation 34, similar to steps S1002 to S1006 of the external output processing in the first embodiment (Figure 24). Also, in step S1407, similar to step S1007 of the external output processing in the first embodiment (Figure 24), calculate the number of balls that enter each of the outlet 24a, general prize entry 31, special electric prize entry device 32, first operation 33, and second operation 34. Furthermore, in step S1408, various parameters are calculated in the same way as in step S1008 of the external output processing in the first embodiment (Figure 24), and in step S1409, the total time is calculated in the same way as in step S1009 of the external output processing in the first embodiment (Figure 24). Then, the calculation result information from step S1408 and the calculation result information from step S1409 are written to the calculation result memory 131 (step S1410). In this case, if other calculation result information is already stored in the calculation result memory 131, the calculation result information is written in a way that does not overwrite the already stored calculation result information. In addition, the current date and time information is read from the RTC 115, and the read date and time information is associated with the calculation result information that was written this time. This makes it possible to identify what timing the calculation result information that was written this time corresponds to.

[0339] Subsequently, in step S1411, the number of balls that enter the gate during the opening / closing execution mode is calculated, similar to step S1011 of the external output processing in the first embodiment (Figure 24). In step S1412, the number of balls that enter the gate during the opening / closing execution mode while the front door frame 14 is open is calculated, similar to step S1012 of the external output processing in the first embodiment (Figure 24). Also, in step S1413, various parameters are calculated, similar to step S1013 of the external output processing in the first embodiment (Figure 24). Then, the calculation result information from step S1414 is written to the calculation result memory 131 (step S1414). In this case, the calculation result information is written in a way that does not overwrite other calculation result information already stored in the calculation result memory 131. Also, the current date and time information is read from the RTC 115, and the read date and time information is associated with the calculation result information that was written this time. This makes it possible to identify which time period the calculation result information written this time corresponds to.

[0340] Subsequently, in step S1415, similar to step S1015 of the external output processing in the first embodiment (Figure 24), the number of balls that enter during the high-frequency support mode is calculated, and in step S1416, similar to step S1016 of the external output processing in the first embodiment (Figure 24), the number of balls that enter during the high-frequency support mode while the front door frame 14 is open is calculated. Also, in step S1417, similar to step S1017 of the external output processing in the first embodiment (Figure 24), various parameters are calculated. Then, the calculation result information from step S1417 is written to the calculation result memory 131 (step S1418). In this case, the calculation result information is written in a way that does not overwrite other calculation result information already stored in the calculation result memory 131. Also, the current date and time information is read from the RTC 115, and the read date and time information is associated with the calculation result information that was written this time. This makes it possible to identify which time period the calculation result information written this time corresponds to. After that, an infinite loop occurs, and it waits until the power supply to the management CPU 112 is completely stopped.

[0341] Figure 33 is a flowchart showing the external output processing performed by the management CPU 112. Note that the external output processing is performed in step S608 of the management processing (Figure 18).

[0342] When the output instruction signal from the main CPU 63 reaches a HI level (step S1501: YES), the calculation result output process is executed (step S1502). In this output process, various calculation results stored in the calculation result memory 131 are output to the reading terminal 102. As a result, the various calculation results stored in the calculation result memory 131 are read by a reading device electrically connected to the reading terminal 102. In this case, if the calculation result memory 131 stores only the various calculation results corresponding to the occurrence of a single calculation trigger, only the various calculation results corresponding to the occurrence of that single calculation trigger are read by the reading device. If the calculation result memory 131 stores various calculation results corresponding to the occurrence of multiple calculation triggers, the various calculation results corresponding to those multiple calculation triggers are read by the reading device.

[0343] Subsequently, the output process for history information is performed (step S1503). In this output process, all history information stored in the history area 124 of the history memory 117 is sequentially output to the reading terminal 102. As a result, the various history information stored in the history area 124 is read by a reading device electrically connected to the reading terminal 102. By outputting not only the various calculation results but also the history information in this way, it becomes possible for an operator using the reading device to perform a detailed analysis of the various calculation results.

[0344] Subsequently, a clear process is performed (step S1504). In the clear process, the history information storage area 125 of the history memory 117 is cleared to "0", and the pointer area 126 is also cleared to "0". This initializes the history area 124. In addition, the clear process clears each area of ​​the calculation result memory 131 to "0". This initializes the calculation result memory 131.

[0345] The embodiment described in detail above provides the following excellent effects.

[0346] When the power supply to the main CPU 63 is cut off, the management CPU 112 calculates various parameters. This makes it possible to manage various parameters on a per-business-day basis.

[0347] When the main CPU 63 detects that the power supply to it will be cut off, the output state of the calculation instruction signal is changed to a HI level, causing the management CPU 112 to calculate various parameters. This makes it possible for the management CPU 112 to calculate various parameters based on instructions from the main CPU 63.

[0348] The various parameters calculated by the management CPU 112 are sequentially written to the calculation result memory 131. This makes it possible to store the various parameters in the management IC 66, and when reading the parameters with a reading device, it becomes possible to read the parameters for multiple business days at once.

[0349] When various parameters are written to the calculation result memory 131, information that allows for the identification of the time when those parameters were calculated is written to the calculation result memory 131 along with those parameters. This makes it possible to analyze the parameter information while knowing when the parameters were calculated.

[0350] Furthermore, when a calculation trigger occurs and the calculation results of various parameters for that trigger are written to the calculation result memory 131, the history memory 117 may be cleared to "0". This makes it less likely that new history information will be written to the history memory 117 when the maximum number of history information items that can be stored has already been stored in the history memory 117.

[0351] Furthermore, the information to be output externally to the reading device may be limited to the various parameter information stored in the calculation result memory 131, while the history information stored in the history memory 117 is not output externally. This makes it possible to reduce the amount of information output externally.

[0352] <Fourth Embodiment> In this embodiment, the processing configuration of the power outage response process executed by the management CPU 112 differs from that of the third embodiment described above. The configurations that differ from those of the third embodiment will be described below. Configurations that are the same as those of the third embodiment will generally not be described.

[0353] Figure 34 is a flowchart showing the power outage response process executed by the management CPU 112 in this embodiment.

[0354] When the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1601: YES), various calculation processes are executed (step S1602). In the various calculation processes, steps S1402 to S1409, steps S1411 to S1413, and steps S1415 to S1417 of the power outage response process (Figure 32) in the third embodiment described above are executed.

[0355] Subsequently, it is determined whether a predetermined parameter among the various parameters calculated in step S1602 is within the reference range (step S1603). Specifically, • Parameter 7: (K3 × "Number of prize balls awarded for winning into the special electric prize device 32" + K5 × "Number of prize balls awarded for winning into the second operating port 34") / Ratio of the total number of game balls dispensed (K2 × "Number of prize balls awarded for winning into the general prize port 31" + K3 × "Number of prize balls awarded for winning into the special electric prize device 32" + K4 × "Number of prize balls awarded for winning into the first operating port 33" + K5 × "Number of prize balls awarded for winning into the second operating port 34") • Parameter 8: K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" / Total number of game balls dispensed (K2 × "Number of prize balls awarded for winning in the general prize winning slot 31" + K3 × "Number of prize balls awarded for winning in the special electric prize winning device 32" + K4 × "Number of prize balls awarded for winning in the first operating slot 33" + K5 × "Number of prize balls awarded for winning in the second operating slot 34") These two parameters are set as the parameters to be determined as to whether or not they are within the reference range. If the value of the 7th parameter is 0.7 or less and the value of the 8th parameter is 0.6 or less, the predetermined parameters are determined to be within the reference range, and a positive determination is made in step S1603.

[0356] Furthermore, the specified parameters are not limited to the 7th and 8th parameters; other parameters may be set as the specified parameters in place of or in addition to these. For example, • Second parameter: The ratio of the total number of game balls entered into the general prize slot 31 (K2) to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5). The system may be configured such that the parameter is set as a predetermined parameter. In this case, for example, the system may be configured such that the predetermined parameter is determined to be within the reference range when the value of the second parameter is 0.1 or greater and 0.2 or less. Alternatively, the system may be configured such that only the predetermined parameter to be determined in step S1603 is calculated in the various calculation processes of step S1602.

[0357] If the specified parameters are not within the reference range (step S1603: NO), the various parameters calculated in step S1602 are written to the calculation result memory 131 (step S1604). In this case, if other calculation result information is already stored in the calculation result memory 131, the calculation result information is written in a manner that does not overwrite the already stored calculation result information. In addition, the current date and time information is read from the RTC 115, and this read date and time information is associated with the calculation result information that was written this time. This makes it possible to identify the timing to which the calculation result information written this time corresponds.

[0358] On the other hand, if the predetermined parameters are within the reference range (step S1603: YES), the process in step S1604 is not executed. As a result, only the parameters that are not within the reference range are written to the calculation result memory 131. Therefore, it is possible to reduce the storage capacity required for the calculation result memory 131 while still retaining the history of any abnormal situations in the calculation result memory 131.

[0359] If a positive result is obtained in step S1603, or if the process in step S1604 is executed, the history memory 117 is cleared (step S1605). In this clearing process, the history information storage area 125 of the history memory 117 is cleared to "0", and the pointer area 126 is also cleared to "0". As a result, the history area 124 is initialized. After the process in step S1605 is executed, an infinite loop is entered, and the system waits until the supply of operating power to the management CPU 112 is completely stopped.

[0360] As described in detail above, according to this embodiment, it is determined whether the contents of the calculated parameters fall within the reference range, and only the parameters determined to fall within the reference range are written to the calculation result memory 131. This makes it possible to reduce the amount of parameters to be stored in the calculation result memory 131, and thus reduce the required storage capacity of the calculation result memory 131.

[0361] <Fifth Embodiment> In this embodiment, the content of the calculation trigger that causes the management CPU 112 to perform calculations on various parameters differs from that of the third embodiment. The configuration that differs from that of the third embodiment will be described below. Configurations that are the same as those in the third embodiment will generally not be described.

[0362] Figure 35(a) is a flowchart showing the trigger identification process executed by the main CPU 63. The trigger identification process is executed when a positive determination is made in step S712 of the management output process (Figure 20).

[0363] Step S1701 determines whether or not a game ball has entered any of the following: the out-out port 24a, the general prize-winning port 31, the special electric prize-winning device 32, the first operating port 33, and the second operating port 34. If the determination in step S1701 is positive, the ball entry counter in the main RAM 65 is added (step S1702). In this addition process, the number of game balls that have entered any of the out-out port 24a, the general prize-winning port 31, the special electric prize-winning device 32, the first operating port 33, and the second operating port 34 is determined based on the number of times step S705 was executed in the management output process (Figure 20) for this processing round. The determined number of game balls is then added to the ball entry counter.

[0364] Subsequently, it is determined whether the value of the ball entry counter is equal to or greater than the trigger reference number of "500" (step S1703). If it is equal to or greater than "500" (step S1703: YES), the ball entry counter of the main RAM 65 is subtracted (step S1704). In this subtraction process, the value of the ball entry counter is subtracted by "500". Subsequently, the output process of the calculation instruction signal is executed (step S1705). In this output process, the output state of the calculation instruction signal input to the 15th buffer 122o at the input port 121 of the management I / F 111 is maintained at a HI level for a specific period of time. This specific period is sufficient for the management CPU 112 to recognize that the output state of the calculation instruction signal is at a HI level.

[0365] Figure 35(b) is a flowchart showing the arithmetic processing performed by the management CPU 112. Note that the arithmetic processing is performed in place of the power outage response processing in the third embodiment described above. Therefore, the arithmetic processing is configured to be performed after the external output processing in the management processing (Figure 18). In the management processing, after receiving the identification completion command from the main CPU 63 (step S606: YES), the history setting processing in step S607, the external output processing in step S608, and the arithmetic processing are repeatedly executed in this order.

[0366] When the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1801: YES), various calculation processes are executed (step S1802). In the various calculation processes, the same processes as steps S1402 to S1418 of the power outage response process in the third embodiment (Figure 32) are executed.

[0367] As described in detail above, in this embodiment, whenever the total number of game balls discharged from the game area PA exceeds a trigger threshold, various parameters are calculated by the management CPU 112. In this case, since various parameters are calculated each time a calculation trigger occurs that repeatedly occurs while operating power is supplied to the main CPU 63, it becomes possible to finely manage the entry pattern of game balls into the game area PA within the scope of one business day.

[0368] Furthermore, since various parameters are calculated based on whether the total number of game balls dispensed from the game area PA exceeds a certain threshold, these parameters are calculated only if the game is being played. This prevents the calculation of various parameters from being performed unnecessarily when the game is not being played continuously.

[0369] <Sixth Embodiment> In this embodiment, the content of the calculation trigger that causes the management CPU 112 to perform calculations on various parameters differs from that of the fifth embodiment described above. The configuration that differs from that of the fifth embodiment will be described below. Configurations that are the same as those of the fifth embodiment will generally not be described.

[0370] Figure 36 is a flowchart showing the trigger identification process executed by the main CPU 63. The trigger identification process is executed when a positive determination is made in step S712 of the management output process (Figure 20).

[0371] Step S1901 determines whether or not a game ball has entered any of the following: the out-out port 24a, the general prize-winning port 31, the special electric prize-winning device 32, the first operating port 33, and the second operating port 34. If the determination in step S1901 is negative, the value of the continuation counter provided in the main RAM 65 is incremented by 1. Step S1902. The continuation counter is a counter used by the main CPU 63 to identify the period during which no game balls have entered any of the out-out port 24a, the general prize-winning port 31, the special electric prize-winning device 32, the first operating port 33, and the second operating port 34.

[0372] If the value of the continuation counter after adding 1 is equal to or greater than the stop threshold value (step S1903: YES), the time measurement flag set in the main RAM 65 is cleared to "0" (step S1904). The stop threshold value is set so that if no game balls enter any of the out port 24a, general prize port 31, special electric prize device 32, first operation port 33, and second operation port 34 for 5 seconds, a positive judgment is made in step S1903. The time measurement flag is a flag used by the main CPU 63 to determine whether or not to measure the time required to determine the timing for switching the output state of the calculation instruction signal to the HI level. If the value of the time measurement flag is "0", the time measurement is not performed, and if the value of the time measurement flag is "1", the time measurement is performed. If a positive judgment is made in step S1901, the time measurement flag is set to "1" (step S1905).

[0373] If a negative determination is made in step S1903, if the process in step S1904 is executed, or if the process in step S1905 is executed, then, provided that the time measurement flag in the main RAM 65 is set to "1" (step S1906: YES), the value of the measurement counter provided in the main RAM 65 is incremented by 1 (step S1907). The measurement counter is a counter used to measure the time required to determine the timing for switching the output state of the calculation instruction signal to a HI level.

[0374] Step S1908 determines whether the value of the measurement counter after incrementing by 1 is equal to or greater than the indicated reference value. The indicated reference value is set so that a positive determination is made in step S1908 when the time measured by the measurement counter reaches 10 hours. If a positive determination is made in step S1908, the value of the measurement counter is cleared to "0" (step S1909), and the output processing of the calculation instruction signal is executed (step S1910). In this output processing, the output state of the calculation instruction signal input to the 15th buffer 122o at the input port 121 of the management side I / F 111 is maintained at a HI level for a specific period of time. This s...

Claims

[Claim 1] A predetermined storage execution means that, when a predetermined event occurs as a result of playing a game, performs a predetermined storage process to ensure that the information corresponding to that event is stored in the predetermined storage means, thereby causing predetermined information to be stored in the predetermined storage means, Each time a predetermined calculation trigger occurs, an information calculation means calculates behavioral information corresponding to the results of the game during a predetermined period, using the predetermined information. A result storage execution means that sequentially stores the pattern information obtained by the calculation by the information calculation means into the calculation result storage means, Equipped with, The result storage execution means includes means for causing the manner information to be stored among the manner information obtained by the calculation by the information calculation means to be stored in the calculation result storage means, The configuration is such that the aspect information obtained by the calculation by the information calculation means that is not to be stored is not stored in the storage means of this gaming machine, including the calculation result storage means. This gaming machine is A predetermined control means capable of executing predetermined progress processing for advancing the game, A means of creating a specific period of advantage when a specific trigger occurs, A notification means capable of notifying the content corresponding to the configuration information stored in the calculation result storage means, A means for which, when the supply of operating power is stopped, the notification of the content corresponding to the mode information in the notification means is terminated, but when the supply of operating power is resumed, the notification of the content corresponding to the mode information before the supply of operating power was stopped is performed, Equipped with, In the event of a specific event that causes the game's progress control to stop, the predetermined storage process by the predetermined storage execution means is not executed. The gaming machine is characterized in that the information calculation means calculates the manner information corresponding to the result of the game during the predetermined period, using the predetermined information during the specific advantageous period.

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